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Power Conscious Test Synthesis and
Scheduling for BIST RTL Data
PathsNicola Nicolici and Bashir M. Al-Hashimi
Purpose
• Investigate power dissipation during testing
• Propose novel power conscious– Test synthesis algorithms– Test scheduling algorithms
Outline
• Motivation
• Built-in self-test (BIST) – Register-transfer level (RTL) data paths
• Power dissipation classification
• Power conscious design space exploration:– Test synthesis– Test scheduling
• Experimental results
• Conclusion
Motivation
• Low power synthesis assumptions– Primary input transition probabilities– State transition probabilities
• High power dissipation during testing– High temperature => reliability decrease– Power/ground noise => yield loss
Motivation (cont)
S1
S2S5
C
SS3S4
State CodeS1 000S2 011S3 001S4 010S5 100
000 001 1
Functional Transitionstransition nt
000 100 1011 010 1001 011 1010 000 1100 010 2
scan sequential circuit
100 010 2010 101 3101 010 3
transition nt
Scan Transitions Shift out S5=100Shift in S4=010
NO correlation
PROBLEM!
Motivation (cont)
• Scan BIST environment– Test vector inhibiting techniques– Modified scan cell design– Low transition test pattern generator
• Standard scan design for test (DFT)– Test vector / scan latch ordering– Extra primary input vectors– New test application strategies
Motivation (cont)
*1
-1
+2 -2
*2
+1
v1 v2
v3 v4 v5 v6
v7 v8 v9 v10
v11 v12
v13
Register VariablesR1 v1,v11R2 v2,v12R3 v7 R4 v5 R5 v6, v8 R6 v3 R7 v9 R8 v4,v10,v13
Clock 1
Clock 2
Clock 3
Clock 4
Clock 5
Motivation (cont)
R1
*
R2 R3 R4 R5 R6 R7 R8
+ -
Clock 1 and 4Clock 2 and 3
Clock 2Clock 3
Note: R8 and – are active in clock 5
BIST for RTL data paths
Library
HDL
RTL synthesis
netlist
netlist
layout
logic optimization
layoutsynthesis
BIST structures:• LFSR• MISR• BILBO• CBILBO +test controller
BIST for RTL data paths (cont)
Test register allocation determines test schedule
LFSR2
M1 M2 M1 M2
T1 T2 T1
T2INTERRELATION NEEDS TO BE CONSIDERED!
• Previous power conscious test scheduling
– No relation: test scheduling and test synthesis
R1 LFSR2LFSR1
Power dissipation classification
• According to necessity for test efficiency– Necessary power dissipation– Useless power dissipation
• According to occurrence during testing– Test application power dissipation– Shifting power dissipation
Power dissipation classification (cont)
• Previous test scheduling approaches assume:– fixed amount of power for each module– not applicable to BIST RTL data paths
C0 C1
MISR0 R2MISR1
Necessary powerUseless power
Inactive resources
+0 +1
Power conscious exploration
• Novel power conscious test synthesis
• Novel power conscious test scheduling
• Exploration strategies using tabu search– Time and Area oriented – TA-TSS – Power Conscious oriented – PC-TSS
R1
+0
LFSR0
+1
LFSR2
+2
LFSR1
+0
LFSR0
+1
R2
+2
useless power
elimination
Necessary powerUseless power
Inactive resources
Power conscious exploration (cont)
TESTSYNTHESIS
useless power
elimination
+0 +1 +2
R3 R4
+0 +1 +2
R3 R4
Necessary powerUseless power
Inactive resources
Power conscious exploration (cont)
TESTSCHEDULING
Power conscious exploration (cont)
• 2 test sessions: 1 for multiplier *, 1 for ALUs (+,-)
R1
*
R2 R3 R4 R5 R6 R7 R8
+ -
Power conscious exploration (cont)
BILBO1
*
BILBO2 R3 LFSR4 LFSR7 BILBO8
+ -
C+ C-
C1 C2 C8
TA-TSS – test session 1
LFSR5 R6
Necessary powerUseless power
Inactive resources
Power conscious exploration (cont)
LFSR1
*
LFSR2 MISR3 LFSR4 LFSR5 BILBO6 MISR7 LFSR8
+ -
C+ C-
C1 C2 C8
PC-TSS – test session 1Necessary powerUseless power
Inactive resources
Power conscious exploration (cont)
BILBO1
*
BILBO2 R3 LFSR4 LFSR7 BILBO8
+ -
C+ C-
C1 C2 C8
TA-TSS – test session 2
LFSR5 R6
Necessary powerUseless power
Inactive resources
Power conscious exploration (cont)
LFSR1
*
LFSR2 MISR3 LFSR4 LFSR5 BILBO6 MISR7 LFSR8
+ -
C+ C-
C1 C2 C8
PC-TSS – test session 2Necessary powerUseless power
Inactive resources
Experimental results
EWF 17 csteps - AMS 0.35 micron
0
500
1000
1500
2000
10 11 12 13 14 15 16 17 18 19
Power constraint (Pu)
Tes
t ap
plica
tion
tim
e (c
lock
cyc
les)
TA-TSS PC-TSS
Experimental results (cont)
EWF 17 csteps - AMS 0.35 micron
01020304050
10 11 12 13 14 15 16 17 18 19
Power constraint (Pu)
BIS
T a
rea
over
hea
d
(sqm
il)
TA-TSS PC-TSS
Experimental results (cont)
EWF 17 csteps - AMS 0.35 micron
0102030405060
10 11 12 13 14 15 16 17 18 19
Power constraint (Pu)
Tes
t ap
plica
tion
pow
er (m
W)
TA-TSS PC-TSS
Experimental results (cont)
EWF 17 csteps - AMS 0.35 micron
0
5
10
15
20
10 11 12 13 14 15 16 17 18 19
Power constraint (Pu)
Shif
ting
pow
er
(mW
)
TA-TSS PC-TSS
Conclusion
• Testable design space exploration – Interrelation: test synthesis and scheduling– Variable power dissipation for each test
• Novel algorithms– Power conscious test synthesis– Power conscious test scheduling
• Ongoing and future work– Test controller: optimise area / performance– 2 chips design and manufacturing