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CONCORDIAVLSI DESIGN LAB
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Power Consumption in CMOS
CONCORDIAVLSI DESIGN LAB
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Power Dissipation in CMOS
Two Components contribute to the power dissipation:
» Static Power Dissipation
– Leakage current
– Sub-threshold current
» Dynamic Power Dissipation
– Short circuit power dissipation
– Charging and discharging power dissipation
CONCORDIAVLSI DESIGN LAB
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Static Power Consumption
CONCORDIAVLSI DESIGN LAB
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Static Power Dissipation
G
S
D
D
G
S
Vo
VDD
GND
B
B
MP
MN
Leakage Current:• P-N junction reverse biased current:
iL= A. is(eqV/kT-1)
• Typical value 1pA to 5A /µm2@roomtemp.
• Total Power dissipation:
PsL= iL.VDD
Sub-threshold Current• Relatively high in low threshold
devices
Vin
CONCORDIAVLSI DESIGN LAB
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Subthreshold Current
Vgs <≈Vt
VssVdd
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Subthreshold Current
CONCORDIAVLSI DESIGN LAB
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Analysis of CMOS circuit power dissipation
The power dissipation in a CMOS logic gate can be
expressed as
P = Pstatic + Pdynamic
= (VDD · Ileakage) + (VDD . Isubthreshold) +
(VDD · Ilshort circuit) + (α · f · Edynamic)
Where α is the switching probability or activity factor
at the output node (i.e. the average number of output
switching events per clock cycle).
The dynamic energy consumed per output switching event is defined as
Edynamic = eventswitching
DDDD dtVi__1
CONCORDIAVLSI DESIGN LAB
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Charging and discharging currents
Discharging Inverter Charging Inverter
CONCORDIAVLSI DESIGN LAB
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Currents due to Charging and Discharging
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Power Dissipation: Dynamic
VDD
Vin
G
S
D
D
G
S
Vo
GND
MP
MN
CL
VDD
Vin
Vout
ic ipip
in
ip
in
tp
0 t1
VDD
CONCORDIAVLSI DESIGN LAB
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Power Dissipation: Dynamic
G
S
D
D
G
S
Vo
GND
MP
MN
CL
VDD ip
During charging
Pdp
1
tp----- ip t VDD Vo– td
0
t1
=
ip t CL
dVo
dt-----------=
PdpC
L
tp------- VDD Vo– Vod
0
VDD
=
PdpC
L
2tp-------- VDD 2=
CONCORDIAVLSI DESIGN LAB
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Power Dissipation: Dynamic
G
S
D
D
G
S
Vo
GND
MP
MN
CL
VDD
in
Pdn1
tp----- in t Vo td
t1
tp
=
in t CL
dVo
dt-----------–=
PdnC
L
tp------- Vo– Vod
VDD
0
=
CL
tp-------
VDD2
2----------------=
During Discharging
CONCORDIAVLSI DESIGN LAB
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Power Dissipation: Dynamic
Total Power dissipation
Pdp+ Pdn = (CL/tp) (VDD)2
= CL. f. (VDD)2
Taking node activity factor α into consideration:
The power dissipation= α CL. f. (VDD)2
CONCORDIAVLSI DESIGN LAB
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• distributed,
• voltage-dependent, and
• nonlinear.
So their exact modeling is quite complex and accurate
power modeling and calculation is very difficult,
inaccurate and time consuming.
The MOSFET parasitic capacitances
CONCORDIAVLSI DESIGN LAB
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Schematic of the Inverter
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CMOS Inverter VTC /short Circuit Current
V out
V in1 2 3 4 5
12
34
5
MN lin
MP off
MN sat
MP sat
MN off
MP linMN sat
MP lin
MN lin
MP sat
G
S
D
D
G
S
Vout
VDD
GND
VGSN
Vin
MP
MN
VTN VDD- |VTP| VDD
ISC
ISC
CONCORDIAVLSI DESIGN LAB
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The short-circuit energy dissipation ESC is due to the rail-
to-rail current when both the PMOS and NMOS devices
are simultaneously on.
ESC = ESC_C + ESC_n
Where
and
DDVv
nDDcSC dtiVE0
_
0
0
_
0 DDVv
pDDdSC dtiVE
Analysis of short-circuit current
CONCORDIAVLSI DESIGN LAB
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Power Dissipation: short circuit current
Short Circuit:
G
S
D
D
G
S
Vo
GND
MP
MN
VinVTN
VDD-|VTP|
tftr
Isc
Vin
tp
Isc
For tr=tf = trfVTN=|VTP|
The short circuit power dissipation:
PscKn
12------- VDD 2VT–( )
3trf
tp-----=
CONCORDIAVLSI DESIGN LAB
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Current flows with load
A: InputB: VTC
C: Current flowD: Current flow
when load is increased
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Factors that affect the short-circuit current
TVV
VI TDD
DD
mean
3)2(12
1
For a long-channel device, assuming that the inverter is
symmetrical (n = p = and VTn = -VTp = VT) and with zero load
capacitance, and input signal has equal rise and fall times (r = f
= ), the average short-circuit current [Veendrick, 1994] is
From the above equation, some fundamental factors that
affect short-circuit current are:
, VDD, VT, r,f and T.)(L
W
tox
CONCORDIAVLSI DESIGN LAB
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Parameters affecting short cct current
For a short-channel device, and VT are no longer
constants, but affected by a large number of
parameters (i.e. circuit conditions, hspice
parameters and process parameters).
CL also affects short-circuit current.
Imean is a function of the following parameters (tox is process-
dependent):
CL, , T (or /T), VDD, Wn,p, Ln,p (or Wn,p/ Ln,p ), tox, …
The above argument is validated by the means of simulation in
the case of discharging inverter,
CONCORDIAVLSI DESIGN LAB
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The effect of CL on Short CCt Current
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Effect of tr on short cct Current
CONCORDIAVLSI DESIGN LAB
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Effect of Wp on Short cct Current
CONCORDIAVLSI DESIGN LAB
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Effect of time step setting on simulation results
Tr (ps) Timestep (ps) MaxStep (ps) iMax (uA) iaverage_inT/2 (uA)
2 10 802.6 1.258
4 10 413.8 1.264
5 10 336.4 1.24
6 10 284.9 1.234
8 10 221 1.245
0
10 20 183 1.231
2 10 73.09 1.202
4 10 64.4 1.213
5 10 58.69 1.21
6 10 65.64 1.208
8 10 76.13 1.207
100
10 20 63.1 1.217
2 10 50.96 1.311
5 10 49.78 1.295
5 20 50.46 1.313
8 10 50.72 1.311
8 20 52.08 1.311
200
10 20 51.25 1.311
CONCORDIAVLSI DESIGN LAB
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Reducing Power Consumption
It can be done in several ways:
Circuit Design
Architecture design
Activity reduction
Changing Vt
Etc.
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Datapath to be optimised for power consumption
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Pipelining the circuit
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Parallelism
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Parallelism and pipelining
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Activity reduction .
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Power Distribution
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Thank you !
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Interconnect
Interconnects in chips are routed in several layers horizontally and vertically and used
according to their application
CONCORDIAVLSI DESIGN LAB
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Interconnect/Via
CONCORDIAVLSI DESIGN LAB
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Large ViasAn example of replacing one large contact cut with
several smaller cuts to avoid current crowding
CONCORDIAVLSI DESIGN LAB
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ElectromigrationElectromigration is the forced movement of metal
ions due to an electric field
Ftotal = Fdirect + Fwind
Direct action of
electric field on
metal ions
Force on metal ions resulting from
momentum transfer from the
conduction electrons
AlAnode
+Cathode
-
Note: For simplicity, the term “electron wind force” often refers to the net effect of these
two electrical forces
<<
E-
-
-
Al AlAl
Al Al Al Al
Al+ -
CONCORDIAVLSI DESIGN LAB
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Electromigration
Effects of electromigration in metal
interconnects:
• Depletion of atoms (Voids):
Slow reduction of connectivity
Interconnect failure
Short cuts (Deposition
• of atoms)
=> Metal atoms (ions) travel toward the positive end of the conductor
while vacancies move toward the negative end
Voids
Hillocks
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CONCORDIAVLSI DESIGN LAB
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Incubation period
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Mean Time To Failure
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Mean Time To FailureDC interconnect, the MTTF is defined as:
kT
EAJMTTF mDC
exp2
A is the area, Jm is the current density, E is 0.5eV,
K is the Boltzsman constant, and T is the absolute temperature.
2
exp
mmm
DC
JDC
ACkJJ
kT
EA
MTTF
mJ is the average current density,
mJ is the average absolute current density and
DC
ACis a constant.
For Ac interconnect the MTTF is defined as
CONCORDIAVLSI DESIGN LAB
http://electronics.stackexchange.com/questions/128120/reason-of-multiple-gnd-and-vcc-on-an-ic
Layout of a controller
CONCORDIAVLSI DESIGN LAB
• Current has to be distributed, it is impractical that any pad can take the total current. The resistance drop is prohibiting
• Power coming in from any one pin will probably have to snake it's away around a lot of stuff to get to every part of the device. Multiple power lines gives the device multiple avenues to pull power from, which keeps the voltage from dipping as much during high current events.
• Need for a clean supply voltage at certain areas.
• Analog devices require special attention and probably different voltage supply.
• Heat distrubution, and removal
Reasons for having multiple supply lines.
CONCORDIAVLSI DESIGN LAB
http://electronics.stackexchange.com/questions/128120/reason-of-multiple-gnd-and-vcc-on-an-ic
The figure represents all of the power and ground pins on a Virtex 4 FPGA in a BGA package with 1513
pins. The FPGA can draw up to 30 or 40 amps at 1.2 volts
Every I/O pin is adjacent to at least one power or ground pin,
minimizing the inductance and
therefore the generated crosstalk.
Xilinx Virtex I/O distribution
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Example
Assume a chip of 0.5cm by 0.5cm fed by one Vdd pad. The chip consumes 1A at 3.3Volts. Determine the voltages on points marked X, Y and Z. Are these values Acceptable? What can you do about it? (assume Jm = 1mA/um2 and a 1µm thick aluminum)
CONCORDIAVLSI DESIGN LAB
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Thank you !