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Power Electronic Systems Laboratory
Diploma Thesis WS 05/06
Electromagnetically Quiet Power Supply
Stefan [email protected]
Supervisor: Marcelo Lobo HeldweinProfessor: Prof. Dr. J. W. Kolar
12th April 2006
Abstract
At the Power Electronic Systems Laboratory of the Swiss Federal Institute ofTechnology research is done to reduce the size of common mode EMC filtersin switched mode power supplies and variable speed motor drives. The targetedpower range of these SMPS’ is around5kW to 50kW . They have a three-phaseconnection at the input.
In order to accomplish that, active EMC filters are being studied, which requiresthe use of HF power amplifiers. These have special EMC requirements regardingtheir supply voltage because they operate at frequencies of up to30MHz. Thisthesis aims to develop a low volume power supply suitable for such active filters.
Different topologies, some of them with promising low emissions, others with lowcomponent count, are searched for and evaluated regarding their total volume. Themain inductors and transformers of two candidate topologies are designed and builtto measure parasitic properties. This leads to mathematical models suitable forsimulation, which account for a broad band of electromagnetic phenomena. Thesimulation results define the size of filters required to meet the maximum con-ducted noise limits, leading to the total volume of those topologies.
An important part of this work is the modeling of the main inductors at frequenciesof up to30MHz and the design of low volume EMC filters.
The smallest converter is built and tested. This includes the final design of the con-trol circuit, PCB layout, thermal verification, initial operation and measurementsof conducted emissions, checking for EMC.
Contents
1 Summary 11.1 Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Evaluation of Topologies and Magnetic Components Design 32.1 Fundamental Considerations. . . . . . . . . . . . . . . . . . . . 3
2.1.1 Topology Families. . . . . . . . . . . . . . . . . . . . . 32.1.2 Influence of Different Current Waveforms on
Conducted Emissions. . . . . . . . . . . . . . . . . . . . 32.1.3 Generic Methods to Reduce EMI. . . . . . . . . . . . . 5
2.2 Comparison Method. . . . . . . . . . . . . . . . . . . . . . . . 92.3 The Passive Approach. . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . 92.3.2 Topology Problems. . . . . . . . . . . . . . . . . . . . . 92.3.3 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . 102.3.4 Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Forward Converters. . . . . . . . . . . . . . . . . . . . . . . . . 132.4.1 Number of Switches Required. . . . . . . . . . . . . . . 132.4.2 A Two-Switch Solution. . . . . . . . . . . . . . . . . . . 132.4.3 The 15W Output Stage. . . . . . . . . . . . . . . . . . . 172.4.4 The 35W Output Stage. . . . . . . . . . . . . . . . . . . 20
2.5 Flyback Converters. . . . . . . . . . . . . . . . . . . . . . . . . 222.5.1 Two-Switch Topology . . . . . . . . . . . . . . . . . . . 222.5.2 Initial Design of the Main Inductor. . . . . . . . . . . . 222.5.3 First Redesign of the Main Inductor. . . . . . . . . . . . 25
3 Simulation 283.1 Design of the Control Loop for Simulation. . . . . . . . . . . . . 28
3.1.1 Common Considerations. . . . . . . . . . . . . . . . . . 283.1.2 Forward Converter. . . . . . . . . . . . . . . . . . . . . 283.1.3 Flyback Converter. . . . . . . . . . . . . . . . . . . . . 303.1.4 Control Related Topology Comparison. . . . . . . . . . 33
3.2 Equivalent Circuits of Magnetic Components. . . . . . . . . . . 343.2.1 General Approach. . . . . . . . . . . . . . . . . . . . . 343.2.2 The Main Transformers. . . . . . . . . . . . . . . . . . 353.2.3 The Forward Converter’s ’zero’-Ripple Inductors. . . . . 41
3.3 Simulation Models of other Parts. . . . . . . . . . . . . . . . . . 423.3.1 Semiconductors. . . . . . . . . . . . . . . . . . . . . . . 423.3.2 Peak Current Mode Controller. . . . . . . . . . . . . . . 42
3.4 Harvesting Data for the Filter Design Process. . . . . . . . . . . 443.4.1 Obtaining Suitable Simulation Parameters. . . . . . . . . 443.4.2 Importing the Data into Matlab. . . . . . . . . . . . . . . 45
4 Filter Design 46
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4.1 General Approach. . . . . . . . . . . . . . . . . . . . . . . . . . 464.2 Common Mode Input Filters. . . . . . . . . . . . . . . . . . . . 47
4.2.1 Obtaining the Noise Spectrum. . . . . . . . . . . . . . . 474.2.2 Filter Topology. . . . . . . . . . . . . . . . . . . . . . . 484.2.3 Dimensioning the Inductors and Capacitors. . . . . . . . 494.2.4 Verification . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.3 Differential Mode Input Filters. . . . . . . . . . . . . . . . . . . 514.3.1 Development Time Considerations. . . . . . . . . . . . . 514.3.2 Updating the Simulation Model. . . . . . . . . . . . . . 524.3.3 The DM Input Filter for the Flyback Converter. . . . . . 52
4.4 Output Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . 534.4.1 Design Procedure. . . . . . . . . . . . . . . . . . . . . . 534.4.2 Forward Converter’s Output Filters. . . . . . . . . . . . 544.4.3 Flyback Converter’s Output Filters. . . . . . . . . . . . . 55
5 Results of the Topology Evaluation 585.1 Total Footprint Area and Volume. . . . . . . . . . . . . . . . . . 58
5.1.1 Common Circuits. . . . . . . . . . . . . . . . . . . . . . 585.1.2 Forward Converter. . . . . . . . . . . . . . . . . . . . . 585.1.3 Flyback Converter. . . . . . . . . . . . . . . . . . . . . 58
5.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6 Finalising the Flyback Converter Design 606.1 Main Inductor Redesign. . . . . . . . . . . . . . . . . . . . . . 60
6.1.1 Several Reasons for a Third Design. . . . . . . . . . . . 606.1.2 New Winding Enumeration. . . . . . . . . . . . . . . . . 606.1.3 Third Inductor Design. . . . . . . . . . . . . . . . . . . 61
6.2 Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 636.2.1 Gate Driver. . . . . . . . . . . . . . . . . . . . . . . . . 636.2.2 Bootstrap and Auxiliary Supply. . . . . . . . . . . . . . 636.2.3 Galvanic Isolation of the Feedback Signal. . . . . . . . . 66
6.3 Control Loop Design. . . . . . . . . . . . . . . . . . . . . . . . 666.3.1 The Structure. . . . . . . . . . . . . . . . . . . . . . . . 666.3.2 Model of the Peak Current Mode Controlled Converter. . 676.3.3 Measurement and Control Transfer Functions. . . . . . . 696.3.4 Loop Shaping and Proper Biasing. . . . . . . . . . . . . 70
7 Construction and Initial Operation 727.1 Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727.2 Initial Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.2.1 Test of the Input Circuit . . . . . . . . . . . . . . . . . . 737.2.2 Test of the Control Circuit. . . . . . . . . . . . . . . . . 737.2.3 Externally Powered Operation. . . . . . . . . . . . . . . 737.2.4 Autonomous Operation. . . . . . . . . . . . . . . . . . . 74
7.3 Thermal Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747.3.1 Tests with the Fourth Flyback Inductor. . . . . . . . . . 747.3.2 Fifth Flyback Inductor. . . . . . . . . . . . . . . . . . . 757.3.3 Thermal Imaging, Maximum Load. . . . . . . . . . . . . 77
8 EMC Measurements 808.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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8.2 EMC with the Fourth Flyback Inductor. . . . . . . . . . . . . . . 808.3 EMC with the Fifth Flyback Inductor . . . . . . . . . . . . . . . 81
8.3.1 No Additional External Filters. . . . . . . . . . . . . . . 818.3.2 Additional Filters. . . . . . . . . . . . . . . . . . . . . . 828.3.3 CM and DM Noise at the Input. . . . . . . . . . . . . . . 83
A Inductive Components 85A.1 Forward Converter . . . . . . . . . . . . . . . . . . . . . . . . . 85
A.1.1 Main Transformer . . . . . . . . . . . . . . . . . . . . . 85A.1.2 Output Inductors. . . . . . . . . . . . . . . . . . . . . . 86
A.2 Flyback Converter. . . . . . . . . . . . . . . . . . . . . . . . . . 89A.2.1 Main Inductor for Discontinuous Mode of Operation. . . 89
B Non-Linear Model for Inductors 94B.1 Model of the VAC CM Inductors. . . . . . . . . . . . . . . . . . 94
B.1.1 General Definitions. . . . . . . . . . . . . . . . . . . . . 94B.1.2 Material Data:VITROPERM 500 F . . . . . . . . . . . . 95B.1.3 Number of Turns. . . . . . . . . . . . . . . . . . . . . . 95B.1.4 Derivation of the Model . . . . . . . . . . . . . . . . . . 97B.1.5 Inductor Models . . . . . . . . . . . . . . . . . . . . . . 100
C Prototype Data 102C.1 Schematic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 102C.2 Component Placement on the PCB. . . . . . . . . . . . . . . . . 106C.3 PCB Layout, Original Size. . . . . . . . . . . . . . . . . . . . . 107C.4 Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . 109C.5 Electrical Specification. . . . . . . . . . . . . . . . . . . . . . . 110
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List of Figures
2.1 Signals S1 and S2. . . . . . . . . . . . . . . . . . . . . . . . . . 42.2 Signals S3 and S4. . . . . . . . . . . . . . . . . . . . . . . . . . 42.3 Signal S2 including equal rise and fall times. . . . . . . . . . . . 52.4 ’zero’-ripple techniques, realisation A (left) and B (right). . . . . 62.5 Equivalent circuit diagram for ZR-transformer. . . . . . . . . . . 72.6 Lσs
Lpin % in dependence ofn andk . . . . . . . . . . . . . . . . . 8
2.7 Normal (left) and low capacitance (right) inductor winding layouts;notice the two differences, one in each of winding layout (red box)and turns layout (enumeration). . . . . . . . . . . . . . . . . . . 8
2.8 Passive, insulated three-phase rectifier. . . . . . . . . . . . . . . 92.9 The two operation modes of the 3-phase passive rectifier. . . . . 102.10 Three-phase passive rectifier: input phase voltage, phase current
and output voltage of the design withC1−3 = 3.68µF andC4−6 =4.7µF , see table2.1for details.. . . . . . . . . . . . . . . . . . . 11
2.11 Forward converter used in topology evaluation. . . . . . . . . . . 132.12 Approximate voltage and current waveforms of the forward converter142.13 Flyback converter used in topology evaluation. . . . . . . . . . . 22
3.1 Forward converter’s minimal control structure. . . . . . . . . . . 283.2 Forward converter’s voltage control loopL . . . . . . . . . . . . 303.3 Control structure used to simulate the flyback converter. . . . . . 313.4 Bodeplot of the flyback’s loop transfer functionL . . . . . . . . . 333.5 Simple equivalent circuit of a transformer winding. . . . . . . . 343.6 Equivalent circuit of a transformer winding. . . . . . . . . . . . 353.7 Simplified two winding transformer equivalent circuit for induc-
tance measurements. . . . . . . . . . . . . . . . . . . . . . . . . 353.8 Impedance curves of the forward converter’s main transformer:
primary side (windings1+2) impedance with other windings open(left) and shorted (right). . . . . . . . . . . . . . . . . . . . . . . 39
3.9 Impedance curves of the forward converter’s main transformer:winding 3 impedance with other windings open (left) and shorted(right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.10 Impedance curves of the forward converter’s main transformer:winding 4 impedance with other windings open (left) and shorted(right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.11 Impedance curves of the flyback converter’s main inductor: pri-mary side (winding1) impedance with other windings open (left)and shorted (right). . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.12 Impedance curves of the flyback converter’s main inductor: wind-ing 2 impedance with other windings open (left) and shorted (right)40
3.13 Impedance curves of the flyback converter’s main inductor: wind-ing 3 impedance with other windings open (left) and shorted (right)40
3.14 Forward converter’s ’zero’-ripple inductor equivalent circuit (theorange marks indicate the equivalent components of figure2.11) . 41
4.1 Simplified three-phase LISN with supply. . . . . . . . . . . . . . 464.2 Path of mixed mode currents. . . . . . . . . . . . . . . . . . . . 47
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4.3 CISPR 22 Class A limit and unfiltered CM noise between150kHzand30MHz at the input of the flyback converter. . . . . . . . . . 48
4.4 CISPR 22 Class A limit and unfiltered CM noise between150kHzand30MHz at the input of the forward converter. . . . . . . . . 48
4.5 Minimal required relative CM filter attenuation for the flyback con-verter, including the6dB margin; higher attenuation means lessdB 49
4.6 CM filter structure, common for flyback and forward converter. . 504.7 Single-phase equivalent circuit of the CM filter, including the LISN504.8 Flyback converter’s input filters. . . . . . . . . . . . . . . . . . . 524.9 Complete LISN including load resistorZo for the development of
output filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544.10 Degenerated LISN used for the development of the output filters. 544.11 Noise spectra of the forward converter’s15W output with different
loads and once with a wrong stray inductance. . . . . . . . . . . 554.12 Π filter used at the15W , 60V output of the flyback converter. . . 564.13 Noise spectra of the flyback converter’s15W output with different
loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.1 Volume contribution and comparison; The total of the three-phasepassive topology is reduced from700cm3 to 0 in order to make theother differences visible.. . . . . . . . . . . . . . . . . . . . . . 59
6.1 First (left) and second (right) bootstrap circuit: capacitively coupled646.2 Third bootstrap circuit: resistive, non-switched. . . . . . . . . . 646.3 Fourth (left) and fifth (right) bootstrap circuit: switched resistors. 656.4 BadVgs of bootstrap MOSFET during power up. . . . . . . . . . 656.5 Control structure of the flyback converter realised in hardware. . 676.6 The flyback converter’s open control loop,L, realised in hardware 71
7.1 On-board input filter measurement. . . . . . . . . . . . . . . . . 72
7.2 Measured insertion loss curves (20 · log10
∣∣∣V2(f)V1(f)
∣∣∣ ⇒ fig. 7.1) of
the flyback converter’s input filter . . . . . . . . . . . . . . . . . 737.3 Sandwich layout: low proximity effect, very high capacitance be-
tween primary and secondary windings; winding enumeration ac-cording to figureC.4 . . . . . . . . . . . . . . . . . . . . . . . . 75
7.4 Magnetic field in a sandwich inductor with different operating modes;The stray inductances are neglected.. . . . . . . . . . . . . . . . 76
7.5 Thermal images1 (top) and2 (bottom) (tab.7.2); The two hot spotson the right hand side are the two diodes of the±15V output. Thehot area in the middle is caused by the two MOSFETs. Metallicsurfaces show up as cold due to low radiation. In fact they are ashot as their surrounding.. . . . . . . . . . . . . . . . . . . . . . 78
7.6 Thermal image3 (tab.7.2) . . . . . . . . . . . . . . . . . . . . . 787.7 Thermal image4 (tab.7.2), bottom side of PCB. . . . . . . . . . 797.8 Thermal image5 (tab.7.2), top side of PCB. . . . . . . . . . . . 79
8.1 EMC test setup. . . . . . . . . . . . . . . . . . . . . . . . . . . 808.2 Total conducted noise, fourth main inductor design, minimum load;
blue: input phase T, green: output+30V , black: background noise 818.3 Total conducted noise, fifth main inductor design, minimum load;
input phase T (blue), output+30V (green), background noise (black)82
v
8.4 Total conducted noise at the input, fifth main inductor design, min-imum (blue) and maximum (black) load. . . . . . . . . . . . . . 83
8.5 Total conducted noise at the+30V output, fifth main inductor de-sign, minimum load; without (blue) and with (green) additionalfilters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
8.6 Separated DM (blue), CM (black) and background (green) noise atthe input under full load, fifth main inductor design. . . . . . . . 84
A.1 Forward converter’s main transformer winding layout. . . . . . . 85A.2 Forward converter’s main transformer equivalent circuit. . . . . . 85A.3 Forward converter’s output inductor winding layout. . . . . . . . 86A.4 Forward converter’s output stray inductor pin diagram (L3 in figure
2.11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86A.5 Forward converter’s ’zero’-ripple inductor equivalent circuit (the
orange marks indicate the equivalent components of figure2.11) . 87A.6 The flyback converter’s main inductor winding layout. . . . . . . 89A.7 The flyback converter’s main inductor equivalent circuit. . . . . . 89A.8 The flyback converter’s main inductor winding layout, fourth design91A.9 The flyback converter’s main inductor winding layout, fifth design92
B.1 The impedance curves of the two VAC cores used in the flybackconverter’s input CM filter.. . . . . . . . . . . . . . . . . . . . . 101
C.1 Flyback converter’s schematic diagram, sheet 1 of 4. . . . . . . . 102C.2 Flyback converter’s schematic diagram, sheet 2 of 4: input filter. 103C.3 Flyback converter’s schematic diagram, sheet 3 of 4: control circuit104C.4 Flyback converter’s schematic diagram, sheet 4 of 4: power con-
version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105C.5 Top placement. . . . . . . . . . . . . . . . . . . . . . . . . . . .106C.6 Bottom placement. . . . . . . . . . . . . . . . . . . . . . . . . . 106C.7 Top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107C.8 MidSignal, second layer. . . . . . . . . . . . . . . . . . . . . . 107C.9 MidPlanes, third layer. . . . . . . . . . . . . . . . . . . . . . . . 108C.10 Bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
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List of Tables
2.1 Passive rectifier designs resulting in60V output voltage. . . . . . 122.2 Forward converter’s main transformer core data. . . . . . . . . . 172.3 Forward converter’s main transformer losses. . . . . . . . . . . . 172.4 Saturation flux densities of N87, 3F3 and 3C96. . . . . . . . . . 182.5 Number of turns per winding on the output inductor. . . . . . . . 19
3.1 Values for the Parameters ofGvd . . . . . . . . . . . . . . . . . . 293.2 Values for the Parameters ofGvi . . . . . . . . . . . . . . . . . . 323.3 Measurements carried out to determine the inductive behaviour of
the forward converter’s main transformer. . . . . . . . . . . . . . 363.4 Stray coefficients and turns ratios for the forward converter’s main
transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1 Filter component values for the flyback converter’s15W output . 57
6.1 Windings of the third flyback inductor and their purpose. . . . . 60
7.1 Output voltages at certain load conditions,V4 is controlled to be14.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.2 Load configurations used for the thermal images, the ambient tem-perature is22.6C . . . . . . . . . . . . . . . . . . . . . . . . . . 77
A.1 Forward converter’s main transformer winding data. . . . . . . . 85A.2 Values of the forward converter’s main transformer equivalent cir-
cuit components (figA.2) . . . . . . . . . . . . . . . . . . . . . . 86A.3 Forward converter’s 15W output inductor winding data. . . . . . 87A.4 Forward converter’s 35W output inductor winding data. . . . . . 87A.5 Forward converter’s output stray inductor winding data. . . . . . 87A.6 Forward converter’s15W/60V output inductor data (figA.5) . . . 88A.7 Forward converter’s35W/30V output inductor data (figA.5) . . . 88A.8 The flyback converter’s main inductor winding data, initial design89A.9 Values of the flyback converter’s main transformer equivalent cir-
cuit components (figA.7), initial design . . . . . . . . . . . . . . 90A.10 The flyback converter’s main inductor winding data, first redesign90A.11 Values of the flyback converter’s main inductor equivalent circuit
components (figA.7), first redesign . . . . . . . . . . . . . . . . 90A.12 Mapping of winding enumeration between measurement and schematic
related illustrations . . . . . . . . . . . . . . . . . . . . . . . . . 91A.13 The flyback converter’s main inductor winding data, fourth design91A.14 Values of the flyback converter’s main inductor equivalent circuit
components (figA.7), fourth design; the simulations neglect wind-ing 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
A.15 The flyback converter’s main inductor winding data, fifth design. 92A.16 Values of the flyback converter’s main inductor equivalent circuit
components (figA.7), fifth design . . . . . . . . . . . . . . . . . 93
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Summary
1.1 Assignment
The aim of this work is the complete design of a high performance insulated powersupply. The power supply should provide energy to a high frequency power am-plifier. For that it must be virtually free from electromagnetic noise in order not toinfluence the operation of the HF amplifier.
The input side of the power supply must be compliant to international EMC regu-lations (CISPR 22) while the output side should present low noise emission levelsthat are tolerable by the HF amplifier. The supplied power is relatively low (50 W)so the challenge is to design a system which is competitive.
A survey on different converter topologies, two actively switched and one passivesolution, shall be carried out aiming for EMC, small dimensions, low costs androbustness while keeping a good regulation of the output voltage. A study aboutwhich switching frequency is to be used as well as what type of commutation is tobe applied should be done.
EMC filters shall be designed both for input and output where the possibility ofusing integrated components could also be researched.
1.2 Solution
The search for possible topologies ends up in three candidates. Those are evaluatedfor suitability and volume occupation. This evaluation is done in several steps.The first candidate, the passive solution, is designed allowing direct calculationof the volume. The two active solutions require more work. First, their mainmagnetic components are designed and built. Measurements lead to equivalentcircuits valid for frequencies of up to30MHz. These equivalent circuits are usedto simulate the conducted, electromagnetic emissions. Filters are designed to keepthose emissions below their limits. The main inductors together with the filtersdetermine the volume of the converters. Control circuits and input rectifiers are nottaken into account as they occupy the same area for both active topologies.
The winner of the volume competition is built. This implies a redesign to cutlosses on semiconductors and provide multiple output voltage levels. Furthermorean auxiliary output provides power to the converter itself.
EMC measurements at the final converter are carried out to verify the input andoutput filters.
1
1.3 Results
The first topology is a totally passive solution. It is mainly a capacitive voltagedivider followed by a three-phase diode bridge. It does not fit the needs of thisassignment at all because of its large volume and bad output voltage regulation.
The second topology is derived from a classical forward converter. The input ismodified to obtain a single switch solution drawing a continuous current. Eventhough it is a single switch solution, two transistors in series are required due tohigh voltage stresses. The outputs are enhanced by ’zero’-ripple devices.
The third topology serves as a benchmark. It is chosen to be a two-switch flybackconverter.
The active, switched solutions use a switching frequency of120kHz. This wayonly the harmonics lay in the regulated area between150kHz and30MHz. Thisreduces the size of the required input and output filters. Even though the volumeof the inductors decreases with increasing frequency, a switching frequency below150kHz results in a lower overall volume. High switching frequencies, where thetotal volume would be smaller again, are not possible because the desired solutionhas no active cooling. The high input voltage would result in excessive switchinglosses at high frequencies.
The EMC limits are obeyed using the main transformer which the EMC filters aredesigned for. Unfortunately, the main transformer shows very high losses due toproximity effects. In order to deliver nominal power to the output, a new trans-former is built. Because of its different characteristics, the EMC limits are violatedat certain frequencies.
1.4 Conclusion
As expected, the main transformers of the forward and flyback converters have thesame size. But interestingly the latter wins the volume competition quite clearly.Even though the forward converter has much lower peak currents at the input, theinput and output filters of the flyback converter together are smaller than the outputfilters of the forward converter.
The small currents but high voltages impose problems regarding the selection ofsemiconductors. The design is limited to SMD components. Diodes built for lowcurrents operate at their thermal limits due to switching losses. A redesign beforeconstruction of the PCB allows to useDO214AAandDO214ACpackages for theoutput diodes. This leads to a much smaller footprint area than is required forD-PAK devices while the size of the main inductor is not changed.
The inter-winding capacitances of the main transformer are very important. Theydetermine the conducted noise emissions at high frequencies, where it is difficultto build suitable filters. It is important to combat noise emissions above10MHz attheir source, in addition to adding appropriate EMC filters.
2
Evaluation of Topologies and MagneticComponents Design
2.1 Fundamental Considerations
2.1.1 Topology Families
The converter to be built is part of a larger converter drawing at least100 timeshigher currents, so PFC is not a requirement. It increases control effort of mosttopologies and is thus a disadvantage regarding volume and cost. Many topologiesrequire one or more switches or even a whole converter per phase to provide PFCfunctionality. This contradicts low volume and price.
Low volume and low cost considerations aim towards a single switch topology. SoDC/DC converters with a prepended B6 diode-bridge rectifier shall be consideredin the search for suitable topologies.
Resonant converters show promising spectral characteristics with low EMI but gen-erally require more switches than can be afforded. Furthermore their control de-mands for much higher complexity. This is not acceptable for the case at hand.Even though the size of the required filters could be reduced by using modulatedfrequency carrier based control.
2.1.2 Influence of Different Current Waveforms onConducted Emissions
As different converter topologies exhibit various switching characteristics, it makessense to compare some common waveforms regarding how fast their amplitudes infrequency domain decay with increasing frequency. The result indicates whethercertain topologies have to be favored over others, because their current waveformsrequire smaller filters.
Spectral Analysis
The four signal types compared are shown in figures2.1and2.2. Their mathemat-ical definitions for one periodTs are as follows:
S1
A(1− t
DTs
)∀ t ∈ [0, DTs]
0 else(2.1)
S2
A ∀ t ∈ [0, DTs]0 else
(2.2)
S3
A + dpp · t
DTs∀ t ∈ [0, DTs]
0 else(2.3)
3
S4
A + dpp · t
DTs∀ t ∈ [0, DTs]
A + dpp
1−D
(1− t
Ts
)else
(2.4)
Transforming the signals into fourier series reveals the amplitudes in dependenceof frequency:
cn =1Ts
∫f(t) exp−inωt dt (2.5)
tDTs Ts
A
tDTs Ts
A
Figure 2.1: Signals S1 and S2
t
A
DTs Ts
dpp
t
A
DTs Ts
dpp
dpp
Figure 2.2: Signals S3 and S4
The complex coefficientscn of signals S1 and S2 are as follows:
S1 cn = A · 1− exp−2iDnπ −2iDnπ
4Dn2π2(2.6)
S2 cn = −iA · 1− exp−2iDnπ
2nπ(2.7)
Both signals have terms decaying with1n ∝
1f . The results for signals S3 and S4
have more terms but the slowest terms of all four signals decay proportional to1n .
From that it is concluded that neither current waveform provides a useful, EMIrelated advantage. The evaluation should thus include topologies derived from theclassical forward converter (S2) as well as such derived from a flyback topology(S1).
4
Slow Switching
Responsible for the similar behaviour of the four different signals presented in theprevious section are the ideal edges. By introducing rise and fall timestr in S2,the signal shown in figure2.3, a more realistic situation is obtained. It can bedirectly related to some MOSFET switching behaviour. The stray inductance of,for example, a flyback converter’s main inductor has similar influence.
tDTs Tstr
A
Figure 2.3: Signal S2 including equal rise and fall times
The amplitudes of the fourier coefficients of this signal decay initially proportionalto 1
n until they decay proportional to1n2 starting atf2 = 1
πtr[1].
This shows that slow or resonant switching is a method to reduce EMI at highfrequencies. Slow switching can be used with nearly any converter topology but itproduces high losses on the transistors.
2.1.3 Generic Methods to Reduce EMI
There are some general rules to obey when designing an EMI tolerant circuit.
Circuit Balancing
Balancing has only a minor impact on conducted emissions. It mainly eliminatesfar field effects of radiated EMI by canceling electric fields. As it is the case withmost EMC related measures, balancing not only helps against emmissions but alsoreduces received noise, improving the circuit’s susceptibility.
PCB Layout
[2] and [3] touch EMI related PCB layout. The main point is to keep loops con-ducting switched currents small, circling only the smallest possible areas. Anotherimportant point is to keep any wires carrying high∂I
∂t as short as possible for min-imal parasitic inductance. These two measures help reducing high voltage spikesand radiation. Additional ground planes and further planes as necessary, placedparallel to ground planes in order to serve as capacitor electrodes, can provide highfrequency short circuits and thus suitable AC return paths. Guard wires can helpwhere no ground plane can be placed.
Planes with apertures can serve as antennas as good as a single wire. A wire cross-ing an aperture of a ground plane on a different layer has an interrupted AC return
5
path if no bias is provided. Strong crosstalking with parallel wires might be theresult.
Floating planes can be worse than no plane at all due to capacitive coupling. Planesalways have to be connected to suitable DC potentials.
’Zero’-Ripple Techniques
[1], [5], [6] and [7] present ripple canceling techniques. At least one of them can beapplied to probably any converter family, on the input as well as on the output side.It is of most use when integrated into an inductor which is required anyway, suchas, for example, the output inductor of a forward converter or the main inductor ofa flyback converter. The technique uses a transformer with a well controlled strayinductance and an additional capacitor. Figure2.4shows two possible realisations.The second form results from exchanging the noisy and quiet ports of the first form.
L1
C1L1s
L1p
L1
C1L1s
L1p
Figure 2.4: ’zero’-ripple techniques, realisation A (left) and B(right)
[6] contains a comparison of both configurations. The voltage of capacitorC1 isassumed to be constant. Inductor voltages and currents count positive from left toright. For version A, the following equations have to be fullfilled for ideal ripplecanceling:
vp=Lpip + Mis transformer equation, primary windingvs=Mip + Lsis transformer equation, secondary windingvs=vp because output voltage equalsvC1
ip=0 zero-ripple condition
(2.8)
Version B yields (2.9):
vp=Lpip + Mis transformer equation, primary windingvs=Mip + Lsis transformer equation, secondary windingvs=0 because output voltage equalsvC1
ip=−is zero-ripple condition
(2.9)
Both equation systems result in the same zero-ripple condition:
M = Ls = LMs + Lσs (2.10)
Two desirements, a low number of turns for the secondary winding and a lowcurrent throughC1, let version B be the better choice than A in most cases. The
6
low number of secondary turns gives a small M. Relating figure2.5 to version Ameans
La = M and Lb = Lp −M ⇒ La Lb (2.11)
For version B, a more suitable relation is obtained:
La = Lp −M and Lb = M ⇒ La Lb (2.12)
La LbC1
Figure 2.5: Equivalent circuit diagram for ZR-transformer
There are restrictions on the turns ration := NaNb
to be used. From the definition ofthe coupling factork, the secondary stray inductanceLσs is calculated.
k
√Lp
(Lp
n2+ Lσs
)!=
Lp
n⇒ Lσs =
Lp
n2
(1k2− 1)
(2.13)
This relation is given by the transformer. Typical values fork are0.97 . . . 0.9998.Another equation forLσs is given by the zero-ripple condition:
M =Lp
n
!= Ls ⇒ Lσs!=
Lp
n
(1− 1
n
)(2.14)
In order to obtain a realisable configuration,Lσs given by (2.13) has to be lowerthanLσs requested by (2.14). This makes it possible to finetune the transformerby adding an external stray inductor. A condition forn depending onk is thusobtained from
Lp
n2
(1k2− 1)
︸ ︷︷ ︸transformer
≤ Lp
n
(1− 1
n
)︸ ︷︷ ︸ZR-condition
⇒ n ≥ 1k2
⇒ n ≥ 1.07 (2.15)
The required, additional inductanceLσe then equates to
Lσe =Lp
n
(1− 1
n
)− Lp
n2
(1k2− 1)
=Lp
n
(1− 1
nk2
)(2.16)
This shows thatLσe inreases very fast duringn = [1 . . . ∼ 2] and becomes smallerfor largern. It is thus desirable to maken as large as possible. As figure2.6indicates, it is also possible to choose a suitablen by adjustingk. The better wayis to use a highk and a highn, because designing a transformer based on a givenk is harder than with a highk. Another advantage of a highn is the increasedrobustness against variations ofk.
7
1 2 3 4 5 6 7 8 9 100
5
10
15
20
25
n
%
k = 0.97k = 0.5
Figure 2.6:LσsLp
in % in dependence ofn andk
Inductor Design
The usual way of winding an inductor or transformer is the one shown in figure2.7 on the left hand side. The figure shows a bobbin as used for E-cores, but theprinciples apply to windings on any core shape.
1 2 3 4 5 6 7 8
9101112131415P
S 1 2 3 4 5 6 7 8
1
13 147 104
3 6 9 12
11852
7 8
1
P S
2
3
4
5
6
Figure 2.7: Normal (left) and low capacitance (right) inductorwinding layouts; notice the two differences, one in each of wind-ing layout (red box) and turns layout (enumeration)
Multiple parallel layers of turns of a single winding cause high parasitic windingcapacitances. In certain applications it might be possible to overcome this by usingjust one layer per winding. If that is not possible one might get a lower capacitivebehaviour by laying the turns as illustrated in figure2.7on the right hand side. Thishas the same effect as placing capactiors in series. The drawback is an ugly windingconsuming slightly more space than a traditionally wound winding. Furthermorethe lower coupling causes higher leakage.
A way to reduce the inter-winding capacitance is to "vertically" sepparate the wind-ings in addition to increasing the clearance between them. This reduces the areasforming parasitic capacitors.
A grounded shield between the windings is only of limited use as it builds a capa-citor between the primary and secondary side too. But a shield, red boxes in figure2.7, can cause the generation of differential instead of common mode noise incertain applications. For the functionality of a transformer it is important not tocreate a short circuit winding by a shield layer.
8
2.2 Comparison Method
For the selection of a suitable topology, a measure for comparison has to be defined.The primary goal is to minimise the volume, including any filters necessary to meetEMC regulation requirements.
Thus the most promising converters are designed and their conducted emissionssimulated. This allows to design the filters necessary to comply with EMC regula-tions. On this way, the total volume of each candidate topology is obtained.
2.3 The Passive Approach
2.3.1 Motivation
The main reason to investigate a passive solution is that it might be possible touse its capacitors as differential mode filters for the host converter. This could bepossible with a topology as shown in figure2.8.
C1
C2
C3
C4
C5 C6
D1 D2 D3
D4 D5 D6
Vo
R
S
T
Figure 2.8: Passive, insulated three-phase rectifier
This topology uses three series capacitors,C1−3, for galvanic insulation and threeparallel capacitors,C4−6, to decrease the THD of the input currents.
2.3.2 Topology Problems
Neglecting the B6 rectifier and treating the rest of the circuit as a complex volt-age divider does not work. The discontinuities introduced by the switching of thediodes are essential.
Another approach would be to assume sinusoidal input currents and to calculate thenecessary phase-shift between input voltage and current using the input impedanceof the converter. For proper values ofC4−6, the input currents are indeed verysimilar to sinewaves. The minimal size ofC1−3 is given by the load power con-sumption.
9
No matter which way is tried, the approximations are too rough. Unfortunatelythe output voltage across a constant load resistor varies strongly in dependence onthe capacitor values1. This topology is even like a constant power source adjustedonly by the values of capacitorsC1−6. That means the output voltage is unstablefor constant power loads. In other words, a mismatched load leads to
√6VN or 0V
at the output. Any linear stabilisation would always cause the maximum power tobe drawn.
Modes of Operation
This topology has two different operating modes, "small" and "large"C4−6. In factthere are infinitely many solutions to obtain a certain output voltage at a certainload. The largerC4−6 are defined, the largerC1−3 must be to maintain a constantoutput voltage. With smallC4−6 there is an interval where three of the six B6diodes conduct at the same time (fig2.9). The input current THD is high (≈ 1.7for C1−3 = 2.73uF , C4−6 = 0 andPo = 15W at 60V ). This interval, occuringonce per2π
6 , disappears with increasingC4−6 and the THD improves (≈ 0.4 forC1−3 = 5uF , C4−6 = 10uF andPo = 15W at 60V ). Unfortunately, at thatoperating point, the peak intput currents reach0.5A per phase with a phase shift of86 against the input voltage. LowerC4−6 do not improve the situation much.
16 17 18 19 20 21 22 23 24 250
100
200
300
400
500
3 diodes3 diodes
3 diodes
Output: 60V, 15WC1.I = current in phase R
ms [50 Hz mains, drawn interval: π]
mA
C1.I, C4−6=0µFC1.I, C4−6=6µFC1.I, C4−6=10µF
Figure 2.9: The two operation modes of the 3-phase passive recti-fier
2.3.3 Evaluation
Simulation
Due to difficulties in the analytical evaluation, the topology is simulated to obtainuseful values for the capacitors on an experimental way. The Simplorer modelimplemented uses an ohmic load to get stable behaviour of the output voltage.ChoosingC4−6 to get a tradeoff between THD and peak current requires adjustingC1−3 to have60V and15W at the output. To obtain values forC1−3 two simula-tions with guessed values are done. A linear interpolation from guessedCA, CB
15− 6V per10% change ofC1−3, independent ofC4−6 and load
10
0 5 10 15 20 25 30 35 40−400
−200
0
200
400
phas
e vo
ltage
[V]
0 5 10 15 20 25 30 35 40−0.5
0
0.5
phas
e cu
rren
t [A
]
0 5 10 15 20 25 30 35 4058
60
62
64
outp
ut v
olta
ge [V
]
ms
Figure 2.10: Three-phase passive rectifier: input phase voltage,phase current and output voltage of the design withC1−3 =3.68µF andC4−6 = 4.7µF , see table2.1for details.
and simulatedVA, VB to a newC1−3
C1−3 = CB + (60V − VB) · CB − CA
VB − VA(2.17)
leads to an output voltage with an average error of less than0.5V .
Postprocessing the simulation data to obtain the THD is done with Matlab. Thedata saved from Simplorer’s View Tool to its binary format can be converted toMatlab .mat matrix files usingmdx2mat2.
Results
The simulation results for various load andC4−6 configurations are listed in table2.1on page12. The indicated phase-shift in degrees is between phase voltage andthe fundamental mode of the phase current.
2http://srf.ch/bitbytes.php
11
2.3.4 Conclusion
The main points of this passive, capacitive coupled rectifier are the following:
• very large volume due to Y (C1−3) and X2 (C4−6) rated capacitors
• constant power source governed byv acrossC1−3 ⇒ line frequency de-pendence; nominal power is always consumed to maintain a constant outputvoltage
• inherent power limitation
• consumes very high apparent power, at least8 times the output real power
• varying voltage (f = 6 · fline) between star point of the phases and negativeoutput potential
• no control or turn-off switches
Even the structural simplicity of this topology can not compensate for the first fivenegative aspects. This topology does not fit the requirements of this project at all.
C4−6[µF ] C1−3[µF ] IR[A] ϕ[] THD PF1 S1[V A] V [cm3]
Po = 50W
0 9.2 0.95 83 1.9 11.5 296 ≈ 75710 11.00 1.05 84 0.9 9.9 343 107320 10.00 1.97 87 0.3 5.4 619
Po = 15W
0 2.73 0.27 83 1.7 11.4 884.7 3.68 0.66 85 0.7 9.1 113 694
6 3.91 0.38 85 0.6 8.4 12010 5 0.49 86 0.4 6.6 151
Table 2.1: Passive rectifier designs resulting in60V output voltage
12
2.4 Forward Converters
Forward converters are typical DC/DC applications. Thus a B6 rectifier is prependedto the candidate topology, leaving a13.4%3 voltage ripple. This ripple is only con-sidered where required by the design. Most calculations are done with average andrms values.
2.4.1 Number of Switches Required
Foward converters generally require at least two switches. Single switch topologiesexist, but the voltage stress of their switch is usually twice that of the two switchtopologies, given a maximum duty cycle of0.5. This is forced by the requirementfor demagnetisation of the transformer core.
Considering this, a single switch topology is not feasible having input voltages ofup to620V (atVN = 230V +10%). But single switch topologies can be expandedto feature two switches in series solving the presented problem.
2.4.2 A Two-Switch Solution
[8] presents a single switch forward topology with a continuous input current. Infigure 2.11 this topology is extended with a ’zero’-ripple output inductor similarto the ones described in [6] and [7], but balanced as proposed in [1]. The ’zero’ripple approach does not much increase the volume of the output inductor which isrequired anyway. Balancing the structure does not increase its volume a lot either.These techniques reduce conducted emissions at both terminals, input and output.
+
C1
D2 D3
T1
T2
D1
D5
D4L1
L2
L3
L4
L6
L8
L7
L9
V
V
L5
C2
+ C3
+Co
i
i
ii i
IN
L2
o1 o2 oi
L1
IN
o
Figure 2.11: Forward converter used in topology evaluation
The prototype described in [8] uses two switches in series to reduce voltage stress.Two low power diodes,D4 andD5, ensure proper voltage clamping. During on-time of the switches, two equal currents flow throughVin+ − L1 − T1,2 − Vin−andL2 − C1 − T1,2. When the switches are turned off,L1 andL2 drive smallcurrents throughL1 − C1 − D1 andC3 − L2 − D1 − C3, forcing a reset volt-age ofVin across the transformer. This puts2 · Vin across the two switches until
3minimum rectifier output voltage:√
6VN sin`
2π6
´, maximum:
√6VN
=⇒ % = 100 ·`1− sin
`2π6
´´13
t
t
t
t
tTsDTs 2DTs
vC3
C3−v
vC3
i
v
o1,o2
T1,T2
Bcore
L1,L2v
INi
C32v
Figure 2.12: Approximate voltage and current waveforms of theforward converter
the magnetisation of the transformer vanishes, switchingD1 off and thus loweringthe voltage acrossT1,2 to Vin. The magnetisation current is overlayed with a largerfreewheeling current throughL1−C1−L2 rechargingC1. The sum of the recharg-ing and magnetisation current have to ensure a continuous, positive input currenteven when the switches are turned off. Thus, for proper operation, condition (2.21)has to be fullfilled.
Iµ =Vin
L1DTs (2.18)
Po = 50W Vo = 60V Io =Po
Vo= 0.83A (2.19)
Irec :12n
IoDTs!= Irec(1−D)Ts ⇒ Irec =
Io
2n· D
1−D(2.20)
Irec >12Iµ ⇒ L1 >
2VinTs
Io· n(1−D) (2.21)
DiodesD4 andD5 are low power diodes used only for voltage clamping. A diodewith higher current capability,D1, is thus needed to conduct the demagnetisation
14
current. In low power designs as the one at hand,D1 can be omitted. The currentscan be handled for example by theUS1M.
Approximations of the most important current and voltage waveforms are shownin figure2.12. The voltagesVC1 andVo are assumed to be constant. [8] contains amore in-depth explanation, including plots of measurements.
Main Transformer Design
The constraint for the duty cycle ratio isD ≤ 0.5. Choosing a maximumD leadsto the required turns ration = N1
N3+N4:
D := 0.45 (2.22)
n = D · Vin,min
Vo + VDf
∣∣∣∣VDf≈0.8V
⇒ n := 3.2 (2.23)
With a minimum input voltageVin,min =√
6 sin(2π6 ) · 230V · 0.9 and a maximum
input voltageVin,min =√
6 · 230V · 1.1 this leads to
D =n · (Vo + VDf )
Vin(2.24)
Vin ∈ [439 . . . 620]V ⇒ D ∈ [0.44 . . . 0.31] (2.25)
During DTs, when the switches conduct, the primary current is constituted of theoutput current4 Io transformed to the primary side and a magnetisation currentIµ.Each primary winding carries half of these currents and has the inductanceL1. Therecharging current freewheeling through the windings during(1−D)Ts has to beconsidered too. It is given by (2.20). The rms currents in the primary windingsresult as follows:
I2,rms ≈ I1,rms =
√(Io
n
)2
D + I2rec (1−D) = 97mA (2.26)
This equation neglects the magnetisation current, wich lowers the rms current dur-ing (1 −D) in L2 and increases it slightly inL1. It increases the currents in bothwindings duringDTs.
The current density and copper fill factor are chosen to beSrms = 3 . . . 4 Amm2 and
k = 0.5. This provides the required wire diameter.
d1,2 = 2√
I1,rms
πSrms≈ 0.18mm (2.27)
⇒ d1,2 := 0.2mm ⇒ Srms = 2.5A
mm2(2.28)
4The current ripple in the output inductor is neglected.
15
A wire diameter of0.18mm would lead toSrms = 3.8 Amm2 . But the0.2mm wire
is available in house and finally fits onto the core too. Core selection is done withan assumed wire diameter of0.18mm.
The secondary side of the transformer is split into aPo1 = 15W and aPo2 = 35Wwinding. The first one delivers power to the active filter amplifier. Its completeoutput stage is shown in figure2.11. The latter serves as an auxiliary power supplyfor the host converter and is not shown at all in figure2.11. The two output stagesare isolated from each other. The design presented here usesVo1 = 60V andVo2 = 30V . Thus the turns ratio between primary winding and the winding ofVo2,N1N10
, equals2n.
The currents in the secondary side windings are
I3,rms = Po1Vo1·√
D ≈ 150mA (2.29)
I10,rms = Po2Vo2·√
D ≈ 700mA (2.30)
requiring wire diameters of
d3 = 0.25mm ⇒ Srms = 3.0d10 = 0.5mm ⇒ Srms = 3.6
A
mm2(2.31)
These wire diameters lead to a winding areaAw proportional toNp:
Aw = Np ·
(2(
d1
2
)2
+1n
(d3
2
)2
+12n
(d10
2
)2)
π
k(2.32)
As maximum flux densitiyB := 120mT is defined to keep core losses undercontrol. This limit is not absolute. It serves as an initial starting point and getschanged depending on the chosen material. Finally a tradeoff between the vol-ume, total losses and temperature rise tells whether a certain transformer design isacceptable or not.
The minimalAe required is given by
Ae ≥VinD
N1fsB(2.33)
To select a suitable core, the productAeAw is built, canceling outN1.
AeAw =VinD
fsB·
(2(
d1
2
)2
+1n
(d3
2
)2
+12n
(d10
2
)2)
π
k(2.34)
=n · (Vo1 + VDf )
fsB· . . . (2.35)
≈ 2619mm4
Cores with according SMD bobbins are preferred, but at least a THT bobbin has tobe available. TheEQcores are for planar integration and thus do not feature accord-ing bobbins. So theEFDcores from Epcos or Ferroxcube are the most promising.
16
The materialsN87 (Epcos) and3C94 (Ferroxcube) are evaluated for this applica-tion.
TheEFD25 provides anAeAw of approximately5 2340 mm4, not enough for thisapplication. The next larger core is theEFD30 with 3609mm4. The core data islisted in table2.26.
Material AL [nH] Ve [mm3] Ae [mm2] Aw [mm2] lw [mm]Ep N87 2050 4690 69 52.3 56.7Fc 3C94 2100 4700 69 52.3 52.9
Table 2.2: Forward converter’s main transformer core data
The lowest number of primary turns to stay belowB is given by
N1 ≥VinD
fsBAe
N1 ≥n · (Vo1 + VDf )
fsBAe
= 196 turns ⇒
N87: 78.8 mH3C94: 80.7 mH
(2.36)
To get an idea about which material is the better choice, the total losses have to becalculated as well as the temperature rise of the final transformer. The results areshown in table2.3. The number of turns is increased to fill the winding window abit more than necessary. This reducesB and thus the core losses too.
Material Np %fill Pe [W ] Pw [W ] Ptot [W ] ∆T [K]Ep N87 220 82 2.4 0.28 2.7 66Fc 3C94 220 82 1.9 0.26 2.2 53
Table 2.3: Forward converter’s main transformer losses
The large difference betweenPe andPw shows, that these designs are not optimisedfor low losses. A largerAe to decrease theB and thus the core losses results in anunacceptably large core. Table2.3shows, that theEFD30-3C94 from Ferroxcubeis the best design found.
2.4.3 The 15W Output Stage
’Zero’-Ripple, Four Winding Inductor L6−9
The output inductor is a ’zero’-ripple design as described in section2.1.3. Addi-tionally, the whole output stage of the forward converter is balanced. In the case of
5EpcosEFD25: 2361mm4; FerroxcubeEFD25: 2332mm4
6The abbreviations Ep and Fc signify Epcos and Ferroxcube, respectively
17
the output inductor this just means to split the primary and secondary windings intwo halves. Both halves can remain on a common core. With a proper board layoutthis reduces the generation of and susceptibility to radiation.
The ’zero’-ripple inductor, consisting ofL5,6−9, is initially treated as a normal,single winding inductorLo1. The allowed current ripple is defined as
∆IL ≤ 0.2 · Io1 =15W
5 · 60V= 50mA (2.37)
This leads to the minimally requiredLo1:
∆IL
!≥
1nVin − Vo1
Lo1DTs ⇒ Lo1 ≥
1nVin − Vo1
∆ILDTs
⇒ Lo1 ≥Vo1
∆ILTs ·
(1− nVo1
Vin
)≈ 6.43mH (2.38)
As this is a DC inductor, care has to be taken to keep the flux density low enoughnot to saturate the core. The candidate core materials are N87 from Epcos, 3F3 and3C96 from Ferroxcube with their saturation flux densities listed in table2.4.
Material N87 3F3 3C96Bsat [mT ] 400 450 500
Table 2.4: Saturation flux densities of N87, 3F3 and 3C96
An airgap is required in order to optimise the total volume of the inductor. Thisdoes not conflict with theAeAw approach as used in section2.4.2 for the maintransformer.
The output inductor for the15W terminal finally contains four windings,N6, N8,N7 andN9, with relationsN6 = N8 andN7 = N9. For design purposes, theprimary windings are combined into oneNp = 2N6. The same applies for the twosecondary windings. A turns rationz = Np
Nsof 20, according to section2.1.3, might
rise problems due to a resulting low number of secondary turns. Thusnz = 16 ischosen.
Calculating the rms currents leads to
Ip,rms ≈ Io1 = Po1Vo1
≈ 250mA
Is,rms = ∆Io1
2√
3≈ 14mA
(2.39)
and therefore suitable wire diameters are
dp = 0.3mm ⇒ Srms = 3.5ds = 0.1mm ⇒ Srms = 1.8
A
mm2(2.40)
The Srms for the secondary winding looks quite low. But the next thinner, in-house available wire has a diameter of0.063mm, leading to a current density of
18
4.5 Amm2 . Furthermore, the secondary winding consits only of a few turns, so its
wire diameter is not a primary concern.
Based on these data, it is possible to calculate theAeAw factor.
Ae ≥Lo1(Io1 + 1
2∆IL)NpBsat
(2.41)
AeAw ≥Lo1(Io1 + 1
2∆IL)Bsat
·
((dp
2
)2
+1nz
(ds
2
)2)
π
k(2.42)
≥ 716mm4 (2.43)
An EFD20 core using3F3 material seems to be a possible solution. It has anAe of31mm2. The airgap und the number of turns required to fit the design constraintsare given by
Np =Lo1Ip
BsatAe=
LIo1 +(
1nVin − Vo1
)DTs
BsatAe≈ 160 (2.44)
δ =N2
p µ0Ae
Lo1≈ 155µm (2.45)
TheEFD20-3F3-A250 core provides a machined160µm airgap. With anAL =250nH from the datasheet, theLp resulting from160 primary turns is6.4mH.
Table2.5shows the final choice for the number of turns per winding.
N6 N8 N7 N9 nz Lσe [µH]80 80 5 5 16 375
Table 2.5: Number of turns per winding on the output inductor
Extra Stray Inductor
As mentioned in section2.1.3, an additional inductor is required, increasing thesecondary winding’s stray inductance by the amount in (2.14). This inductor islabeledL5 in figure2.11. Low tolerances are required for good performance of the’zero’-ripple device. A core with an airgap suits thus better than one without.
The ER9.5/2.5/5-3F3-A160 is with 0.5cm3 the smallest ER core. It comeswith an SMD bobbin, has a70µm airgap and provides anAL of 160nH ± 8%.48 turns are necessary to obtain375µH as listed in table2.5. A wirediameterof 0.1mm leads to a28% filled winding window. The total losses of4mW arenegligible. The metal clamp provided for that core must not be used, because itbreaks the core. The core halves have to be taped or glued together.
19
Required Capacitors
33µF are chosen for capacitor7 C2. This is a tradeoff between size, price and goodripple suppression. The resulting voltage ripple atC2 is
∆VC2 =∆IL
4fpC2≈ 3.2mV (2.46)
The capacitor has an SMD package occupying1.2cm3. Due to the relatively highESR, it should be placed in parallel to a much smaller, ceramic chip capacitor.
Furthermore an output capacitorCo1 (fig 2.11) is necessary to prevent large voltageovershoots upon load disconnect. When the load is switched off at full power, theenergy stored inLo1 discharges intoCo1, causing a voltage rise∆Vo1.
∆Vo1 = −Vo1 +√
V 2o1 +
Lo1
Co1I2Lo1
(2.47)
For Co1 = 4.7µF this results in a1V , respectively1.7% overshoot, not includingthe latency of the control loop. This represents the additional voltage overshootoccuring after the gate drive is turned off.
Depending on the effectiveness of the ’zero’-ripple device,Co1 needs to be a lotlarger in order to further reduce the voltage ripple. As the ’zero’-ripple stray induc-tor can not get tuned exactly due to tolerances, there is always a certain ripple atthe output. Furthermore high frequency noise reaches the output terminal becauseof the non ideal behaviour of the ’zero’-ripple transformer. A10µF capacitor8
accounts for0.4cm3.
2.4.4 The 35W Output Stage
Choice of the Topology
It can be argued whether to implement the35W output inductor analogously tothe 15W output inductor or not. There are at least three possibilities. The useof one, single inductor, employing a balanced inductor with one winding on eachrail and designing a ’zero’-ripple device. All of these three topologies result inapproximately the same size for the inductor. The ’zero’-ripple approach needstwo relatively small additional components but it provides at least a fourth orderfilter or something better if correctly tuned.
During that time of the project, the ’zero’-ripple inductor of the15W output stageis already built and measured. To save time, the35W output inductor is not built.Instead, the measurements of the15W device are adjusted to obtain an equivalentcircuit for the35W output inductor.
7NIC NACEW330M100V10x10.5, 33µF , 100V , Distrelec part number8007628NIC NACEW100M100V6.3x8, 10µF , 100V , Distrelec part number800760
20
Inductor Design
The35W at 30V lead to a DC output current of1.2A. Limiting the current rippleto 20% of that value requires, according to (2.38), an inductor of at least750µH.
The minimal core factorAeAw calculates to1927mm4, using wire diameters of0.71mm and0.16mm for the ’zero’-ripple device’s primary and secondary wind-ings respectively. This applies for anEFD25 from Ferroxcube, featuring anAeAw
of 2262mm4. 3F3 is chosen as core material.
The complete inductor data as well as the data of the additional stray inductor islisted in tablesA.4, A.5 andA.7. The primary windings are namedL11,13, the twosecondary windingsL12,14.
Loss Considerations
The losses in the semiconductors are not calculated analytically. The necessarycurrent and voltage waveforms are recorded during the simulations done in orderto get data for the filter design process. The gathered data includes better approx-imations of the switching losses than would be obtained from analytical models.The conduction losses are easier to calculate without simulation. But due to thelow power and high voltages the switching losses dominate. So it does not makesense to neglect them. The calculations based on the simulations incorporate bothtypes of losses.
The criterium for the selection of the semiconductors is not the balance of switch-ing and conduction losses. They are chosen to be as small as possible. This leadsto an optimisation of the occupied volume instead of low losses. The choice ofsuitable components is very small. So the two different optimisation targets do notmake any big difference in the result.
21
2.5 Flyback Converters
2.5.1 Two-Switch Topology
A flyback converter, very common for auxiliary power supplies, is used as a bench-mark for the ’zero’-ripple enhanced forward converter. The flyback topology iskept as simple as possible. It does not make use of any special technique to reduceconducted emissions. This reduces the size of the converter itself but increases thevolume of the input and output filters required to get the same characteristic as theforward converter (s.2.4).
To limit the voltage stress on the switches toVin, a two-switch topology as shownin figure2.13is chosen. It does not need any clamping or lossy snubbing circuits.
L1
D3
Co
T1
T2
D2
D1
VoVin L2
Figure 2.13: Flyback converter used in topology evaluation
The device operates in discontinuous conduction mode to allow for a larger controlbandwidth. Furthermore it is expected that the discontinuous mode is worse thanthe continuous mode of operation regarding emitted EMI. Thus this topology op-erating with discontinuous magnetisation is the worst case scenario regarding thesize of the required filters for sufficient damping of the conducted emissions.
The initial design provides two electrically isolated outputs. One of two outputsprovides15W at60V , the other delivers35W at30V . Figure2.13shows only oneof the two output stages. Values corresponding to the primary winding are indexedwith 1, with 2 for the60V and with3 for the30V output winding.
2.5.2 Initial Design of the Main Inductor
The minimal input voltageVin,min is relevant for the maximum power the flybackcan deliver to its outputs at a given maximum duty cycleD1Ts.
Vin,min =√
6 · sin(
2π
6
)· 0.9 · VN ≈ 439V (2.48)
There are three conditions giving limits for the duty ratioD1, the turns ratiosn1i :=N1Ni
and the maximum primary winding inductance. Even though multiple outputinductors have as manyn1i as output stages, the degree of freedom is the same asthe one for the single output flyback, once the desired output voltages are fixed.
22
Energy Flow Condition
The conditionsV2 = 60V and V3 = 30V ask for n12n13
= V3V2
. It remains thequestion of the maximum permissiblen12. It is given by the condition that theoutput voltage transformed back to the input may not exceed the input voltage.Otherwise the energy stored in the inductor would go back to the input insteadof to the output. Relationship (2.49), well known from single output two-switchflybacks (fig2.13), applies unmodified for multiple output flybacks too. The reasonfor this is that the rate of change of the flux,B, is governed by the winding showingthe largest voltage to turns ratioVi
Ni.
Vin,min > n12V2 ⇒ n12 <Vin,min
V2≈ 7.3 (2.49)
Condition for Discontinuous Magnetisation
Another constraint has to be met for discontinous magnetisation. After magnetisa-tion duringD1Ts, the core must be able to completely demagnetise duringD2Ts.
D1 + D2
!≤ 1 (2.50)
(2.50) results for a single output flyback in the well known equation (2.51).
D1 ≤n12V2
n12V2 + Vin,minsingle output only! (2.51)
It is derived from the equality of the energy stored in the inductor at the end ofD1Ts (transistors on) and at the beginning ofD2Ts (transistors off). In the case ofone output, this equality results in a linear relationship betweenI2 and I1 whichultimately leads to (2.51).
12L1I
21 = E1
!= E2 =12L2I
22 ⇒ I2 = n12I1 (2.52)
I1 =Vin,min
L1D1Ts (2.53)
I2 =V2
L2D2Ts
insertn−→ I2
n12=
n12V2
n212L2
D2Ts
(2.52)=⇒ I1 =n12V2
L1D2Ts (2.54)
Setting (2.53) and (2.54) equal, and then substituting the result into (2.50) leads to(2.51).
Fork output windings, (2.52) becomes
E1!=
k∑i=2
Ei (2.55)
23
This way the linear result from (2.52) becomes non-linear. But obtainingD2 =f(D1) works still the same way. (2.55) for k = 3 results in
D2 =Vin,minD1√
n212V
22 + n2
13V23
(2.56)
Thus, for complete demagnetisation of the core,D1 has to meet the followingconstraint:
D1 ≤√
n212V
22 + n2
13V23√
n212V
22 + n2
13V23 + Vin,min
n12=2≈ 0.28 (2.57)
Considerations for n12
A largen12 allows for longer duty cycles, which reduces the switching frequencyharmonics. The high input voltage demands short duty cycles in order to obtain alow V s area, leading to a small core. This votes for a smalln12 too. But the peakcurrents increase with decreasingn12. Thus, as a tradeoff,n12 = 2 is chosen.
Power Transfer Condition on L1
Usingn = 2, the maximum duty cycle to stay in discontinuous mode is given by(2.57). This allows to calculate the maximum primary winding inductanceL1 fora given total input powerPin = 50W .
Pin
fs=
12L1I
21 (2.58)
I1 =Vin
L1D1Ts (2.59)
⇒ L1 ≤V 2
in,minD21
2Pinfs≈ 1.2mH (2.60)
The larger the chosenL1, the lower are the peak and rms currents in the inductor.For the rms currents, this influence is only of orderx
14 . L1 = 700µH is chosen for
this design. This decision is a trade-off between peak magnetisation, rms currents,core size and wire diameters.
Knowing L1, (2.58) and (2.59) can be used also to obtain the range ofD1 for avarying input voltage.
D1 =√
2PinL1fs ·1
Vin(2.61)
Vin ∈ [439 . . . 620] ⇒ D1 ∈ [0.21 . . . 0.15] at50W (2.62)
The next step is to calculate the primary and secondary rms currents in order tochoose suitable wire diameters. The rms input current is derived directly from the
24
peak input current. The rms output currents need to be derived via the mean outputcurrents, as there is a constant voltage load.
P2 =1Ts
∫ Ts
0V2i2(t)dt ⇒ I2 =
P2
V2(2.63)
I1,rms = I1 ·√
D13 ≈ 0.29A
I2,rms = P2V2· 2√
3D2≈ 0.39A
I3,rms = P3V3· 2√
3D2≈ 1.83A
(2.64)
d1 = 0.355mm ⇒ Srms = 2.9d2 = 0.355mm ⇒ Srms = 4.0d3 = 0.8mm ⇒ Srms = 3.6
A
mm2(2.65)
These data serve to calculate theAeAw factor as done for the forward converter insection2.4.2.
AeAw =VinD1
fsB·
((dp
2
)2
+1n
(ds1
2
)2
+12n
(ds2
2
)2)
π
k(2.66)
≈ 2094mm4∣∣ B = 200mT, k = 0.5
This leads to anEFD25 core with an SMD bobbin (AeAw = 2262mm4). The3C96 material is chosen due to its low losses. The required number of turns for anair gap of400µm areN1 = 65, N2 = 33 andN3 = 17, leading to a94% filledwinding window. The expected temperature increase due to core and copper lossesis less than70C.
2.5.3 First Redesign of the Main Inductor
At the beginning of the project, only one output winding of the flyback inductor isconsidered. It is wrongly assumed that multiple outputs with the same total load donot change the converter behaviour drastically. Later investigations show that thedemagnetisation time is reduced, allowing a larger duty ratioD1 for an increasednumber of output windings. The equations in section2.5.2are not the inital ones,they are modified to take multiple outputs into account. But they still neglect animportant detail.
Under the wrong assumptions, the designed main inductor seems to be capable totransfer only40W at 120kHz. Measurements (tab.A.9) discover the reason, thevery large primary winding stray inductance. The cause is the airgap in combina-tion with the vertical separation (figA.6) of the primary from the other windings.To allow the conversion of50W a redesign is necessary, taking into account thestray inductance.
A larger core, anEFD30 filling 11.8cm3, is required. Nevertheless the stray coef-ficients are assumed to stay about the same:
σx =Lxσ
Lxσ + LxMLx = Lxσ + LxM (2.67)
25
σ1 = 0.200 σ2 = 0.148 σ3 = 0.164 (2.68)
Next, the minimal main inductanceL1M required to deliver50W is calculated. Themaximum duty ratioD1,max is given by the discontinuous current condition (2.57).Taking the stray inductance into account changes (2.60) by the factor(1 − σ1),because only the main inductanceL1M contributes to the power transfer, but thewholeL1 limits the peak current for givenD1,maxTs andVin,min.
L1 ≤D2
1,maxV 2in,min (1− σ1)2fsPin
= 1mH (2.69)
This new maximum forL1 is still above the initially chosen700µH. But as theinfluence of multiple outputs is discovered after this redesign, a wrongD1 ≤ 0.21leads toL1 ≤ 567µH. Thus a newL1 = 550µH is used for the first redesign.This number is used in most simulations for the filter design. As the primary sidepeak currents are higher with a lowerL1, this does not reduce the size of the filters.As seen later on, the smallest possible ferrite cores are used anyway. So this choicehas only a positive influence on the filters.
(2.61) is modified in order to give a better estimation ofD1 than the initial approx-imation based onn, Vo andVin.
D1 =√
2PinL1fs
1− σ1· 1Vin
(2.70)
⇒ D1 ∈ [0.21 . . . 0.15] (2.71)
The formulae to calculate the rms currents in the windings are modified too. In caseof the primary winding, they have to consider that the current is not instantaneouslyswitched off. When the transistors are turned off, the stray inductanceL1σ drivesa current through the freewheeling diodes. This current ceases afterσ1D1Ts.
I1,rms = I1 ·√
(1 + σ1) D1
3
=Vin,min
L1· Ts ·
√(1 + σ1) D3
1
3(2.72)
≈ 405mA
Obviously this effect can not be seen at the output windings. Their rms currentsare calculated according to (2.64).
The rest of the redesign is done as for the initial design described in section2.5.2.The results are listed in appendixA.2.1.
26
The Output Capacitors
It does not really matter what output capacitors are used in the simulation. Thefilter design process takes the used values into account. The capacitors requiredat the35W output are calculated in a later design step.10µF at each of the twooutputs are used in the simulations. This is a very low value. It is large enough forcorrect operation and has only a low influence on the filter design process. Eventhough this value is considered then, it is preferred not to have a big impact.
27
Simulation
3.1 Design of the Control Loop for Simulation
3.1.1 Common Considerations
Purpose
In order to design small filters, the designed converters are simulated mostly with-out filters. This allows to calculate the minimal attenuation of the filters. The nec-essary controllers are developed using the loop shaping method. The result consistsof the controller’s transfer functions suitable for numerical implementation in thesimulations.
Disturbances
Both converter topologies feature two coupled output stages. Only one of whichis actively controlled. The other is only regulated due to their coupling. A thor-ough analysis of the voltage regulation would include the consideration of the loaddisturbance transfer functions from one output to the other.
Direct and coupled load disturbance issues are of minor importance for the filterdesign process as they influence frequencies way below of those relevant to theEMC filters. The controllers have to be redesigned once the filter characteristicsare known.
Input voltage disturbance supression is not looked at, because it is not relevant forthe filter design process.
3.1.2 Forward Converter
Control Mode
The control structure looks as in figure3.1. The output voltage is directly con-trolled by modification of the PWM duty cycle. No inner current control loopis used. To enhance the control quality regarding load disturbances, it might benecessary to design a current feed forward path or an inner current control loop.
Gvd+ Kr
Hm
Vref Vout
Figure 3.1: Forward converter’s minimal control structure
28
Converter Transfer Function Gvd
The duty cycle to output voltage transfer functionGvd is given by the impedanceof the controlled output stage. There is no dependence on the other output stagebecause the current in the output inductor is governed by the average voltage acrossit, which is in turn given by the output voltage, the input voltage, the transformerturns ratio and the duty cycle, which all do not depend on the load of the otheroutput stage. This simplification can only be used without input filter as it assumesa constant input voltage.
Gvd =Vo
D=
Vin
n13· 1LoCos2 + Lo
RLs + 1
(3.1)
(3.1) simplifies the ’zero’-ripple enhanced output stage into a second order lowpass consisting ofLo in series withCo in parallel with the load resistorRL. Thissimplification is valid because it can be proved that the response given byLo, Co
andRL really dominates the transfer functionGvd.
Depending on which output stage is to be controlled, the appropriate values forLo,Co andRL have to be substituted. Table3.1shows the appropriate assignments.
Output Vin n13 Lo Co RL
15W / 60V 538 3.2 6.4mH 10µF 240Ω35W / 30V 538 6.4 756µH 10µF 25.7Ω
Table 3.1: Values for the Parameters ofGvd
Controller Form
The critical point for control is the180 phase jump at the resonance frequency ofGvd. The resonance peak must stay below0dB. An integral part in the controllerlowers the phase by90. That makes it impossible to obtain a control loop witha crossover frequency above the resonance ofGvd. A lead-lag controller can notchange this fact. An integral controller is required to eliminate steady state errors.A pure integral part is used together with a low pass in series. The low pass allowsa higher cutoff frequency as it improves damping at the resonance ofGvd.
Loop Shaping
The35W output is controlled. Control has to be stable down to a minimal load of1W at the35W output. The resonance peak is damped by a low frequency polein the controller. But this reduces the available phase margin, resulting in a lowcrossover frequency.Kr with its pole at1.26krad
s allows for a crossover frequencyof 680 rad
s .
Kr =ωα
s· 1
sωp
+ 1
∣∣∣∣∣ ωα = 80rad
sωp = 1.26e3
rad
s(3.2)
29
The loop transfer function is calculated with
L = Kr ·Gvd ·Hm (3.3)
The biggest advantage of controlling the35W output is that the15W output doesnot need to be loaded for stable operation. There might be only a very low guar-anteed load at the15W output, but a minimal load at the35W output is almostassured.
10−2 10−1 100 101−100
−50
0
50
Gai
n dB
10−2 10−1 100 101−360
−270
−180
−90
Pha
se °
kHz
Figure 3.2: Forward converter’s voltage control loopL
3.1.3 Flyback Converter
Control Mode
Peak current mode control seems to be the easiest way to control a flyback con-verter, at least for resistive loads. Often it is assumed that the flyback inductorappears in that control mode as a controlled current source. In fact this is not ex-actly true. At a constant switching frequency and a given primary side peak currentit provides effectively a power source. The linearisation at a certain output voltageresults in a current source.
As the largest load steps are expected on the35W and not on the15W output, thefirst is controlled. The voltage of the latter follows due to magnetic coupling of thetwo outputs.
The control structure used for simulation is shown in figure3.3. The transfer func-tion from the reference peak current to the actual peak current is assumed to be1in the frequency range of interest. This simplification neglects the sampling effect.
30
Converter Transfer Function Gvi
The peak current control method reduces the inductor model to a power source.Its output power is determined by the switching frequency and the primary sidepeak current. Thus the simplified transfer function from the peak current to theoutput voltage consists mainly of the output filters. The filters of all outputs haveto be transformed to the same turns ratio and connected in parallel. In combinationwith the load resistors they form the output impedanceZ ′ as shown in the controlstructure (fig3.3). Ideal coupling between the output windings is assumed.
+ +Vref Kr Z’
Gv
Gi V’
Gvi
Figure 3.3: Control structure used to simulate the flyback con-verter
The power pushed into the output stages is given by
P =12
(1− σ1) L1I2fs (3.4)
It is related to the average currentI ′ flowing through the output filters. All filtersare transformed to the output stage beeing controlled and have thus the same outputvoltageV ′.
I ′ =P
V ′ (3.5)
⇒ I ′ =1
2V ′ (1− σ1) L1I2fs (3.6)
(3.6) is linearised inI andV ′.
I ′ ≈ I ′s + i′ =∂
∂II ′∣∣∣∣Is,V ′
s︸ ︷︷ ︸GI
· i +∂
∂V ′ I′∣∣∣∣Is,V ′
s︸ ︷︷ ︸GV
· v′ + I ′∣∣Is,V ′
s(3.7)
The third term in (3.7) represents the steady state average output current. Theparameters with indexs are steady state values, with exemption of the switchingfrequencyfs. The parametersi andv′ are their small signal portions.
GI =i′
i=
fsL1σ1Is
V ′s
(3.8)
GV =i′
v′= − fsL1σ1I
2s
2V ′2s
(3.9)
31
Transforming the output impedance of the60V output to the controlled30V outputand connecting it in parallel with the output impedance of the30V output resultsin Z ′ as follows.
gCo =(
1sCo
+ Resr
)−1
+1
n223
(1
sCo+ Resr
)−1
=(
1sCo
+ Resr
)−1(1 +
1n23
)(3.10)
This is valid for two equal output capacitorsCo.
Z ′ =[gCo +
1RL3
+1
n223RL2
]−1
(3.11)
The power conversion transfer functionGvi from the primary side peak currentito the output voltagev′ is given, according to figure3.3, by
Gvi =v′
i= GI ·
Z ′
1− Z ′GV(3.12)
Table3.2shows the values used inGvi. The load resistors are varied to verify thecontrol loop with different loads.
n23 Co Resr RL2 RL3 V ′s Is L1 σ1
2 10µF 10mΩ 240Ω 25.7Ω 30V 1.42A 550µH 0.25
Table 3.2: Values for the Parameters ofGvi
Controller Form
The phase ofGvi decreases from0 to −90 already at low frequencies. A con-troller with an integral part to eliminate steady state errors lowers the phase byanother90 at any frequency. It makes thus sense to leverage the phase in certainfrequency ranges by using a lead-lag controller. It allows to compensate the lowfrequency zero. The minimal load for stable operation can be increased that way.
The simulation uses a purely mathematical controller. The realisation in hardwarehas a slightly different structure anyway. The equation for the controllerKr is
Kr =ωα
s·
sωz
+ 1s
ωp+ 1
(3.13)
Loop Shaping
The crossover frequencyωco of the control loopL is chosen to be4kHz at full load.
L = KrGvi (3.14)
32
The controller’s zeroωz is placed at50rad/s to compensate for the pole at lowloads. Settingωp to 3 · ωco leaves an appropriate phase margin.
A bodeplot of the resulting loop transfer function is shown in figure3.4.
10−3 10−2 10−1 100 101 102−100
−50
0
50
100
Gai
n dB
10−3 10−2 10−1 100 101 102
−180
−150
−120
−90
−45
0
Pha
se °
kHz
15+35 W1+1 W
Figure 3.4: Bodeplot of the flyback’s loop transfer functionL
The following controller, enhanced by an anti wind-up, is used in the simulations.
Kr =1.695 s + 84.741.326e-5 s + 1
· 1s
(3.15)
3.1.4 Control Related Topology Comparison
The lowest harmonic of the converter’s input voltage is300Hz. Good regulation ofthe output voltage requires thus active control at frequencies above≈ 3kHz. Thisbandwith is limited by the resonant frequencies of the filters. Appropriate damp-ing of the filters reduces the problem. But the barely damped output stage of theforward converter imposes severe restrictions. Its nature requires it to be a secondorder circuit with a low resonant frequency. The flyback converter, if peak currentmode control is used, shows a first order behaviour in the relevant frequency range.It allows higher cutoff frequencies in the voltage control loop as the phase of thecontrol to output transfer function changes only by90 instead of180. It should bepossible to work around the low frequency zero of the forward converter by usingpeak current mode control too. But for the simulation of common and differentialmode noise the regulation quality of the output voltage is not very important.
A second, more thorough controller design targeted at realisation in hardware hasto take care about the input and output filters. In case of peak current mode control,the sampling effect has to be considered.
33
3.2 Equivalent Circuits of Magnetic Components
3.2.1 General Approach
The accurate simulation of common and differential mode noise between150kHzand30MHz requires equivalent circuits of the most important inductors. Thesecircuits have to reproduce the behaviour of the inductors in the relevant frequencyrange. Thus main and stray inductances as well as the coupling of the windingshave to be considered. The equivalent circuit needs to model the copper losses,the core losses and the capacitive parasitics also. The losses are best modeled byresistors in series and parallel to a winding. The capacitive behaviour is representedby a capacitor parallel to a winding.
It remains the question where to place these elements. Do they need to appearin each winding or is it sufficient to place them at the primary side? The strayinductance of a two winding transformer can be placed on either side. Multiplewindings and known turns ratios allow to measure a distinctive stray inductancefor each winding. It is obvious that each winding has its own copper losses andthus the equivalent circuit requires a series resistor per winding. The placement ofthe parasitic capacitors is not that obvious. A capacitor in one winding influencesthe impedance of the others via magnetic coupling. Impedance measurements inthe range from100Hz to 100MHz show multiple resonant peaks. This supportsthe physical interpretation that each winding should have a parasitic capacitance.These considerations result in an equivalent circuit for each winding as shown infigure3.5.
Figure 3.5: Simple equivalent circuit of a transformer winding
In realitiy the parasitic capacitance, the stray and the main inductance are dis-tributed across each other. It is not possible to model this with a limited numberof ideal components. But to get a bit closer to this fact, the parasitic capacitanceand the core and copper losses can be split in two parts. This gives the equivalentcircuit per winding used for simulation of the flyback and forward converter’s maininductors (fig3.6). As shown later, the simulation model of the forward converter’soutput inductors uses a slightly different equivalent circuit.
Knowing the equivalent circuit, measurements have to be defined to obtain therequired parameters. Theoretically it should be possible to write down as manyequations as parameters. Then it must be possible to calculate the parameters basedon an equal number of measurements. In practice this approach is not promisingdue to the complexity of the equivalent circuits. Remember thati windings as theone shown in figure3.6are magnetically coupled. The parameters are obtained inmultiple steps.
34
C11R13
R12
L1
L12
C12
R14
R11
Figure 3.6: Equivalent circuit of a transformer winding
The first step allows to compute the stray and main inductance of each windingas well as their coupling factors. Only the copper loss resistors and the inductorsof the equivalent circuit are considered in this step. Measurements are taken atfrequencies where the influence of the other components is minimal.
The second step is the measurement of the parasitic capacitance. The impedanceamplitude of each winding is measured at a frequency where its phase is as closeto −90 as possible. The pins of the other windings are unconnected and theirparasitics are neglected.
The parameters obtained so far are put into a frequency domain model in matlab.The measured impedance is plotted in the same graph as the impedance of themodel. The parasitic capacitors are adjusted to get a best overall match of theresonance peaks across all measurements. The core loss resistors are adjusted todampen these peaks until the impedance curve of the model approximately matchesthe measured one. From a physical point of view, the core loss resistor should existonly once, in the equivalent circuit of the magnetising winding. But distributing itacross all windings seems to give better results.
At the end, the inter-winding capacitances are measured.12 i(i− 1) measurements
combined with as many equations result in the values for the same number ofcapacitors. In the case ofi = 3 capacitors, one capacitance might become negative.
3.2.2 The Main Transformers
The Forward Converter’s Main Transformer as an Example
As described above, the first step requires a simplified equivalent circuit. Figure3.7 shows such a circuit for two winding measurements. Transformers with mul-tiple windings are treated as two winding transformers by considering only twowindings per measurement.
Lsig1 Lsig2
L1M
ideal, n:1
Figure 3.7: Simplified two winding transformer equivalent circuitfor inductance measurements
35
The forward converter’s main transformer, as defined in appendixA.1.1, shall serveas an example. Seven measurements are carried out to determine the main induc-tanceL1M , which is ideally coupled to the other windings, the stray coefficientσi
for each windingi = 1 . . . 4 and the turns ratiosn1i for i = 2 . . . 4. Seven measure-ments and eight parameters leave one degree of freedom. But as the turns ratiosshould be known, an overdetermined system is obtained. Recalculating the turnsratios might reveal deviations from the real turns ratios. The reason is that the cho-sen model is just an approximation. The best parametrisation of this model, pro-viding nearly the same curves as measured, might need parameters that make onlysense in a mathematical manner. Negative stray inductances are the most commonsymptoms for the discussed model. But it is possible to make all of them positiveby minor adjustments on the turns ration12, chosen to be the degree of freedom.This way, a physically meaningful parametrisation of the simulation model is ob-tained.
measured shorted LZmeas
winding winding
1 - A = 115.5 mH
1 2 B = 128.8 µH
2 - C = 119.1 mH
3 1 D = 12.00 mH
3 - E = 70.26 µH
4 1 F = 3.126 mH
4 - G = 33.27 µH
Table 3.3: Measurements carried out to determine the inductivebehaviour of the forward converter’s main transformer
Table3.3shows the results of the seven measurements. To simplify the equations,some parameters are substituted and some relationships are given for clarity.
Li = LiM + Lσi with stray inductance Lσi = σiLi (3.16)
To expressLσi based onLiM , the parameterδi is defined as
δi =σi
1− σi⇒ σi =
δi
1 + δi⇒ Lσi = δiLiM = σiLi (3.17)
36
The seven equations leading to the yet unknown parameters follow.
A = L1M · (1 + σ1) (3.18)
B = L1M ·(
σ1 +σ3
1 + σ3
)(3.19)
C =L1M
n212
· (1 + σ2) (3.20)
D =L1M
n213
· (1 + σ3) (3.21)
E =L1M
n213
·(
σ3 +σ1
1 + σ1
)(3.22)
F =L1M
n214
· (1 + σ3) (3.23)
G =L1M
n214
·(
σ4 +σ1
1 + σ1
)(3.24)
The combination of the formulae for measurementsA, B andC gives
L1M =√
n212C(A−B) (3.25)
δ1 =A
L1M− 1 (3.26)
δ2 =L1M
A−B− 1 (3.27)
n12 = 1 is a design parameter. But with the measurement results this leads to somenegativeδi. A range ofn12 resulting in positiveδi, (3.30), is thus calculated.
δ1 ≥ 0 ⇒ n212 ≤
A2
C(A−B)(3.28)
δ2 ≥ 0 ⇒ n212 ≥
A−B
C(3.29)
A−B
C︸ ︷︷ ︸0.96869
≤ n212 ≤ A2
C(A−B)︸ ︷︷ ︸0.97086
(3.30)
n12 = 0.985 is chosen to fit this requirement for positiveδi. The deviation fromthe expectedn12 = 1 is due to measurement inaccuracies and a simplified model.Based on this value, the remaining parameters are calculated. Equations for mea-surementsD andE lead ton13 andδ3.
n13 =√
L1M
D − E· 11 + δ1
(3.31)
δ3 =D
L1Mn2
13 − 1 (3.32)
37
If the resultingδ3 is negative, it can also be shifted into a positive region by adjust-ing n12 according to
n12 ≥A√
C(A−B)· D − E
D∨ D > E (3.33)
The additional conditionD > E is always fulfilled. Furthermore the argumentof the square root is guaranteed to be positive. The reason for both is that theinductance of a winding is always higher when the other windings are open thanwhen one or more of them are shorted.
MeasurementsF andG analogously equate ton14 andδ4 with a condition onn12
to get a positiveδ4.
n14 =√
L1M
F −G· 11 + δ1
(3.34)
δ4 =F
L1Mn2
14 − 1 (3.35)
n12 ≥ A√C(A−B)
· F −G
F∨ F > G (3.36)
For all performed measurements it is possible to find an12 fulfilling ( 3.30), (3.33)and (3.36) at once. A correctly built and measured transformer should result innij
near their theoretical values. This should also result in positive stray inductances.The stray coefficientsσi are calculated according to (3.17). The results for theforward converter’s main transformer are provided in table3.4.
parameter result
L1M 115.46mH
n12 0.985n13 3.111n14 6.109σ1 3.250e-4σ2 7.904e-4σ3 5.532e-3σ4 1.032e-2
Table 3.4: Stray coefficients and turns ratios for the forward con-verter’s main transformer
The winding series resistances and the inter-winding capacitances can be directlymeasured. The latter is reduced from four to three parameters by treating the twoprimary windings1 and2 as one winding. For the design of the common modefilter this gives no disadvantage beyond the inaccuracies of the used model itself.The parasitic winding capacitances are determined as described in the previoussection. TableA.2 shows the results.
The impedance plots generated in matlab to line up the impedance of the modelwith the measured one are shown on page39.
38
102 103 104 105 106 107 10820
50
80
110
140
dBΩ
75.9kHz
30MHzz(p)par
model
measured
102 103 104 105 106 107 108
−90
−45
0
45
90
degr
ees
f [Hz]
−19°
102 103 104 105 106 107 10810
40
70
100
dBΩ
4.2MHz 30MHz
z(p)par
model
measured
102 103 104 105 106 107 108
−90
−45
0
45
90
degr
ees
f [Hz]
−19°
Figure 3.8: Impedance curves of the forward converter’s maintransformer: primary side (windings1 + 2) impedance with otherwindings open (left) and shorted (right)
102 103 104 105 106 107 10810
40
70
100
dBΩ
75.9kHz 30MHz
z(s1) model
measured
102 103 104 105 106 107 108
−90
−45
0
45
90
degr
ees
f [Hz]
102 103 104 105 106 107 108−10
20
50
80
dBΩ
692kHz 30MHz
z(s1) model
measured
102 103 104 105 106 107 108
−90
−45
0
45
90
degr
ees
f [Hz]
Figure 3.9: Impedance curves of the forward converter’s maintransformer: winding3 impedance with other windings open (left)and shorted (right)
102 103 104 105 106 107 1080
30
60
90
dBΩ
75.9kHz 30MHz
z(s2) model
measured
102 103 104 105 106 107 108
−90
−45
0
45
90
degr
ees
f [Hz]
102 103 104 105 106 107 108−20
10
40
70
dBΩ
912kHz 30MHz
z(s2) model
measured
102 103 104 105 106 107 108
−90
−45
0
45
90
degr
ees
f [Hz]
Figure 3.10: Impedance curves of the forward converter’s maintransformer: winding4 impedance with other windings open (left)and shorted (right)
39
102 103 104 105 106 107 108−20
10
40
70
100
dBΩ
1.6MHz
30MHz
z(p) model
measured
102 103 104 105 106 107 108
−90
−45
0
45
90
degr
ees
f [Hz]
13°
102 103 104 105 106 107 108−20
10
40
70
100
dBΩ
3.8MHz
30MHz
z(p) model
measured
102 103 104 105 106 107 108
−90
−45
0
45
90
degr
ees
f [Hz]
Figure 3.11: Impedance curves of the flyback converter’s maininductor: primary side (winding1) impedance with other windingsopen (left) and shorted (right)
102 103 104 105 106 107 108−20
10
40
70
100
dBΩ
1.6MHz
30MHz
z(s1) model
measured
102 103 104 105 106 107 108
−90
−45
0
45
90
degr
ees
f [Hz]
71°
102 103 104 105 106 107 108−20
10
40
70
100
dBΩ
18MHz
30MHz
z(s1) model
measured
102 103 104 105 106 107 108
−90
−45
0
45
90
degr
ees
f [Hz]
Figure 3.12: Impedance curves of the flyback converter’s maininductor: winding2 impedance with other windings open (left)and shorted (right)
102 103 104 105 106 107 108−40
−10
20
50
80
dBΩ
1.5MHz
30MHz
z(s2) model
measured
102 103 104 105 106 107 108
−90
−45
0
45
90
degr
ees
f [Hz]
72°
102 103 104 105 106 107 108−40
−10
20
50
80
dBΩ
30MHz
z(s2) model
measured
102 103 104 105 106 107 108
−90
−45
0
45
90
degr
ees
f [Hz]
Figure 3.13: Impedance curves of the flyback converter’s maininductor: winding3 impedance with other windings open (left)and shorted (right)
40
Adaptations for the Flyback Converter’s Main Inductor
The parametrisation of the flyback converter’s main inductor equivalent circuit isdone exactly the same way as for the forward converter’s main transformer, exceptthat there are only three windings. Thus measurementsF , G and their accord-ing equations are omitted. The results for several different designs are listed inappendixA.2. The impedance plots for the initial design are shown on page40.
Observations
There are good reasons for the differences between the mathematical models andthe impedance measurements on pages39and40.
Many of the HF resonances are due to self-resonances of the ferrite cores. Theused equivalent circuits are not capable of reproducing these effects.
The non-linear behaviour of the magnetic material changes with frequency andmagnetic field. Non-linear inductances and losses are difficult to model with linear,conservative circuits.
3.2.3 The Forward Converter’s ’zero’-Ripple Inductors
The ’zero’-ripple transformers can be treated as normal four-winding transformers.So the same procedure as used for the main inductors is employed here too inorder to obtain the inductances and stray coefficients. The equivalent circuit for thesimulation (fig3.14) is a bit different. It is adapted to the use as a filter inductor.The parasitic capacitances are measured directly. In comparison to the previousequivalent circuits, the current one neglects the core losses. The small currentripple keeps them low enough. Additionally the circuit does not feature any copperloss resistors for the two secondary windings. Their very short wire lengths makesthe according resistors neglectable.
R51
R11
R21
L11 L1
L31 L3
L41 L4
L21 L2
C034
C013
C024
C11
C21
C2
C51
L5
Co
L6-9
L5
k=1
Figure 3.14: Forward converter’s ’zero’-ripple inductor equivalentcircuit (the orange marks indicate the equivalent components offigure2.11)
The inductor at the15W output is built and measured. The values for the35Woutput are derived from the former without actually building the device. The circuitparameters for both devices are listed in appendixA.1.2.
41
3.3 Simulation Models of other Parts
3.3.1 Semiconductors
The currents through the semiconductors as well as their voltage stresses are cal-culated. Most results are already available from the design of the inductors. Thecalculations are verified using standard diode and MOSFET models delivered withSimplorer. Using the simulation data it is possible to get approximate values forthe conduction and switching losses in the semiconductors. Suitable devices areselected based on these values. The chosen devices for the flyback converter arelisted in appendixC.4. The same diodes and transistors are used for the forwardconverter. Of course this selection involves also the verification of the thermalstress. An ambient temperature of50C is assumed. The devices are pushed totheir limits because it allows to use very small packages.D-PAK andDO-214AA
provide much smaller footprints thanD2-PAK and larger packages not available inSMD versions. The use of SMD packages is mandatory to reduce the total boardsize. Accepting THT packages would more or less prevent devices beeing placedon opposite board sides.
Unfortunately, of the chosen semiconductors, there is only a Simplorer simulationmodel for theUS1M. Due to the necessary effort, the development of VHDL AMSmodels for the other semiconductors is out of discussion. So similar devices arechosen which asimulation model1 is available for.
The rectifier and output diodes are replaced by theUS1Mmodel. The real outputdiodes result in lower losses than theUS1M. Thus there is a safety margin. Thesame applies for the two MOSFETS represented by a model of theIRFBF20S .
3.3.2 Peak Current Mode Controller
A comparator, an RS-flipflop and a clock source are required to build a peak cur-rent mode controller in hardware. For all these elements there is a simulation modelavailable in Simplorer. But multiple conversions between the digital and contin-uous domain complicate the construction. It is more simple to write a VHDLAMS model and load this into Simplorer. Even though Simplorer should recogniseVHDL generics and provide a GUI to set them, it confuses the units. As a shortworkaround they are hardcoded. Interestingly Simplorer seems to have no prob-lems if multiplePROCESSblocks write to the same signal. In hardware this wouldnot be possible, but in a software simulation there is no reason against it as longas not many processes write to the same signal during one simulation step. In thatcase, the final value would be undefined.
LIBRARY ieee;LIBRARY std;LIBRARY basic_vhdlams;USE std.standard.ALL;USE ieee.std_logic_1164.ALL;USE ieee.math_real.ALL;
1http://model.simplorer.com/
42
USE basic_vhdlams.ALL;
ENTITY pmc ISPORT (
-- peak mode controlled PWM output signal:QUANTITY pwm : OUT real;
-- peak reference:QUANTITY refpk : IN real := 0.0;
-- current value of control target:QUANTITY meas : IN real := 0.0
);END ENTITY pmc;
ARCHITECTURE behav OF pmc ISSIGNAL active : boolean := false;SIGNAL srefpk, smeas : real := 0.0;
BEGIN-- set pwm outputif active use
pwm == 1.0;else
pwm == 0.0;end use;
-- QUANTITIES must be sampled into signals-- to get the attention of a PROCESS.-- This is the necessary discretisation step.-- Without a process we can neither clock nor latch.PROCESS BEGIN
loopsrefpk <= refpk;smeas <= meas;wait for 10 ns; -- causes controller delay
end loop;END PROCESS;
clock : PROCESSBEGIN
LOOPactive <= true; -- activate comparator / latch-- wait for the rest of the control period.-- 120 kHz, GENERIC would be preferred...WAIT FOR 8333.333333333 ns;
END LOOP;END PROCESS clock;
latch : PROCESS (active, srefpk, smeas)BEGIN
if active and ( srefpk <= smeas ) then-- cause gate drive output to go lowactive <= false;
end if;END PROCESS latch;
END ARCHITECTURE behav;
43
3.4 Harvesting Data for the Filter Design Process
3.4.1 Obtaining Suitable Simulation Parameters
Choosing the Step Time Tt
The main consideration for the determination of the maximumTt is the slope ofthe switching transients. Even though there are FFT algorithms that transform anumber of samples not beeing a power of two, it is more convenient to work witha power of two. Furthermore the simulation’s output signals that are not band lim-ited. To reduce the influence of aliasing artefacts at frequencies below30MHz, thesimulation shall provide information at much higher frequencies than60MHz. 223
samples are chosen for a simulation duration of20ms, one line period. This resultsin Tt = 2.384185791ns. It seems Simplorer is not able to do the computation ofTt itself. This number has to be entered directly for correct behaviour with a forcedconstant step time.
The simulation output data has to be limited to a total size of less than2GB. Oth-erwise Simplorer 7 might truncate the data. This gives severe limitations on theamount of output channels recorded during one simulation run. It seems that An-soft has not implemented large file support for the simulation data base (.ddb files)backend. This is required for random access to files larger than2GB on several32bit operating systems.
Required Simulation Duration
The CISPR 22 Class A limits impose restrictions on the spectral emissions between150kHz and 30MHz. They require a measurement bandwidth offbw = 9kHzand a measurement point everyfd = 4kHz in that range. Notice that these binsoverlap. Calculating the necessary simulation duration to get a frequency sampleevery4kHz would result in the wrong measurement bandwidth and a sample every9kHz is not correct either. A discrete fourier transform alone, such as the FFT, doesnot provide the required measurement based on simulation data. No matter whatsimulation and step duration is used.
The overlapfov of the required measurements is
fov = fbw − fd = 5kHz (3.37)
The greatest common divisor offov andfd is fk,max = 1kHz. This is the maximaldistance between two samples in frequency domain allowing the calculation of therequired spectrum. This is done by just summing up the correct frequency samplesto form one new sample every4kHz.
With l as the number of samples, the distance of the frequency samples is given by
ft =1Tt
=⇒Nyquist th. fmax =
ft
2(3.38)
fk =ft
l(3.39)
44
The minimal simulation duration is
Tmin = lmin · Tt =ft
fk,max· Tt = 1ms (3.40)
Care has to be taken to eliminate discontinuities in the first derivative of the50Hzline oscillation. This can be accomplished by adding an appropriate sine signal tothe simulation results or by using the supply symmetry. Omitting this fakes thesimulation results because the FFT assumes a true periodic signal. Adding a50Hzsine signal to the simulation results does not influence the filter design process,because the50Hz component is not of interest in this case.
To sort out eventual transients, the first several milliseconds are not used. For easiercancellation of the50Hz line component, the simulation duration is chosen to be20ms, one line period, but only the last10ms are taken for evaluation. This resultsin fk = 100Hz, much less than necessary. Anfmax of 210MHz leaves a largemargin towards aliasing problems.
The Simplorer output data consists of8 byte samples. This allows to log about30channels during a10ms long simulation.
3.4.2 Importing the Data into Matlab
Matlab is chosen to compute the conducted common and differential mode noisebased on the simulation data. There are various ways to import Simplorer data intoMatlab. The difficulty is that Simplorer outputs the data in row major format andMatlab needs its binary files in column major format. Saving the simulation datain some ASCII format and writing a matlab script reading those files is out of dis-cussion. This format is not suitable at all for large amounts of data. Thus a simple,console based application is written in C++ which converts binary Simplorer.mdx
files to binary Matlab.mat files. In order to perform the matrix transform fromrow major to column major format, the whole data is loaded into memory. Theprogrammdx2mat can read ASCII formatted and binary 8 byte double Simplorer.mdx files as generated by the DAY Postprocessor of the View Tool.mdx2mat
writes uncompressed version 6 Matlab files containing one matrix of data namedsimres . These files can also be read by Matlab 7.
The program, including its source code, can be found athttp://srf.ch/. It compilesunder Linux with g++, theGNU C++ compiler2, 3.4 and similar versions. A Win-dows executable can be compiled usingMinGW3 and its accompanying packages.It is written for IA324 compatible platforms. Portability is not an issue becauseSimplorer is limited to such systems.
2http://gcc.gnu.org/3http://www.mingw.org/4x86 32 bit, such as: i386, i486, i586, any Pentium, AMD Athlon based systems,. . .
45
Filter Design
4.1 General Approach
The EMC limit for conducted noise relevant for this project is that of theCISPR1
22 Class A regulation. Most required measurement characteristics are described insection3.4.1. The measurement signal, which the noise spectrum is derived from,is the voltageVL1−3 across the LISN resistorsRL1−3 (fig 4.1). Between150kHzand500kHz, the noise spectrum must be below78dBµV . It must be lower than72dBµV in the range from500kHz to 30MHz. Simulation of the noise spectrumcorresponds to quasi peak measurement. So the curves for quasi peak detectionhave to be taken.
LL50u
CL250n
RL50R
VRL,i
Figure 4.1: Simplified three-phase LISN with supply
The conducted noise can be split into three classes, that is to say common mode(CM), differential mode (DM) and mixed mode (MM) noise [11]. CM currents aresymmetric and flow in all supply phases in the same direction. The CM currentloop is closed via protective earth (PE). The pure DM currents are symmetric toobut in such a manner that the sum of the DM currents in each phase is zero. TheMM curents is what remains. They are asymmetric and close their loop via PE.They are caused by the switched drain to source capacitanceCds of the MOSFETin combination with the capacitanceCCPE between the MOSFET’s case and PE.A simplified schematic neglectingCCPE suggests, thatCds gets charged and dis-charged by a symmetric current through the DC rails of the rectifier. This wouldcause a pure DM current in two of the three phases. But there is a third path(fig 4.2) to the supply via PE due toCCPE and the inter-winding capacitance ofthe main inductor. The inductor, not using any special methods, forms an unbal-anced impedance in the DM current path forcing an asymmetric current in the DCrails to the rectifier, because a part of theCds charge and discharge current flowsvia PE. The three current paths, via positive rail, negative rail and PE, can also beseen as a complex current divider with three different impedances.
The filter design process is split into two steps. First a CM filter is designed. Ithas to attenuate the pure CM noise to a maximum of6dB less than the CISPRlimit. Then a filter is designed to bring the combination of MM and DM noise toat least6dB below the limit. The6dB margin ensures that the sum of all noise
1http://www.iec.ch/
46
LLCL
RL
Ccpe
MM current
Figure 4.2: Path of mixed mode currents
classes complies with the limit. Even though MM noise has more similarities withCM than with DM noise, it is easier to pair it with DM noise in order to design thefilters.
Vcm =13
3∑i=1
VRLi(4.1)
Vmd = VRLi− Vcm ← MM and DM noise together (4.2)
The stray inductance of the CM filter is very helpful for the DM filter. If it is largeenough, there is no need for an additional inductor. A capacitor in combinationwith the stray inductance provides a second order filter. Furthermore, MM noise isattenuated by the full CM filter inductance, not only by the stray inductance. Thusthe CM filter needs to be integrated in the simulation used to design the DM andMM filter.
The filter design process does not distinguish between DM and MM noise. Justthe sum of them is taken into account. But there are filter topologies which dampthe DM noise very well but might even increase the MM noise. An inductor in thepositive rail, where the main inductor lies, without corresponding balancing part inthe negative rail, which the MOSFET is connected to, is such an example.
4.2 Common Mode Input Filters
4.2.1 Obtaining the Noise Spectrum
The procedure to obtain the noise spectrum is for both converters, the flyback andthe forward, exactly identical. Simulations provide the voltagesVRLi
across thethree LISN resistors. Formula (4.1), an FFT and the summation as described insection3.4.1lead to the desired spectrum. The result of thefft( . . .) function inMatlab has to be modified to get useful values. This is done by the wrapper functionfftsrf( . . .) . The employed Matlab scripts can be found on the accompanyingdisc or athttp://srf.ch/eth/da/.
47
106 10760
70
80
90
100
110
120
130
Hz
dBµV
Figure 4.3: CISPR 22 Class A limit and unfiltered CM noise be-tween150kHz and30MHz at the input of the flyback converter
Figure4.3 shows the CM noise at the input of the flyback converter without thefinal filters. Figure4.4 is the same for the forward converter. The similaritiesbetween the two spectra suggest that the final filters have about the same volume.The negative rails of both converter outputs are connected to PE, the worst casescenario.
106 10760
70
80
90
100
110
120
130
Hz
dBµV
Figure 4.4: CISPR 22 Class A limit and unfiltered CM noise be-tween150kHz and30MHz at the input of the forward converter
The difference between the limit and the noise curve plus6dB shows directly thenecessary minimal filter attenuation.
4.2.2 Filter Topology
Is it possible to get a sufficient attenuation with only one filter stage consistingof a CM inductor and capacitors to PE? That is the main question regarding aminiaturisation of the filter volume. Linear inductor models approve it. But amore accurate, non-linear model of the inductor shows that a fourth order filteris required. The higher the inductance of the CM coil, the higher is its parasiticcapacitance. The capacitance of the Y capacitors is very limited for two reasons.
48
The earth leakage current has to be limited for safety reasons. Furthermore highcapacitances result in very voluminous packages because Y capacitors must beable to suffer high voltage spikes without braking. Due to the low capacitancesone has to work mainly with the filter’s inductors. The attenuation of a secondorder filter shows a parasitic zero about one to two decades above its pole. Thusthe attenuation at high frequencies is too low. This behaviour is illustrated in figure4.5by the gray, dashed line.
106 107
−60
−50
−40
−30
−20
−10
0
Hz
dB
minimal attenuation2nd order filter4th order filter
Figure 4.5: Minimal required relative CM filter attenuation for theflyback converter, including the6dB margin; higher attenuationmeans lessdB
The next question is how the two filter stages are placed. Capacitors on the inputside of the rectifier have to be of Y or X2 type and have thus a low value or verylarge volume. But a filter there attenuates noise produced by the switching ofthe rectifier diodes. In this case, no heatsink is used. Thus CM noise originatingfrom the rectifier is very low. But any inductor on the input side of the rectifierprovides an additional protection against line voltage spikes and helps to attenuateMM currents. It enhances the effectiveness of the protection varistors. So at leastone of the two stages should be placed on the input side. The inductor there needsthree windings, whereas the DC side CM filter inductor needs only two windings.As single layer windings are preferred due to their low parasitic capacitance, ahigher inductance on the same core can be attained on the two-phase DC side thanon the three-phase input side. Thus the stage providing poles at lower frequency isput on the DC side and the stage with poles at higher frequency is placed before therectifier. This filter structure, common for flyback and forward converter, is shownin figure4.6.
4.2.3 Dimensioning the Inductors and Capacitors
In order to keep the line frequency currents to PE small, the CM filter capacitorsmust be of low value. There are SMD Y capacitors with up to4.7nF produced bymuRata. The first filter stage on the DC side of the rectifier requires two capacitorsin parallel, the second stage needs three of them. Thus the chosen2.2nF percapacitor is already quite a high value.
The toroidal ferrite coreT60006-L2009-W914 from Vacuumschmelze is the small-
49
L1C1
L2 C2
stage 1 stage 2
Figure 4.6: CM filter structure, common for flyback and forwardconverter
est suitable core consisting of their high permeability materialVITROPERM 500
F. The small CM currents and needs for high inductances ask for such a material,which provides high attenuation, good damping, stable operation at high tempera-tures and very high saturation, thus allowing for compact CM chokes. Because thismaterial is highly non-linear even at relatively low frequencies, an accurate, non-linear model of the final inductor is required. An existing Mathcad model (app.B)for the same core family is taken and modified to represent the chosen core. Theinductance in dependance of the frequency is calculated for each inductor and ex-ported to Matlab files. The filter design scripts load these files and calculate thefilter attenuation based on these inductor values. Iteratively adjusting the numberof turns leads to the final filter components. The red line in figure4.5 shows theresult for the flyback converter.
To obtain the attenuation formulae, the filter is converted to its single-phase equiv-alent circuit (fig4.7). Then it is treated as a complex current divider in frequencydomain.
LL /3
L1 L2
3 CL 3 C1 2 C2
RL /3
Resr /3 Resr /2
Io
Ii
ZL ZB ZAZC ZD
Figure 4.7: Single-phase equivalent circuit of the CM filter, in-cluding the LISN
The formulae for the filter attenuationAF use the component naming of figure4.7.Resr = 5mΩ is the equivalent series resistance of the capacitors.ZL is the LISNimpedance. Above150kHz it can be approximated by three50Ω resistors. Insteadof using the linear impedanceZLi = sLi of the inductors, the complex, non-linearimpedance ofL1 andL2 is imported from the Mathcad model (app.B).
prerequisites: AF :=Io
Iis := iω (4.3)
50
ZL ≈ 50Ω3
∀ ω ≥ 2π · 150kHz (4.4)
ZA =12
(1
sC2+ Resr
)(4.5)
ZB =13
(1
sC1+ Resr
)(4.6)
ZC = ZL + sL1 +13R1 (4.7)
ZD = sL2 +12R2 +
ZBZC
ZB + ZC(4.8)
AF =ZA
ZA + ZD· ZB
ZB + ZC(4.9)
4.2.4 Verification
The filter design process shows that both converters need the same volume for theirfilter. Fourth order filters are required, each consisting of twoT60006-L2009-W914
cores and five SMD ceramic chip capacitors with2220 footprints.
Verification of the filter by simulation needs some effort. A non-linear time domainmodel is required. The used Mathcad model is in frequency domain, where alsothe whole filter is developed. The development and verification of an accurate timedomain model goes beyond the scope of this project. The filter is experimentallyverified during the converter’s assembly, test runs and EMC measurements.
4.3 Differential Mode Input Filters
4.3.1 Development Time Considerations
The stray inductance of the CM filter can be used for the DM filter to reduce itssize. The only prolem is that the CM filter inductors’ stray inductances have to bemeasured. They depend too much on how the inductors are wound to figure themout mathematically.
Unfortunately there was no time to wait two weeks until the CM filter cores arrived.The decision for one of the topologies had to be taken before. Thus it was notpossible to take the volume of the DM input filters into account. The DM filter wasbuilt during the development of the final converter.
The footprint areas and volumes speak for themselves. Inclusion of the DM filtervolumes would not change the decision at all. The current waveforms suggest thatthe flyback converter needs larger filters due to the high current spikes. The factthat both converters operate at the same input voltage and switching frequencyand take the same amount of energy per switching cycle out of the input filter
51
speaks against it. This argues that the total size of all filter elements before themain inductor should approximately be equal. The difference between the twoarguments is the frequency range they target. The latter argument is valid for lowfrequency where the filters are larger than at higher frequencies. Thus both inputfilters should be of comparable size.
4.3.2 Updating the Simulation Model
In order to get MM noise under control, the designed CM filter is linearised at240kHz, the frequency between150kHz and30MHz with the largest amplitude.The linearised filter is implemented in the simulation model. It is important toemploy coupled inductors. Less accurate solutions would be too far from reality.
The implementation of the linearised CM filter in the simulation ensures that theinfluence of the CM filter is accounted for while computing the MM and DM noise.Especially for the MM noise this is very important. It is attenuated by the full CMfilter, not only by the inductor’s stray inductances.
4.3.3 The DM Input Filter for the Flyback Converter
As for the CM filter, there has to be a filter stage on either side of the rectifier.A high capacitance is placed across the input DC rails as close as possible to theswitches. More than33nF does not seem to be available in the form of X2 ratedceramic chip capacitors. Three of them are placed between rectifier and line sideCM filter stage. Thus both, the DC and the AC side capacitors, use the CM filter’sstray inductance to provide together a fourth order DM filter. Unfortunately addi-tional inductors are required. TheDR73series from Coiltronics suits this purpose.The low currents and high voltages, respectively the requirement for X2 rated ca-pacitors, encourage the use of inductors to lower the filter’s poles. They allowsmaller and cheaper filters than attainable with additional capacitors. To damp anynoise class originating from anywhere in the converter, including the rectifier, threeinductors are placed between the line side CM filter inductors and its capacitors(fig 4.8).
L1
C1
L2
C2
C3
L3L4
C4
CM
CM
DM DM
Figure 4.8: Flyback converter’s input filters
There are only few components to choose from. Furthermore, deriving the for-mulae for the attenuation of the filter, including the coupling of the CM filter, is
52
quite difficult. It is much faster to dimension the components by simulation. Eventhough1ms is required for an accurate spectrum,111µs provide already a suf-ficient approximation to select the right values for the components. The correctbehaviour of the filter is verified afterwards by a longer simulation.
Unfortunately, the CM filter’s DC side stray inductance is the cause for a resonancepeak slightly above150kHz. The oscillation across the rectifier is large enough toput the noise spectrum above the limit. Thus an additional inductor is requiredto place the resonance frequency below150kHz. This produces lower losses thandamping the filter. Furthermore, if the filter was damped, larger components wereneeded to get at least the same attenuation. The undamped input filter is not aproblem for the control loop, because the converter employs peak current modecontrol.
4.4 Output Filters
4.4.1 Design Procedure
The15W and the35W output have different requirements regarding noise limits.Noise at the15W output has to be less than78dBµV between150kHz and500kHz.Between500kHz and30MHz the limit is 68dBµV . It has to be measured using aLISN similar to the one used to design the input filters. These limits are demandedby the final application of this output stage. It powers a linear amplifier with abandwidth of up to30MHz. The only restriction for the35W output is that theoutput voltage ripple should be less than100mV .
The latter can be achieved by putting a sufficently large capacitance at the output.This is barely possible for the15W output. The capacitance would consume toomuch space on the board. A filter of higher order provides a smaller solution.
To figure out how the noise has to be measured, one has to consider what a filterdoes. A filter does not reduce the noise currents in a loop. It just provides ashort, low impedance path. The noise currents follow primarily this path back totheir source. Thus the noise currents in the measurement resistors decrease. Thisleads to the conclusion, that an input filter does not attenuate the noise currents atthe outputs. The output stages need to have their own CM, DM and MM noisefilters. Furthermore, an existing filter on the input side can be neglected duringdevelopment of the output filter.
Remains the question on how to measure the noise at the output. Normally, theoutput stage’s ground potential is not the same as PE. Thus a full LISN as shownin figure 4.9 has to be used. If the load was not connected to PE it would begalvanically isolated from PE.
The case at hand is a bit special. The ground potential of the15W output is to beconnected to PE. This provides a very low impedance return path for noise currents.A CM filter becomes unnecessary. The LISN can be modified, because there is noneed for a dedicated, capacitively coupled path to PE. The degenerated "LISN" infigure4.10is used to measure the simulated noise at the15W output. The circuit
53
Co
CL
RL
ZoLL
Ii Iofilter LISN load
Figure 4.9: Complete LISN including load resistorZo for the de-velopment of output filters
has a load resistor in place of a voltage source. The power flow direction of thenoise is reversed. The rest of the design process is the same as for the input filters.The difference between the limit and the noise curve indB added to the attenuationof the filter already existent in the simulation provides the necessary attenuation ofthe final filter.
CoCL
RL
Zo
LL
Ii Iofilter "LISN" load
Figure 4.10: Degenerated LISN used for the development of theoutput filters
The output filters have to be verified at minimal and maximal load. The attenuationis dependent on the load. In case of the flyback converter, the switching frequencyharmonics increase with growing load. But the other noise is maximal at minimalload (fig4.13).
4.4.2 Forward Converter’s Output Filters
The noise at both outputs is simulated. As expected, the ’zero’-ripple devices op-erate as fourth order filters even when their stray inductors are wrong by20%. Asufficiently large capacitor at the output prevents voltage overshoots caused by theenergy stored in the filter inductor. Its design is described in section2.4.3.
A hanning window is used to cut off the discontinuities at the begin and end ofthe signal interval. Thus its periodic continuation results in a continuous signal.Without windowing, the spectra would approach a slope of−20dB per decade dueto the discontinuity created virtually by the fft, no matter what order the filter is ofand what attenuation it provides.
Both outputs use the same filter topology. Each of them has a10µF capacitor at
54
106 107−20
0
20
40
60
80
Hz
dBµV
stray ind. 20% off15W load0.5W load
Figure 4.11: Noise spectra of the forward converter’s15W outputwith different loads and once with a wrong stray inductance
its output. Whether the maximal output voltage ripple complies with the100mVlimit depends on the ’zero’-ripple device. It seems to be capable to limit the voltageripple to the desired value even when the stray inductance is not tuned perfectly.The simulations confirm that there is no need for a filter in addition to the ’zero’-ripple devices.
4.4.3 Flyback Converter’s Output Filters
15W , 60V Output
Two output capacitorsCo = 4.7µF in parallel are used in the simulation. In-creasing this capacitance a lot is not acceptable. The60V make it difficult to findsuitable SMD devices. The attenuation of this filter is calledAS . The impedanceZLo of the LISN together with the load resistor is given by
LL = 50µH CL = 250nF RL = 50Ω
Vo = 60V Po = 0.5 . . . 15W ⇒ Zo =V 2
o
Po(4.10)
ZLo =
[(1
sCL+ RL
)−1
+ (sLL + Zo)−1
]−1
(4.11)
The output capacitors in the initial simulation are represented as ideal capacitorsCo with equivalent series resistanceResr = 5mΩ. The current attenuation
AS :=Io
Iiin simulation, see figure4.10 (4.12)
is used as filter performance meter. Basically the voltage at the LISN resistorRL isrelevant. But the transfer functionAV from the LISN input currentIo to the LISN
55
output voltage across the resistorRL is the same for all output filters. Becausethe filter design process is not interested in an absolute attenuation but rather inan attenuation relative to the one present in the simulation, the additional termAV
gets canceled. It is thus safe to consider onlyAS .
Co = 4.7µF (4.13)
Z1 =1
sC1+ Resr (4.14)
AS =Z1
2ZLo + Z1(4.15)
The necessary attenuation could be reached by a second order filter. But a lowimpedance output is required and right after the flyback inductor and the outputdiode there has to be a capacitor. Thus one ends with a third order filter. Thechosen structure is shown in figure4.12.
L3 66u
R3 44R
C1
2u2
C2
1u
Resr Resr
Figure 4.12:Π filter used at the15W , 60V output of the flybackconverter
The attenuationAF of this filter is given by
AF :=Io
Ii(4.16)
Z1 =1
sC1+ Resr (4.17)
Z2 =1
sC2+ Resr (4.18)
Z3 =(
1sL3
+1
R3
)−1
(4.19)
AF =
[1Z1
+(
Z3 +Z2ZLo
Z2 + ZLo
)−1]−1
1ZLo
(4.20)
The necessary component values are listed in table4.1. They are used to obtainthe curves as shown in figure4.13. A filter with less attenuation would be alsosufficient. But as the parts are only available in discrete values, this filter is chosen.
56
C1 C2 Resr L3 R3
2.2µF 1µF 5mΩ 66µH 44Ω
Table 4.1: Filter component values for the flyback converter’s15W output
106 107
−40
−20
0
20
40
60
80
Hz
dBµV
without π filter15W, incl. filter0.5W, incl. filter
Figure 4.13: Noise spectra of the flyback converter’s15W outputwith different loads
35W , 30V Output
The voltage ripple∆Vo at this output has to be limited to100mV . It is approxi-mated by the energy transferred to the output capacitor per switching cycle.
∆E =Po
fs(4.21)
This is related to the voltage difference in the output capacitor. The load currentis neglected in the calculation. It is assumed to keep the capacitor in steady stateduring several switching cycles.
∆E =12Co
[(Vo + ∆Vo)
2 − V 2o
](4.22)
Setting equations4.21and4.22equal, then solving forCo provides
Co =2Po
fs · (2Vo∆Vo + ∆V 2o )
(4.23)
⇒ Co ≥ 97µF (4.24)
Considering the available parts and their sizes, an electrolytic SMD capacitor with330µF is chosen.
57
Results of the Topology Evaluation
5.1 Total Footprint Area and Volume
5.1.1 Common Circuits
The common mode filters at the input have the same size. They are not identicalbut use the same inductor cores and capacitors of the same size. The rectifiers arethe same for both converters, flyback and forward. Furthermore both use the samenumber of transistors. The control and gate drive circuits are assumed to consumethe same volume too.
Because the converters are compared relative to each other, the volume and foot-print of the just named circuits and components is neglected. In fact, the finalcomparison is reduced to the outputs due to the similarity of the inputs.
The main inductors are bothEFD30. Their dimensions are31 × 30 × 14 mm3,resulting in a volume of13cm3.
The size of the differential mode input filters is unknown at this time of the project.The comparison neglects these filters. But the outcome is so clear that this doesnot change anything.
5.1.2 Forward Converter
The output stages of the forward converter consist of the freewheeling diodes,(4 × DO-214AA), the ’zero’-ripple devices (EFD20, EFD25) and four capacitorsof various sizes. Adding up the boxed volume of these parts results in a volume of23cm3. This is far less than can be expected on a PCB because the space betweenthe parts is not accounted for.
5.1.3 Flyback Converter
Most of the volume is contributed by the output capacitor of the35W, 30V output.The other relevant parts are the two freewheeling diodes, the two ceramic chipcapacitors and the inductor of the60V output. All together have a volume of9cm3.
5.2 Conclusion
The numbers are clear. The40cm3 of the forward converter, including4cm3 forthe control circuit, loose against the26cm3 of the flyback converter. Is it possibleto guess the final size of the converter? A rule of thumb sais one third for each of
58
input filter, conversion parts and output filter. But the calculated numbers are notthe space effectively consumed on the board. It is just the sum of the individualpart’s volumes. There is no term for the spacing between the parts caused by wiringand safety regulations. The thermally caused spacing requirements are taken intoaccount. It is not known yet whether the parts can be perfectly distributed acrosstop and bottom side of the PCB in order to minimize its total size.
The final flyback converter’s two output stages fill a rectangle of8.1cm2 respec-tively a box of14.3cm3. One stage on the top, the other on the bottom side. Thesize of the whole converter is121 × 38 × 22 mm3 = 101cm3, effective layoutdimensions and component height. This includes all components, fuses and pro-tection varistors also.
40
35
30
25
20
15
10
5
0
7003cm
Flyback
Forward
3−passive
ControlSemiconductorsInductors
CapacitorsTotal
Figure 5.1: Volume contribution and comparison; The total of thethree-phase passive topology is reduced from700cm3 to0 in orderto make the other differences visible.
59
Finalising the Flyback Converter Design
6.1 Main Inductor Redesign
6.1.1 Several Reasons for a Third Design
There are several reasons for a third design of the flyback converter’s main inductor.For one, an auxiliary supply is wanted which is galvanically decoupled from bothmain output terminals. The initial plan to power it by the30V output is abandoned.Furthermore, the first redesign, respectively the second design, has some flaws(s.2.5.3). Then, there is no flyback inductor wound on anEFD30 core at this stageof the project. A new one is built anyway.
Last but not least the output freewheeling diodes operate at their thermal limits.The output currents are no issue but the switching losses might be too high. Thisis solved by splitting each of the two output stages,60V and30V , into symmetri-cal three level outputs. This needs two diodes per output but halves the switchedvoltage. The switching losses are drastically reduced as they are proportional tothe square of the switched voltage. The currents in the diodes remain the same.The output filters are split into two equal halves, their attenuation remains approx-imately the same.
The final schematics with all relevant part names are shown in appendixC.1.
6.1.2 New Winding Enumeration
The new inductor has six windings. Their use is defined in table6.1. The IDscorrespond to the red numbers in figureC.4. They are used as indices in formulaethroughout this chapter.
ID n V W purpose
1 1 − 52 input winding2 4 30 7.5 pos. amplifier output3 4 30 7.5 neg. amplifier output4 8 15 17.5 pos. host AUX output5 8 15 17.5 neg. host AUX output6 8 15 2 own AUX supply
Table 6.1: Windings of the third flyback inductor and their purpose
60
6.1.3 Third Inductor Design
The necessary formulae are explained in sections2.5.2and2.5.3. This design takesthe stray inductance and the influence of multiple output windings into account.The formulae from section2.5.3are thus modified to contain another output. Theyare reduced where possible to three outputs, making use of the symmetry.
The demagnetisation condition provides an upper limit forD1. See section2.5.2for an explanation of the formula. A toleranceη = 10% for the output voltages isadded.
D1 ≤(1− η)
√2n2
12V22 + 2n2
14V24 + n2
16V26
Vin,min + (1− η)√
2n212V
22 + 2n2
14V24 + n2
16V26
= 0.355 (6.1)
The maximumL1 is given by the power condition.Pin is now52W . σ1 = 0.3 isemployed as a conservative approximation. It is based on measured values of thefirst design.
L1 ≤D2
1,maxV 2in,min (1− σ1)2fsPin
= 1.36mH (6.2)
L1 is chosen to be
L1 := 780µH (6.3)
This makes the primary side peak currents larger than with a higher inductance, butit keeps the core smaller. The resulting currents are similar to the ones observed inthe filter design process.
The chosenL1 results in a new maximumD1 andD2.
D1 =√
2PinL1fs
1− σ1= 0.27 (6.4)
D2 =D1Vin,min
(1− η)√
2n212V
22 + 2n2
14V24 + n2
16V26
= 0.49 (6.5)
These values lead to the RMS currents in the windings.
I1 =Vin,min
L1D1Ts ≈ 1.26A (6.6)
I1,rms = I1 ·√
(1 + σ1) D1
3≈ 430mA (6.7)
Ix,rms = 2 ·√
13D2
· Px
Vx︸︷︷︸Ix,avg
∀ x ∈ 2, 3, 4, 5, 6 (6.8)
61
Ix,rms ≈x ∈ 2, 3 : 413mA
x ∈ 4, 5 : 1928mA
x = 6 : 220mA
This allows to select proper wire diameters. It is aimed for an RMS current densityof Srms = 4 A
mm2 . The diameters and thus the effective current densities are chosenas follows.
d1 = 0.35mm 4.5 Amm2
d2,3 = 0.35mm 4.3 Amm2
d4,5 = 0.8mm 3.8 Amm2
d6 = 0.3mm 3.1 Amm2
(6.9)
A peak magnetisation ofB = 160mT and an attainable fill factor ofk = 0.5 resultin a core factor of
AeAw =Vin,minD1
fsB
[(d1
2
)2
+2
n12
(d2
2
)2
+2
n14
(d4
2
)2
+1
n16
(d6
2
)2]
π
k(6.10)
≈ 3425mm4
That means it is not possible to build the inductor with anEFD25, but anEFD30(3609mm4
)should be fine.
The EFD30-3C96 from Ferroxcube is chosen. This relatively new material pro-vides lower losses than3F3 or 3C94. The coilformerCSH-EFD30-1S-12P isused.
This design procedure calculatesN1 by filling the winding window. Then a lowerN1 is chosen, which is a multiple ofn16. The correct inductanceL1 is obtained byadjusting the airgapδ.
N1 = floor
(Awk
π·
[(d1
2
)2
+2
n12
(d2
2
)2
+2
n14
(d4
2
)2
+1
n16
(d6
2
)2]−1
(6.11)
= 93
=⇒ N1 := 80 (6.12)
δ =AeN
21 µeµo − L1le
L1µe≈ 653µm (6.13)
62
That means the core halves need to have a gap ofδ2 ≈ 327µm between them.
Measurements reveal a much largerL1 than expected with these construction data.The primary side inductance is experimentally adjusted to beL1 = 906µH. Thenecessary airgap isδ2 ≈ 890µm. The high stray inductance causes a part of theprimary winding’s magnetic flux go only through one of the two core halves. TheAL becomes thus much higher, requiring a larger airgap for the same inductance.The fact that the flux must go perpendicular to the core axis through the windingwindow does not increase theAL a lot, because the winding window is nearlyfilled.
The expected core losses arePcore = 1.32W . Together with the copper lossesPCu = 0.5W this should result in a temperature rise of not more than52C.
The complete inductor data can be found in appendixA.2.1.
6.2 Control Circuit
6.2.1 Gate Driver
The two MOSFET gates are powered by a common driver. The high side transis-tor’s gate is decoupled from the other by a small1 : 1 transformer with anEP7-3F3
core.2× 37 turns of0.2mm wire are used. The circuit is shown in figureC.4. Thegates are driven by aUC3844 from TI. This IC incorporates all necessary ampli-fiers and references for control. Furthermore it clamps the duty cycle to50%. TheIC allows low impedance supplies of up to30V . But the start threshold voltage isbetween14.5V and17.5V . The undervoltage lockout mechanism has a hysteresisof 5 . . . 6V . This is necessary for the bootstrap circuit beeing used.
6.2.2 Bootstrap and Auxiliary Supply
During normal operation, the converter’s control and gate drive circuits are pow-ered via winding6 of the main inductor, the auxiliary15V output stage. Beforestartup, the output capacitor of the auxiliary supply is charged to the start thresholdvoltage of theUC3844. The capacitor is discharged during the first few switchingcycles. It has to be large enough not to reach the under voltage lockout limit untilthe output stages are operational. The bootstrap supplies described below do notneed to provide the full operating power. They just have to charge the auxiliarysupply’s output capacitor, which the whole startup energy is taken from. A68µFcapacitor does the job for the converter at hand.
There are various possibilities for the bootstrap circuit.
1. capacitively coupled, single cycle (fig6.1)
2. capacitively coupled, multi cycle (fig6.1)
3. non-switched resistor (fig6.2)
63
4. resistor switched by a BJT (fig6.3)
5. resistor switched by a FET (fig6.3)
All four approaches take their energy from the input DC rails after the main rec-tifier. Because all circuits are linear regulators, a multiple of the required poweris consumed. It is thus favorable to switch the bootstrap supply off once it is notneeded any more.
The first two possibilities (fig6.1) are very similar. Both couple the low auxiliaryvoltage through a capacitor to the much higher input voltage. The first version isdesigned to chargeCaux in one step to the necessary voltage. After the chargecycle, the energies inCaux andCbs are more or less equal. This requires a largeCbs. The second version, in figure6.1on the right hand side, employs the variationof the input voltage to chargeCaux during multiple cycles. Both versions are notsuitable for the topology at hand. The first one requires too much space, the latterdoes not work because there is just a DC voltage at the input rails as long as thereis no load.
Cbs
Caux Caux
Cbs
Figure 6.1: First (left) and second (right) bootstrap circuit: capaci-tively coupled
The second approach (fig6.2) is the most trivial one. A very small current flowscontinuously, even when the converter is operating, from the input rails trough aresistor into the auxiliary supply’s output capacitor. For the case at hand, up to2Ware lost, all the time. A lower bootstrap current, leading to lower losses, wouldcause unacceptably long start delays. Even though a bad solution, it can be used ifno other is found. It is possible to implement it even on a board which is designedfor one of the other bootstrap methods.
Caux
Rbs
Figure 6.2: Third bootstrap circuit: resistive, non-switched
The last two versions mainly use the same principle as the resistive solution. Butthey allow the current in the main resistors to be switched off once it is not requiredany more. The fourth version uses a BJT for that purpose. It is switched on or
64
off based on the voltage inCaux. If the zener voltage is higher thanVCaux , thenthere is a current through the base keeping the transistor switched on. The circuit’sdrawbacks are the part tolerances. The minimal start voltage of theUC3844, thezener voltage and finally the auxiliary’s supply voltage all vary over a broad range.But they have to maintain a certain non-overlapping order for the circuit to workproperly. In the fifth version, the FET is controlled by an RC element consisting
Caux
Tbs
Rbs
Caux
Rbs
Tbs
Ct
Rt
Figure 6.3: Fourth (left) and fifth (right) bootstrap circuit:switched resistors
of Rt andCt (fig 6.3). Unfortunately it does not take into account the pulsatingcharge curve of the DC rail capacitors. Thus the FET is switched on and off at300Hz. This prevents the implemented version from working as intended. Thisdesign assumes that the bootstrap supply’s input voltage is charged within lessthan one sixth of a line period. The input filters slow down this process. Figure6.4shows the transistor’s gate to source voltage. A redesign might try to damp the
Figure 6.4: BadVgs of bootstrap MOSFET during power up
oscillations right at the FET’s gate. In the mean time, the third, purely resistivesolution is used.T200 in figureC.3is replaced by two further43kΩ / 1W resistorsin series connectingR208 to Vcc. C204 is not placed. The other components are lefton the board.
65
6.2.3 Galvanic Isolation of the Feedback Signal
The positive15V of the 35W output are controlled. An optocoupler is used tocouple the feedback loop across the galvanic isolation. Unfortunately, optocouplershave very large component tolerances. Their CTR might vary by a factor of up to12. This leads directly to very different crossover frequencies of the open controlloop. To reduce this influence, aTCLT1103 is used. It provides a CTR between0.8 and2. The main influence on the loop bandwidth remaining is the load.
The optocoupler splits the controller into two parts, the gate drive side and theoutput voltage sensing circuit. The error building and the integral part are bothplaced at the converter’s output side. This way, the tolerances of the optocouplerand related parts do not make their way into the steady state error. The componentsproviding the controller’s pole are placed as close as possible to the gate drive IC.This minimises noise getting through the built-in amplifier into the peak currentcomparator.
The whole control circuit is shown in figureC.3. C202 provides the integral partof the controller. Together withR200,201 it provides also the controller’s zero.ComponentsR210, R211 andC205 use the gate drive IC’s internal amplifier foradjusting the overall loop gain and to build a pole.
The low passR205/C206 at the current sense input, pin3, kills the spikes generatedacrossR304,305 during turn-on ofT302 (fig C.4). It is used instead of an activeleading edge blanking circuit.
Slope compensation to stabilise the feedback loop is not necessary. The duty cycleis clamped to a maximum of0.5 by the UC3844. This guaranties stable peakcurrent control even during transients in continuous conduction mode, in case theconverter’s state allows it at all.
6.3 Control Loop Design
6.3.1 The Structure
Figure6.5 shows the control structure of the whole converter, including the con-troller. The blue blockGvi represents the converter’s power part, including alloutput stages. It is basically the same as in section3.1.3, but this timeZ ′ has toinclude the final output filters.
Tcs is the transfer function from the referenceIref to the effective peak currentI inthe main inductor’s primary winding.Gvi transformsI into the output voltageV ′.The compensatorKc, error building, integral part and zero, drives the optocouplerGo. The optocoupler output is amplified byKa, the transfer function from theopto-transistor current to the control voltageVc. Ka includes the controller’s pole.ThusKa andKc together provide a lead-lag controller.Hs takes care about theattenuation due to the current sensing resistors.
66
+Tcs V’
Gvi
GoHsVref
KcKa
Gv
Z’Gi
Figure 6.5: Control structure of the flyback converter realised inhardware
6.3.2 Model of the Peak Current Mode Controlled Converter
Peak Current Controller
[12] describes an accurate model forTcs, taking into account the sampling effect.The mathematically exact small signal transfer function of said model is
i
iref
= a · esTs
esTs − 1 + a· 1− e−sTs
s(6.14)
a =M1 + M2
M1 + Mc(6.15)
In (6.15), M1 is the active slope of the current,M2 is the negated down slope, apositive number too, andMc is the compensation slope.Mc is 0 in the case at handbecause no slope compensation is used.
A second order Padé approximation of the exact model (6.14) leads to (6.16).
Tcs =i
iref
≈
[1 +
1Qs
(2s
ωs
)+(
2s
ωs
)2]−1
(6.16)
Qs =2
π(
2a − 1
) (6.17)
For the calculation ofa, relationships from the continuous conduction mode areused. This is a conservative simplification. If the continuous mode of operation isstable, then the controller works in discontinuous mode too. (6.15) results in
a =2D′
min
D′ D′ = 1−Dss D′min =
0.51 + Mc
M1
(6.18)
D′min becomes0.5 becauseMc = 0. Dss is the steady state value of the duty cycle
ratio. The auxiliary supply is assumed to draw aboutP2 = 1W , half of the possiblepower.
Pss =6∑
x=2
Px = 51W (6.19)
67
Iss =
√2Pss
L1 (1− σ1) fs(6.20)
Dss =IssL1fs
Vin,avg(6.21)
Transfer Function Gvi
The conversion transfer functionGvi is very similar as already used for the simu-lation model.Z ′ is calculated according to (3.11), but with a differentgCo. Thefollowing equations show, how the newgCo is obtained. The component enumer-ation is the same as in figuresC.1 throughC.4. The formulae seem to neglectsmall capacitors, such asC302, in parallel with large ones. In fact, for exampleC318 = 330.1µF is used to takeC302 into account.
The equvivalent series resistance of a capacitor is calledEx with the accordingcapacitor beeingCx. It is calculated atωesr = 2π · 240kHz.
tan(δ) = 0.12 (see datasheets) (6.22)
Ex =tan(δ)ωesrCx
(6.23)
TheZ ′ is parametrised by the desired output power. The parameters areP23, P45
andP6, indexed according to the main inductor windings delivering the power.Together with the output voltages,V2,3 = 30V , V4,5 = 15V andV6 = 15V , thisallows direct calculation of the load resistors.
RLx =V 2
x
Px∀ x ∈ 2, 4, 5, 6 (6.24)
The two current sense resistors are aggregated into one shuntRs.
Rs = R304 + R305 (6.25)
All components are transformed to the same15V equivalent output winding. Theimpedances at outputs2 and3 are thus divided byn2
24 = 4. Furthermore the for-mulae make use of balanced components. For example,C314 is not in the formulae,C313 is used instead.C314 andC313 appear in parallel, coupled by windings2 and3 to winding4, the controlled15V output.
Zx =1
sCx+ Ex ∀ x ∈ 313, 318, 320 (6.26)
Za =[2n2
24
Z313+
2Z318
+1
Z320
]−1
(6.27)
68
Ra =
[6∑
x=4
1RLx
]−1
(6.28)
Z2 =1
2n224
·
[(1
sL301+
1R306
)−1
+(
sC321 +1
RL2
)−1]
(6.29)
Z ′ =[
1Za
+1
Ra+
1Z2
]−1
(6.30)
The transfer functionsGV andGI are the same as given by (3.9) and (3.8). Gvi iscalculated according to (3.12) but with the newZ ′.
6.3.3 Measurement and Control Transfer Functions
The Two Part Controller
The resistorR204 is not relevant forKa. It only reduces the power dissipated bythe opto-transistor. The attenuation by a factor3 is due to internal resistors in thecontroller IC.Ka is mainly used to adjust the overall loop gain and thus the controlbandwidth.
Ka = − R206R210
3 · (R206 + R211) (R210C205s + 1)(6.31)
For design purposes, (6.31) is written in a "gain times pole" form.
Ka = − A ·Gp (6.32)
A =R206R210
3 · (R206 + R211)(6.33)
Gp =1
R210C205s + 1(6.34)
The other side of the controller,Kc, contains the zero and the integral part.
Rc =[
1R200
+1
R201 + R202
]−1
(6.35)
ωz =1
C200Rc(6.36)
Kc =1
R203· s + ωz
s(6.37)
A second possibility to adjust the overall loop gain is thus given byR203.
69
Other Transfer Functions
The CTR of the optocoupler has to be varied in order to see the range of resultingcrossover frequencies.
Go = 0.8 . . . 2 (6.38)
The influence of the shunt resistors is given by
Hs =1Rs
(6.39)
6.3.4 Loop Shaping and Proper Biasing
Most resistors of the control circuit are used to set the steady state operating pointand limit the power dissipation of critical parts. They have to be designed to allowoperating points in the whole dynamic range. The start point for the design is thepeak current comparator. TheUC3844 uses an internal0 . . . 1V ramp. The outputof the internal, preceeding operational amplifier is attenuated by a factor3. Thus allsteady state operating points resulting in amplifier output voltages (UC3844/U200,pin 1) in the range0 . . . 3V must be allowed.
This leads to the biasing network of the opto-transistor. Because this depends itselfon the loop gain and generates thus a circular dependency, the problem is solvediteratively. This leads faster to useful values than a direct mathematical solution.
R206 transforms the opto-transistor current into a voltage.R204 has to protect theopto-transistor from consuming too much power. Both resistors are chosen basedon steady state operating point constraints.R204 must be low enough not to saturatethe opto-transistor but high enough to protect it from high power dissipation. It isselected depending on the value ofR206.
The resistorsR200, R201 andR202 have several influences. They determine to-gether withC202 the controller’s zero (eq.6.36). But they set also the referencevalue for the output voltage.
V ′ · R200
R201 + R202
!= 2.5V (6.40)
Both relations together, (6.40) and (6.36), lead to the final choice. The converter’spole created at low load conditions is below1Hz. Thus a very low frequency zerois required. A largeC202 = 2.2µF is selected. Then the resistors are chosenaccordingly.
To obtain a high loop gain,R203 should be as low as possible. But a too low valuewould result in excessive heating of the optocoupler LED and the voltage referenceD201. Thus a low value still resulting in valid operating points and allowing for thewhole dynamic range is chosen.
Finally, the loop gain is adjusted by definingR210 andR211. The pole frequencyis then placed slightly above the maximum crossover frequency.
The resulting control loop (6.41) is shown in figure6.6 for different load resistorsand varying CTR. The influence ofTcs is visible in form of the double pole at half
70
the switching frequency (60kHz).
L = KcGoKaHsTcsGvi (6.41)
10−4 10−3 10−2 10−1 100 101 102−100
−50
0
50
100G
ain
dB
10−4 10−3 10−2 10−1 100 101 102−250
−200
−150
−100
−50
0
Pha
se °
kHz
50.3W, Gopt=0.8
0.7W, Gopt=0.8
50.3W, Gopt=2
0.7W, Gopt=2
Figure 6.6: The flyback converter’s open control loop,L, realisedin hardware
71
Construction and Initial Operation
7.1 Construction
There are three components which are not SMD,L300, C323 andC324. The pins ofthe main inductorL300 are shortened, then it is soldered on the board as if it wouldbe an SMD package. The legs of the two DC rail capacitors are bent radiallyoutwards, then they are soldered on their special footprints. All other componentsdo not need any cheating.
The input filter is soldered onto the PCB first. This allows to do some attenuationmeasurements with the network analyserHP4396A as shown in figure7.1. Therectifier diodesD100 andD104 are both shorted for that purpose. Two measure-ments are carried out, one for the common and the other for the differential modeattenuation.
50R
50R
Filter
Source
SenseHP4396A
V1 V2
Figure 7.1: On-board input filter measurement
For the CM measurement, pins1 to 3 of L100 are shorted, they provide the outputterminal. The positive and negative DC rails are shorted too in order to provide theinput terminal. The measurement voltage is injected between the input terminalandPE. A measurement of the voltage between output terminal andPE, comparedto the injected voltage, provides the attenuation.
For the DM measurement, the input terminal is provided by the two DC rails af-ter the rectifier. The rectifier diodes are shorted as before. The output voltage ismeasured between pins1 and2 of L100.
The results for both measurements are shown in figure7.2. Comparing figure4.5with the CM filter attenuation in figure7.2predicts problems. But instead of chang-ing the filter components, the whole converter is built. The EMC measurementshave to reveal the effective converter behaviour. There are too many differencesbetween effective noise propagation and these attenuation measurements. For ex-ample, the DM measurement should be done by current instead of voltage injec-tion. Furthermore there are quite a few differences between the simulations and thefinal converter.
72
150k 1M 10M 30M−80
−70
−60
−50
−40
−30
−20
Hz
Inse
rtion
loss
[dB
]
DMCM
Figure 7.2: Measured insertion loss curves (20 · log10
∣∣∣V2(f)V1(f)
∣∣∣ ⇒fig. 7.1) of the flyback converter’s input filter
7.2 Initial Operation
7.2.1 Test of the Input Circuit
As a first test, the converter is supplied with a very low input voltage,VN,rms =5V . This does not activate the bootstrap circuit. The control circuit can not operateeither at such low voltages. But this test shows the correct operation of the rectifierand it checks for short circuits within the input filter components. A voltage of√
6 · 5V − 2 · VD across the DC rails indicates correct operation.
7.2.2 Test of the Control Circuit
For this second test, the three-phase5V supply is removed. The15V to power thegate drive side of the control circuit are applied by an external power supply. Theswitched off opto-transistor sets the amplifier input to0V . This voltage is invertedand causes the gates to be driven at the maximum duty cycle of0.5Ts. Measuringthe gate to source voltage of the two transistors with an oscilloscope might indicatemajor malfunctions in the control and gate drive circuit.
7.2.3 Externally Powered Operation
The power for the gate drive circuit is still provided externally. A diode in thesupply wire prevents the external supply from becoming a sink. The externallysupplied voltage is rised to start the gate drive. Then it is decreased to slightlybelow the voltage existing when the control circuit is powered by the internal aux-iliary supply. Thus a takeover happens once the converter starts correct operation.It is important to provide some load to the converter. These tests are done at abouthalf the nominal load.
73
7.2.4 Autonomous Operation
The external supply is removed. The converter is powered up. Operation starts onlyif the bootstrap circuit provides enough power. The problems described in section6.2.2are discovered at this point. So the transistor is replaced by two further43kΩresistors.
7.3 Thermal Test
The load tests are done during EMC measurements. One scan from150kHz to30MHz takes about2h 30. This allows the converter to reach its thermal equilib-rium. The tests are done at21C room temperature without forced cooling. AsEMC regulations demand, the prototype is placed on a wooden table. Thus there ispractically no thermal conduction away from the test circuit except radiation andconvection.
7.3.1 Tests with the Fourth Flyback Inductor
The long test runs at minimal load of1W result in a winding temperature of about150C on the main inductor. This is far more than expected. The calculated tem-perature rise at full load is70C, resulting in a final inductor temperature of90C.The effective temperature is60C above the expected one. This has also impli-cations for the semiconductors. They operate at higher ambient temperature andhave to conduct higher currents than predicted. At full load this leads to failureof the input side freewheeling diodes. The next turn on of the according transistordestructs it. Thus the input DC rails are shorted and the three fuses melt.
As a solution, the cause of the high inductor temperature needs to be found. Build-ing a better inductor solves the problems described above.
Because the core temperature is much lower than the winding temperature, it issuspected, that the wire diameters are too small. This contradicts the mathematicalmodel of the transformer. The4.5 A
mm2 should not cause such high losses.
The proximity effect is neglected in the inductor design. The special winding lay-out (fig A.8) forces high magnetic fields within the primary winding itself. In amathematical context this is equal to strongly reducing the wire diameters. Anotherphenomena causing the same symptoms is the skin effect. At a switching frequencyof 120kHz, the currents in a flyback converter’s main inductor have large ampli-tudes at240kHz, 360kHz and higher harmonics too, where the skin effect becomesrelevant for the used wire diameters.
It is decided to build another main inductor. It provides a solution to cut down thelosses due to the proximity effect. The skin effect is still neglected. If the newinductor runs much cooler, then the proximity effect is the problem. Otherwise,one has to take care about the skin effect.
74
7.3.2 Fifth Flyback Inductor
Design Considerations
The argument to favor a winding layout as in figureA.8 are the very low inter-winding capacitances. Keeping them low allows for smaller filters. To reduce theproximity effect, the winding layout has to be changed. The new layout resultsin much higher inter-winding capacitances. Thus there is a problem. The filter’sattenuation is probably not high enough to pass EMC tests with the new inductor.Slightly exceeding the EMC limits but having an otherwise working converter isstill a step forward in comparison to a converter operating only with a load of lessthan2W .
bobbin
1a
tape2 3
4 5
61b
+ tapeCu shield
Cu shield+ tape
Figure 7.3: Sandwich layout: low proximity effect, very high ca-pacitance between primary and secondary windings; winding enu-meration according to figureC.4
To keep the proximity effect low, a sandwich layout as shown in figure7.3 is asuitable solution. But it is the worst case scenario regarding the inter-windingcapacitances. A copper shield between the primary and secondary windings, con-nected to a "quiet" potential, helps to reduce the generated CM noise. Due to theshort term unavailability of copper tape or aluminum foil at the institute and timepressure, the inductor is built without shield. The construction data and impedancemeasurements are listed in appendixA.2.1. The capacitance between the primaryand the output windings of the60V output is11 times higher than that of the pre-vious, fourth design. This has severe implications on both, CM and DM noise.
The new design has the advantage that the coupling factors of the output windingsare much higher than in the previous design. This reduces the load dependence ofthe output voltages a lot. Furthermore, the primary winding’s stray coefficientσ1
is about40 times lower in the new design (0.01 versus0.54). It is expected that thisincreases the DM noise because the primary winding’s current, after the transistorsare switched off, decreases very fast due to the low stray inductance.
High stray coefficients seem actually to be the source of the strong proximity ef-fect. To transfer the same energy per switching cycle, an inductor with large straycoefficients needs a higher peak flux than one with low stray coefficients, if thetotal primary inductance is the same. It follows, that keeping the stray coefficientslow, reduces the proximity effect in a flyback inductor. This lowers of course theprimary side peak current too.
One might assume that the sandwich layout (fig7.3) reduces the magnetic field in
75
H bobbin
1a
1b
DTs − ...... − DTsH H
flyback inductornormal transformer
2
"only" core magnetisation"no" core magnetisation
Figure 7.4: Magnetic field in a sandwich inductor with differentoperating modes; The stray inductances are neglected.
the windings. For a normal transformer this is the case. But a flyback inductor doesnot have currents in the primary and secondary winding at the same time. Thus thefields are not compensated. This is shown in figure7.4. The stray inductances areneglected, ideal coupling of the windings is assumed. In a flyback inductor, thereduction of the proximity effect is only due to the lower stray coefficients. Lowerstray coefficients shorten the time during which there is a high magnetic field anda current at once in a winding, besides improving the energy transfer.
Considering that small stray coefficients reduce the primary side peak currents butalso generate more high frequency noise due to steep current slopes, an optimiseddesign might be found. Due to the available time this is not done in this thesis.
Another difference to the previous design is the higher peak of the magnetic fluxin the core. In the previous design, the core remains cooler than predicted, onlythe windings get very hot. This is compensated to better balance core and windinglosses.
Test Results
The same test runs are done as for the previous inductor design. Running it atthe minimal load of1W results in a20C temperature rise in the main inductor.Operation at40W output power produces a temperature rise of100C. This is stillmore than the predicted70C for 50W , but it is acceptable. The neglected skineffect and the not fully eliminated proximity effect are assumed to be the cause.
V2,3 [V ] V4,5 [V ] P2,3 [W ] P4,5 [W ] Ptot [W ]51.6 27.2 12.6 6.0 18.648.3 25.1 11.1 13.8 24.942.7 21.2 10.7 24.8 35.5
Table 7.1: Output voltages at certain load conditions,V4 is con-trolled to be14.5V
The converter is not able to deliver the full50W to its outputs. The output voltagesdrop with increasing load. To deliver50W , the output currents would need to be
76
a lot higher than the output stages are designed for. Table7.1 shows the outputvoltages at certain load conditions. The indices are according to appendixC.1.The EMC tests done at "maximum load", described in the next chapter, are runat a total output power of up to40W , without forced cooling. As later thermalmeasurements show, the junction temperatures of certain parts might be slightlyabove their maximum ratings during the EMC measurements.
7.3.3 Thermal Imaging, Maximum Load
To further investigate the thermal issues, an IR camera is employed. It deliversabout130 frames per second. Individual frames can be captured. Because thecamera produces only raw values instead of a certain temperature per pixel, thecaptured images are imported into Matlab for postprocessing. This allows mappingto a colour gradient which correlates directly toC.
These measurements aim to clarify the neccessity of forced cooling. Table7.2shows the load configurations and state of the fan used when the images are cap-tured. All images use the same colour gradient. If the1W/5cm fan is switched on,it blows from the bottom right to the top left corner of the image. The airflow iscoplanar to the PCB. The fan is placed about6cm away from the converter.
Img.nr. V2,3 [V ] V4,5 [V ] P2,3 [W ] P4,5 [W ] Ptot [W ] Fan
1 57.5 28.2 8.3 17.8 26.1 off2 57.5 28.2 8.3 17.8 26.1 on3 46.0 22.9 10.1 27.5 37.6 on
4 + 5 52.8 26.8 13.2 19.6 32.8 on
Table 7.2: Load configurations used for the thermal images, theambient temperature is22.6C
Figure7.5shows images1 and2. They are captured at the same load configuration.The first image shows the converter without forced cooling, for the second image,the fan is turned on. The temperature drop caused by forced cooling is about30Cat the hot spots.
Figure7.6shows the converter operating at37.6W output power. The fan is turnedon. This image shows the problematic components, the two output diodes of the30V (±15V ) output stage. Due to the voltage drop, the current through the diodesreaches its designed upper limit at lower load than the output stage is designed for.Operation at more load does not make sense, because the output voltages would betoo low for most applications.
These images indicate, that a fan is necessary if the converter operates with morethan about20W at the30V output. TheES2Ddiodes are designed for an operatingjunction temperature of up to150C with a thermal resistance to their leads of20
CW .
77
20
40
60
80
20
40
60
80
Figure 7.5: Thermal images1 (top) and2 (bottom) (tab.7.2); Thetwo hot spots on the right hand side are the two diodes of the±15V output. The hot area in the middle is caused by the twoMOSFETs. Metallic surfaces show up as cold due to low radia-tion. In fact they are as hot as their surrounding.
20
40
60
80
Figure 7.6: Thermal image3 (tab.7.2)
The fourth thermal image (fig7.7) shows the bottom side of the converter. The60V output stage is on the left hand side. Its diodes stay cool at13W . Thus quitehigh load is possible at this output if the load at the30V output is kept low in orderto reduce the voltage drop.
The voltage drop can be corrected by the addition of some turns in the appropriatewindings. This would allow to draw more power with nearly the same losses in theoutput diodes. But in order to avoid destruction due to overvoltages, the minimalload would have to be known. Load circuit protection by zener diodes or varistorsmight be necessary.
Thus the power limitation of the60V output is actually not the current in thediodes, but rather the dropping output voltage and the current in the main inductor.
78
20
40
60
80
Figure 7.7: Thermal image4 (tab.7.2), bottom side of PCB
20
40
60
80
Figure 7.8: Thermal image5 (tab.7.2), top side of PCB
The40C spot at the top/back border of the board in figure7.7 is the control andgate driver IC,UC3844. The four small, very hot spots are the bootstrap resistors.Low values are chosen,4× 47kΩ, to shorten the bootstrap delay. The losses couldbe decreased by choosing higher resistances and allowing for longer bootstrap de-lays.
79
EMC Measurements
8.1 Setup
The converter is placed on a wooden table,80cm above a grounded (PE) aluminumsheet. On the back wall, at a distance of80cm, there is a grounded aluminumsheet too with the dimensions as required by the CISPR 22 regulations. The poweris taken directly from a distribution box at the back wall. The LISN is insertedbetween outlet and converter. The LISN’s output is fed to an EMI test receiverfrom Rohde & Schwarz, theR&S ESPI. For some measurements, a noise splitteris connected between LISN and test receiver. This allows to measure CM and DMnoise separately.
testreceiver
R&SESPI
Table
grounded (PE) Al sheet
3ph outlet
load
80cmSchaffner4 x LISN
23
2
1
3
3
+30,−30V30V
grounded (PE) Al sheet at the wall
+30V
load
load
−30V
Figure 8.1: EMC test setup
8.2 EMC with the Fourth Flyback Inductor
The first test measurements are done at minimum load. The fourth design of themain inductor is used, which the filters are designed for. As described in section7.3, it has very low inter-winding capacitances. But because the proximity effectis neglected during its design, the inductor can only be used at minimum loadconditions. The scan results for the input side, blue wires in figure8.1, those forthe+30V output, green wires, as well as the background noise are shown in figure8.2. These measurements respresent the total noise. CM and DM noise are notsplit.
80
SGL
dBµV
dBµV
TDF
2 QP
VIEW
3 QP
CLRWR
1 QP
VIEW
15 0 k Hz 30 M H z
M T 1 6 0 ms
R BW 9 kH z
P RE A MP O F FAt t 1 0 d B AU T O
PRN
30 .M a r 06 18 :3 1
1 M H z 10 M H z
20
25
30
35
40
45
50
55
60
65
70
Figure 8.2: Total conducted noise, fourth main inductor design,minimum load; blue: input phase T, green: output+30V , black:background noise
The background noise is measured with power turned on, but the power plug atthe PCB is rotated by90, so onlyPE is plugged in. The black trace in figure8.2represents the background noise on input phase R.
As the plots show, the converter fulfils the EMC regulations. The curves of inputand output noise are similar at low frequencies, because the filters are tuned toprovide only as much attenuation as is required. They diverge at frequencies around1 to 10MHz because of different filter structure and noise path impedance. At highfrequencies, about20MHz, the curves are again similar because the filters becomeinefficient. The inter-winding capacitance between primary and secondary side ofthe main inductor dominates. That means, increasing it gives a lot of trouble.
8.3 EMC with the Fifth Flyback Inductor
8.3.1 No Additional External Filters
To be able to deliver the full power to the output, the fifth main inductor is solderedonto the board. The new measurements approve the fear of too high inter-windingcapacitances. Figure8.3 shows the same measurements as figure8.2, but for thenew inductor. Notice the different scales of the ordinates. Despite similar back-ground noise, the input and output conducted noise is a lot higher over the wholefrequency range. The spike at7MHz can safely be ignored. It is only measured onworking days and disappears during week-ends.
81
2 QP
VIEW
SGL
TDF
dBµV
dBµV
VIEW
3 QP
CLRWR
M T 1 6 0 ms
R BW 9 kH z
P RE A MP O F FAt t 1 0 d B AU T O
1 QP
15 0 k Hz 30 M H z
PRN
31 .M a r 06 15 :2 7
1 M H z 10 M H z
20
30
40
50
60
70
80
90
Figure 8.3: Total conducted noise, fifth main inductor design, min-imum load; input phase T (blue), output+30V (green), back-ground noise (black)
These measurements, taken at minimal load, fulfil the required EMC regulationsat the input only up to about5.5MHz. The output violates the requirements at lowand high frequencies. The next step is to try to push the emissions below the limitsby putting toroid cores onto the wires.
8.3.2 Additional Filters
The input is enhanced by a toroid from Fair-Rite, product number5943000301 .It is used as a CM inductor with three turns per phase. ThePEconductor is twistedaround the three phases before and after the toroid which is placed2cm awayfrom the PCB connector. The measurement result is shown in figure8.4. At highload, the first switching frequency harmonic violates the regulations. The nextviolation occurs at8MHz. A comparison with figure8.3 shows, that the noise athigh frequencies is attenuated by10dB. Nevertheless, at high load, the regulationsare still violated.
The additional output filters, usingVITROPERM 500Ftoroid cores from Vacuum-schmelze, have more impact. Two are used, one on the+30V and the other onthe−30V output rail. Each of them gets5 turns. The advantage of this materialis that it provides very high core losses at high frequencies and high inductance atlow frequencies. This can be seen in figure8.5. The two curves show the outputnoise measured without and with the additional inductors. Unfortunately, the highfrequency noise, as at the input, is not attenuated by the additional filters at all.With the additional inductors, the EMC requirements are fulfilled for frequenciesup to13MHz.
82
SGL
TDF
dBµV
dBµV
1 QP
VIEW
2 QP
CLRWR
15 0 k Hz 30 M H z
R BW 9 kH z
M T 1 6 0 ms
P RE A MP O F FAt t 1 0 d B AU T O
02 .A p r 06 15 :4 1
PRN
1 M H z 10 M H z
20
30
40
50
60
70
80
90
Figure 8.4: Total conducted noise at the input, fifth main inductordesign, minimum (blue) and maximum (black) load
8.3.3 CM and DM Noise at the Input
In order to get a better idea of the noise source characteristic, the LISN output isfed to the passive three-phase noise separator described in [13], which also showsthe used LISN in detail. The noise separator selectively attenuates one of the noiseclasses and lets the other pass through. Its output is connected to the EMC testreceiver. Figure8.6 shows the measured DM (blue), CM (black) and background(green) noise at the input under full load.
As expected, the DM noise dominates at low frequencies. It can easily be atten-uated by appropriate filters. At high frequencies, the CM noise dominates. HFfilters with very low parasitic effects are required to successfully attenuate theseconducted emissions. It is less difficult to reduce them by modification of theirsource instead of adding filters.
83
SGL
TDF
dBµV
dBµV
3 QP
CLRWR
R BW 9 kH z
P RE A MP O F FAt t 1 0 d B AU T O
2 QP
VIEW
M T 1 0 0 ms
15 0 k Hz 30 M H z
02 .A p r 06 12 :4 3
PRN
1 M H z 10 M H z
20
25
30
35
40
45
50
55
60
65
70
75
80
Figure 8.5: Total conducted noise at the+30V output, fifth maininductor design, minimum load; without (blue) and with (green)additional filters
dBµV
dBµV
SGL
TDF
1 QP
VIEW
15 0 k Hz 30 M H z
2 QP
VIEW
3 QP
CLRWR
M T 1 6 0 ms
R BW 9 kH z
P RE A MP O F FAt t 1 0 d B AU T O
03 .A p r 06 18 :2 0
PRN
1 M H z 10 M H z
10
20
30
40
50
60
70
80
90
Figure 8.6: Separated DM (blue), CM (black) and background(green) noise at the input under full load, fifth main inductor de-sign
84
Appendix A
Inductive Components
A.1 Forward Converter
A.1.1 Main Transformer
4a4b
21
bobbin
3b3atape
121110987 6
54321
L4a
L2
L3a
L3b
L1
L4b
Figure A.1: Forward converter’s main transformer winding layout
winding 1 2 3 4wire diameter 0.20 0.20 0.25 0.50 mm
number of turns 220 220 2× 35 2× 18 #
on a FerroxcubeEFD30/15/9-3C94 core
Table A.1: Forward converter’s main transformer winding data
C11
R11
R13
R12
L11
L1
L4
L3
L31
L41
R31
R41k = 1
C012
C013
C023C12
R14
R42
R32
R33 R34
R44R43
C31
C41
C42
C32
C21
R21
R23
R22
L21
L2C22
R24
Figure A.2: Forward converter’s main transformer equivalent cir-cuit
85
winding Lx Lx1 Rx1, Rx2 Rx3, Rx4 Cx1, Cx2
x = mH µH Ω kΩ pF
1 115.4 37.5 1.59 2000 6.62 119.0 94.1 1.68 2000 6.63 11.934 66.4 0.20 206 83.24 3.094 32.3 0.03 53 310.0
C012 C013 C023
−28 53.6 109.7 pF
Table A.2: Values of the forward converter’s main transformerequivalent circuit components (figA.2)
A.1.2 Output Inductors
bobbin4tape
fr4
21
3 121110987 6
54321
L4L2 L3 L1
Figure A.3: Forward converter’s output inductor winding layout
8765 4
321
Figure A.4: Forward converter’s output stray inductor pin diagram(L3 in figure2.11)
86
winding 1 2 3 4figure2.11 L6 L8 L7 L9
wire diameter 0.3 0.3 0.1 0.1 mm
number of turns 80 80 5 5 #
on a FerroxcubeEFD20/10/7-3F3-A250 core
Table A.3: Forward converter’s 15W output inductor winding data
winding 1 2 3 4section2.4.4 L11 L13 L12 L14
wire diameter 0.71 0.71 0.16 0.16 mm
number of turns 22 22 4 4 #
on a FerroxcubeEFD25/13/9-3F3 core with a custom150µm airgap
Table A.4: Forward converter’s 35W output inductor winding data
wire φ turnsmm #
stray ind. for15W output 0.10 2× 23stray ind. for35W output 0.16 2× 10
on a FerroxcubeER9.5/2.5/5-3F3-A160-S core
Table A.5: Forward converter’s output stray inductor winding data
R51
R11
R21
L11 L1
L31 L3
L41 L4
L21 L2
C034
C013
C024
C11
C21
C2
C51
L5
Co
L6-9
L5
k=1
Figure A.5: Forward converter’s ’zero’-ripple inductor equivalentcircuit (the orange marks indicate the equivalent components offigure2.11)
87
winding x = Lx Lx1 Rx1 Cx1
µH µH Ω pF
primary 1 1536.1 159.5 1.23 19primary 2 1536.1 111.1 1.21 20secondary 3 6.0 2.8 - -secondary 4 6.0 3.5 - -ext. stray 5 347.5 - 1 15
C013 C024 C034
16 16 5.5 pF
Table A.6: Forward converter’s15W/60V output inductor data (figA.5)
winding x = Lx Lx1 Rx1 Cx1
µH µH Ω pF
primary1, 2 1, 2 162.0 26.9 0.20 19secondary1, 2 3, 4 2.1 0.3 - -ext. stray 5 64.2 - 1 15
C013 C024 C034
16 16 5.5 pF
Table A.7: Forward converter’s35W/30V output inductor data (figA.5)
88
A.2 Flyback Converter
A.2.1 Main Inductor for Discontinuous Mode of Operation
fr4
tape
bobbin
12
3
121110987 6
54321
L2 L1
L3
Figure A.6: The flyback converter’s main inductor winding layout
C11
R11
R13
R12
L11
L1 L2
L3
L31
L21
R31
R21
k = 1
C012
C013
C023
C12R14
R22
R32
R33 R34
R24R23
C31
C21
C22
C32
Figure A.7: The flyback converter’s main inductor equivalent cir-cuit
Initial Design
This inductor is constructed and used to conduct the measurements.
winding 1 2 3wire diameter 0.355 0.355 0.800 mm
number of turns 65 33 17 #
on a FerroxcubeEFD25/13/9-3C96 core with a300µm airgap
Table A.8: The flyback converter’s main inductor winding data,initial design
89
wdg Lx Lx1 Rx1, Rx2 Rx3, Rx4 Cx1, Cx2
x = µH µH mΩ kΩ pF
1 564.2 140.9 80 600 3.92 145.4 2.52 50 155 4.13 38.4 0.375 8 41 61.8
C012 C013 C023
4 2 16 pF
Table A.9: Values of the flyback converter’s main transformerequivalent circuit components (figA.7), initial design
First Redesign
A wrong assumption shows that the inductance of the initial design is too high toconvert50W at the given minimal input voltage. Thus a redesign is done. Thesedata are used for nearly all the simulations and the whole filter design process. Theinductor is not built, the data is derived from the measurements of the previousdesign.
winding 1 2 3wire diameter 0.40 0.45 0.90 mm
number of turns 62 31 16 #
on a FerroxcubeEFD30/15/9-3C96 core with a550µm airgap
Table A.10: The flyback converter’s main inductor winding data,first redesign
wdg Lx Lx1 Rx1, Rx2 Rx3, Rx4 Cx1, Cx2
x = µH µH mΩ kΩ pF
1 413 137 80 600 3.92 117 2.5 50 155 4.13 30 0.37 8 41 61.8
C012 C013 C023
4 2 16 pF
Table A.11: Values of the flyback converter’s main inductor equiv-alent circuit components (figA.7), first redesign
90
Fourth Main Inductor
This is the inductor used on the prototype board. It provides an additional2W at15V output to supply the control and gate drive circuits. Furthermore the two mainoutputs are both split into two symmetric outputs of half the voltage. This reducesthe switching losses in the output diodes and thus allows the use of smaller devices.
Note the difference of the winding enumeration between measurement and schematicrelated illustrations. TableA.12 defines the correct mapping. The measurement re-lated enumeration scheme is used throughout this chapter.
relation winding enumerationschematic 1 2 3 4 5 6measurement 1 2a 2b 3a 3b 4
Table A.12: Mapping of winding enumeration between measure-ment and schematic related illustrations
1
bobbin
tape3
24
200um
121110987 6
54321
L1
L4
L3aL3b
L2a
L2b
Figure A.8: The flyback converter’s main inductor winding layout,fourth design
winding 1 2 3 4wire diameter 0.355 0.355 0.8 0.3 mm
number of turns 80 2× 20 2× 10 10 #
on a FerroxcubeEFD30/15/9-3C96 core with a890µm airgap
Table A.13: The flyback converter’s main inductor winding data,fourth design
91
wdg Lx Lx1 Rx1, Rx2 Rx3, Rx4 Cx1, Cx2
x = µH µH mΩ kΩ pF
1 589.0 317.3 350 82 147.3 31.6 195 43 35.4 6.2 22 24 9.5 1.6 80 1
C012 C013 C014 C023 C024 C34
8.2 9.5 6.9 42 14.5 14.1 pF
Table A.14: Values of the flyback converter’s main inductor equiv-alent circuit components (figA.7), fourth design; the simulationsneglect winding 4
Fifth Main Inductor
This inductor is built to reduce proximity losses. It has very high inter-windingcapacitances but very good magnetic coupling. Even though it is necessary to buildit with a shield as shown in figureA.9, it is built without1. Besides the changes inthe winding layout, this design uses a higher peak flux than the previous designin order to balance the core and winding temperatures, respectively losses. Theinductor is pin compatible to the previous one (figA.8). 3M Kapton tape is usedfor insulation. The primary winding is isolated from the others by two tape layersinstead of a single one.
bobbin
1a
tape2a 2b
3a 3b
41b
+ tapeCu shield
Cu shield+ tape
Figure A.9: The flyback converter’s main inductor winding layout,fifth design
winding 1 2 3 4wire diameter 0.45 0.45 0.8 0.3 mm
number of turns 64 2× 16 2× 8 8 #
on a FerroxcubeEFD30/15/9-3C96 corewith a500µm airgap (1mm total)
Table A.15: The flyback converter’s main inductor winding data,fifth design
1No suitable shielding material available within the allowed time.
92
wdg Lx Lx1 Rx1, Rx2 Cx1, Cx2
x = µH µH mΩ pF
1 699.1 9.1 175 52 180.1 1.0 90 243 46.7 0.1 20 854 10.9 0.5 60 309
C012 C013 C014 C023 C024 C34
94 80 27 73 28 22 pF
Table A.16: Values of the flyback converter’s main inductor equiv-alent circuit components (figA.7), fifth design
93
Appendix B
Non-Linear Model for Inductors
B.1 Model of the VAC CM Inductors
This is the mathematical, non-linear model for the used Vacuumschmelze ferritecoresT60006-L2009-W916 . An approximation of the parasitic capacitance isderived in [17]. The used model is based on an existing model for larger cores ofthe same family developed by Marcelo Lobo Heldwein. Taking an existing modelhas the advantage that the model is experimentally verified.
The formulae are given in Mathcad style notation. Mathcad’s definition operator:= is replaced by the normal equal sign. The variablei serves mostly as an indexinto arrays. In other words,fi is an array of frequency values, or in this case, thefrequency axis.j =
√−1 is used as the complex unit.
B.1.1 General Definitions
finit = 100Hz (B.1)
fend = 100MHz (B.2)
l = 1000 (B.3)
i = 0 . . . l (B.4)
fi = finit · 10log
„fend1Hz
«−log
„finit1Hz
«l
·i (B.5)
ωi = 2πfi (B.6)
µo = 4π · 10−7 Tm
A(B.7)
c = 2.99792458 · 108 m
s(B.8)
εo =1
c2µo(B.9)
94
B.1.2 Material Data: VITROPERM 500 F
Constants
Bsat = 1.2T (B.10)
µinit = 100000 (B.11)
ρvitro = 115µΩ ·m (B.12)
Permeability Curves
µmodi= µinit ·
1(fi
40kHz + 1)0.81 (B.13)
µxi = 10−7 ·
(fi
400Hz + 1)0.988
(fi
100kHz + 1)0.27 (B.14)
µ2i = µxi · |µmodi|2 (B.15)
µ1i =√
µ2modi
− µ22i
complex permeability (B.16)
µi = µ1i − j · µ2i (B.17)
B.1.3 Number of Turns
Core Data: VAC 9.8x6.5x4.5 - T6000-6-L2009-W914
OD = 11.2mm (B.18)
ID = 5.1mm (B.19)
H = 5.8mm (B.20)
le = 2.56cm (B.21)
Ae = 0.059cm2 (B.22)
AL,init = 25.5µH · 0.75 (B.23)
Aw =π
4ID2 (B.24)
95
Maximum Number of Turns
Pin = 50W (B.25)
Vrms =√
6 · 0.9 · 230V ·
√√√√ 62π·∫ 4π
6
2π6
sin(φ)2dφ (B.26)
Irms ≈√
23· Pin
Vrms(B.27)
Srms,ref = 4A
mm2(B.28)
Dw,ref = 2 ·
√Irms
πSrms,ref(B.29)
Dwire = 0.2mm (B.30)
Srms =Irms(
Dwire2
)2· π
(B.31)
Cinternal = π · (ID −Dwire) (B.32)
Nmax =Cinternal
3Dwire(B.33)
Desired Inductance, Low Frequency
Lm = 400µH (B.34)
N = ceil
(√Lm
AL,init
)= 5 (B.35)
Achieved Inductance, Low Frequency
AL,i = AL,init ·|µ1i |µinit
(B.36)
Lmi = AL,iN2 (B.37)
Rs,approx,i =0.05mΩ ·
(fi
13Hz + 1)1.8
(fi
50kHz + 1)1.7 (B.38)
96
Ls,approx,i = 500µH · 1(fi
65kHz + 1)1.5 (B.39)
Zi = j · 2πfi ·µi
µinit· LM (B.40)
Rcorei = < (Zi) (B.41)
B.1.4 Derivation of the Model
DC Wire Data
lcon = N · le conductor length (B.42)
DCu = 0.2mm (B.43)
DCu,iso = 0.25mm (B.44)
ACu,p =π
4D2
Cu (B.45)
leq = [2H + (OD − ID) + 2DCu,iso] (B.46)
T = 75C (B.47)
ρCu = 1.78 · 10−8Ω ·m ·[1 + 0.0039 ·
(T
1C− 20
)](B.48)
Rdc =N · leq · ρCu
ACu,p(B.49)
Skin Effect in the Wire
σCu =1
ρCu(B.50)
δi =1√
πfiσCuµo(B.51)
ζi =DCu√2 · δi
(B.52)
Kelvin Functions:
n = 0 . . . 1 n ∈ N, array index (B.53)
M = 81 (B.54)
97
KBern,i =M∑
p=0
(−1)n+p(
ζi
2
)n+2pcos[
14 · (n + 2p) · π
]p! · (n + p)!
(B.55)
KBein,i =M∑
p=0
(−1)n+p+1(
ζi
2
)n+2psin[
14 · (n + 2p) · π
]p! · (n + p)!
(B.56)
FRi =ζi
4 ·√
2·
[KBer0,iKBei1,i −KBer0,iKBer1,i
K2Ber1,i
+ K2Bei1,i
−KBei0,iKBer1,i + KBei0,iKBei1,i
K2Ber1,i
+ K2Bei1,i
](B.57)
Raci = Rdc · FRi · 2 (B.58)
Rac,approxi = Rdc ·[
fi
7MHz+ 1]0.82
(B.59)
Rsi = Raci + Rcorei (B.60)
Rpi =L2
miω2
i + R2si
Rsi
(B.61)
Lpi =L2
miω2
i + (Raci + Rcorei)2
ω2i Lmi
(B.62)
Rp,approxi =Rdc
(fi
a + 1)b·(
fi
c + 1)d
(fi
e + 1)f
(B.63)
Adjust a . . . f [Hz] to approximateRp with Rp,approxi . Thesea . . . f apply onlyto formulaB.63. FormulaB.64uses its own set of values for coefficientsa . . . m.They have to be figured out by aligning the curves ofLp,approxi andLpi .
Lp,approxi = a ·
(fi
b + 1)c(
fi
d + 1)e·(
fi
f + 1)g ·
(fi
h + 1)k(
fi
l
)m (B.64)
98
Parallel Capacitance
NL = 1 number of layersN1 = 3 ·N number of turns in layer 1N2 = 0 number of turns in layer 2
ε = 3.6 relative permittivity of the coatingecoat = 0.7mm core coating width
(B.65)
Davg = ID +OD − ID
2(B.66)
η =N2
N1(B.67)
leq = 2H + (OD − ID) + 2DCu,iso (B.68)
heq = Davg (B.69)
eeq =DCu,iso −DCu + ecoat
2(B.70)
Co = ε · εo ·leqheq
eeq· (N1 + N2) equivalent initial capacitance (B.71)
Cp =Co
3
(1 +
e2eq
h2eq
)· 1 + η + η2
(1 + η)2(B.72)
final capacitance for windings in the same direction
Cp,1 =Co
3
(1 +
e2eq
h2eq
· 1− η + η2
(1 + η)2
)(B.73)
final capacitance for windings in oposite direction
RCpi =πρvitroheq
Ae· FRi (B.74)
99
B.1.5 Inductor Models
Series Model
TheZLi of this model is used to design the CM filters.
ZLi =[
1Rsi + j · 2πfiLmi
+ j · 2πfiCp
]−1
(B.75)
ZL,approxi =[
1Rs,approxi + j · 2πfiLs,approxi
+ j · 2πfiCp
]−1
(B.76)
Parallel Model
ZL,pi =
[1
Rpi
+1
j · 2πfiLpi
+1
1j·2πfiCp
+ RCpi
]−1
(B.77)
ZL,p,approxi =[
1Rp,approxi
+1
j · 2πfiLp,approxi
+1
1j·2πfiCp
+ RCpi
]−1
(B.78)
100
104 105 106 107
102
103
104
Hz
Ω
104 105 106 107−90
−60
−30
0
30
60
90
Hz
deg model’s Z
L2model’s Z
L1Z
L2 measured
ZL1
measured
Figure B.1: The impedance curves of the two VAC cores used inthe flyback converter’s input CM filter.
101
Appendix C
Prototype Data
C.1 Schematic Diagram
RSTPE
Vin
GNDf
CM Input Filters & Rectifier
input.sch
GN
D
V15
GA
TE
DR
V
ISE
NSE
Vm+Vm-V
in
Control Circuit control.sch
GND
Vin
V15+
V15-
V30+
VA
UX
GA
TE
DR
V
ISE
NSE
V30-
V15GND
V30GND
Power Conversion
power.sch
3 X3C
2 X3B
1 X3A
3 X2C
2 X2B
1 X2AX1AX1BX1CX1D
Figure C.1: Flyback converter’s schematic diagram, sheet 1 of 4
102
R S T PE
1 2 3
4 5 6
L100
VA
C T
6000
-6-L
2009
-W91
4
C10
02n
2, Y
2C
101
2n2,
Y2
C10
22n
2, Y
2
C10
4
2n2,
Y2
C10
3
2n2,
Y2
3.5m
H, 2
x14
turn
s, 0
.2m
m w
ire30
0uH
, 3x4
turn
s, 0
.2m
m w
ireD
100
MR
A40
07T3
D10
1M
RA
4007
T3D
102
MR
A40
07T3
D10
3M
RA
4007
T3D
104
MR
A40
07T3
D10
5M
RA
4007
T3
C10
633
n, X
2
C10
733
n, X
2
C10
5
33n,
X2
Vin
GN
Df
1 2
3 4
L101
VA
C T
6000
-6-L
2009
-W91
4F1
00
500m
A, F
F101
500m
A, F
F102
500m
A, F
R10
0
CU3225K250G2
R10
1
CU3225K250G2
R10
2
CU3225K250G2
L102
100u
L103
100u
L104
100u
L105
220u
Figure C.2: Flyback converter’s schematic diagram, sheet 2 of 4: input filter
103
GN
D
V15
GA
TED
RV
ISEN
SE
Vm
+
Vm
-
R20
382
0RR
200
150k
R20
230
k
D20
1
TL43
1
C20
2
2u2
D20
0TC
LT11
03
Vin
GN
D
GN
D
Vcc
GN
D
C20
4
47n, GRM43DR73A473
R20
982
0k
R20
743
k
R20
843
k
D20
2
18V
D20
3
1n41
48
Vcc
D20
520
VD
204
US1
M
GN
D
CO
MP
1
FB2
CS
3
RC
4G
ND
5
OU
T6
VC
C7
REF
8U
200
UC
3844
R20
633
0R
Vcc
GN
D
R21
1
10k
R21
0
82k
C20
010
0nC
201
1u
GN
D
Vcc
C20
31u
R20
5
7k5
C20
62p
2
GN
DC
207
1n, 1
0%G
ND
Vre
f
Vre
f
R21
3
6k8,
1%
C20
810
0p
T200
BSP
300
R20
41k
1
R21
2
330R
, 1%
f = [2
17 -
271]
kH
z --
> [1
08 -
136]
kH
z op
erat
ion
C20
5
2p2
R20
11k
1
Figure C.3: Flyback converter’s schematic diagram, sheet 3 of 4: control circuit
104
GN
D
Vin
D301
US
1M
D302
US
1M
C309
100n, GRM55DR73A104
D303
ES
2G
D305
ES
2D
D307
ES
2D
7.5
W, 30V
17.5
W, 15V
2W
, 15V
C318
330u, N
AC
Z331M
25V
V15+
V15-
C300
100n
C313
4u7
C321
2u2
L301
33u, D
R73-3
30
R306
22R
C302
100n
V30+
VA
UX
C304
100n
GA
TE
DR
V
R301
6R
8
R305
0R
5, 350m
W
T300
EP
7-3
F3
C305
220n
C306
220n
D300
18V
R300
6R
8R
302
4k7
ISE
NS
E
LT
RT
GT
R303
4k7?
C310
1n, GRM31BR73A102
1
5
2
6 7 8 3 412
11
10
9
L300
EF
D30-3
C96
D304
ES
2G
V30-
C301
100n
C303
100n
D306
ES
2D
V15G
ND
1
2 3 4 5 6
17.5
W, -1
5V
C319
330u, N
AC
Z331M
25V
C320
68u, N
AC
Z101M
25V
R309
n.p
.
R308
n.p
.
R310
n.p
.
R312
n.p
.
R311
n.p
.
C311
n.p
., 2
00V
C312
n.p
., 2
00V
C315
n.p
., 1
50V
C316
n.p
., 1
50V
C317
n.p
., 1
50V
2x37 t
urn
s, 0
.2m
m
0R
5 s
hunt:
Wel
wyn L
R1206-R
50F
I (F
arnel
l 7746164)
R304
0R
047
0R
047 s
hunt:
ME
GG
ITT
TL
2B
R047F
TE
(F
arnel
l 156231)
C324
1u, 350VL
302
33u, D
R73-3
30
R307
22R
C314
4u7
C322
2u2
7.5
W, 30V
V30G
ND
C323
1u, 350V
R313
1M
R316
1M
R315
1M
R314
1M
T301
FQ
D2N
80
T302
FQ
D2N
80
P
GA
TE
Figure C.4: Flyback converter’s schematic diagram, sheet 4 of 4: power conversion
105
C.2 Component Placement on the PCB
Figure C.5: Top placement
Figure C.6: Bottom placement
106
C.3 PCB Layout, Original Size
Figure C.7: Top layer
Figure C.8: MidSignal, second layer
107
Figure C.9: MidPlanes, third layer
Figure C.10: Bottom layer
108
C.4 Bill of Material
C100 2n2, GA355DR7GC222KY02L D307 ES2D
C101 2n2, GA355DR7GC222KY02L F100 OMT250, 750mA
C102 2n2, GA355DR7GC222KY02L F101 OMT250, 750mA
C103 2n2, GA355DR7GC222KY02L F102 OMT250, 750mA
C104 2n2, GA355DR7GC222KY02L L100 VAC T6000-6-L2009-W914
C105 33n, GA355XR7GB333KY06L L101 VAC T6000-6-L2009-W914
C106 33n, GA355XR7GB333KY06L L102 100u, DR73-101
C107 33n, GA355XR7GB333KY06L L103 100u, DR73-101
C200 100n, 50V L104 100u, DR73-101
C201 1u, GRM21BR71E105KA99L L105 220u, DR73-221
C202 2u2, GRM21BR61E225KA12L L300 EFD30-3C96
C203 1u, GRM21BR71E105KA99L L301 33u, DR73-330
C204 47n, GRM43DR73A473KW01L L302 33u, DR73-330
C205 2p2, 50V R100 CU3225K250G2
C206 2p2, 50V R101 CU3225K250G2
C207 1n, 50V R102 CU3225K250G2
C208 100p, 50V R200 150k
C300 100n, 50V R201 1k1
C301 100n, 50V R202 30k
C302 100n, 50V R203 820R
C303 100n, 50V R204 1k1
C304 100n, 50V R205 7k5
C305 220n, 50V R206 330R
C306 220n, 50V R207 43k
C309 100n, GRM55DR73A104KW01L R208 43k
C310 1n, GRM31BR73A102KW01L R209 820k
C311 n.p., 200V R210 82k
C312 n.p., 200V R211 10k
C313 4u7, GRM31CF51H475ZA01L R212 330R, 1 %C314 4u7, GRM31CF51H475ZA01L R213 6k8, 1 %C315 n.p., 150V R300 6R8
C316 n.p., 150V R301 6R8
C317 n.p., 150V R302 4k7
C318 330u, NACZ331M25V R303 4k7
C319 330u, NACZ331M25V R304 0R047
C320 68u, NACZ101M25V R305 0R5, 350mW
C321 2u2, GRM31CR71H225KA88L R306 22R
C322 2u2, GRM31CR71H225KA88L R307 22R
C323 1u, 350V R308 n.p.
C324 1u, 350V R309 n.p.
109
D100 MRA4007T3 R310 n.p.
D101 MRA4007T3 R311 n.p.
D102 MRA4007T3 R312 n.p.
D103 MRA4007T3 R313 1M
D104 MRA4007T3 R314 1M
D105 MRA4007T3 R315 1M
D200 TCLT1103 R316 1M
D201 TL431..DBZ T200 BSP300
D202 18Vz T300 EP7-3F3
D203 1n4148 T301 FQD2N80
D204 US1M T302 FQD2N80
D205 20Vz U200 UC3844
D300 18Vz X1A BERG-1-1
D301 US1M X1B BERG-1-1
D302 US1M X1C BERG-1-1
D303 ES2G X1D BERG-1-1
D304 ES2G X2 BERG-1-3
D305 ES2D X3 BERG-1-3
D306 ES2D
C.5 Electrical Specification
Parameter Sym. Value Unit
Nominal input voltage, phase - neutral VN 230 Vrms
Guarantieed maximum input voltage Vin,max 253 Vrms
Theoretical maximum input voltage, not tested Vin,mth 280 Vrms
Minimum input voltage Vin,min ≤ 207 Vrms
Maximum ambient temperature TA,max 50 C
Efficiency at18.6W output load (12.6W /6.0W ) η1 72 %Efficiency at35.5W output load (10.7W /24.8W ) η2 76 %
The theoretical maximum input voltage is limited by the maximum input DC railvoltage of700V . It is not tested, but the affected components should theoreticallywithstand this voltage, according to their specification. This also applies to theboard layout.
The maximum ambient temperature varies depending on the load and whetherforced cooling is applied or not. It is also related to the maximum load to beapplied. See section7.3.3for details.
The maximum load is limited by the output diodes of the30V output. The loadat this output should be kept below25W to 35W , depending on the load at theother output, ambient temperature and cooling. The other strong limitation of themaximum output power is the maximum allowable voltage drop.
110
Glossary
D duty cycle ratio
Io output current
LiM main inductance of windingi (coupling factor= 1)
Np number of a primary winding’s turns
Pe core losses of an inductor
Po output power
Pw copper losses of an inductor
Ts switching period of a converter
VN RMS voltage between a phase and neutral
Vo output voltage
Xrms root-mean-square value of signalx(t)
X average value of signalx(t)
δi main inductance stray coefficient of windingi: Lσi = δiLiM
Iµ peak magnetisation current (e.g. in a transformer)
X peak value of signalx(t)
σi total inductance stray coefficient of windingi: Lσi = σiLi
fs switching frequency of a converter
CISPR The International Special Committee on Radio Interference
CTR Current Transfer Ratio, the gain of an optocoupler
EMC Electro Magnetic Compliance
EMI Electro Magnetic Interference
ESR Equivalent Series Resistance
LISN Line Impedance Stabilisation Network
n turns ratio of a transformer:nij := NiNj
= Nprimary
Nsecondary
PCB Printed Circuit Board
PFC Power Factor Correction
SMD Surface Mount Device
SMPS Switched Mode Power Supply
THD Total Harmonic Distortion of a signal
THT Through Hole Topology (to avoid THD: Through Hole Device)
111
Bibliography
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[10] Kollmann, R. andBetten, J.: Closing the Loop with a Popular Shunt Regu-lator, Power Electronics Technology, 2003; vol. Sept., pp. 30–36http://www.powerelectronics.com/
[11] Qu, S.andChen, D.: Mixed-Mode EMI Noise and Its Implications to FilterDesign in Offline Switching Power Supplies, IEEE Transactions on PowerElectronics, 2002; vol. 17, no. 4, pp. 502–507
[12] Tan, F. D. and Middlebrook, R. D.: A Unified Model for Current-Programmed Converters, IEEE Transactions on Power Electronics, 1995;vol. 10, no. 4, pp. 397–408
[13] Heldwein, M. L., Nussbaumer, T., Beck, F.andKolar, J. W. : Novel Three-Phase CM/DM Conducted Emissions Separator, Swiss Federal Instituteof Technology Zürich, Power Electronic Systems Laboratory, 2005
[14] Kolar, J. W. et al.: Status of the Techniques of Three-Phase Rectifier Systemswith Low Effects on the Mains, Technical University Vienna, Dept. ofElectrical Drives and Machines, 1999
[15] Nussbaumer, T., Heldwein, M. L. andKolar, J. W. : Common Mode EMCInput Filter Design for a Three-Phase Buck-Type Rectifier System, SwissFederal Institute of Technology Zürich, Power Electronic Systems Labo-ratory, 2006
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