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Abstract — This paper presents a new topology for the
electronic power transformer, also known as Solid State
Transformer (SST), for application in isolated grids, as an
alternative to the transformers nowadays used in transformer
stations. The proposed SST consists of Modular Matrix
Converters (MMC) that produce the voltages to be applied to the
high frequency transformers, guaranteeing nearly zero average
value at the working frequency of these transformers, 2 kHz,
therefore avoiding their saturation. High Frequency
Transformers (HFT) are used to reduce the volume and weight of
the overall system. The HFT is then connected to a Four Arms
Matrix Converter (FAMC), used to control the voltage and
frequency at the output and the power factor at input of the SST,
using a sliding mode control technique. To reduce harmonic
contents in input currents and output voltages it is used second
order filters. The system is designed in MATLAB/SIMULINK
software and it is sized to operate with voltages 10 kV / 400 V and
630 kVA rated power. Then, the proposed SST is tested under
several possible working conditions.
Index Terms — High Frequency Transformer, Matrix
Converter, Power Factor Regulation, Sliding Mode Control, Solid
State Transformer, Voltage Regulation.
I. INTRODUCTION
HE transformers are one of the most important assets in
electrical energy systems because they enable the voltage
change of a network to a most appropriate level, allowing
energy transmission at different voltage levels, and over long
distances.
Voltage regulation in the Low Voltage (LV) grid is usually
performed at no load, through tap changers. This regulation is
made by steps and doesn’t allow a continuous control of the
voltage in real time.
In the last years, there has been a significant increase of
decentralized energy production, in particular, in the LV grid,
through photovoltaic panels, wind turbines, biomass systems,
microturbines, etc. This new reality has introduced new
challenges to the Distribution System Operators (DSOs). In
particular, overvoltages in the LV grid produced by the
microgenerators, have become a major problem.
Therefore, issues as overvoltages caused by microgeneration
or voltage sags caused by short-circuits in the grid may arise.
The output voltage of the transformer can be disturbed by sags
and swells in the MV grid. In these cases, the SST can present
advantages, because it allows a continuous control of the output
voltage in real time, allowing a stable voltage amplitude, even
with sags or swells in the input.
The SST is a relatively recent technology and presents the
main features of classical transformers – galvanic isolation and
voltage transformation. It is composed by high frequency
transformers, which allows a substantial reduction in the total
volume and weight of the overall equipment. The use of power
electronic converters is required, because of the high frequency
transformers.
II. TRANSFORMER: STATE OF ART
A. Classic Transformers
In an electrical energy grid, the transformers are the heaviest
and the most expensive equipment. According to [2], the main
advantages of the classic transformers are: high efficiency,
robustness, reliability and relatively inexpensive. However,
they present some disadvantages as increased voltage drop for
higher loads, the sensibility to the output currents harmonics,
the voltage regulation at no load and performed by steps, the
losses without load and the oil presence, which can be harmful
to the environment, with the possibility of fire [2] [3].
B. Solid State Transformer (SST)
The SST can minimize or eliminate many of the classic
transformers disadvantages. However, they usually present
lower efficiencies, higher costs and their reliability has not yet
been tested, considering that they are a relatively recent
technology [2]. In comparison to the classic transformers, the
mains advantages of SST are [2]: lower volume and weight,
protection of the load from disturbances at the transformer input
(digs, overvoltages, frequency variation and harmonics), unity
power factor at the input, control of the output voltage, input
currents with lower harmonic contents, possibility of
integrating DC energy storage and protection of the MV grid
from disturbances at the output of the transformer.
The basic structure of SST is presented in fig. 1, where two
power electronics converters are used, one in the SST input and
another one in the SST output, and a high frequency transformer
in the middle. Also, these systems can have DC storage links in
the primary, secondary or both sides of the transformer.
Power Electronic Transformer as a Solution for
Voltage and Frequency Regulation in Isolated
Electrical Networks
D. R. Pereira, MSc Student, IST, S. F. Pinto, Member, IEEE, and J. F. Silva, Member, IEEE
T
2
Figure 1 – SST basic structure [11].
The core of HFT can integrate ferrite alloys, amorphous
metals or nanocrystalline alloys, being the nanocrystalline
alloys those which have a better compromise between losses
and the saturation of the magnetic flux density. However, they
present higher costs that, consequently, will rise the cost of the
SST.
The SST can be an alternative to the traditional transformers
in any electrical system but, due to their functionalities, its
implementation may be particularly interesting for certain
applications [2] [4], namely: electrical traction systems,
offshore energy production (for example, offshore wind
turbines) and smart grids. In the electrical grid, SST can be used
for interconnection between electrical power sources and the
distribution/transport grid, in substations or transformer
stations.
III. MATRIX CONVERTER
A. Single-phase matrix converter
The single phase matrix converter is composed by four fully
controllable bidirectional switches (fig. 2) which allow the
interconnection between two single phase systems. In this
converter, some topological constraints should be considered,
which impose restrictions in the switching states of the
semiconductors. It isn’t possible to short-circuit the input
phases of the converter (voltage source features) and it is not
allowed to leave the converter output phases open (current
source features).
Figure 2 – Single Phase Matrix Converter.
The switches are defined by the variable 𝑆𝑘𝑗 (1), with k and j
the indexes which represent the switches in fig. 2.
𝑆𝑘𝑗 = {
1 , if switch is OFF0 , if switch is ON
(1)
B. Four Arms Matrix Converter (FAMC)
The FAMC is composed by twelve fully controllable
bidirectional switches (fig. 3), that allow the interconnection
between a three-phase system without neutral conductor and
with features of voltage source and a three-phase system with
neutral conductor and features of current source. The switches
are assumed to be ideal.
.
Figure 3 - Four Arms Matrix Converter.
The state of each switch can be defined as in (1) and,
therefore, it is possible to establish a switching matrix 𝐒𝐢𝐧𝐭,
according to (2).
𝐒𝐢𝐧𝐭 = [
𝑆11 𝑆12 𝑆13
𝑆21 𝑆22 𝑆23
𝑆31 𝑆32 𝑆33
𝑆41 𝑆42 𝑆43
] (2)
In order to fulfill the topological restrictions of this converter,
the instantaneous sum of each row of 𝐒𝐢𝐧𝐭 should be always one,
which leads to 81 possible switching combinations.
Using the matrix 𝐒𝐢𝐧𝐭, we can relate the output voltages with
the input voltages and the input currents with the output
currents – (3).
[
𝑉𝐴
𝑉𝐵
𝑉𝐶
𝑉𝑁
] = 𝐒𝐢𝐧𝐭 [
𝑉𝑎𝑉𝑏
𝑉𝑐
] 𝑎𝑛𝑑 [
𝐼𝑎𝐼𝑏𝐼𝑐
] = 𝐒𝐢𝐧𝐭𝐓 [
𝐼𝐴𝐼𝐵𝐼𝐶𝐼𝑁
] (3)
1) Control of output currents
To control the matrix converter output currents it is used the
sliding mode controller [5] [6] [7], requiring the representation
of the possible switching states in the 𝛼𝛽0 coordinates, using
(5), where 𝐂𝐓 is the transpose of Concordia transformation
matrix, defined in (4).
𝐂 = √2
3
[ 1 0
1
√2
−1
2
√3
2
1
√2
−1
2−
√3
2
1
√2]
(4)
[
𝑉𝛼𝑉𝛽
𝑉0
] = 𝐂𝐓 [
𝑉𝐴𝑁
𝑉𝐵𝑁
𝑉𝐶𝑁
] (5)
3
In this control method, the output currents are compared with
their reference values, according to (6).
{
𝑒𝛼 = 𝐼𝛼𝑟𝑒𝑓− 𝐼𝛼
𝑒𝛽 = 𝐼𝛽𝑟𝑒𝑓− 𝐼𝛽
𝑒0 = 𝐼0𝑟𝑒𝑓− 𝐼0
(6)
The current errors (6) are quantified, through three level (-1,
0, 1) hysteresis comparators and the input voltages are divided
into twelve distinct zones, whose limits correspond to the
intersections between MV line-to-line voltages and their
symmetrical. Considering the errors from the comparators and
the localization zone of the input voltages, it is possible to
choose the switching states (called switching vectors) that
guarantee the tracking of the converter output currents.
There are three possible situations for the 𝛼 component error:
If 𝑒𝛼 > 0, then 𝐼𝛼𝑟𝑒𝑓> 𝐼𝛼 , so 𝐼𝛼 should be increased,
that corresponds to apply a vector with 𝑉𝛼 > 0;
If 𝑒𝛼 < 0 then 𝐼𝛼𝑟𝑒𝑓< 𝐼𝛼 , so 𝐼𝛼 should be decreased,
corresponding to a vector with 𝑉𝛼 < 0;
If eα = 0 then 𝐼𝛼𝑟𝑒𝑓= 𝐼𝛼 . In this situation it should
be chosen a vector with 𝑉𝛼 = 0. The same criterion is applied to the 𝛽 and 0 components of
the current errors.
After analyzing the 81 possible switching combinations, it is
concluded that there are always two vectors which are available
for the control of the output currents, providing some degree of
freedom to control the power factor at the converter input.
2) Power Factor Control at the input
The input currents control is made in dq coordinates, using
the Blondel-Park transformation, as in (7), where 𝜃𝑑𝑞 is the
transformation angle. At these coordinates, the reactive power
is given by (8), assuming a balanced and symmetrical system of
voltages at the converter input.
[
𝑋𝑑
𝑋𝑞
𝑋0
] = 𝐃𝐓 [
𝑋𝛼
𝑋𝛽
𝑋0
] 𝑤𝑖𝑡ℎ 𝐃 = [
𝑐𝑜𝑠 (𝜃𝑑𝑞) −𝑠𝑖𝑛 (𝜃𝑑𝑞) 0
𝑠𝑖𝑛 (𝜃𝑑𝑞) 𝑐𝑜𝑠 (𝜃𝑑𝑞) 0
0 0 1
]
(7)
𝑄𝑖𝑛𝑑𝑞= 𝑉𝑑𝐼𝑞 (8)
To obtain 𝑃𝐹 = 1, the reactive power, 𝑄𝑖𝑛𝑑𝑞, must be zero,
which implicates 𝐼𝑞𝑟𝑒𝑓= 0. The control is made by calculating
the difference between the reference current 𝐼𝑞𝑟𝑒𝑓 and the
measured current 𝐼𝑞 at the CMQB input, according to (9).
𝑒𝑖𝑞 = 𝐼𝑞𝑟𝑒𝑓− 𝐼𝑞
(9)
In this case, one hysteresis comparator is used to obtain two
levels for the error 𝑒𝑖𝑞 (-1,+1).
Two situations can be referenced:
If 𝑒𝑖𝑞 > 0 then 𝐼𝑞𝑟𝑒𝑓> 𝐼𝑞 , so it should be chosen a
vector to increase 𝐼𝑞;
If 𝑒𝑖𝑞 < 0 then 𝐼𝑞𝑟𝑒𝑓< 𝐼𝑞 , so it should be chosen a
vector to decrease 𝐼𝑞 .
Based on this referenced situations and taking into account
the two vectors available from the output currents control, it is
possible to choose the vector that better controls the power
factor at the converter input. In order to do that, the input
currents must be estimated through the output currents using a
predictive method.
When 𝑒𝛼 = 0, 𝑒𝛽 = 0 and 𝑒0 = 0 in the output currents
controller, the non-application of the ideal vector will not affect
significantly the shape of the output currents waveform. Thus,
it is possible in this, and only in this case, to choose the best
vector for the input power factor control from the 81 possible
switching states.
IV. SST – PROPOSED SOLUTION
The proposed topology for the SST is presented in fig. 4,
containing the Modular Matrix Converters (MMC), the high
frequency transformers (HFT) and the Four Arms Matrix
Converter (FAMC).
Figure 4 – Proposed solution for the SST.
A. Modular Matrix Converters (MMC)
The MMC are used to apply at the transformers input
voltages with zero average value at the working frequency of
the transformers, 2 kHz, to avoid their saturation. Due to
limitations that still exist in nowadays semiconductor
technologies, each CMM consists of several single phase matrix
converters connected in series. Therefore, the voltages in the
semiconductors won't destroy the electronic devices. This series
association also allows the increase of SST modularity.
The control of the CMM is made in 𝛼𝛽0 coordinates and it
is based on the expression for the calculation of the voltage
average value during one switching period, 𝑇𝑠 = 1/𝑓𝑠,
according to (10).
𝑉𝑚é𝑑𝑖𝑜 = 𝑓𝑠 ∫ 𝑣(𝑡)𝑑𝑡𝑇𝑠
(10)
The blocks diagram of the control system is presented in fig.
5, where 𝑉𝑇𝐴𝐹𝛼,𝛽is related to the CCM output voltages and
4
𝑉𝑎𝑏𝑐𝛼,𝛽′ is related to the CMM input voltages.
Figure 5 – Blocks Diagram of the CMM control system.
The blocks “Alpha Decision” and “Beta Decision” decide
what should be the relation between the inputs and the outputs
voltages of the CMM (+1 or -1) in order to keep the integrators
output, for each of the components α and β, within a specified
variation band. This variation is obtained in order to guarantee
that the switching frequency is in accordance with the operating
frequency of HFT.
The block “final decision” is responsible to take the final
decision about the voltages ratio, based on the requests from the
individual blocks mentioned above. If these blocks present, at
their outputs, symmetrical decisions (1 and -1), then the final
decision block chooses to keep the previous switching states,
corresponding to the decision of one of the individual blocks,
in order to reduce the switching losses
Using this method it is possible to guarantee that the input
voltages of the HFT present the waveform shown in fig. 6. In
this figure, it can be seen that the average switching frequency
is 2 kHz.
Figure 6 - Voltages at the input (red) and output (blue) of one of the CMM.
B. Four Arms Matrix Converters (FAMC)
The sliding mode control, discussed in section III.B for an
isolated matrix converter, can be used here, with some changes.
The voltages are measured at the entrance of SST and not at the
FAMC input. In the topology presented in fig. 4, the phase shift
between the SST input voltages and the FAMC input voltages
can be considered only dependent on the MMC controller.
Thus, for the calculation of the localization zone for the input
voltages of the FAMC, this fact is taken into account as may be
necessary to compensate a phase shift of 180 degrees.
On the other hand, to estimate the input current 𝐼𝑞 of the SST
based on the output currents, it is necessary to take into account
the switching state in the CMM and the transformation ratio of
the HFT.
C. Input Filter
The SST is connected to the MV grid using a LC filter, with
damping resistance. The equivalent single phase scheme is
shown in fig. 7.
Figure 7 – Single phase equivalent scheme for the input filter (star
connection).
The criterion for the dimensioning of the filter capacitors is
to minimize the phase shift between the current 𝐼𝑎 and the
current 𝐼𝑎′ . Therefore, the capacitance of the capacitors is given
by (11), where 𝐼𝑚𝑖𝑛 is the minimum working current of the SST
and 𝜙𝑖𝑛𝑚á𝑥 is the maximum allowed phase shift between 𝐼𝑎 and
𝐼𝑎′ [8].
𝐶𝑚á𝑥 =
√3𝐼𝑚𝑖𝑛 𝑡𝑔(𝜙𝑖𝑛𝑚á𝑥)
𝜔𝑟𝑒𝑑𝑉𝑀𝑇
(11)
The inductance is obtained from (12), where 𝜔𝑐𝑖𝑛 is the
cutoff angular frequency of the filter.
𝐿𝑖𝑛 =
1
𝜔𝑐𝑖𝑛2 𝐶𝑖𝑛
(12)
The damping resistance is obtained from (13) [8], where 𝜁𝑖𝑛
is the filter damping coefficient.
𝑟𝑝 =𝑍𝑓𝑖𝑛
2𝜁𝑖𝑛
com 𝑍𝑓𝑖𝑛= √
𝐿𝑖𝑛
𝐶𝑖𝑛
(13)
For delta connection, the capacitance required for the filter
capacitors is three times lower than the capacitance required for
star connection.
The filter parameters are shown in tab. 1.
Table 1 – Input filter parameters.
𝐿𝑖𝑛(𝑚𝐻) 20,9
𝐶𝑖𝑛(𝜇𝐹) 1,62
𝑟𝑝(𝛺) 109,25
5
D. Output filter
The output filter is star connected, according to fig. 8.
Figure 8 – SST Output filter.
The output inductance is given by (14), wherein 𝑓𝑐𝑜𝑚 is the
average switching frequency, 𝛥𝑖 is the current ripple and
𝑉𝑖𝑛𝑚𝑎𝑡𝑟𝑖𝑥 is the line-to-neutral voltage at the FAMC input [1].
𝐿𝑜𝑢𝑡 =√2𝑉𝑖𝑛𝑚𝑎𝑡𝑟𝑖𝑥
6𝑓𝑐𝑜𝑚𝛥𝑖 (14)
The capacitance is obtained considering an adequate cutoff
angular frequency, 𝜔𝑐𝑜𝑢𝑡, according to (15).
𝐶𝑜𝑢𝑡 =
1
𝜔𝑐𝑜𝑢𝑡2 𝐿𝑜𝑢𝑡
(15)
The output filter parameters are presented in tab. 2.
Table 2 – Output filter parameters.
𝐿𝑜𝑢𝑡(𝜇𝐻) 𝐶𝑜𝑢𝑡(𝜇𝐹) 500 200
E. Output voltage controller
The blocks diagram of the system used to size the output
voltage controller is shown in fig. 9, where 𝛼𝑣 and 𝛼𝑖 are the
gains of the current and voltage sensors, respectively. The
controller is one of the type PI (Proportional and Integral) and
it is assumed that the FAMC is represented by a delay 𝑇𝑑 ,
corresponding to half of the average switching period, and a
gain 1/𝛼𝑖, according to the transfer function shown in (16) [9].
𝐺(𝑠) =
1/𝛼𝑖
1 + 𝑠𝑇𝑑
(16)
Figure 9 - Blocks diagram of the system.
The closed loop transfer function, relatively to the output
voltage and to the reference voltage, is given, in the canonical
form, by (17) [9].
𝑉𝑜𝑢𝑡𝛼𝛽0(𝑠)
𝑉𝑜𝑢𝑡𝛼𝛽0𝑟𝑒𝑓 (𝑠)
=
𝛼𝑣𝑇𝑑𝐶𝑜𝑢𝑡𝛼𝑖
(𝑠𝐾𝑝 + 𝐾𝑖)
𝑠3 +1𝑇𝑑
𝑠2 +𝐾𝑝𝛼𝑣
𝑇𝑑𝐶𝑜𝑢𝑡𝛼𝑖𝑠 +
𝐾𝑖𝛼𝑣
𝑇𝑑𝐶𝑜𝑢𝑡𝛼𝑖
(17)
Comparing the denominator of (17) with the characteristic
polynomial given by (18), it is possible to obtain the parameters
of the PI controller using (19) [9].
𝐷(𝑠) = 𝑠3 + 1.75𝜔𝑛𝑠2 + 2.15𝜔𝑛2 + 𝜔𝑛
3 (18)
𝐾𝑝 =
2.25𝐶𝑜𝑢𝑡𝛼𝑖
1.752𝑇𝑑𝛼𝑣
𝑎𝑛𝑑 𝐾𝑖 =𝐶𝑜𝑢𝑡𝛼𝑖
1.753𝑇𝑑2𝛼𝑣
(19)
V. OBTAINED RESULTS
A. Low voltage (LV) grid
The implemented LV grid, to test the proposed SST, is shown
in fig. 10.
Figure 10 - Implemented LV grid.
The parameters of the LV grid represented in fig. 10 can be
found in tab.3. It should be noted that the distribution lines (DL)
are modeled by the 𝜋 equivalent scheme, wherein the
respectively values of capacitances, inductances and resistances
were taken from [10].
Table 3 - Parameters of the implemented LV grid.
Zone
Consumption Power per phase (kVA)
Power factor per phase
A B C A B C
1 67 67 67 0,8 0,8 0,8
2 62 62 69 0,8 0,8 0,9
3 25 23 20 0,9 0,8 0,85
4 7 8 8 0,9 0,8 0,8
Zona
Injected power (kVA) per phase
Power factor per phase
A B C A B C
5 29 23 26 1 1 1
DL Dist. [m]
𝑹𝒍𝒊𝒏𝒆 [𝛀]
𝑪𝒍𝒊𝒏𝒆 [𝝁𝑭]
𝑳𝒍𝒊𝒏𝒆 [𝒎𝑯]
1 300 Active conductor: 0,0531 Passive conductor: 0,1038
0,21 0,066
2 200 Active conductor: 0.0354 Passive conductor: 0,0692
0,14 0,044
Fig. 11 and fig. 12 show the proper behavior of the system in
terms of output voltage control, even with unbalanced output
currents, originating neutral current.
6
Figure 11 - SST output voltages, obtained for the LV grid test.
Figure 12 –SST output currents, obtained for the LV grid test.
In the medium voltage (MV) grid, the currents present some
switching noise and harmonic distortion (fig. 13). However,
these currents are nearly in phase with the respective line-to-
neutral voltages (fig. 14).
Figure 13 – SST input currents, obtained for the LV grid test.
Figure 14 - Voltage and current in phase A at the SST input, obtained for the
LV grid test.
1) Voltage sag at MV grid
A voltage sag was produced in MT grid with a depth of 30%,
during 3 cycles (fig.15). However, this voltage sag does not
produce any changes in the amplitude of the SST output
voltages (fig. 16).
Figure 15 - SST input voltages.
Figure 16 – SST output voltages.
As can be seen in fig. 17, the power factor remains nearly
unitary, even during the disturbance.
Figure 17 - Voltage and current in phase A at the SST input.
2) Voltage swell at MV grid
The overvoltage in the MV grid is 30% of the nominal
voltage, during of 3 cycles (fig. 18). Still, the output voltages of
the SST (fig. 19) remains unaltered in amplitude during the
perturbation, as it was intended.
Figure 18 - SST input voltages.
7
Figure 19 –SST output voltages.
Fig. 20 shows that despite the input currents decrease, the
power factor remains nearly equal to one, all the time.
Figure 20 – Voltage and current in phase A at the SST input.
3) Harmonics at MV grid
In this case, the voltages in the MV grid present 6% of fifth
harmonic, fig. 21. However, the SST output voltages, fig. 22,
show no noticeable harmonic content.
Figure 21 - SST input voltages.
Figure 22 - SST output voltages.
By observing the fig. 23, the fundamental component of the
current in phase A has nearly the same phase of the voltage in
phase A, showing a relatively good follow-up of the reference
current 𝐼𝑞𝑟𝑒𝑓.
Figure 23 – Voltage and current in phase A at the SST input.
4) Load variation in the low voltage (LV) grid
In this situation, the consumption in the zone 1 is reduced to
50% over 3 cycles, and the obtained output currents are shown
in fig. 24. The SST output voltages maintain the same
amplitude, except for some disturbances at the instants when
the load suddenly changes in the LV grid – fig. 25.
Figure 24- SST output currents.
Figure 25 - SST output voltages.
The reactive power absorbed by the SST remains nearly
equal to zero, as it can be seen in fig. 26.
Figure 26 – Voltage and current in phase A at the SST input.
8
5) Microgeneration variation
In this situation, there is a decrease of 50% in
microgeneration, which results an increase in the power
supplied by the SST to the LV grid, as seen in fig. 27, while the
SST output voltages keep a constant amplitude, except in the
distortions occurred during the disturbance moments – fig. 28.
Figure 27 - SST output currents.
Figure 28 - SST output voltages.
The power factor at the SST input remains nearly equal to
one, as it can be seen in fig. 29.
Figure 29 – Voltage and current in phase A at the SST input.
6) Bidirectional power flow
In this case, an inductive load and microgeneration are
connected to the SST output. The load parameters are presented
in table 3 for the zone 2. The power injected by the
microgenerators is set to gradually change between the values
presented in tab. 4.
Table 4 – Power injected by the microgenerators.
Injected Power per phase (kVA) Power Factor Start End
A B C Total A B C Total 1
17 13 15 45 100 80 90 270
The increased power injected by the microgenerators results
in the currents increase at the SST output, as it can be seen in
fig. 30. Nevertheless, the output voltages amplitude remain
constant– fig. 31.
Figure 30 – SST output currents.
Figure 31 – SST output voltages.
Fig. 32 shows a reversal of the active power flow through
the SST.
Figure 32 – Active power at the SST input.
VI. CONCLUSIONS
In this paper, the proposed SST presents robustness against
various scenarios, namely: voltage sags, voltage swells and
voltage harmonics, in the MV grid, and load/microgeneration
variation, in the LV grid.
The output voltages controller showed a good behavior, with
approximately zero tracking errors (eα, eβ and e0) and a very
fast dynamic, as it is usual in the control method that was
chosen.
Even though the SST input currents present some harmonic
9
content, this issue is not very relevant due to the amplitudes of
those currents. Moreover, the power factor remained always
nearly unitary, even during disturbances, revealing, therefore, a
good behavior of the power factor controller at the SST input.
In order to improve the input currents, it is important to do
further investigation in the filters design and the control
methods, including refined choices for the space vectors. It also
can be considered to use the SVM modulation process for the
four arms matrix converter.
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