Power Format Wp

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Introduction

Cadence led the industry with the ormation o the Power Forward Initiative

and the introduction o a complete RTL-to-GDSII low-power solution enabled

by the Silicon Integration Initiatives (Si2s) Common Power Format (CPF)

more than six years ago. At that time, the industry was not quite sure whether

the power intent side-le approach was the right methodology to address the

challenges o advanced low-power design. At present, the Cadence Low-

Power Solution has achieved wide adoption and has been proven by hundreds

o design tapeouts around the world. Many prestigious companiessuch as

ARM, Fujitsu, Faraday, GUC, Hisilicon, SandLinks, STARC , and TSMCalong

with numerous third-party tool suppliersincluding Apache, Atrenta, Calypto,

and SpringSothave adopted the power intent side-le approach and

endorse the Cadence Low-Power Solution publicly. For more success stories

about customers using the Cadence CPF-enabled solution, visit the ocial

Power Forward Initiative website and download A Practical Guide or

Low-Power Design.

Fundamental Dierences Between UPF and CPF

An alternative power ormat in the industry is IEEE 1801-2009, which includes

the Accellera Unied Power Format (UPF) 1.0. Although UPF 1.0 shares

similarities with CPF, it has some undamental dierences in how the power

intent is dened. In CPF, power intent is primarily described by an abstract data

object called a power domain starting at the register transer level (RTL). As the

design fow evolves rom RTL design to physical design, each power domain

will eventually be rened into a primary set o power supplies to uniquely

dene this power domain. UPF 1.0, however, lacks such abstraction capability,

so an RTL designer using UPF 1.0 has to describe the exact physical power

network at RTL. The main diculty o this approach is that RTL designers do

not have the complete physical power network inormation.

There are other major dierences between UPF 1.0 and CPF, such as how

the isolation and level shiter logic between power domains is dened. IEEE

1801-2009 introduces the concept o the supply set, which has many similar

Si2s contribution o the Open Low-Power Methodology (OpenLPM) to IEEE, in 2011 marked an

important milestone in the development o power ormat standards or the industry. Cadence,

among many other industry leaders, supports this contributionit shows the most promising path

or the industry to converge on one power ormat standard. Methodology convergence, however,

is a pre-requisite or uture power ormat convergence. This paper explains what methodology

convergence is; why the OpenLPM is a promising step toward power ormat convergence; and

how Cadence technologies can help customers develop low-power designs successully while the

industry is progressing along the path to convergence.

The Evolution o Power Format Standards:

A Cadence ViewpointAuthored by Qi Wang, Solutions Marketing Group Director, Cadence Design Systems, Inc.

Contents

Introduction .................................1

Fundamental Dierences Between

UPF and CPF ................................1

Power Format Convergence

Requires Methodology

Convergence ................................3

Cadence Low-Power Solution ......3

Summary .....................................4

Resources ....................................4
http://www.si2.org/?page=811http://www.powerforward.org/http://www.powerforward.org/DesignGuide.aspxhttp://www.powerforward.org/DesignGuide.aspxhttp://www.businesswire.com/news/home/20110531006613/en/Open-Low-Power-Methodology-Ushers-Era-Power-Interoperabilityhttp://www.businesswire.com/news/home/20110531006613/en/Open-Low-Power-Methodology-Ushers-Era-Power-Interoperabilityhttp://www.powerforward.org/DesignGuide.aspxhttp://www.powerforward.org/DesignGuide.aspxhttp://www.powerforward.org/http://www.si2.org/?page=811


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properties to the power domain in CPF, and many other constructs to close the methodology dierences between

UPF 1.0 and CPF (such as the way to speciy isolation and level shiter logic using the driving/receiving power

domain o a signal).

I1

Top

VSS

pon

VDD

VDD_SW

An example of a simple design with two

power domains. The top design has oneexternal supply VDD and one of theinternal blocks uses the switched version ofthe top supply, controlled by the signalponat the top level.

Figure 1: A simple design with power gating

To describe the above design using UPF 1.0, the power intent le would be as ollows:

create_power_domain PD_blue include_scope

create_power_domain PD_green elements { I1 }create_supply_net VDD domain PD_bluecreate_supply_net VSS domain PD_bluecreate_supply_net VDD_SW domain PD_bluecreate_supply_port VDDcreate_supply_port VSSconnect_supply_net VDD -port VDDconnect_supply_net VSS port VSScreate_supply_net VDD_SW domain PD_green reusecreate_supply_net VSS domain PD_green -reuseset_domain_supply_net PD_blue primary_power_net VDD primary_ground_net VSSset_domain_supply_net PD_green primary_power_net VDD_SW primary_ground_net VSScreate_power_switch PSW domain PD_blue \

output_supply_port {vout VDD_SW} input_supply_port {vin VDD} \control_port { control pon } on_state {on vin control} off_state { off !control}

Figure 2: Power intent in UPF 1.0

As indicated by Figure 2 above, designers using UPF 1.0 have to lay out almost the complete physical power

structure at RTL, which is not only a dicult task but also a completely unnecessary one. Using the power domain

concept in CPF or the supply set construct in IEEE 1801, the power intent o the example design can be described

easily at RTL, as shown below:

create_power_domain PD_blue include_scopecreate_power_domain PD_green elements { I1 }add_power_state PD_green state off

{-supply_expr {PD_green.primary.power == OFF}-logic_expr { !pon }}

create_power_domain PD_blue defaultcreate_power_domain PD_green instances { I1 } \

-shutoff_condition { !pon } \-base_domains PD_blue

Note: in this example the implicit supply set of power domain PD_green is used, referred to as PD_green.primary.

Power Intent in 1801 Power Intent in CPF

Figure 3: Power intent in 1801 and CPF

It is clear that the methodology to describe power intent at RTL by using either CPF or the new constructs in IEEE

1801 is a much better approach than that o UPF 1.0. Unortunately, the IEEE 1801 standard has included all the

constructs rom UPF 1.0. As a result, within the same standard there are two radically dierent methodologies to

describe the same power intent. Such a mix o methodologies in the same standard not only creates conusion or

users but also adds unnecessary diculties or tool vendors to support the standard. It is no surprise that two years

www.cadence.com 2

The Evolution o Power Format Standards: A Cadence Viewpoint


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ater the release o IEEE 1801-2009, there is still a lack o tool support or the new 1801 methodology or power

intent creation. Many EDA tool vendors who already support UPF 1.0 have chosen merely to continue with the

Accellera UPF 1.0 approach or their support o the IEEE 1801 ormat.

This explains why designers who want to use IEEE 1801-2009 are pressuring vendors to support the true essence o

the 1801-2009 specication, not just the UPF 1.0 method that was included in the initial 1801-2009 specication

or Accellera compatibility. There are strong signs both within the EDA industry and the user community that the

momentum is nally shiting to acilitate this change.

The ollowing picture demonstrates the current status o all power standards:

CPF 2.0 (Si2)

IEEE 1801-2009 (UPF 2.0)

UPF 1.0

Interoperable Subset

Figure 4: Current status of all power formats

Power Format Convergence Requires Methodology Convergence

To achieve ull interoperability among dierent vendors supporting di erent power ormats, the methodology

dierences between CPF and IEEE 1801 must be addressed. Cadence supports the eort to develop a converged

power methodology with the IEEE 1801 Working Group. There are two major objectives to be achieved through

this eort. First, IEEE 1801 needs to dene a process to censure the incompatible methodology as enabled by

some UPF 1.0 constructs (such as power supply netdriven power intent specication). Second, the Si2 needs to

contribute the Open Low-Power Methodology, or OpenLPM, which consists o a set o unique CPF eatures that are

currently not available in IEEE 1801. One such eature is the ormal hierarchical design approach, including macro

modeling or hardened intellectual property (IP).

To acilitate this methodology convergence eort, Cadence joined the IEEE 1801 Working Group as a voting

corporate member. The eort has already gained wide industry support, including rom heavyweights like TI,

Qualcomm, LSI, and STMicroelectronics. It will benet all EDA suppliers, as it eliminates redundant investment in

multiple and conficting methodologies and ormats.

Cadence Low-Power Solution

The Cadence Low-Power Solution currently enables mixed tool fow interoperability through support or UPF using

an import eature in the Encounter Conormal Low Power product. Conormal Low Power can import a UPF le

along with the corresponding design and library, and export a semantically equivalent CPF le. The CPF le can

then be used by other Cadence tools to continue the design fow. This approach has been successully used by

several customers on real production designs.

Until the converged methodology becomes a reality, Cadence will continue to provide ormat interoperability using

Conormal Low Power import support or IEEE 1801-2009. We will also continue to invest in CPF and the CPF-

enabled Cadence Low-Power Solution. As such, customers who have already adopted CPF are assured o a more

robust and mature Cadence solution going orward. For those who are not currently using CPF but who would like

to benet rom its dierentiated eatures, the production-proven Cadence Low-Power Solution will provide theneeded support or immediate design use. And or all users, the IEEE Working Groups methodology convergence

eorts ensure that their current and ongoing investment in CPF will be leveraged even ater the converged

methodology is available.

The CPF-enabled Cadence Low-Power Solution has been leading the industry with its comprehensive and mature

technology (see Figure 5). The classical technologies included in the solution are Incisive Enterprise Simulator (or

low-power unctional verication), Virtuoso AMS Designer (or power domainaware mixed-signal simulation),

Encounter RTL Compiler (or power-aware logic synthesis and design-or-test synthesis), Encounter Conormal

Low Power (or power-aware ormal verication), Encounter Test (or power-aware automatic test pattern

generation), Encounter Digital Implementation System (or power-aware physical implementation), Encounter

Power System (or power integrity signo analysis), and Encounter Timing System (or timing signo).

www.cadence.com 3



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Most recently, Cadence added Virtuoso and Palladium technologies into the CPF-enabled solution suite.

Automatic CPF import/export in the Virtuoso environment enables static verication o the power structures o a

schematic using Conormal Low Power. CPF-enabled emulation and hardware acceleration in the Palladium system

is the industrys only solution that addresses system-level verication o power management using real system

sotware or applications.

Chip PlanningChip Planning Solution

ESL DesignC-to-Silicon

Compiler

LogicDesign

Encounter RTLCompiler

Encounter Test

Analog/CustomDesign

VirtuosoPlatform

DigitalImplementationEncounter Digital

Implementation System

Package DesignAllegro Package

Designer

TrueMulti-ObjectiveDe

sign

System-LevelVerification

Incisive EnterpriseSimulator

Incisive SoftwareExtensions

Incisive EnterpriseSimulator

Incisive FormalVerifier

Encounter ConformalLow Power

Virtuoso AMSDesigner

FunctionalVerification

PlanandMetrics

IncisiveEnterpriseManager

Power IntentVerification

Encounter ConformalLow Power

Closed-LoopPower-AwareVerification

ExplorationChip Planning SolutionEncounter RTL Compiler

EstimationEncounter RTL CompilerIncisive Palladium DPA

AnalysisEncounter Digital

Implementation SystemEncounter Power System

SignoffEncounter Power SystemEncounter Timing System

Front-to-BackPowerPredictability

PowerIntent

Figure 5: Overview of Cadence technologies enabled by CPF

Summary

Cadence will continue to invest in low-power design technologies that deliver unique value to customers. We

are also committed to supporting customers with mixed power ormat fows. The UPF import capability inConormal Low Power can be used to address the immediate needs o customers using UPF who also want

to benet rom part o the Cadence Low-Power Solution. Over the long term, Cadence is dedicated to the

methodology convergence eort at IEEE and Si2, and we intend to ully support the converged methodology

standard once it becomes available.

Resources

Power Forward Initiative: http://www.powerorward.org/

A Practical Guide or Low-Power Design: http://www.powerorward.org/DesignGuide.aspx

Open Low-Power Methodology: http://www.businesswire.com/news/home/20110531006613/en/Open-Low-

Power-Methodology-Ushers-Era-Power-Interoperability

Power Intent Formats: Light at the End o the Tunnel? Sorin Dobre (Qualcomm), Pete Hardee (Cadence), ColinHolehouse (ARM), and Minh Chau and Rol Lagerquist (Texas Instruments): http://www.eetimes.com/design/

eda-design/4236219/Power-Intent-Formats--Light-at-the-End-o-the-Tunnel-

Cadence is transorming the global electronics industry through a vision called EDA360.

With an application-driven approach to design, our sotware, hardware, IP, and services help

customers realize silicon, SoCs, and complete systems efciently and proftably. www.cadence.com

2012 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Allegro, Conormal, Encounter, Incisive, Palladium, and

Virtuoso are registered trademarks o Cadence Design Systems, Inc. All others are properties o their respective holders. 22884 06/12 MK/DM /PDF

http://www.powerforward.org/http://www.powerforward.org/DesignGuide.aspxhttp://www.businesswire.com/news/home/20110531006613/en/Open-Low-Power-Methodology-Ushers-Era-Power-Interoperabilityhttp://www.businesswire.com/news/home/20110531006613/en/Open-Low-Power-Methodology-Ushers-Era-Power-Interoperabilityhttp://www.eetimes.com/design/eda-design/4236219/Power-Intent-Formats--Light-at-the-End-of-the-Tunnel-http://www.eetimes.com/design/eda-design/4236219/Power-Intent-Formats--Light-at-the-End-of-the-Tunnel-http://www.eetimes.com/design/eda-design/4236219/Power-Intent-Formats--Light-at-the-End-of-the-Tunnel-http://www.eetimes.com/design/eda-design/4236219/Power-Intent-Formats--Light-at-the-End-of-the-Tunnel-http://www.businesswire.com/news/home/20110531006613/en/Open-Low-Power-Methodology-Ushers-Era-Power-Interoperabilityhttp://www.businesswire.com/news/home/20110531006613/en/Open-Low-Power-Methodology-Ushers-Era-Power-Interoperabilityhttp://www.powerforward.org/DesignGuide.aspxhttp://www.powerforward.org/

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