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:// . . .
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C C D .
100
1
300
200
250DynamicPower
Possible trajectory for
P o w e r
C o n s u m p
t i o n
Source: ITRS Roadmap 2007
Cross-Over
2
1990 1995 2000 2005 2010 2015 2020
10 -2
10 -4
10 -6
150
100
50
0
Gate-OxideLeakage
Sub-ThresholdLeakage
g - e ec r cs
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0255075
100125150
Power Dens ity(Watts/cm 2)
Leakage Power
Dynamic Power
E : A C : .
0%
20%
40%
60%
80%
100%
Itanium 2 Itanium 3
Leakage Power
I/O Power
Dynamic Power
Itanium 2:180nm, 1.5V, 1.0GHz,221MTx (core+cache)
Itanium 3:130nm, 1.3V, 1.5GHz,410MTx (core+cache)
E : : .
250nm 180nm 130nm 90nm 65nm
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The basic strategy of power gating is to provide
two power modes: a low power mode between these modes at the
appropriatetime and in the appropriate manner to maximize
power savings while minimizing theimpact to performance.
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