Power Integrity: A Nanoscale VLSI Challenge Raj Nair, Anasim Corporation Oct. 2, 2008

Power Integrity: A Power Integrity: A Nanoscale VLSI ChallengeNanoscale VLSI Challenge

Raj Nair, Anasim CorporationRaj Nair, Anasim CorporationOct. 2, 2008 Oct. 2, 2008

October 2008October 2008 © 2008© 2008AnaSIMAnaSIM 22

OverviewOverview

Scaling & its less-known L*di/dt Scaling & its less-known L*di/dt challengechallenge

The Power Wall, breaking throughThe Power Wall, breaking through True-Electromagnetic PI analysisTrue-Electromagnetic PI analysis Energy & Noise ManagementEnergy & Noise Management Non-disruptive ScalingNon-disruptive Scaling SummarySummary


Scaling ProgressionScaling Progression


Planar CMOS transistor Planar CMOS transistor ScalingScaling

Gate

Source DrainBody

L

Tox

Gate

Source DrainBody

L

Tox

Gate

Source Drain

Body0.7 L

0.7 Tox

Gate

Source Drain

Body0.7 L

0.7 Tox

11

0.490.49

0.7

0.7

1

1

1Freq

1Delay

43.17.0

1Freq

7.0Delay

A lower Energy*Delay*Costproduct… but challenges led to a severe Power Wall


0.1

1

10

100

’71 ’74 ’78 ’85 ’92 ’00 ’04 ’08

Pow

er (

Wat

ts)

40048008

80808085

8086

286

386

486

Pentium®processors

Processor power doubles every ~36 months…

0.1

1

10

100

’71 ’74 ’78 ’85 ’92 ’00 ’04 ’08

Pow

er (

Wat

ts)

40048008

80808085

8086

286

386

486

Pentium®processors

0.1

1

10

100

’71 ’74 ’78 ’85 ’92 ’00 ’04 ’08

Pow

er (

Wat

ts)

40048008

80808085

8086

286

386

486

Pentium®processors


CPU On-Chip Voltage DroopsTime(s)Volts

(V)

+500.00m

+1.00

+30.00u +30.05u +30.10u +30.15u

Voltage Droops BlueScreens!

CPU On-Chip Voltage DroopsTime(s)Volts

(V)

+500.00m

+1.00

+30.00u +30.05u +30.10u +30.15u

Voltage Droops BlueScreens!BlueScreens!

Scaling Challenge: CPU Chip Scaling Challenge: CPU Chip PIPI

Power doublesevery ~36 months

Transistors doubleevery ~18 months

Operating modescreate load shifts

Which createsupply voltage‘droops’

Managed by package devices

(Original figure from C. Baldwin)(Original figure from C. Baldwin)

Mother Board

Capacitors

MicroprocessorHeat Spreader

PackageSubstrate

Pentium™ is a trademark of Intel® Corporation


Package CAP Loop-L scalingPackage CAP Loop-L scaling

and gives

Quintuplet and Triplet loop-L scaling

0.01

0.1

1

10

P858 P860 P1262 P1264

Process

loo

p-L

, p

H

Q-scaling T-scaling

Load shift induced voltage noise equation and derivation of packagecomponent characteristics scaling

Inversely related to process scaling(on-die cap) & (freq. scaling)2

65nm

<<0.1pH! References:Nair2001 Intel Assembly Technology Journal – Invited Paper on ‘Pathfinding’2002 Intel Technology Journal paper “Emerging Directions for Packaging…”

ftp://download.intel.com/technology/itj/2002/volume06issue02/art07_emergingdirections/vol6iss2_art07.pdf


On-die L & L*di/dt challengeOn-die L & L*di/dt challengeConsider a Roots of Two Scaling [1] scenario:

Capacitance-per-unit-area, Ca, scales by 2 , operating voltage scales by2

1, frequency

scales by 2 , and chip area scales by 2

1.

Following this constant-power scaling direction, and inspecting the change in Dynamic Voltage Droop in a unit area (/ua) of integrated silicon, we get:

Since C/ua scales by 2 and voltage scales by 2

1, I scales by 2 * 2 .

Assuming the effective L/ua doesn't change, C

L reduces by a factor of

2

1.

Multiplying I and C

L in the scaled process generation, the dynamic voltage droop amplitude:

IC

L scales by 2 * 2 *

2

1, or by a factor of 2 for constant power scaling.

References:Nair, Nair & Bennett, 2008EDADesignline® publications “A Power Integrity Wall follows the Power Wall” & “Dynamic Voltage Droops & Total PI”

http://www.edadesignline.com/howto/207100271

http://www.edadesignline.com/howto/208200205


The Power WallThe Power Wall

0.1

1

10

100

’71 ’74 ’78 ’85 ’92 ’00 ’04 ’08

Pow

er (

Wat

ts)

40048008

80808085

8086

286

386

486

Pentium™processors


References:Nair2001 Intel Assembly Technology Journal – Invited Paper on ‘Pathfinding’2002 Intel Technology Journal paper “Emerging Directions for Packaging…”

CPU power is now capped or reducingin Multi-Core, SoC Architectures

Pentium™ is a trademark of Intel® Corporation

ftp://download.intel.com/technology/itj/2002/volume06issue02/art07_emergingdirections/vol6iss2_art07.pdf


Scaling into the Nanoscale Scaling into the Nanoscale EraEra

Drain induced barrier lowering in short channel devices makes leakage increase with Vds (V-Supply)

Sub-threshold channel leakage dominates V-supply dependent leakage.

Source:Narendra & ChandrakasanLeakage in Nanometer Technologies, Springer Publications, 2005

Greater challenges…High-K is only a partial solution


Power, Performance, Power, Performance, LeakageLeakage

PowerPower Active power estimated Active power estimated

as (as (P=P=CVCV22f), f), VV P P With supply-V scaling, VWith supply-V scaling, VTT

must scale for must scale for performanceperformance

LeakageLeakage IIOFFOFF 10 10ее((VVTT/S)/S), and S ~= , and S ~=

85mV/decade85mV/decade IIOFFOFF rises 10X with 85mV rises 10X with 85mV

reduction in Vreduction in VTT Short channel barrier Short channel barrier

lowering (DIBL, ) lowering (DIBL, ) I IOFFOFF Source: S. Narendra, Tyfone, Inc.


Power TrendPower Trend

Reference: Narendra, ICCAD ‘03

Leakage power now equals active power!!Both strongly dependent upon supply voltage.

0%0%4%18

%42

%54%

0%

0

5

10

15

0.01 0.1 1

Channel length (um)

Po

wer

tre

nd

- 6 0 %

- 4 0 %

- 2 0 %

0 %

2 0 %

4 0 %

6 0 %

8 0 %

1 0 0 %

1.4X

Switching

Sub-threshold leakage

LeakageTotal

PresentPresentPresent


Performance w/ Voltage Performance w/ Voltage ScalingScaling

IIDSDS (V (VGSGSVVTT)) Linear dependence in Linear dependence in

deep nanoscale CMOSdeep nanoscale CMOS

Delay & FrequencyDelay & Frequency CCVVdddd/I/Idsds ~constant ~constant Nanoscale CMOS delay Nanoscale CMOS delay

and performance are and performance are roughly constant within roughly constant within a a ΔΔVVdddd range of Vrange of Vdddd

OpportunityOpportunity Use lowest possible VUse lowest possible Vdddd!! 0

100

200

300

400

500

0 0.2 0.4 0.6 0.8

Drain Voltage (V)

Dra

in C

urre

nt (

m A/m

m)

Vg = 0.8V

0.7V

0.6V

0.5V

0.4V

0.3V

Intel’s 15nm NMOS

0

100

200

300

400

500

0 0.2 0.4 0.6 0.8

Drain Voltage (V)

Dra

in C

urre

nt (

m A/m

m)

Vg = 0.8V

0.7V

0.6V

0.5V

0.4V

0.3V

Intel’s 15nm NMOS

25 nm

15nm

Chau et al., IEDM 2000Accurate supply noise estimation a must

}}}


Voltage Minimization is Key Voltage Minimization is Key

Total power strongly V-dependent Total power strongly V-dependent Active power proportional to VActive power proportional to V22 Leakage (tunneling) also related as VLeakage (tunneling) also related as Vxx (DIBL, E- (DIBL, E-

field, tunneling distance reduction with V)field, tunneling distance reduction with V) Energy / task minimized similarlyEnergy / task minimized similarly

ΔΔIIDSDS ~linearly related to ~linearly related to ΔΔV in nanoscale V in nanoscale processesprocesses

How low can you go? How low can you go? Digital: supply gatingDigital: supply gating Analog: fine grain supply voltage control Analog: fine grain supply voltage control Need accurate noise, power integrity estimationNeed accurate noise, power integrity estimation

Reference: Nair, AZ Nanotechnology Symposium 2006


Supply Noise Analyses Supply Noise Analyses ExamplesExamples

Chip grid IR drop analysisPower Grid == Resistance

Package simulationChip == current source

Are these the high levels of approximation (for design optimization) desirable??


On-Chip Analysis ChallengeOn-Chip Analysis Challenge

Atomic or Abstract? Atomic or Abstract? Analyze supply surface Analyze supply surface

ripples by ‘molecular’ ripples by ‘molecular’ interactions? interactions?

Polygonal AnalysesPolygonal Analyses Nanoscale IC’s today Nanoscale IC’s today

face face exploding exploding computational computational complexity (R, L, C, I, dI)complexity (R, L, C, I, dI)

Energy & EfficiencyEnergy & Efficiency Must know IC’s supply Must know IC’s supply

ripples for optimizationripples for optimization


Meeting the ChallengeMeeting the Challenge Differential Power Differential Power

Voltage is a potential Voltage is a potential difference; treat difference; treat power grid power grid differentiallydifferentially

Partition hierarchically & Partition hierarchically & exploit symmetryexploit symmetry

ECD: Continuum modelsECD: Continuum models Grid is uniform; treat as a Grid is uniform; treat as a

voltage-continuum voltage-continuum along a along a single surfacesingle surface USPTO PUB USPTO PUB

Include R, L, C and solve Include R, L, C and solve ‘true-electromagnetically’‘true-electromagnetically’

Abstract silicon, packageAbstract silicon, package Include Include distributed modelsdistributed models

for silicon loads, CAP, pkg for silicon loads, CAP, pkg and board componentsand board components


Abstraction & Physics-based Abstraction & Physics-based SimsSims

High levels of AbstractionHigh levels of Abstraction Power GRID as SURFACEPower GRID as SURFACE DISTRIBUTED circuit load DISTRIBUTED circuit load

currents & capacitancecurrents & capacitance SYMMETRY in physical as SYMMETRY in physical as

well as electrical aspects well as electrical aspects

Comprehensive ModelingComprehensive Modeling All All gridgrid electromagnetic electromagnetic

properties, R, properties, R, LL, C used, C used Actual block load current Actual block load current

profiles used; profiles used; di/dtdi/dt, load , load activityactivity factors included factors included

Physics based SimulationPhysics based Simulation Field solver employed for Field solver employed for

Maxwell’s equationsMaxwell’s equations on on ‘surfaces’ / NO ‘models’ ‘surfaces’ / NO ‘models’


On-Die CAP for Noise On-Die CAP for Noise ReductionReduction

With Die Caps

Without Die Caps

With Die Caps

Without Die Caps

Simple, lumped SPICE analyses indicate On-Die CAP helps in ΔVCC reductionArea cost, Gate Oxide leakage are concerns

Reference: Narendra, ICCAD ‘03


SoC Power Integrity SoC Power Integrity SimulationSimulation

Do CAPACITORS (reactive devices) really absorb/expend noise energy?

9 x 7mm chip

5nF /sq. cm distributedCAP

100mA peak noise pulseof 100pswidth

Power grid simulation

Explicit CAP LENS

Pulse noise source

Differential noise

R+L+C Dynamic Noise Simulation in -fp

Source: D. Bennett, ANASIM Corp., -fp power integrity aware floor planner, www.anasim.com

Animation slideUse slide show

http://www.anasim.com/


Single active circuit block in a 4x4mm IC

-fp ‘what-if’ experiments showing effect of gate switching -fp ‘what-if’ experiments showing effect of gate switching time and on-chip de-cap on maximum voltage droop.time and on-chip de-cap on maximum voltage droop.

resonance

Resonant effects; More / Less Resonant effects; More / Less CAP?CAP?


CAP Connectivity & NoiseCAP Connectivity & Noise

CAPACITOR blocks from IO ring corners connected into Core power grid increased noise in the core grid

Corner CAPs connected to IO Ring Corner CAPs connected to Core Grid

Analysis on a CLOCK chip

Source: ANASIM Corp., -fp power integrity aware floor planner, www.anasim.com



SoC Power Grid a Noise SoC Power Grid a Noise ConduitConduit

Low impedance grids Low impedance grids conduct and sum up conduct and sum up supply noise supply noise

Low energy loss in Low energy loss in global power grids global power grids more, sustained more, sustained noisenoise

Scaling and high Scaling and high perf. perf. high high local local di/dt &di/dt & loop loop inductanceinductance leads to leads to greater local noise greater local noise

Reference: Bennett, EEDesign 2003 article, www.anasim.com

Animation slide



Power Gating & Noise FlowPower Gating & Noise Flow

Source: ANASIM Corp., -fp power integrity aware floor planner, www.anasim.com

Power Gating transforms preferred pathways for noise flow in addition to transientnoise generation due to large switched capacitances…

Animation slide



Example: System-level Chip Example: System-level Chip Sim Sim

GUI or Netlist capture GUI or Netlist capture Chip NETLISTChip NETLIST Load current profiles are Load current profiles are

pulse100gap100 and pulse100gap100 and pulse200gap200pulse200gap200

SYMMETRY in physical as SYMMETRY in physical as well as electrical aspects well as electrical aspects

Experiment-1 resultsExperiment-1 results Chip grid ANIMATION & Chip grid ANIMATION &

MirrorMirror Notice substantial Notice substantial

voltage variation of top voltage variation of top left cornerleft corner

Cap 200pF added: Cap 200pF added: resultsresults

Chip grid ANIMATION & Chip grid ANIMATION & MirrorMirror

-fp simulation schematic illustration(hyperlinked image)


Chip Grid R, L + C DesignChip Grid R, L + C Design

With fixed on-chip capacitance value, increase in grid With fixed on-chip capacitance value, increase in grid wire width (reduction in resistance with minimal benefit wire width (reduction in resistance with minimal benefit in inductance) reduces noise to a pointin inductance) reduces noise to a point

Increase in capacitance on-die has sub-linear benefit in Increase in capacitance on-die has sub-linear benefit in noise reduction; more CAP is not always good…noise reduction; more CAP is not always good…

Noise at 10u wire width and varied on-chip cap

100

125

150

175

200

2 3 4 5

On-chip CAP (nf)

Noise (mv)

Maximum noise with grid wire width, 3nf cap

0

50

100

150

200

250

300

5 10 20 30 40 50

Wire width (microns)

Noise (mv)


How does it help design?How does it help design?f bridges the PI gap bridges the PI gap

Complements Complements IR Drop IR Drop traditional IC analysis with traditional IC analysis with true-electromagnetictrue-electromagnetic sims sims

EnergyEnergy: Optimizes supply : Optimizes supply voltage domain levels voltage domain levels

Optimizes Optimizes power grids;power grids; front-endfront-end CAP planning CAP planning

Reduces costReduces cost: Routing, : Routing, Chip Area, Design EffortChip Area, Design Effort

System-LevelSystem-Level analysis analysis

Minimizes costly design iterations

http://www.anasim.com/pi-fp-info.pdf




Dynamic Energy Dynamic Energy ManagementManagement

Power Power Performance, Performance, Energy Energy Battery Life Battery Life

Power & EnergyPower & Energy Task completion at low Task completion at low

power with low frequency, power with low frequency, but same energy (Pbut same energy (PT)T)

Must minimize voltage!Must minimize voltage!

Circuits/Design in SoC’sCircuits/Design in SoC’s Adaptive Voltage Scaling, Adaptive Voltage Scaling,

Dynamic Voltage scalingDynamic Voltage scaling PowerWise™ compliant PowerWise™ compliant

example in figureexample in figure Benefits in V-domainsBenefits in V-domains

Figure source: Mobile Handset Designline How To, 2007

Learning from CPUs’ VID bus and Adaptive Voltage Positioning for Power Integrity


External Voltage & Noise External Voltage & Noise ControlControl

Distributed Local Voltage RegulationDistributed Local Voltage Regulation Multiplies bandwidth: smaller the regulator, faster it can beMultiplies bandwidth: smaller the regulator, faster it can be Local placement ensures low latency, high loop bandwidthLocal placement ensures low latency, high loop bandwidth Decentralized, simple, hardware energy management Decentralized, simple, hardware energy management

designdesign Issues: Component testingIssues: Component testing

Stacked Active Passives Integration (SAPI)Stacked Active Passives Integration (SAPI) Non-disruptive, practical and low-costNon-disruptive, practical and low-cost

References: Nair, US Patents 6084385, 6081105, 5955870, USPTO publication 20030081389, US Patent 7291896

http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=6084385.PN.&OS=PN/6084385&RS=PN/6084385



http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=2&f=G&l=50&co1=AND&d=PG01&s1=20030081389&OS=20030081389&RS=20030081389


Prescott-CPU ANR InclusionPrescott-CPU ANR Inclusion

54p

Lmb

0.42m

Rmb

6m/n_oscRosc

3.3n/n_oscLosc

504u*n_oscCosc

10u*n_2tC2t

385p/n_2tL2t

6.5m/n_2tR2t

3.5p

Lpkg

0.26m

Rpkg40ps/188nRdie

V2

ANR Schematic & the PSC POR Model: Illustrations

Trace

Board

4m

R4

385p

L4

20m

R3

6n

L3

504uC1

3.3nL2

18n

L1

5V1

30m

R16mR2

Q1

ANR Component

Package conn.

22uC2

Reservoir CAP

G1

1

188nCdie

6.5m/n_idcRidc

60p/n_idcLidc

2.2u*n_idcCidc

0.22m

Rsock

18p

Lsock

20u*n_mlccCmlcc

1.2n/n_mlccLmlcc

3.5m/n_mlccRmlccvid

Vvr

Reference: Intel® Prescott CPU-PKG simulation model, ComLSI ANR


Prescott Pre-ANRPrescott Pre-ANR

Nom. VDD


Prescott Post-ANRPrescott Post-ANR

Nom. VDD

No spatial info,V as f(x,y,t)


Advanced SiP SimulationAdvanced SiP Simulation Near load systemsNear load systems

Active Noise Active Noise Regulator*Regulator*

Distributed Local (POL) Distributed Local (POL) Voltage RegulatorsVoltage Regulators

Spatial & TemporalSpatial & Temporal Power supply variation Power supply variation

in x, y and tin x, y and t Data can feed into Data can feed into

future future Dynamic Timing Dynamic Timing AnalysisAnalysis??

Simulation speed Simulation speed allows ‘allows ‘what-ifwhat-if’ ’ experiments for experiments for optimizationoptimization

Chip power grid noise

ANR attached to top left corner of gridReference:* Nair & Bennett, ComLSI Power Management Designline article http://www.powermanagementdesignline.com/howto/175800373

Animation slideUse slide show

http://www.comlsi.com/index.htm

http://www.powermanagementdesignline.com/howto/175800373


Managing Leakage PowerManaging Leakage Power

Classical techniquesClassical techniques Dual or Multi-VDual or Multi-VTT processes processes High-K gate oxideHigh-K gate oxide SLEEP Transistors (gate-level)SLEEP Transistors (gate-level)

Threshold voltage modulationThreshold voltage modulation Adaptive Body Bias / Dynamic Body BiasAdaptive Body Bias / Dynamic Body Bias

Supply voltage modulationSupply voltage modulation Adaptive Voltage Scaling / Dyn. Voltage Adaptive Voltage Scaling / Dyn. Voltage

ScalingScaling Power GatingPower Gating

Scalable, fundamental solutions? Scalable, fundamental solutions?

Most of these complicate the design/tool flowsubstantially…


Addressing Scaling AND Addressing Scaling AND PowerPower

Planar device ScalingPlanar device Scaling VVTT, V, VDDDD reaching limits reaching limits Loss of channel Loss of channel

controlcontrol Variations (VVariations (VTT, L, Leffeff…)…) Leakage limiting gate Leakage limiting gate

dielectric scalingdielectric scaling

Double Gate devicesDouble Gate devices Lower leakageLower leakage Lower parasitics (C, R)Lower parasitics (C, R) Lower fabrication costLower fabrication cost Lower delays Lower delays higher higher

performance! performance!

FinFET

Source: L. Mathew, SOI 2007


Planar Contender from Planar Contender from Intel®Intel®

Reference: Marczyk & Chau, Intel®, 2005

30, 20 and 15nm transistors claimed…

High-K integrated, provides low-leakage on-die CAP


Double Gate VariantsDouble Gate Variants

Gate 1

Gate 2

FINFET ITFET MIGFET

Source: L. Mathew, SOI 2007


Lower Total Cost of DG Lower Total Cost of DG DevicesDevices

Substantially reducedSubstantially reduced Processing stepsProcessing steps LeakageLeakage

ImprovedImproved Parasitics/PerformanceParasitics/Performance Record IRecord IONON/I/IOFFOFF

No area penalty / greater No area penalty / greater area utilizationarea utilization

Novel circuits feasibleNovel circuits feasible But challenges remainBut challenges remain

Process, DesignProcess, Design

Source: L. Mathew, SOI 2007 “Very promising for low power, low cost Handheld applications”


SummarySummary

Supply voltage minimization is key to IC Supply voltage minimization is key to IC energy managementenergy management

Accurate, true-electromagnetic, spatio-Accurate, true-electromagnetic, spatio-temporal noise analysis essentialtemporal noise analysis essential

Innovative power delivery and integrity Innovative power delivery and integrity management solutions are also neededmanagement solutions are also needed

CMOS Scaling has some distance to go CMOS Scaling has some distance to go with innovative deviceswith innovative devices

3-D (SiP, PoP, SAPI) integration will drive a 3-D (SiP, PoP, SAPI) integration will drive a more feasible continuation of Moore’s Lawmore feasible continuation of Moore’s Law


Anasim InfoAnasim Info Anasim bringing sea change into SoC Anasim bringing sea change into SoC

methodology with methodology with physics-based analyses andphysics-based analyses and high levels of abstractionhigh levels of abstraction

Benefits to chip resource usage, area, energy, Benefits to chip resource usage, area, energy, performance, and total design effort/costperformance, and total design effort/cost

Fills the GAPFills the GAP in Total Power Integrity analyses in Total Power Integrity analyses Non-disruptive, Non-disruptive, Win-Win-WinWin-Win-Win engagement engagement Links, tel. Links, tel. [email protected]@anasim.com +1 480-694-5984 +1 480-694-5984

AnasimAnasim White Papers White Papers pifp1.pdfpifp1.pdf, , pifp2.pdfpifp2.pdf, , pifp3.pdfpifp3.pdf Product - Product - -fp brochure-fp brochure ComLSI, ComLSI, parent coparent co..

mailto:[email protected]


http://www.anasim.com/papers/pifp1.pdf



http://www.comlsi.com/


Backup


PI-FP Tool EnvironmentPI-FP Tool EnvironmentSimulation netlist

.TRAN 200e-12

.PLOT 20

.ACC 0.0060

.PRINTNODE ALLGgrid1 0.2 0.2 0.0005 0.0080 0.030 10e-9 10e-9Igrid1 0.1 0.1 0.02 0.02 pulse.txt 1Ttline1 1 2 0.01 10e-9 100e-12 0.3Ngrid1 1 0.11 0.11

pulse.txt : Current Source

0 022E-12 0.03090169940E-12 0.05877852560E-12 0.08090169980E-12 0.095105652100E-12 0.1120E-12 0.095105652140E-12 0.080901699160E-12 0.058778525180E-12 0.030901699200E-12 0


PI-FP Tool Environment PI-FP Tool Environment contd.contd.

Multi-Grid Multi-Grid designdesign L calculationL calculation

Planar or 3DPlanar or 3D Include multiple Include multiple

chips in stacked chips in stacked or planar designor planar design

Code efficiencyCode efficiency Each GRID on its Each GRID on its

own core (CPU)own core (CPU)


Floorplanning / OptimizationFloorplanning / Optimization

GRID wire width, spacing, pitchGRID wire width, spacing, pitch Metal resource savings, routing / timing Metal resource savings, routing / timing

facilitationfacilitation DECAP optimizationDECAP optimization

Area savingsArea savings Block placement tweaks for PIBlock placement tweaks for PI

Noise generation, propagationNoise generation, propagation Chip-Package co-simulationChip-Package co-simulation Operating voltage (Energy) tuningOperating voltage (Energy) tuning Resonance detection and avoidance…Resonance detection and avoidance…


IO Ring impact on Core IO Ring impact on Core NoiseNoise

The voltage regulators, connecting between the IO Ring and the Core Grid are seen to become significant noise injection nodes with the inclusion of loads and the IO Ring. Pictures above are snapshots of dynamic plots.

Analysis on a customer CLOCK chip

Documents

Power Integrity: A Nanoscale VLSI Challenge Raj Nair, Anasim Corporation Oct. 2, 2008