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http://soc.hanyang.ac.kr
Power Management Circuits
2016년 2학기
한양대학교 노정진교수.
1
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Outline– DC-DC Converter
• Linear Regulator
• Buck Converter
• Boost Converter
• Basic Building Blocks
– Feedback Loop, Modeling and Stability
– Circuit Examples• Energy Harvesting
• Battery Charger
• Multiple Output System
• Dynamic Voltage Scaling
• Boost Converter for LEDs
• Multiphase DC-DC Converter
• Fully-Integrated DC-DC Converter
2
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DC-DC Converter
3
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Example of Power Management
http://soc.hanyang.ac.kr
Linear Regulators
(a) Regulator with source follower output stage
_
+VREF
IBIAS ILOADC
M0
VIN
A0
VG
VOUT
VSS
(b) Source follower with gate overdrive
(c) Common-source output stage
5
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Inductor and Capacitor
6
vL
iL
1
CiCv
1
2
2
1vCW
2
2
1LiLW
dt
dt
(J)
(J)
C
iC
v
iL L
v
Current:
Energy:
Current:
Energy:
http://soc.hanyang.ac.kr
Converter
+
v(t)
-
R
Vg(t)
+
vs(t)
-
DTs Ts t
Vs(t)
Vg
On Off
offon
on
TTT
CycleDuty
ggss
T
ss
Tss DVVDTT
dttvT
vs
)(1
)(1
0
Duty Cycle
SPDT switch and a load
7
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Voltage ripple
t
V
Actual waveform v(t)=V+Vripple(t)
DC component V
Actual output voltage
Waveform
In a well-designed converter, the output voltage ripple is small. Hence the waveform can be easily approximated by ignoring ripple
-> Small ripple approximation
VtvVv
tvVtv
ripple
ripple
)(,
)()(
Converter
8
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Buck Converter
+
v(t)
-
C R
L
Vg
12
iL(t)
Switch1 Switch2
+
V(t)
-
C R
L
Vg
iL(t)+
V(t)
-
C R
L
Vg iL(t)
Buck Converter
9
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Buck Converter analysisSwitch1
Inductor voltage and Capacitor current
Small ripple approximation :
)(tvvv gL
VVv gL
Switch2
Inductor voltage and Capacitor current
Small ripple approximation :
)(tvvL
VvL
Rtvii Lc /)(
RVIic /
Rtvii Lc /)(
RVIic /
10
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Inductor volt-second balance: applied to inductor over one switching period
Equation to zero and collect terms
The voltage conversion ratio is therefore
ssg
Ts
L TDVDTVVdttv ')()()(0
0)'( DDVDVg gDVV
DV
VDM
g
)(
Buck Converter analysis
11
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Boost Converter
Boost Converter
Switch1 Switch2
+
V
-
C R
L
Vg
)(tiL+
V(t)
-
C R
L
Vg
)(tiL
12
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Boost Converter analysis
Net volt-seconds applied to inductor over one switching period
Equation to zero and collect terms
The voltage conversion ratio is therefore
t
VL(t)
Vg
DTs D`Ts
Vg-V
sgsg
Ts
L TDVVDTVdttv ')()()(0
0')'( VDDDVg
DDV
VDM
g
1
1
'
1)(
'D
VV g
13
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Switch1
Inductor voltage and Capacitor current
Small ripple approximation :
Switch2
Inductor voltage and Capacitor current
Small ripple approximation :
Rvivv cgL /
RViVv cgL /
Rviivvv LcgL /
RvIivVv cgL /
Boost Converter analysis
14
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Capacitor charge balance
Collect terms and equate to zero
Eliminate V to express in terms of Vg
ss
Ts
c TDR
VIDT
R
Vdtti ')()()(
0
0')'( IDDDRV
RD
VI
'
RD
VI g
'2
t
iC(t)
-V/R
DTs D`Ts
I - V/R
Boost Converter analysis
15
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Basic Buck Converter
• Basic DC-DC converter without protection circuits
VoutL
CR1
R2
Rload
Vg
compensator
bufferand
deadtimecontroller
S-Rlatchsawtooth
wavegenerator
comparator
clock
error ampVFB
Vref
reset
S
R
Qclock
generator
Vc
16
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Sawtooth Waveform
• Sawtooth waveform and clock generator
Vb
VCC
Ib
M1
clock
Comparator
Vsawtooth
C
17
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Buffer and Non-Overlapping Circuit
• Large power transistor requires buffer block
• Non-overlapping to reduce shoot-through current in power transistor
Pdr_b
Ndr
VCC
VSS
VCC
VSS
18
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PI Compensator
• OTA and external R-C components
1C
1R2C
OTAVc
19
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OTA Error Amplifier
• Conventional Mirror OTA– Load cap=10pF– Tail current=200uA, quiescent output current=400uA
• Cascoded output may be used for higher gain– Drawback: limited output swing
VpVn
Vo
M1 M2
M3 M4
It
M0
M6
M8M7
M5
Vss414 1
Vb
20
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High-Performance Error Amp.
• Gain Boosting Technique– Load cap=10pF
– Tail current=200uA, quiescent output current=40uA
VpVnVo
M1 M2
M3 M4
It
M0
M6
M8M7
M5
Vcc
Vss
M9 M10
M12M11
M13 M14
41814 1 8 1
Vb
21
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Current Sense Schemes
• Current sense resistor in series with power transistor– Most accurate technique
– Additional resistance causes higher power loss
• Use turn-on resistance of power transistor for current sense
– Turn-on resistance varies too much for process, temperature, etc.
• Current sense circuits– accurate
– Circuit design is complicated
– Extra quiescent current loss
22
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Current Sense Circuit
• Current sense circuit for Buck converter
MP2
R
CO
L1
_ +
MS2
MR
M2 M1
MP1
MS1
MN1
VC
IO
VO
I1I1
VB
VQ
IP1IP2
Isen
Vadd
VIN
VA
VIN
VQ
23
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Current Programmed Control
+
v(t)
-
R
+
-
+
vg(t)Switching converter
vref
Compensatoric
d(t)
CurrentProgrammed
controller
Convertervoltage and
current
statetindependenanlongerno
titi cTSL
)()(
24
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C
+
v(t)
-
R
L
Clock
Analog Comparator
Rf
S Q
R
Latch
is(t)Rf
MeasureSwitchCurrent
is(t)
vg(t)
is(t) iL(t)
D1
Q1
0 Ts
ic(t)Rf
< Buck Converter >
< Current Programmed Controller >ControlInput
+
-
Compensator+-
vref
v(t)
< Conventional output voltage controller >
Current Programmed Control
25
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Small-Signal Modeling and Stability
26
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DC Transformer Model
Basic Equation of an ideal dc-dc converter
Switchingdc-dc
converter
+
Vg
-
Control input D
Ig
+
V
-
I
Powerinput
Poweroutput
outin PP VIIV gg
gVDMV )( )(DM
II g
27
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DC Transformer Model
+
Vg
-
Ig
M(D)I
Dependent Source
+-
M(D)Vg
+
V
-
I
Powerinput
Poweroutput
. .
1 : M(D)Ig I
+
V
-
Poweroutput
Powerinput
+
Vg
-
Control input DDC Transformer
28
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DC Transformer Model
4. Solve circuit3. Push source through transformer
2. Insert dc transformer model1. Original system
Switchingdc-dc
converter
D
+
V
-
I
R
+
Vg
-
R1
+
V1
-
+
V
-
R
M(D)R1
M(D)V1
2
121 )(
)(RDMR
RVDMV
. .
1 : M(D)
+
V
-
+
Vg
-
R1
R
+
V1
-
29
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AC Modeling
Buck-Boost Converter
+
v(t)
-
C R
1 2
L
i(t)vg(t)
+
v(t)
-
C RL
i(t)vg(t)
Switch1 Switch2
+
v(t)
-
C RL
i(t)vg(t)
30
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AnalysisSwitch 1
Inductor voltage and capacitor current
Small ripple approximation:
Low frequency averaged value:
)()(
)( tvdt
tdiLtv gL
R
tv
dt
tdvCtic
)()()(
gL Vv R
Vic
TsgL tvdt
tdiLtv )(
)()(
R
tv
dt
tdvCti Ts
c
)()()(
Inductor voltage and capacitor current
Small ripple approximation:
Low frequency averaged value:
Switch 2
)()(
)( tvdt
tdiLtvL
Rtv
tidt
tdvCtic
)()(
)()(
TsL tvdt
tdiLtv )(
)()(
Rtv
tidt
tdvCti Ts
Tsc
)()(
)()(
VvL RV
Iic
31
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Linearization Process
Rtv
titddttvd
C TsTs
Ts
)()()('
)(
TsTsgTs tvtdtvtd
dt
tidL
)()(')()(
)(
TsTsg titdti )()()(
Nonlinear because of multiplication of the time-varying quantity
with other time-varying quantities such as i(t) and v(t).
If the converter operates in steady-state condition
DIIRD
VIVD
DV gg ,
','
32
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DC quiescent values plus small ac variation
)()(
)()(
tdDtd
tvVtv ggTsg
)()(
)()(
)()(
tiIti
tvVtv
tiIti
ggTsg
Ts
Ts
For inductor voltage, insert the perturbation expression
))())(('())())((())((
tvVtdDtvVtdDdt
tiIdL gg
)('))((1))(1()(' tdDtdDtdtd
Remove DC term and second-order terms
)()()(')()(
tdVVtvDtvDdt
tidL gg
Linearization Process
33
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For capacitor current, insert the perturbation expression
R
tvVtiItdD
dt
tvVdC
)())()()('(
))((
dIR
tvtiD
dt
tvdC
)()('
)(
Remove DC term and second-order terms
))())((()( tiItdDtiI gg
)()()( tdItiDti g
Remove DC term and the second-order terms
For input current, insert the perturbation expression
Linearization Process
34
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)()()(')()(
tdVVtvDtvDdt
tidL gg
+-
- +
Dvg(t)
L
^
^
^
^
(Vg-V)d(t)
+ L di(t)/dt -D`v(t)
^
^RCId(t)
C dv(t)/dt +
v(t)
-
^
v(t)/R^D`i(t)^
dIR
tvtiD
dt
tvdC
)()('
)(
^
^ ^I d(t) ^D i(t)vg(t)
ig(t)
)()()( tdItiDti g
Linearization Process
35
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Small-Signal Equivalent Circuit
^
^I d(t)^D i(t)
^^
^RC
I d(t)
D’ i(t)
C dv(t)/dt v(t)/R^
+-
-+
D`v(t)Dvg(t)
L
+ L di(t)/dt -
^
^
(Vg-V)d(t)
^
^
vg(t)^
ig(t)
RC
v(t)/R^
L1 : D
. . .
.
D` : 1
vg(t)^
ig(t)
^I d(t)
+ L di(t)/dt -^
(Vg-V)d(t)^
^I d(t)
+
v(t)
-
^
Use Transformer
36
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Canonical Model
All PWM CCM DC-DC converters perform similar basic function
* They transform voltage and current levels, ideally with 100% efficiency
* Low-pass-filter of waveforms
* Control of waveforms by variation of duty cycle
Canonical Model
* A standard form of equivalent circuit model, which represents above physical properties
* Plug in parameter values for a given specific converter
37
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Development of Canonical Model
DC transformer model.
. .
1 : M(D)
Power input Control input Load
+
V +v(s)
-
R
D
+
Vg +vg(s)
-
^ ^AC variations in vg(t) induce ac
variations in v(t).
38
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Control to output transfer function: )()()()(
)()( DHDMse
sd
svsG evd
Inclusion of ac duty cycle variation.
Development of Canonical Model
39
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Canonical Modeling Example (Buck-Boost Converter)
^
I d RC
+
V+v(s)
-
^
L1 : D
. . .
.
D’ : 1
Vg+vg(s)
I d
(Vg - V )d(t)^
^
^
I d RC
+
V+v(s)
-
^
L1 : D
. . .
.
D’ : 1
Vg+vg(s)
^ d I/D’
d (Vg-V)/D
^
^
I d RC
+
V+v(s)
-
^
L1 : D
. . .
.
D’ : 1
Vg+vg(s)
^
d (Vg-V)/D
d I/D’d I/D’ ^^
.Node A
40
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^
I d RC
+
V+v(s)
-
^
L1 : D
. . .
.
D’ : 1
Vg+vg(s)
^
d (Vg-V)/D
d I/D’^
d (sLI)/D’
^
I d RC
+
V+v(s)
-
^
L1 : D
. . .
.
D’ : 1
Vg+vg(s)
^
d (Vg-V)/D d (sLI)/D’
.d DI/D’
d DI/D’
^
^
Node B
2
RC
+
V+v(s)
-
^
L/D’
.
.
D’ : D
Vg+vg(s)
(I/D’)d(s)
{(Vg-V)/D-(sLI)/(DD`)}d(s)^
^
^
Canonical Modeling Example (Buck-Boost Converter)
41
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Canonical Model Summary
Converter
Buck
Boost
BoostBuck
)(DM Le )(se )(sj
D LD
V2 R
V
'
1
D 2'D
L)
'1( 2 RD
sLV
RD
V2'
'D
D 2'D
L)
'1(
22 RD
sDL
D
V
RD
V2'
42
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Feedback Loop
• Complete DC-DC converter with feedback loop
Transistor gate driver
C
+
v
-
L
Pulse-width modulation
vg D1
Q1
< Switching Converter >
Load
iload
Power input
H(s)
+Gc(s)
vc
+-ve
Hv
Error signal
Sensorgain
Compensator Referenceinput
vref
43
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Effect of Negative Feedback on Network TransferFunctions
Three independent input Control input variation
Power input voltage variation
Load current variation
Output variation can be expressed as
)(sd
loadi
gv
)()()()()()()( sisZsvsGsdsGsv loadoutgvgvd
v
44
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Effect of Negative Feedback
functiontransferouputtocontrolconvertersd
svsG
load
g
i
vd
v
0
0)(
)()(
functiontransferoutputtolineconvertersv
svsG
loadidg
vg
00)(
)()(
impedanceoutputconvertersi
svsZ
gv
dload
out
0
0)(
)()(
45
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Small-Signal Model
46
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Complete Block Diagram
Gc(s)
H(s)H(s)v(s)
1VM
ve(s)Reference
input
vref(s)Errorsignal
CompensatorPulse-widthmodulator
Sensorgain
vc(s)^
^
^^
-+v(s)
Duty cyclevariation
Output voltagevariation
-+
Gvg(s)ac linevariation
Zout(s)
Load currentvariation
Gvd(s) +
iload(s)^
d(s)^
Converter power stage
vg(s)^
^
47
http://soc.hanyang.ac.kr
Effect of Negative Feedback
Mvdc
outload
Mvdc
vgg
Mvdc
Mvdcref
VGHG
Zi
VGHG
Gv
VGHG
VGGvv
/1/1/1
/
T
Zi
T
Gv
T
T
Hvv out
loadvg
gref
111
1
""/)()()()( gainloopVsGsGsHsT Mvdc
: Product of gains around the forward and feedback paths of the loop.
)(sT
48
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Loop Gain T(s)
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
80dB
60dB
40dB
20dB
0dB
-20dB
-40dB
1pf
1zf
cf
2pf
decadedB /40
decadedB /20
decadedB /40
dBQdBT0
T
f
Example of loop gain T(s)
2
2
11
0
1)(1
)1()(
ppp
z
ssQ
s
s
TsT
49
http://soc.hanyang.ac.kr
T/(1+T)
1
11
TforT
Tfor
2
2
11
0
1)(1
)1()(
ppp
z
ssQ
s
s
TsT
T
T
1
c
c
ffT
frequencycrossoverfT
1
1
50
http://soc.hanyang.ac.kr
Graph of T/(1+T)
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
80dB
60dB
40dB
20dB
0dB
-20dB
-40dB
1pf
1zf
cf
2pfdecadedB /20
decadedB /40T
T
1
T
f
T
T
1
51
http://soc.hanyang.ac.kr
T/(1+T) & Frequencies
)(1
)(1)(
)(1
)(
)(sHsT
sTsHsv
sv
ref
M
vdc
refV
sGsGsHsT
sTsT
sHsv
sv )()()()(
)(1)(
)(1
)(
)(
At low frequencies, is large (good)T
At high frequencies, is small (bad)-> unable to reject the disturbance
T
52
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1/(1+T)
Line and load variations are rejected by 1/(1+T(s))
11
1)(
1
Tfor
TforsT
)(11
sT
53
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Graph of 1/(1+T)T1
1
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
80dB
60dB
40dB
20dB
0dB
-20dB
-40dB
-60dB
-80dB
1pf
zf
cf 2pf
decadedB /40
decadedB /20
decadedB /40
dBQdBT0
f
1pf
zf
dBQdB
T0T1
1
decadedB /20
54
http://soc.hanyang.ac.kr
1/(1+T) & Frequencies
)(
)(
)(1
)(
)(
)(
sT
sG
sT
sG
sv
sv vgvg
g
)(
)(
)(1
)(
)(
)(
sT
sZ
sT
sZ
si
sv outout
load
At low frequencies, is largeT
At high frequencies, is smallT
No effect on disturbance transfer function at high frequencies
)()(1
)(
)(
)(sZ
sT
sZ
si
svout
out
load
)()(1
)()(
)(sG
sT
sGsv
svvg
vg
g
55
http://soc.hanyang.ac.kr
Stability
Adding a feedback loop can cause an otherwise stable system to become unstable.
Phase margin test is sufficient for designing most voltage regulators.
56
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Phase Margin Test Positive phase margin: stable system
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
60dB
40dB
20dB
0dB
-20dB
-40dB
-60dB
-80dB
1pf
cf
frequencyC rossover
dBQ
T
f
zf
m
T
T
0
-90
-180
T
57
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Phase Margin Test Negative phase margin: unstable system
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
60dB
40dB
20dB
0dB
-20dB
-40dB
-60dB
-80dB
1pf
cf frequencyCrossover
dBQ
T
f
)0(m
T
T
0
-90
-180
-270
T
2pf
58
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Stability and Circuit Design
Examples
59
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Current-Mode Boost Converter• Boost Converter
– Deliver only DC power to the load
Vout
Buffer
Vg
Error Amp
CO
Clock
Comparator
S Q
R
Latch
D1
M1
+
-
Compensator vref
LR3
R4
+
-
RL
fc Ri
fs Ri
60
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AC Simulation: Control-To-Output• Current-mode boost converter without compensation
– Sufficient phase margin, but DC gain is too low
61
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AC Simulation: Compensator• PI compensator
– Adds two poles and one zero
62
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AC Simulation: Complete Loop• Complete feedback loop gain
– Higher DC gain for accurate output control
– Phase margin: 59
63
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• Energy source detected, then harvested.
• Harvested energy converted and saved in a capacitor or a secondary cell.
64
Energy Harvesting
* IDTechEX (England)“-The Energy Harvesting Market will growto 4.4 billion dollars in 2020 from 650 million dollars in 2010 “
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Energy Sources for Harvesting
65
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Energy Harvesting – Example 1
66
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Energy Harvesting – Example 2
67
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Energy Source Example – Solar Cell
68
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Energy Harvesting Circuits – Example 1
69
“An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection”, IEEE JSSC 2012
http://soc.hanyang.ac.kr
Start-Up from Low Harvesting Voltage
70
“An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection”, IEEE JSSC 2012
http://soc.hanyang.ac.kr
Energy Harvesting Circuits - Example 2
71
“A 10mV-input boost converter with inductor peak current control and zero detection for thermoelectric and solar energy harvesting with 220mV cold-start and -14.5 dBm, 915MHz RF kick-start”, IEEE JSSC 2015
http://soc.hanyang.ac.kr 72
Battery Charger
http://soc.hanyang.ac.kr
- 최근 이동성과 편리함, 그리고 다양한 기능을 갖춘 스마트 제품 등이 등장하면서, 전력을 공급하는 2차 배터리가 핵심 부품으로 자리 잡고 있다.
- 한번 사용하고 버리는 1차 배터리와 달리 충전할 수 있는 2차 배터리는 충전하여 사용할 수 있다.- 2차 배터리인 Li-ion 배터리는 에너지 밀도가 높고 소형화에 유리하며, 수명이 길다.- Ni-Cd에서 발생되는 메모리 효과 없어 최근 휴대용 기기에 많이 채택됨
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Battery Charger
http://soc.hanyang.ac.kr
Charger
LinearRegulator
SwitchingRegulator
VBAT
+
-+
-~ ~
Rectifier
AC
DC
VDD
ConstantCurrent
VBAT < VREF
RS
ConstantVoltage
VREF
VBAT
+
-
Icharge Icharge
>_VBAT VREF
- 배터리를 충전시키기 위하여 AC전압을 rectifier를 이용하여 DC로 변환- 변환된 DC는 battery charger를 통해 배터리를 충전시킨다.- Charger는 크게 linear charger와 switching charger로 분류됨
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Battery Charger
http://soc.hanyang.ac.kr
Itc
VCT
Charge current
Charge voltage
Constant current
Constant voltage
Trickle current
End of charge
Iend
(1/40C)
Ichg
VBAT
Time (s)
Vol
tage
(V
)
Cu
rren
t (A
)
■ Trickle current (TC) 방식- 작은 전류를 이용하여 안정적으로 배터리
를 충전시킴- 충전 시간이 길다
■ Constant current (CC) 방식- 큰 전류를 공급- 충전시간 단축- Overcharge에 대한 위험성 (배터리 손상)
■ Constant voltage (CV) 방식- 전압이 일정하게 해줌
- 안정적으로 배터리를 충전하기 위해 TC, CC, CV 방식이 모두 이용됨
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Li-ion 배터리의 충전 방식에 따른 전압 및 전류
http://soc.hanyang.ac.kr
VIN
VOUT
BatteryCIN
+
-
Blocking diode
Q1
Isense Vsense
Linear controller
■ Linear charger의 장점- 최소한의 외부소자를 이용함으로 전체 시스템 크기가 작다- 스위칭 동작이 없으므로 노이즈가 없는 출력전압 생성
■ Linear charger의 단점- 큰 입출력 전압차로 파워 트랜지스터에 소모되는 전력이 크다- Charging 전류가 증가할 수록 발열 문제가 심각
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Linear battery charger
http://soc.hanyang.ac.kr
Rce
llC
cell
Bat
tery
■ Switching charger의 장점- 스위칭 동작에 의한 높은 전력변환효율- 높은 부하 전류를 공급- 발열이 적다- 넓은 입력전압 범위 가짐
■ Switching charger의 단점- Linear charger에 비해 설계 복잡도 증가- 큰 인덕터 사용으로 전체 시스템 크기 증가- 스위칭 동작에 의한 노이즈 발생
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Switching battery charger
http://soc.hanyang.ac.kr
Linear chargerSwitching charger
Buck SEPIC
장점
⦿구현이 쉽다
⦿시스템 크기가 작다
⦿비용이 낮다
⦿넓은 입출력 전압 범위를
가진다
⦿효율이 높다
⦿하나의 인덕터를 사용한다.
⦿넓은 입출력 전압 범위를 가진다
⦿효율이 높다
⦿입력, 출력 사이 DC isolation 가
능
단점⦿효율이 낮다
⦿열문제가 크다
⦿시스템 설계가 복잡하다
⦿시스템 크기가 크다
⦿비용이 높다
⦿EMI 문제
⦿시스템 설계가 복잡하다
⦿시스템 크기가 크다 (두 개의 인
덕터 및 energy transfer 커패시터
가 필요하다)
⦿비용이 높다
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Linear charger와 switching charger의 비교
http://soc.hanyang.ac.kr 79
Multiple Output System
http://soc.hanyang.ac.kr
Single-inductor multi-output DC-DC converter- Footprint of conventional boost converter
TLV61225 PCB LayoutSupply voltage: 2.3 ~ 6.0VOutput voltage: 3.0 ~ 6.5V
Power inductor (LQH3NP)TLV61225 package
0.8mm
1.85mm
3mm
3mm
1.1mm
80
http://soc.hanyang.ac.kr
Single-inductor multi-output DC-DC converter
[1] Single-inductor multi-output (SIMO) dc-dc converters with high light-load efficiency and minimized cross-regulation for portable devices
Many LDO regulators Many switching converters SIMO
81
http://soc.hanyang.ac.kr
Design issues■ Cross-regulation■ Load/Line-regulation■ Stability■ Load current
Single-inductor multi-output DC-DC converter
SIMO structure Timing diagram
Cross-regulation
82
http://soc.hanyang.ac.kr
Single-inductor multi-output DC-DC converter
Multiple energizing cycles per switching period
[2] Single-inductor-multiple-output switching dc-dc converters
Single energizing cycles per switching period
83
http://soc.hanyang.ac.kr
Single-inductor multi-output DC-DC converter
Schematic of SIMO example
[3] A pseudo-CCM/DCM SIMO switching converter with freewheel switching
84
http://soc.hanyang.ac.kr 85
Dynamic Voltage Scaling
http://soc.hanyang.ac.kr
fVCP DDdyn 2
DVS embedded power management
[4] A DVS embedded power management for high efficiency integrated SoC in UWB system
Embedded power management module in UWB systems The DVS function in UWB system operation
86
http://soc.hanyang.ac.kr
Design issues■ Fast transient time ■ Variable output voltages■ Low power system
DVS embedded power management
[4] A DVS embedded power management for high efficiency integrated SoC in UWB system
Full structure of the power management module
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http://soc.hanyang.ac.kr 88
Boost Converter for LEDs
http://soc.hanyang.ac.kr
Boost converter for display
Smart phones (Galaxy[left] and iPhone[right])
LEDs
89
http://soc.hanyang.ac.kr
Design issues■ Efficiency■ Constant current driving ■ Fast transient
Boost converter for display
[5] A charge-recycling buck-store and boost-restore (BSBR) technique with dual outputs for RGB LED backlight and flashlight module
Function block of the conventional LCD panelWith LED backlight module
Power dissipation
90
http://soc.hanyang.ac.kr
A Multiphase buck converter with a rotating phase-shedding scheme for efficient light-load control.
Youngkook Ahn, Inho Jeon, and Jeongjin Roh, IEEE Journal of Solid-State Circuits, vol. 49, no. 11, pp. 2673-2683, Nov. 2014.
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Multiphase DC-DC Converters
http://soc.hanyang.ac.kr
(a) Heavy load, (b) Light load92
Operation of 4-phase converter.
http://soc.hanyang.ac.kr 93
Block diagram of 4-phase converter
http://soc.hanyang.ac.kr 94
Chip and measurement results
http://soc.hanyang.ac.kr
A 50-MHz fully-integrated low-swing buck converter using packaging inductors
Youngkook Ahn, Hyunseok Nam, and Jeongjin Roh, IEEE Transactions on Power Electronics, vol. 27, no. 10, pp. 4347-4356, Oct. 2012.
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Fully-integrated DC-DC Converter
http://soc.hanyang.ac.kr 96
Full integration of dc-dc converters
- Recently, according as miniaturization of portable appliance is accelerated, dc-dc converter's fullintegration is required.
- The dc-dc converter has difficulty doing full integration with large external passive components.
- The size of the filter inductor and capacitor can decrease with increased switching frequency.
- There are several challenges in the development of fully integrated dc-dc converters.
http://soc.hanyang.ac.kr 97
Comparison of low & high frequency operation
■ Low frequency operation (1 ~ 3MHz)
1. Advantages- High efficiency- Small inductor ripple current
2. Disadvantages- Large external passive component
( inductor, capacitor) - Require the number of I/O pins- Packaging parasitic
■ High frequency operation (50MHz ~ )
1. Advantages- Reduce the size of inductor and capacitor- Fast transient response- Full integration
2. Disadvantages- Low efficiency - Large inductor ripple current- Switching power loss
http://soc.hanyang.ac.kr 98
Inductor design for fully-integrated dc-dc converters
1. On-chip spiral inductor
- Suffer from high parasitic resistance and capacitor- A significant die area- Process variation- Low Q factor
2. Bonding-wire inductor
- Small parasitic components- High Q factor- Variations are depend on the accuracy of bonding machines (<5%)- It may require an additional bonding process
3. Packaging inductor
- It includes both parasitic inductance of bonding wires and lead frames- Small parasitic components
- High Q factor- Major errors are determined by the variation of the bond-wire length
On-chip spiral inductor
Packaging inductor
http://soc.hanyang.ac.kr 99
Example RLC values for different packages [*]
- Packages have different R-L-C values due to different characteristics, including size, layout, andlead counts.
-The value of packaging inductance can be controlled by compromising between pin counts used forimplementing the packaging inductor and the switching frequency of a dc-dc converter.
PackageBody size
(mm)Leadcount
R (Ω) L (nH) C (pF)
corner center corner center corner center
QFP 28 x 28 208 0.9 0.65 12.0 8.0 0.2 0.06
SSOP 5.3 x 10.2 28 0.3 0.25 2.9 1.3 0.2 0.08
MDIP 19 x 6.35 14 0.15 0.05 7.0 3.0 0.65 0.25
EBGA 27 x 27 215 0.75-0.9 0.6-0.8 5.0-7.8 2.5-4.0 0.08-0.12
■ Bonding wire parasitic elements are not included in this table
[*] National Semiconductor Application Note AN-1205, Electrical performance of packages. (2001). [Online]. Available:http://www.national.com.
http://soc.hanyang.ac.kr 100
Equivalent circuit model of package inductors and electrical data
Pac
kage
[*] MQFP data sheet, [Online]. Available: http://www.amkor.com.
http://soc.hanyang.ac.kr 101
Geometric reconfiguration of packaging inductors
- Positive mutual inductance increase the realinductance of packaging inductors, whereas negativemutual inductance decreases it.
-The spiral-shaped structure of the packaginginductor can suppress the negative coupling effect aswell as increase the total inductance
-The total inductance of the spiral-shaped packaginginductor can be written as [*]:
■ Spiral-shaped packaging inductor
negativepositiveStot MMLL
[*] J. Aguilera and R. Berenguer, “General consideration,” inDesign and test of integrated inductors for RF applications,Dordrecht, The Netherlands: KAP, 2003, ch. 2.
http://soc.hanyang.ac.kr 102
Fully-integrated buck converter
Vso
ft
PW
M1
- The designed chip employs the voltage-mode control to generate the PWM signal.
- The package lead and bonding wire inductance exiting in a package is to implement a high Q inductor.
http://soc.hanyang.ac.kr 103
Micrograph of the fabricated chip
Components Area (mm2)
Decoupling capacitor 3.53
Output capacitor 3.90
Power transistors 0.28
Controller 0.85
■ Area breakdown of a chip
* MIM capacitance = 1fF/um2
http://soc.hanyang.ac.kr 104
Test setup and performance summary
Technology 0.13-um CMOS
Die size 3.6 x 2.8 mm2
Peak efficiency 68.7% @VIN/VOUT =3.3 V/2.0 V76.8% @VIN/VOUT =2.5 V/1.8 V
Switching frequency 50 MHz
Inductor 19.9 nH (packaging inductance)
Output capacitor 3.4 nF (MIM capacitance)
Decoupling capacitor 3 nF (MIM capacitance)
Input voltage 2.5–3.3 V
Load current Maximum 300 mA
Output voltage ripple 300 mV
Output voltage drop 9% @100% IMAX
Line regulation 7.14%/V@VIN=2.8 V to 3.3 V, Io=50 mA
Load regulation 0.046%/mA@Io=100 mA to 300 mA, VIN=2.8 V
■ Performance of the fabricated chip
■ Load and line transient test setup
http://soc.hanyang.ac.kr 105
Measured load and line regulation waveforms
■ Load regulation (40 mA to 120 mA) ■ Line regulation (2.8V to 3.3 V)
http://soc.hanyang.ac.kr 106
Measured power efficiency
■ 68.7% @VIN=3.3 V, VOUT =2.0 V
■ 76.8% @VIN=2.5 V, VOUT =1.8 V
http://soc.hanyang.ac.kr
Thank you.
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