Design of SHAKTI Processor based Safety Systems for

Nuclear Power PlantBy

Satya Rajesh Medidi, M. Manimaran, N. Anil, Ankit Kumar, Dr. D. Thirugnana Murthy, K. MadhusoodananProf. V. Kamakoti

Indira Gandhi Centre for Atomic Research

IIT-Madras

Speaker (IGCAR)

• Introduction• Distributed Architecture of PFBR• Fault tolerant methods• Hot standby architecture• Computer based systems / Real Time

Computers• VME bus based 68020 CPU card• Component Obsolescence• SHAKTI CPU card• Road map

Agenda

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• Instrumentation and Control (I&C) systems provide protection, control, supervision and monitoring in nuclear power plants

• I&C systems are designed as per AERB SG D-10, D-20 & D-25 safety guides.

• I&C systems are classified as ◦ Safety Critical Systems (SCS)

Play principal role in achievement or maintenance of nuclear power plant safety

◦ Safety Related Systems (SRS) Play a complementary role to the Safety Critical

systems◦ Non-Nuclear Safety Systems (NNS)

Play auxiliary or indirect role in achievement of nuclear power plant safety

Introduction

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In modern nuclear power plants, computer based systems (CBS) are extensively used for Instrumentation and Control systems.

CBS intrinsically contains four important functions:◦ Scanning the inputs from sensors◦ Processing logics◦ Diagnostics◦ Generation of outputs for actuators/final control

elements and Sending the processed data for storage & display purpose

Introduction

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Typically the CBS is backplane bus based system comprises of ◦ CPU card◦ Analog Input /Output cards ◦ Digital Input /Output cards

No operating System

Application software is fused in EPROM

Computer Based Systems

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Distributed Architecture of PFBR

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Single Failure CriterionFault tolerance can be achieved in two

waysDiversity

◦ Advantage: Common cause failures can be avoided

◦ Disadvantage: Stock inventory will be high

Redundancy :◦ Cold redundancy ◦ Warm redundancy◦ Hot redundancy (SRS systems of NPP)

Dual redundant systems with Switch Over Logic

◦ n-way redundancy with voting logic (SCS systems of NPP) Triplicated systems with 2/3 voting logic

Fault Tolerant Methods

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Hot Standby Architecture

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Typical I&C system cabinet

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RTC1

DI & RO simulatorAI simulator

RTC2

SOLS

Development system at Lab

No bug listsAvailability from more than one vendorTrack record in the marketCompatibility with backplane busPreferably proven track record in Safety

Applications

Motorola 68020 based CPU card is used in Safety critical and Safety Related systems of Prototype Fast Breeder Reactor (PFBR).

Criteria for Processor Selection for Safety Applications

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VME CPU CardCPU : MC68020 @ 25MHzFPP : MC68882 @ 25MHzVME Controller : VIC068AEPROM : 1MB, 16 bit widthSerial Port : 4 No’sRTC : 1No Battery backedVME Master Interface : A32:D32, A24:D16, A16:D16Display : 4 digit alpha-numericLED Indications : VME access, EEPROM access, WDT,

RUN,DBE. Control Logic : Altera MAX7256S CPLDSRAM with ECC : 2MB, 32 bit width, Battery backedEEPROM : 128KB, 8 bit width (For storing

configuration data)Watchdog Timer : Programmable - milliseconds to

seconds (10 ms – 5 secs),

WDT Testability : on demand, Potential Free Contact O/P for status

Local Area Network : 2 No’s Hardwired TCP/IP Ethernet module

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Block Diagram MC68020 based CPU card

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Component Obsolescence• 68020 is obsolete• The component life cycle is less than product

(Reactor) life cycle • NPPs designed to operate for 40 to 50 years.• Electronic components used in CBS becoming

obsolete in 10 to 15 years• 25% Spare inventory to sustain for next 10

years

• Obsolescence of processor used in CPU card creates demand not only on the hardware but also on the software used in the system

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Ways to overcome obsolescenceHDL based designsWith open specificationOpen tool chain for application

developmentVerification framework for open

specificationsFPGA or ASIC routeIntegration with third party peripherals

with IP cores

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Why SHAKTI processor?Open SpecificationVerification FrameworkExpertise (IIT-M)Obsolescence free road mapBackward compatibility

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Courtesy: Prof.V.Kamakoti, IIT-M, Chennai 15/24

Proposed Solution

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Proof of concept• To have proof of concept SHAKTI processor

based piggy back board is designed which acts as a snap-in pin to pin replacement for MC68020 on CPU base board without altering control glue logic, EDAC logic and VME Interface logic.

• To establish hardware compatibility with MC68020 CPU card, SHAKTI processor is associated with wrapper Logic. Wrapper logic translates SHAKTI core's read and write cycles to MC68020 read and write cycles respectively.

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Piggy back BoardSHAKTI Processor and it's associated wrapper

logic is being implemented in Artix 7 family FPGA from Xilinx Inc.

Piggy back board consists of Artix 7 FPGA, associated power circuitry, reset circuitry, clock circuitry, level translation circuitry, debug circuitry and pin grid array for connecting to MC68020 CPU card.

Power, reset and clock for piggy back board are derived from CPU base board. Power supply sequencing of core and input/output modules of FPGA is done by power circuitry.

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Interfaces Joint Test Action Group (JTAG) port and Serial

port are provided on piggy back board for debug purpose.

JTAG port is also used for loading FPGA configuration data on on-board flash memory of piggy back board.

Uni-directional and bi-directional level translators with latch-up protection are provided on piggy back board to enable voltage compatibility across voltage domains of piggy back board and CPU base board.

To establish software compatibility, the application programs of MC68020 CPU card is modified accordingly.

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Road MapThe design of wrapper logic is taken up by IIT-M,

Chennai and is in progress. Piggy back FPGA board for implementing SHAKTI

processor is under fabrication. Application program that is intended to work on

MC68020 CPU card will be compiled and build with the RISC V tool-chain. The same will be flashed in CPU board.

Functionality and performance of the SHAKTI CPU card will be evaluated with the existing CPU card.

Full scale CPU card will be designed with the same specifications of existing CPU card.

Thoroughly verified SHAKTI processor based CPU card will be deployed in CBSs of nuclear power plants.

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Road Map

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References[1] AERB SG D-1, 2003. Atomic energy regulatory board: safety classification and seismic categorisation for structures, systems and components of pressurized heavy water reactors. In: AERB Safety Guide No. AERB/NPP-PHWR/SG/D-1. AERB SG D-1, Mumbai, India[2] AERB SG D-25, 2010. Atomic energy regulatory board: computer based systems of pressurized heavy water reactors. In: AERB Safety Guide No. AERB/NPPPHWR/SG/D-25. AERB SG D-25, Mumbai, India.[3] M. Manimaran, A. Shanmugam, P. Parimalam, N. Murali, S.A.V. Satya Murty, 2015. Software development methodology for computer based I&C systems of prototype fast breeder reactor Nucl. Eng. Des 292 46–56.[4] https://riscv.org/ Dt. 01/10/2016[5] http://rise.cse.iitm.ac.in/shakti.html Dt. 01/10/2016[6] Chetal, S.C., Balasubramaniyan, V., Chellapandi, P., Mohanakrishnan, P., Puthiyavinayagam, P., Pillai, C.P., Raghupathy, S., Shanmugham, T.K., Sivathanu Pillai,C., 2006. The design of prototype fast breeder reactor. Nucl. Eng. Des. 236,852–860[7]https://www.xilinx.com/products/silicon-devices/fpga/artix-7.htmlDt. 01/10/2016

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AcknowledgmentThe authors express wholehearted thanks to • Dr. A.K. Bhaduri, Director IGCAR.

• Members of Electronics and Instrumentation Group, IGCAR.

• SHAKTI team of IIT-M for their valuable contribution.

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Thank You

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