Presentation Title Arial 28pt BoldDr. Iltcho Angelov, Associate Professor, Chalmers University • Part II: Overview of the Angelov-GaN model parameter extraction Dr. Roberto Tinti,

Welcome

Dr. Ilcho Angelov

Associate Professor

Microwave Electronics Lab

Department of Microtechnology and Nanoscience

Chalmers University Goteborg Sweden

Roberto Tinti

Device Modeling Product Planner

Agilent EEsof EDA

© Agilent Technologies

Accurate Modeling of GaAs & GaN HEMT's for

Nonlinear Applications Innovations on EDA Webcast, May 7 2013

Agenda

• Part I: Non linear, self-heating and dispersion modeling in

the Angelov-GaN model

Dr. Iltcho Angelov, Associate Professor, Chalmers University

• Part II: Overview of the Angelov-GaN model parameter

extraction

Dr. Roberto Tinti, Agilent Technologies

May 7, 2013

Innovations on EDA Webcast

2

I.Angelov FET model extraction: [email protected]

Outline:1Empirical Nonlinear IV and Capacitance LS

Models

2Self-heating and Dispersion modeling

3LS Model Implementation and Model Evaluation,

Summary Part1. Acknowledgements: H. Zirath, C. Fager, M. Ferndahl, N. Rorsman,

M. Mierzwinski, F. Sischka, D.Root, S. Maas, W. Curtice, D.Schreurs

M.Rudolph, colleagues from Mitsubishi for the help, support and

valuable discussions,

GHZ Centre Chalmers, Goteborg, Sweden, SSF.

Presenter Part1: Iltcho Angelov MEL, Chalmers Univ. Goteborg, Sweden [email protected]

Additional info on FET Modeling on Chalmers Web page:

https://document.chalmers.se/workspaces/chalmers/mikroteknologi-och/iltcho-angelow-

documents/openfolder

Accurate Modeling of GaAs & GaN HEMT's

for Nonlinear Applications: Part1

mailto:[email protected]


1Physical Models- very important in the device design stage.

2Table Based Models- accurate in the Measurement range!

Typ. 1000 measurement points! X-parameters, Neural Models -now!

Problems: Outside Measured Frequency Range ? Harmonics? Change of

working conditions :Temp,Rtherm,Ctherm etc. ? Manufacturing tolerances?

Scaling to High Power Devices( it is easier with smaller devices and scale later).

Do not provide feedback for the device quality, change of parameters-> this is

important issue for foundries! Data set is large>20 mB->slow.

3Empirical Equivalent Circuit Models. 100-200 measurements points

Accurate enough for many applications-1-10%.

Comparably easy to understand and extract, compact form- parameter list.

Extendable out of the Measurement Range> from 65GHz to 230GHz [Ref:46-48].

Possibility to tune& change model parameters, production tolerances, Rtherm...

Provide feedback for device parameters change, quality of processing .

All model types have their place. We should use the right type for the

specific application. We can mix& integrate different type models- example:

Empirical &Physical[49]; Empirical &Table Based ( ETB[44,45] ) etc.

2 Model Types


Ids, Igs &Cap. Model Function Selection

3

1Physical !!! 2.Single definition -∞+ ∞; Infinite & correct derivatives.

3. Flags, conditions should be avoided ( device don’t have flag)!

4.The best solution is to split (if possible) the model F on independent parts:

F= f1[Ψ1(Vgs)]*f2[Ψ2(Vds)]

5. The model parameters should be responsible for specific things:

Current, Voltage, Cap, Slope, etc.

6 When possible, use the inflection points to construct the model.

This reduce model parameters, simplifies the extraction.

7 Directly extractable! Available in CAD tools!

If the guess for modeling function F is good, extracted argument is linear

function :

f1a(Vgs)=1+Tanh[P1.Vgs]

Ψ1a(Vgs)=ArcTanh[(f1a]= P1*Vgs

A pocket calculator can be used for extraction.


Ids Model Function Selection

4

FET Ids-> solution of Schrodinger equation:

Error type functions

Typical for FET: f1(Vgs)=1+erf(Vgs)

The error function is not always available in CAD tools and

simple& direct reverse extraction is not possible.

Replacement of error functions for FET modeling:

a) GaAs: f1a(Vgs)=1+Tanh[P1.Vgs] extraction:Ψ1a(Vgs)=ArcTanh[(Ids/Ipk0)-1]

b) GaN and SiC: f1b(Vgs)=1+Tanh[Sinh(P1.Vgs)] extraction: Ψ1b(Vgs)=ArcSinh [ArcTanh[(Ids/Ipk0)-1]]

c)We need to fit different profiles i.e. Adjustment possibilities! d) Using inflection point( Ipk0, Gmax) will make model compact and

exact at important, critical point -Gmax with predefined Gm shape.


Ids Model Function Selection- direct

Direct Extraction Ψ Examples GaN, SiC 5

-4

-3

-2

-1

0

1

-15 -10 -5 0

SiC

PsiVd10PsisinhVd10

Vgs

P1

-3

-2

-1

0

1

2

-6 -5 -4 -3 -2 -1 0 1 2

GaN

PsiSinhVd10PsiVd=10

Vgs

P1

a) GaAs: f1a(Vgs)=1+Tanh[P1.Vgs] Ψ1a(Vgs)=ArcTanh[(Ids/Ipk0)-1]

b) GaN and SiC: f1b(Vgs)=1+Tanh[Sinh(P1.Vgs)] Ψ1b(Vgs)=ArcSinh[ArcTanh[(Ids/Ipk0)-1]]

c)Directly extractable; d)Using Tanh[Sinh] improves the harmonics fit for low P1<1

H.Rohdin ED-33,N5,May1986 pp. 664

ns(Vg)=ns0(a+(1-a)tanh[(V’g-Vgm)/V1]]


Ids Model Function Selection 4

Spectral content( derivatives) 6

ds 1

3 3 5 51 1 1

1

3 3 5 51 1 1

1

I ef=1+Erf[( )]/(2/Sqrt[ ]); ( )

1* * ( * ) ( * )

3

(1 tanh( ))

1

10

; ( );

1* * ( * ) ( * )

3

(

2

15

1 tan

gs

gs

pks

gs gs gsds pk pk pk pk

pksds pk


ds pk

P V V

I ef I I P V I P V I P V

I I P V V GaAs

I I I P V I P V I P V

I I

1

3 3 5 51 1 11

h( 1)); 1 ( ( )); ,

* * ( * )

sin

1 1

6 40)

h

( *

gs pks


P V V GaN SiC

I I I P V I P V I P V

5-th different

3-rd different

DC ,1-st equal

-8 -6 -4 -2 0Gate voltage , V

1

2

3

4

5

mg,

Am

v

You get Rectangular

Gm shape directly


High Power,High Frequency FET EC

Parasitic elements :Rg,Rgd,Rd,Rs,Ri, Cds,Lg,Ld,Ls, layout elements etc.

New: Rdel, Cdel shunting the gate control node Vgsc> a)Frequency dependent gate control and delay. b) Frequency dependent Rs for SiC

1. Nonlinear: Ids, Igs, Igd,Cgs,Cgd-> we need models. Models are controlled by intrinsic voltages!

Simplified Dispersion

2 backgate Model: Crf,Rc

3Physical K. Kunihiro, Y.Ohno

SiC FET

7

Idss

Igs

Igd

Thermal subciruit.


1 Preliminary screening for device selection for modeling!

2 Measurements. The general rule is that the device should be measured

sweeping Vgs from Pinch-off to the full channel current (typically Vgs=+0.8 GaAs),

stepping Vds. To get the important points, matrix of 10Vgs and 10 Vds is typical.

Screening ,device selection for modeling, tolerance evaluations:

a) Resistances Ron and Rof( FET Transistor functionality): Vds in the linear

region, below the knee, sweeping Vgs from pinch-off to full channel current.

Vds=0.1 to 0.2V is good choice for GaAs FET, Vds=1to 2V for GaN, SiC FET.

b) Full saturation current Isat for Vds at the knee.

for GaAs FET Vds=0.8V, Vgs=+0.8; for GaN FET; Vds= 6to 8V, Vgs= +0.8 to+1V

c) transconductance gm for Isat/2 ;gm for Isat, Vds at the knee.

d) Pinch-off current at Maximum operating Vds- important for high voltage, high

power FET applications. Device biased at Class C ( or AB)

e)S-parameter Measurement for Capacitive and parasitic parts extraction.

f) Screening Optional: Ft, Fmax at Isat/2 Vknee

g) Screening Optional: Pout for Zl= 50 ohm; low RF (0.5 to1 GHz) Pin = 0 dBm

GaAs, Pin= 14 dBm (GaN) for Isat/2; Vds=Vknee; Pin depends on the device size.

This logical flow is Implemented in ICCAP

FET Measurements for Modeling, Screening for

tolerance extraction:

8


1 FET Transistor functionality

evaluation:Rds(Ron)=Rd+Rs+Rch(f(Vgs)).

1

10

100

1000

104

105

106

107

-2 -1,5 -1 -0,5 0 0,5

Vds=0.1

Rds2=10kOhm

Ron=6 Ohm

RdsRds2

Rds

Vgs

Roff=5MOhm

Roff=10kOhm

Meas. 1 We need Rs,Rd to account for the intrinsic voltage drop. Nonlinear

Models for currents& capacitances are controlled by intrinsic voltages.

Ids vs. Vgs for low Vds in the knee region in the linear part of the IV: sweeping Vgs,

fixed low Vds. Cold extraction, Vds=0, from S-par is not good for GaN!

->safe measurement, GaN-> Vds=1v, GaAs-> Vds=0.1v .

Rds(Ron)=Vds/Ids: For gate in the middle S-D we can consider :

Rs=Rd=Rch=Rds/3 Very good staring values for optimization.

1 2 3 4 5 6 7 8 9 10 11 12 13 140 15

0.1

0.2

0.0

0.3

VDS

Idsm

0

5

10

15

20

25

30

-0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

ids(vg)

Ids(mA)@Vd=0.2V

Ids(m

A)

Vgs(V)

9

Good device:Ron=3 oHm,Roff>3MOhm

Working device:Ron=6 oHm;Roff=10 kOhm GaN,Vds=1V Ids vs. Vgs


Measurements Ids vs. Vgs

0

20

40

60

80

100

-0,6 -0,4 -0,2 0 0,2 0,4 0,6

ids(vg)

GaAs

Ids(mA)@Vd=0.2V

Ids(mA)@Vd=1V

Ids(m

A)

Vgs(V)

0

20

40

60

80

100

120

-0,6 -0,4 -0,2 0 0,2 0,4 0,6

ids(vg)

Gm:Vd=1Gm:Vd=02Ids(mA)@Vd=1V

Gm

(mA

/V)

Vgs(V)

Vpks

Vpk0

P1s=Gms/Ipks

P10

GaAs

Ipks

Gms

DVpk

0

0,005

0,01

0,015

0,02

0,025

0,03

0,035

0,04

0 0,2 0,4 0,6 0,8 1

Gm:Enhansment FETGmVd02

GmVd06

GmVd08

GmVd04

GmVd1

GmVd12

Gm

(mA

/V)

Vgs(v)

Meas 3. IV - Ids=f(Vgs, Vds) at Vpks &and corresponding Ipks Gmmax for Vds>Vknee

P1s= Gms/Ipks Vpk0 voltage & Ipk0 current at Gm (=Gm0) for Vds<Vknee

Gm for GaAs ,GaN,SiC, FET&CMOS are usually

bell shaped.

Part of DVpk is due to

voltage drop on Rs * Ids

DVpk~0.2V (GaAs,CMOS)

DVpk~0.6-1V (GaN).

This should be conisdered

as the device is controlled

from intrinsic voltages.

10


Measurements: Ids vs. Vds, Vgs param.

0

20

40

60

80

100

0 0,5 1 1,5 2 2,5

Ids(mA)@Vg=0.6VIds(mA)@Vg=0.4VIds(mA)@Vg=0.2VIds(mA)@Vg=0VIds(mA)@Vg=-0.2VIds(mA)@Vg=-0.4V

Ids(

mA

)

Vds(V)

Vknee

as

ar

GaAs

• αr: slope at Small currents, Low Vds

• αs: slope High Saturated currents ,Low Vds

• : slope at high Vds & small currents.

• I.e. we need 3 parameters

to model the slope Ids vs.Vds(min.)

11

Imax(Isat) at Vknee

1 2 30 4

0.1

0.2

0.3

0.4

0.5

0.0

0.6

VDS

Idsp

.i

IdVd1SIM1.VDS=DCFETM16exp..DC.IDS.i=0.151SIM1.VGS=-1.250000

2.000


3.000

Ids3sSIM1.VDS=DCFETM16exp..DC.IDS.i=0.456SIM1.VGS=0.500000

2.000


3.000

1 2 3 40 5

100

200

300

400

500

0

600

SIM1.VDS

DC

FE

TM

16

exp

..D

C.ID

S.i, m

A

Readout

IdVd1

3.0000.155

IdVd2

Readout

Ids3s

3.0000.423

Ids4s


2.000


3.000


2.000


3.000

lambda1=0.027;IdsVd2=IdsVd1(1+lambda1) lambdaSelfHeat=-0.083;

Ids4=Ids3s(1+lambda1)*(1+lambdaSelfHeat)

Slope at low power is positive =+0.027

Slope at high power is negative=-0.083

CW

Pulsed

The negative slope at high dissipated power is due to selfheating, it is not observed

in pulse IV! The effect should be modeled with a thermal network!


Self-Heating: Models without Self-Heating> not suitable for

Pdc>0.3W. Be careful if Rtherm is not listed in model parameters!

12

Self-heating effects are due to:

1 Change of mobility: Reduced mobility at higher temperature ->smaller Gm :

P1T =gm/Ipk; P1T=P1(1+TcP1*DTj) Linear function + -100C (TcP1=-0.003)-negative

2 Change of carrier concentration: This will reduce the channel current:

Ipk0T=Ipk0(1+TcIpk0*DTj) (TcIpk0=-0.003)-negative

3 Device speed: mobility change will influence capacitances, tau :

Cgs0T=Cgs0(1+TcCgs0*DTj); Cgd0T=Cgd0(1+TcCgd0*DTj) (TcCgs0=+0.003)

4 RF and dispersion characteristics: influenced by traps (at higher temperature

things worsen) Rc=f(T) (TcRc=-0.002); Crf =f(T) (TcCrf=+0.002)

5For all FET, important temperature coefficients are similar:

TcIpk0=-0.0025 to -0.0035;& negative:

TcP1 =-0.0020 to -0.0035;& negative:

TcCgs0=0.002 to 0.0035;&positive

6Temperature coefficients can be found making CW measurements at 3

temperature( 25,75,125C) .

7 Rtherm is not constant with temperature. For high dissipated power>10W

should be considered: Rtherm(T)=Rtherm(1+TcRtherm*DTj).


13

aaa

-1 -0.5 0 0.5 1

Gate vo ltage, (V)

0

10

20

30

40

50

60

I

Ids

gmpks

Vpks

Ipks

11 (( )); /

(1 tanh( )).tanh( )(1 )p

p m gs mpk

s

p kks m p

ds dspks ds

VP PV g I

I V VI

a

0

20

40

60

80

100

0 0,5 1 1,5 2 2,5


Ids(

mA

)

Vds(V)

Vknee

as

ar

Ids model1: Simple 5 Parameters,

Vds>Vknee: Ipks,Vpks,P1, as,

With 5 parameters, typical global error <10%. The model give directly correct shape of the IV and transconductance Gm.

Single definition -∞+ ∞; Infinite & correct derivatives.

Ids, gm are exact( defined) at Vpks


14

0

20

40

60

80

100

0 0,5 1 1,5 2 2,5


Ids(

mA

)

Vds(V)

Vknee

as

ar

0

20

40

60

80

100

120

-0,6 -0,4 -0,2 0 0,2 0,4 0,6

DVpk=Vpks-Vpk0

Gm:Vd=1

Gm:Vd=02

Gm

(mA

/V)

Vgs(V)

VpksVpk0

P1s

P10

Ids model2 : 11 Parameters Model:

Ipks, Vpks, P1, as,DVpk,ar, P2,P3, B1,B2

1 11

2 3

1 30 2

( ) tanh( )

( ( ))[(1 )(1 tanh( ))]

= + * ( 1 + tanh( ))

(1 tanh( )).tanh( . )(1 )

(( ) )( ) ( )

p

p

pk ds pks pks s ds

m s

pks

R S

ds

p

ds ds ds

gsm pk

pks

V V V V V

P f T V

V

P P

I V V

P V V gs pks gs pkm

I

P PV V V V

a

a

a a a

a

D

D

D

Idsmodel1+5 parameters for:

1DVpk- change for the Vpk vs. Vds

2P2,P3-adjust different GM shapes

3ar-slope at small currents

11 parameters model : 5par. + DVpks,P2,P3,ar,

B1,B2;

P1 for Low Vds is higher than P1s for High Vds

DP1- is reduction of P1=Gm/Ipk for high Vds

B1,B2 : track the change DP1 vs.Vds


Ids Equations – Extended:

Breakdown& Dispersion

.

2 3

1 1

1 2 30

.)(

( )

(( ) ( ) ( )

; Ipk=f (T); =f(T)self-heating

( ) tanh(

(1 tanh( )) tanh( )(1 )

( ) )

/

p

p

m mpk m

spk ds pks pks pk BGaBGates td es

ds pk ds ds

gs gs gsm pk pks pkm

pk

sbtrdgkb VV

T

V V V VV V KV

I I V V

P T V V P V V P V

e

V

P g I P

a

a

D D

22

= + * ( 1 + tanh( )); = + * ( 1 + tanh( ))

- )

.( - )s

p R

dg tr

S p R S

b

n n

V VV

a a a a a a

Ids Breakdown very

Important for

High Power designs

Back-gate-Dispersion parameter

15

Ids parameters=14 (Ids-10, Breakdown param.=4)

7 important Ids parameters: Ipk,P1,Vpk,DVpk,ar,as, are found

directly from measurements and provide accuracy <5% CAD tool is used for the extraction and optimization.


5

P1s=2.7 (HEMT) P1s=1.1 (Linear HEMT) P1s=5.3 (High Gain GaAs HEMT)

0

0,005

0,01

0,015

0,02

0,025

0,03

-0,1 0 0,1 0,2 0,3 0,4 0,5 0,6

Metamorphic 2x10um

P1=5.3

GmVd02GmVd04GmVd06GmVd08

Gm

Vgs0

10

20

30

40

50

-2 -1,5 -1 -0,5 0 0,5

MT3GaAs Linear

P1=1

GmVd01GmVd0.6GmVd1.1GmVd1.6GmVd2.1

Gm

VGS

0

0,005

0,01

0,015

0,02

0,025

-6 -5 -4 -3 -2 -1 0 1 2

GaN100um

P1=0.25

Gm6VGm10V

Gm

Vgs

0

0,1

0,2

0,3

0,4

0,5

0,6

-1,5 -1 -0,5 0

GaN2mm Eudina

P1=1.5

GmVd5GmVd10

Gm

Vgs

0

0,005

0,01

0,015

0,02

0,025

0,03

-14 -12 -10 -8 -6 -4 -2 0 2

DSiC1mm

P1=0.15

GmVd10GmVd2.5

Gm

Vgs

0

10

20

30

40

50

60

70

80

-1 -0,8 -0,6 -0,4 -0,2 0 0,2 0,4 0,6

W50umGaAsHEMT

P1=2.7

GmVd1.1GmVd03GmVd0.7

Gm

Vgs

P1s=0.15;SiC P1s=0.25;GaN 1 P1s=1.5;GaN 2

Variety of Gm shape, P1s= Gms/Ipks: GaN ,SiC, GaAs FET.

Models should be able to handle this. 16


5

It is important to find the reason for the specific effect,

Gm dependence etc. to model and implement this properly. Example 1;Gm shape- doping profile (Ids dependence vs. Vgs)-Ids=f(Ψ(Vgs)),P2,P3

Example 2; GaN FET –Rs,Rd are bias dependent, Rs=f(Ids), Rd=f(Ids),

Example 3 ;Rs,Rd temperature dependent-self-heating. Rs=f(T)

Usually we have several physical effects on the top of each other. I.e. we need several,

properly designed measurements to distinguish between effects like specific Ids

measurements, Measurements at 3 equally spaced temperatures, pulsed IV etc...

Gm shape,P1s= Gms/Ipks are results from specific effect.

17

Rs Temperature dependent

-3 -2 -1 0-4 1

0.02

0.04

0.06

0.08

0.10

0.12

0.00

0.14

VGS

Gm

Verilo

g2

Rs Bias dependent

-3 -2 -1 0-4 1

0.05

0.10

0.15

0.00

0.20

VGS

Gm

Verilo

g2

P2=0.16P3=0.31

-3 -2 -1 0-4 1

0.046

0.092

0.138

0.184

0.000

0.230

VGS

Gm

SD

D

Example 1:

Parameters of the

F=f(Ψ(Vgs)) function changed

Example 2: Rs

Bias dependent

Example 3:Rs,Rd

temperature dependent


Ids Model Function Selection

18

Ψ = P1p ((AA (Vgs - Vpk) + (1 - AA) (Vgs - Vpk2)

+ P2p (Vgs - Vpk)^2 + P3p (Vgs - Vpk)^3))

GaAs

3 2 1 0 10.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

Gate voltage, V

gm,

Av

We can add part of Ψ2 working at other voltage Vpk2, and combine.

We can create large variety of Gm shapes with only 2 extra parameters Vpk2, AA.

Example: Vpk=-0.3; Vpk2=-2; AA=0 to 1

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5-3.0 1.0

0.02

0.04

0.06

0.08

0.10

0.00

0.12

Vgs

ma

g(Y

(2,1

))

Vpk2=-2.0v; Vpk=-0.3V, AA=0.1;

At some moment we should stop to increase parameters->

we can switch to Table Based Model or ETB !!!


19

GaN Empirical &Table Based

(ETB) LS Model

ETB LSM FET I =Ipk0.tanh(α table) (1+tanh(P1*ψ table)) (1+ λ *λtable)

ETB: Modeling Complicated IV & Cap shapes. Combine the best of Empirical and Table Based Models

Empirical model serves as spline function Complicated data (parts of the model) loaded using data set

High accuracy and good description of harmonics and good convergence. Significant reduction of required

measured points(100-200 OK).

Easy to extrapolate out of the measured IV and frequency range.

1 Difficult to model parameters replaced with table data.

2. Good convergence and infinite number of derivatives.

3. User access to technologically & mounting

dependent parameters: Ipk0, Vpk, P1, Ron, Rtherm,

Ctherm etc. 1 ETB FET (MTTS 1999 pp. 2350)

2 ETB HBT (EUMC 2004 pp. 229)

3 ETB FET (Wiley Int. J. of RF and Microwave Computer-Aided Engineering

Vol.14, No. 2, 2004, pp. 122, Johnson et al.)

Complicated Ids(Vgs) Complicated Ids(Vds)


FET Igs Equations –

These devices have Gates!

. ))) exp( * )); , 0.8

Simple: parameters Igs model - ; slope =1/(Vt* ):

(exp( tanh

3

((

(exp( .tanh(( ))) exp(

Vj

*

g, Ij Pg

)); , 1.2jg

gg g

g g

jj jggs

g

s

j

g

d jggd

PP V GaAs VjgV

P V V GaN

I V

I V P

I

VjgI

Igs-Vgs SiC MESFET

-6 -5 -4 -3 -2 -1 0 1-7 2

0.00

0.01

0.02

0.03

-0.01

0.04

DCGaN200umIgvsVdexp..vg

DC

GaN

200um

IgvsV

dexp..

ig

vg

ig.i

-25 -20 -15 -10 -5-30 0

-0.00004

-0.00002

0.00000

-0.00006

0.00002

vgS

iC2

x5

0Ig

svsV

gse

xp

..ig

.iig

.i,

A

)))

)))

e(1 . ( ((

(1 . ( ((

xp

exp

bdgate bdgate

bdgate bdgategd

bdgatgs e

bdgat

ggsbd

gd d ed

s

b g

I V

I

I

I

K E V

K E VV

Gate parameters:

Vjg;Ij;Pg

20

Vds=10,20,40V;Vgd 70V

-20 -15 -10 -5-25 0

-0.00006

-0.00004

-0.00002

0.00000

-0.00008

0.00002

BSiC1..Vgs

BS

iC1..

Ig

vg

ig.i

Igs Breakdown model:3 parameters 6 tot 3-simple Igs model + 3Kbdgate,Ebdgate,Vbdgate

Igs-Vgs AlGaN/GaN HEMT

In ADS is implemented diode

equation, shifting the

coordinate system at Vjg ,at

which we operate the device


21

Important for Large&High Power devices: 1.The Gate Control is delayed and reduced at high frequency: Large&High Power Devices do not respond immediately at RF!

Cdel =2-3fF- is the capacitance of the gate footprint, Rdel=2kOhm(chan. resistance)

2 Current slump -In some cases at RF we do not reach the DC Ids values.

3. (Back-gate) voltage will change the effective Vgs at RF ->dispersion

4. Higher Rs and Rd/ mm for SiC and GaN FET in comparison with GaAs FET

5. Rd, Rs bias and temperature dependent! (A.Inoe et al., IMS2006 WE2F2, M. Thorsel)

6. Self-heating model-must! Mounting quality is critical.

7. Breakdown important for high power devices!

8 Keep device safe<Pmax!

Organize measurements properly. For GaN

Dual region measurements& simulations: A)High Ids, Low Vds;

B)Low Ids, High Vds -Cover the load line!!!

High Power devices

2 4 6 8 10 12 14 16 180 20

0.1

0.2

0.3

0.4

0.0

0.5

vdid

.iDCLowvoltage..vd

DC

Lo

wvo

lta

ge

..id

.i

Vdsh

Pm

ax

Pmax

A

B

LoadLine


Large-Signal Modeling of AlGaN/GaN HEMTs

GaAs vs. GaN Model

The main difference in the GaN FET model in comparison with the default

GaAs model in Verilog implementation are:

1. Modified psi function( tanh(sinh(psi)) Ids model 3 .

2. Capacitance model which can provide peaking for Cgs, Capmodel 3,4.

The capacitances are implemented as charge-Capmodel4 and as capacitance : Cap model3 –

This keep the model compatible with simulators with capacitive implementation.

3. Temperature and bias dependent Rd, Rs –this is important when device is pushed hard.

4. Enhanced dispersion modeling, back gate approach Vbg, delay circuit to model the knee

walkout.

5. The Ids breakdown exponent can be adjusted with parameter Ebd.

6. GS and GD junction breakdown is also included we push device to the limits. Setting

Kbdgate=0 will switch-off the junction breakdown ( default=0)

7. Many functional changes made by Tiburon to improve the stability.

8 Verilog model can be used as mainframe. When device has some specifics features

the model equations can be easily changed.

22


Model Parameters GaN tot. 69

GaN

Ids parameters:12

Cap parameters:15

Thermal parameters:8

Igs:3

23

Parasitics&package

GaN model implemented in VerilogA :> ADS 2009:

1 f1(Ψ)=1+Tanh[Sinh(P1.Vgs)]

2Rd and Rs are bias( Rd2) and temperature dependent (TcRs),

Rsbdep=Rs*(1+Rd2*(1+tanh(Ψ))); Rdbdep=Rd*(1+Rd2*(1+tanh(Ψ)));

RsbdepT=Rsbdep*(1+TcRs*DTj); RdbdepT=Rdbdep*(1+TcRs*DTj);

3 Dispersion(Rc,Rcmin,Crf,Rcin Crfin)+Backgate Kbgate+ Rdel, Cdel

4Breakdown for GS,GD Junctions: Kbdgate,Vbdgs,Vbdgd, Pbdg

5 GaN+Noise :RF and LF;Tiburon DA :ADS 2010 ;MO-implementation

Breakdown:7

Dispersion:8


SS Equivalent Circuit Extraction

for GAN FET

1 Small Signal extraction from multibias S-parameter measurements

Capacitances are extracted from S-par measurements in 3-10 GHz range,

depending on the device size.

2Measured &Extracted SS capacitances should be verified for Charge

Conservation:

gd gs

gs gdC CV V

24

3 Cappy; Berroth- Cold FET method (VDS=0)

for extraction will not give correct results for

GaN!The reason for this : Rs and Rd are bias and

temperature dependent.

GaN Resitances Rd,Rs depend strongly on the

dissipated power. For constant power they are

quite constant with Vds.

When cold values for Rs and Rd are used,

unrealisticly high Output Power and PAE will

be predicted! Cold values should be used only as a

start and limit the optimization values.

1

2

3

4

5

6

7

8

0

0.5

1

1.5

2

2.5

3

3.5

-1.5 -1 -0.5 0 0.5 1

Pdc=const

RdVd8

RdVd14

RdVd10

PdcVd8

PdcVd10

PdcVd14

Rd(O

hm

)

Pd

c(W

)

Vgs(V)

Rd

Bias dependence Rd,Pdc vs. Vgs(Ids)


Cap Models FET GaN

•Cgdpi-minimum cap; Cgs0,Cgd0: capacitances at the inflection point; P11,P21:slope

vs.Vgs,Vds , Cgs,Cgd vs. Vds

•

-6 -4 -2 0Vgsc , V

200

400

600

800

1000

sgC

,Ff

-8 -6 -4 -2 0 2Vgsc , V

100

200

300

400

500

dgC

,Ff

5 10 15 20 25 30 35 40Vdsc , V

100

200

300

400

500

600

700

800

sgC

,Ff

5 10 15 20 25 30 35 40Vdsc , V

100

200

300

400

500

dgC

,Ff

25

3 2 1 0 1 20123456

Vgs V

Cgs,

ff

1.0 0.5 0.0 0.5 1.04

2

0

2

4

Vgs V

Qgs,

q

Some GaN devices show peaking modeled with the term m The charge Qgs or Qgd is 0

when terminal voltage is 0 for charge conservation.

hi1 10 11 gs 111 ds

hi2 20 21

222

ds gs 10

gs1 gspi gs0T hi1 gsdepl

111 111 hi2

gsdepl

P

P =P + P *V +P *V ;

P =P +P *V ;y=((V /P )-1);

C =C +C (1+Tanh[P ]+ *C ) *

(2 P +(1-P +Tanh[P ]) ) ;

C =(( +y^2)^(-1-MJC))*

( +(1-2*MJC)*y^2);

m

m (12)


Cap 1 vs. Charge2 Implementation ADS (Cap and Charge implemented)

1Cap implementation: DC current can be observed in HB for capacitor

2 Charge implementation, will not produce DC Current via cap.

Icap=0; Use the charge implementation!!! 26

-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4-1.4 0.6

0.0

2.0E-13

4.0E-13

6.0E-13

8.0E-13

-2.0E-13

1.0E-12

VGS

Cgs1

DC

gs

Cgs2

-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4-1.4 0.6

4.510E-13

9.520E-13

-5.000E-14

1.453E-12

VGS

Cg

d1

DC

gd

Cg

d2

-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4-1.4 0.6

-1.5E-14

-1.0E-14

-5.0E-15

-2.0E-14

0.0

VGS

DC

gs

Readout

m4

m4VGS=DCgs=-2.087E-16VDS=0.500000

-1.400

-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4-1.4 0.6

-2E-28

-1E-28

0

1E-28

-3E-28

2E-28

VGS

DC

gd

Readout

m5

m5VGS=DCgd=1.010E-28VDS=1.000000

0.150

-1.3

-1.1

-0.9

-0.7

-0.5

-0.3

-0.1

-1.5

0.0

0

5

10

15

-5

20

Vgs

dB

m(V

load[::,1])

dB

m(H

B1P

sV

d2P

0C

AP

2..V

load[::,1])

Pin=3 dBm,RF=5GHz;Vd=3V;1-st Harmonic

-1.3

-1.1

-0.9

-0.7

-0.5

-0.3

-0.1

-1.5

0.0

-15

-10

-5

0

-20

5

Vgs

dB

m(V

load[::,2])

dB

m(H

B1P

sV

d2P

0C

AP

2..V

load[::,2])

Pin=3 dBm,RF=5GHz;Vd=3V;2-nd Harmonic

-1.3

-1.1

-0.9

-0.7

-0.5

-0.3

-0.1

-1.5

0.0

-16

-14

-12

-10

-18

-8

Vgs

dB

m(V

load[::,3])

dB

m(H

B1P

sV

d2P

0C

AP

2..V

load[::,3])

Pin=3 dBm,RF=5GHz;Vd=3V;3-rd Harmonic

50 100 150 2000 250

-7

-2

3

-12

8

time, psec

ts(I

gsp.i),

mA

ts(H

B1P

sV

d2P

0C

AP

2..Ig

sp.i),

mA

1-st harmonic, Charge&cap, 2-nd harmonic Charge&Cap, 3-rd Charge&Cap

Cgs:Cap&Charge& DCgs is small<3% Cgd:Charge&Cap DCgd<1%

Igs with Cap Implementation Waveforms for Charge&Cap similar, but not equal.

Cap current is the same order as diode current. Harmonics are correct from the charge implmentation!

-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2-1.6 0.0

0.000005

0.000010

0.000000

0.000015

Vgs

real(Ig

sp.i[:

:,0])

-0.1507.985E-6

Idiode

Igscap

Idiodeindep(Idiode)=plot_vs(real(Igsp.i[::,0]), Vgs)=7.985E-6

-0.150


Small Signal GaN Dispersion Problems

GaN HEMTs are dispersive. 27

Vds=2V

Vds=2V

Gm Dispersion GaAs GdsDispersion GaAs GdsDispersion GaN

-3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5-4.0 0.0

0.057

0.114

0.171

0.229

0.286

0.343

0.000

0.400

vg

diff

(DC

1.D

C.id

.i)diff

(DC

1.D

C.id

_exp.i)

-25 -20 -15 -10 -5 0 5 10 15 20 25-30 30

freq (200.0MHz to 30.00GHz)

S(4

,3)

Readout

m4

S2

1m

ea

s

Readout

m7

m4freq=S(4,3)=26.728 / 162.059Vgs=-2.000000, Vds=30.000000

200.0MHz

m7freq=S21meas=20.912 / 168.956Vgs=-1.800000, Vds=15.000000

200.0MHz

5 10 15 20 250 30

5

10

15

20

25

0

30

freq, GHz

(S(2

,1))

Readout

m8

ma

g(S

(4,3

))

Readout

m5

m8freq=(S(2,1))=18.605 / 170.719Vgs=-1.600000, Vds=30.000000

200.0MHz

m5freq=mag(S(4,3))=21.596Vgs=-1.600000, Vds=30.000000

200.0MHz

DC Gm; GaAs Model ;Simulated Mag S21: 3 dB higher with GaAs model

0.917 1.733 2.550 3.367 4.1830.100 5.000

200

400

600

800

0

1000

freq, GHz

real(Z

(2,2

))re

al(Z

(4,4

))

Example: GaAs Model used to model GaN

GaN DC Gm

GaN


Large Signal GaN Dispersion Problems 28

DC Ids vs Vds fit is good using GaAs model But at RF: Knee is different!

1.Solution : using GaAs model :sacrifice the fit at CW to get the RF fit

2.Use the GaN VA model with Bias dependent Rd,Rs,Rdel, Cdel, Kbgate

3. In severe cases, further increase of complexity of the GaN model making

additional, RF controlled part of Ids.

4. Improve the passivation and fix the problem, instead spending time to model the

problem. It is more important, practical to fix the problem, instead modeling problem.

1 2 3 4 5 6 7 8 90 10

0.114

0.229

0.343

0.457

0.571

0.686

0.000

0.800

vd

DC

1.D

C.id

.iD

C1.D

C.id

_exp.i

5 10 15 20 25 300 35

0.07

0.14

0.21

0.28

0.00

0.35

Vds(V)

Ids(A

)

Zl from 50 to 280 oHm

Red measured, Blue :Model without Knee walkout modeling facilities

GaAsModel used to model GaN


Dispersion Modeling Implementation

1 Simple> Rc,Crf at the output, usually implemented in CAD tools

Rc is bias dependent! Rc1=Rcmin+Rc/(1+tanp)

2 Back-gate Approach (SS): (J. Conger, A. Peczalski, M. Shur, SC,Vol. 29, No.1)

3 Physical Approach: (K. Kunihiro, Y.Ohno, ED, Vol. 43, No. 9) 4 Device is symmetric>output and input dispersion: Rcin,Crfin

From ADS2009; GaN Extended dispersion Modeling

–combined Rc , back-gate+ Rdel,Cdel:8 par.

29

Input

dispersion

Output Dispersion

Rc,Crf

Rc1=Rcmin+Rc/(1+tanp)

Back-gate node

DCRFIds=(Ids

Severe knee w

+ KRFDC*Id

alkout:

sRF) ;


Sweeping real Zload RF=4 GHz;Pin=14 dBm

GaN DC Ids (red) and dynamic Ids(Blue) sweeping real Zload

30

1LSNA & Load-Pull Measurements for Knee walkout

problems: GAN FET: Real Load Evaluation!

INDEX (1.000 to 8.000)

Z

2 3 4 5 6 71 8

29

30

31

32

33

28

34

INDEX

dB

m(v

2m

[::,

1])

5 10 15 20 25 300 35

0.07

0.14

0.21

0.28

0.00

0.35

Vds(V)

Ids(A

)

Zl from 50 to 280 oHm

Sweeping real Zload

50-280 Ohm

Sweeping real Zload Pin=14 dBm

Output Power for different

impendances

2GHz

2 4 6 8 10 12 140 16

0.00

0.05

0.10

0.15

0.20

-0.05

0.25

v2mts

i2m

ts

v2sts

i2sts

i1m

tsi1

sts

5 6 7 8 9 104 11

-0.05

0.00

0.05

0.10

0.15

-0.10

0.20

v2sts

i2m

tsi2

sts

i1m

tsi1

sts

12GHZ18GHz

6.5 7.0 7.5 8.0 8.5 9.06.0 9.5

0.00

0.05

0.10

-0.05

0.15

v2sts

i2m

tsi2

sts

i1m

tsi1

sts

Knee walkout: 2GHz Vmin=0.8V(DCKnee GaAs) 12GHz Vmin=4.5V 18GHz Vmin=6.3V

The high freqency IV slump is accurately modeled with the gate control network Rdel,Cdel

Univ. Cardiff,UK first used LSVNA and this approach.


2Combined LSNA & Load-Pull Measurements -

the best approach for LS evaluation :Examples GaN device.

31

INDEX (1.000 to 32.000)

a2

_sim

[::,1

]/b

2_

sim

[::,1

]a

2[::,1

]/b

2[::,1

]

2Measured and simulated Load

Impedances C band.

I2,V2 should be correct to get this

right!

-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4-1.6 0.6

2.0

2.5

3.0

3.5

1.5

4.0

VGS

Pout1

meas

Vgs

mag(P

out1

sim

)

-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4-1.6 0.6

0.5

1.0

1.5

2.0

0.0

2.5

VgsP

dcsim

VGS

Pdcm

eas

1Measured (points) and modeled RF

and DC Power Load Pull C- band

100 200 300 4000 500

-0.10-0.050.000.050.100.15

-0.15

0.20

Time(ps)

Ids(A

)

5 10 15 20 25 300 35

-0.05

0.05

0.15

-0.15

0.25

Vds(V)

Iga

te (

A)

100 200 300 4000 500

-0.10-0.050.000.050.10

-0.15

0.15

Time(ps)

Iga

te(A

)

5 10 15 20 25 300 35

-0.05

0.05

0.15

-0.15

0.25

Vds(V)

Ids(A

)

-4 -3 -2 -1 0-5 1

-0.05

0.05

0.15

-0.15

0.25

Vgs(V)Ig

ate

(A)

-4 -3 -2 -1 0-5 1

-0.05

0.05

0.15

-0.15

0.25

Vgs(V)

Ids(A

)

a)

b)

c)

d)

e)

f)

3Measured and modeled Waveforms Vds=15V;

C -band Harmonic Load pull evaluation.


Conclusions part1

A general purpose large-signal modeling approach for GaAs,GaN

FET was proposed, implemented in CAD tools and

experimentally evaluated.

Thank you for your attention! S.D.GL.

Meyer’s Law, part of Murphy’s Law:

It is a simple task to make things complex, but

a complex task to make them simple

42 32


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[40] Angelov A. Inoue, T. Hirayama, D. Schreurs, J. Verspecht “On the Modelling of High Frequency& High Power Limitations of FETs INMMIC Rome 2004

[41] Angelov at all “ On the large-signal modelling of AlGaN/GaN HEMTs and SiC MESFETs, EGAAS 2005 pp.309 - 312

[42] Angelov at all “Large-signal modelling and comparison of AlGaN/GaN HEMTs and SiC MESFETs”, 2006. APMC 2006 pp:279 - 282

[43] ADS,MO, Ansoft Designer user manuals

[44] Angelov at all “An empirical table-based FET model” MTT, Vol. 47, N12, Dec.1999 pp:2350 - 2357

[45] Johnson at all ”Generalized nonlinear FET/HEMT modeling (p 122-133) Wiley International Journal of RF and Microwave Computer-Aided EngineeringVol.14, No. 2, 2004, pp. 122

[46] S.Gunnarsson at all” 220 GHz (G-Band) Microstrip MMIC Single-Ended Resistive Mixer ; Microwave and Wireless Components Letters, IEEE Volume 18, Issue 3, March 2008 pp.215 - 217

[47] S.Gunnarsson at all A 220 GHz Single-Chip Receiver MMIC With Integrated Antenna ;Microwave and Wireless Components Letters, IEEE Volume 18, Issue 4, April 2008 pp:284 – 286

[48] S.Gunnarsson at all; A G-band (140 – 220 GHz) microstrip MMIC mixer operating in both resistive and drain-pumped mode , IEEE MTT-S 2008 pp 407 – 410

[[49] T. Oishi1, H. Otsuka1, K. Yamanaka1, Y. Hirano1, I. Angelov2Semi-physical nonlinear model for HEMTs with simple equations INMMIC 2010 Goteborg

[50] Angelov at all On the Large Signal Evaluation and Modeling of GaN FET” ,IEICE 2010 July

[51] Gauthier and F. Reptin CS MANTECH Conference, April 24-27, 2006, Vancouver, British Columbia, Canada,pp.49G.

[52] Sylvain L. Delage, at all “Korrigan: An European Project on GaN”, EuMW 2005,. GAAS 2005, La Défense, October 2005. ...

[53] S.piotrowicz at all Overview of AlGaN/GaN HEMT technology for L- to Ku-band applications International Journal of Microwave and Wireless Technologies, 2010, 2(1), 105–114


Dispersion Treatment Summary 34

Output Dispersion

Rc,Crf

Rc1=Rcmin+Rc/(1+tanp)

Back-gate node

DCRF

dsDCRF

; KRFDC=1 (7)

I = IPK0 * ( 1 + tanh(x1p)) * tanh(Alphap * Vds) *

( 1 + LAMBDA * Vds + LSB0 * exp(Vdg

Ids=(Ids + KRFDC*IdsRF)

IdsRF = IPK0 * ( 1 + tanh(x1p)) * tanh(Alphap *

- VT

V

R))

rf)

PKS VPKS VPKS LPHA

SB2 TR

Vpkm = V - D + D * tanh(A * Vds)

-V * (Vdg

*

( 1 +

- V

LAMBDA *

)^2

Vrf)

- Vbg

2.5

5.0

7.5

10

.0

12

.5

15

.0

17

.5

20

.0

22

.5

25

.0

27

.5

0.0

30

.0

0.0

0.2

0.4

0.6

-0.2

0.8

ts(v2)

ts(i2.i)

ts(v2m)

ts(i2m

)

1)in not very severe cases modify only the output conductance Rcmin Rc 2) More advanced (difficult) SS cases when you treat both Gds, Gm - use backgate Kbg- i. e you insert the back gate feedback to the gate voltage control. 3) High frequency delay, mild knee walkout :Rdel Cdel 4) In severe knee walkout cases you need to modify the Ids current - the knee current is dependent on drain and gate at RF. This modification can be done by users, both in the VA implementation or SDD:


Common mistakes

A1

1.Too much input power when doing S-parameters, S21 is compressed.

The input power should be small (typ-40dBm), should not change DC current.

Take a look in the ICCAP modeling book( Franz Sischka) for the golden rules

2. Resistances in the bias lines not measured.

3. Gate current Igs not monitored or Igs compliance too low.

4.When working with dispersive devices like GaN a separate

a)Ids vs Vgs, (Vds parameter)

b) Ids vs Vds (Vgs parameter) measurements should be made.

For GaN devices, depending on

the starting point , direction (up or down),

Ids can differ >10% 2 4 6 8 10 12 140 16

0.020.040.060.080.100.120.140.160.180.20

0.00

0.22

Vds(v)

Ids (

A)

Measured Ids vs. Vds , Vgs

parameter

a) stepping up with Vds- triangles,

b) stepping Vds down- cross.


A3

GaN GS,GD Breakdown Measurements

Compliance is not fast enough and difficult to model.

m1indep(m1)=plot_vs((idsp.i), vd)=-0.003

40.000

4 9 14 19 24 29 34-1 39

-0.003

-0.002

-0.001

0.000

0.001

-0.004

0.002

vd

(idsp.i)

Readout

m1m1indep(m1)=plot_vs((idsp.i), vd)=-0.003

40.000

Gate -Drain breakdown

measurement setup

-18 -16 -14 -12 -10 -8 -6 -4 -2 0-20 2

-1.5

-1.0

-0.5

0.0

0.5

1.0

-2.0

1.5

vg

igp.i, m

A

Readout

m1

m1vg=igp.i=0.001

2.000

2For Common Source Device:

Source without via, using needles.

We can use resistors to limit& define safe currents levels.

The same resistors used in the CAD tool to extract models for breakdown.

1Common Gate Device: we split the GS, GD Junctions:

Rmeas=1 kOhm defines the current in the measurement path

Rcon=1MOhm defines the current in the connected path.

Injected current <0.1mA/mm for safety!!!

Gate -Source breakdown

measurement setup.


Gate Charge models :

Capacitance1 or Charge2 Models?

1 Capacitance implementation >we don’t need

transcapacitances! Cap directly from SS extraction!

2 The Cap. Functions should be well defined -∞+ ∞.

30 31

g

0 1 2

1 10 111

11

11 2 20 21

0 3 4 111

3 4 4 140 1

High voltage effects for C

. . ; .

. . ; .

.(1 [ ]).(1 [ ])

.(1 [ ]).(

: tanh tanh

tanh t1 [ ] 2anh )

gs ds ds

ds ds

gs gsp gs

gd gdp gd

gd

P P V V P P V

PP P V P P V V

S C C C

C C C P

S

P

s gd 111& cross-coupling from Vds -

C

2; ; ; :

P

Vgs Vgd Vgs VgdIgsc Cgs Igdc Cgd

t t t tHB

0

0

1 42 3

11 41

log[cosh[ ]] log[cosh[ ]]1 ; 2 tanh[ ]; 4 ; 3 tanh[ ];

Total Cha

. .( 1) 2

. .( 4) 3

Charge Implementation :2

( , )

( , )

gsp gs gs gs

gdp gd gd gd

gs gs gs gsds

gd gd gs gdgd

Lc Th Lc Th

P P

C V C V Lc Th

C V C V Lc Th

Q C V V dV

Q C V V dV

rge Implementation Qg Qgs Qgd

2 4 6 8 10 12 14 16 180 20

5.0E-13

1.0E-12

1.5E-12

2.0E-12

0.0

2.5E-12

Vds

Cgs

Vd

''C:\users

\Angelo

v\A

DS

\AD

Sfile

s\w

p4\w

p4n1_prj

\data

\cgsvdcon3.d

s''.

.Cgs

m1Vgs=-3.900Vds=20.000000, freq=1.000000GHzplot_vs(Cgd, Vgs)=9.879E-14

-4.0 -3.5 -3.0 -2.5-4.5 -2.0

2E-13

4E-13

6E-13

0

8E-13

Vgs

Cg

d

m1

Vg

''C:\

use

rs\A

ng

elo

v\A

DS

\AD

Sfile

s\w

p4

\wp

4n

1_

prj\d

ata

\cg

dvg

co

nd

3.d

s''.

.Cg

d

A4

Integration vs. terminal voltage!

Remote voltage parameter! We will always have some difference in

the simulated S-parameters using

capacitance or charge implementation,

using the same coefficients!

> S.Maas Nonlinear Microwave Circuits

Cgs,Cgd

Measured,

Simulated


Extraction & Fit IV parameters flow

Summary:

1. On resistance Ron Extraction. Ron= Rs+Rs+Rch

2 Igs parameter extraction and fit.

3Extraction of lambda (slope Ids vs. Vds at high Vds, above the knee.

4. Extraction, fit Iknee with Ipk0 (Isat/2), P1=Gm/Ipks, Vpks

5. Fit for linear part Ids vs. Vds <Vknee (alphas, alphar, B1, B2).

6. Thermal resistance fit Rtherm.

7 Fit Gm with P1

8 Extraction of second P2 and third derivative P3 parameters.

Repeat the procedure 4-8, because parameters are interdependent

9. Global IV optimization . Typical, at this point fit <2- 5%.

10. Breakdown parameter for Ids, Igs (optional) followed by Global IV optimization

A5

Implemented in ICCAP2013


Cap Direct extraction using the CAD tool . A6

Cgs, Cgd extracted directly using the CAD tool

-1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1-1.2 0.0

40

60

80

100

20

120

Vgate_sweep

Cgs1N

Readout

Cgsmin

Cgsminindep(Cgsmin)=plot_vs(Cgs1N, Vgate_sweep)=55.238Vdrain_sweep=2.400000, freq=5.000000GHz

-1.200

-1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1-1.2 0.0

20

30

40

50

10

60

Vgate_sweep

CgdN

1

-0.10013.931

Cgdmin

Cgdminindep(Cgdmin)=plot_vs(CgdN1, Vgate_sweep)=13.931Vdrain_sweep=2.400000, freq=5.000000GHz

-0.100

Small Signal extraction good papers: Dambrine ,Berroth,Manohar, Sommer,

Shirakawa ,Campbell


LSVNA Measurement Set-up

Active Load Pull A7

a1

b1

a2

b2

On-wafer DUT

LSNAVI

VQ

ΓL

I/Q

mod.

10 MHz

f0

2f0 50 Ω

I/Q

mod.

VI VQ

The active, injection

based harmonic load-pull

measurement setup.

2 2 2

1 2 2 2

2

; ; ;2 2

where Zc is the system impedance.

IN OUT

C C

a b a aP P

Z Z b

02

,

02

02

0

0,

fb

eVVA

fb

faf

QI VVj

QI

The circulator separates the injected and

outgoing wave, terminating b2 in a 50 Ω

load. This gives full control of ΓL seen by

the DUT at f0, according to:

It is very fast& accurate!

The amplifier at the output should

provide enough power to

compensate circulator&cable

losses ( 2-3 dB).


Self-Heating:Models without Self-Heating not suitable for Pdc>0.3W .

Be careful if Rtherm is not listed in model parameters! A8

10 20 300 40

0.10

0.20

0.00

0.30

ASiC1..Vds

AS

iC1..Id

vd

id.i, A

0

0,1

0,2

0,3

0,4

0,5

0,6

0 10 20 30 40 50

DPulsedIVEudinaM

IdVg-2IdVg-1.6IdVg2IdVg1.6IdVg1.2IdVg08IdVg04IdVg0IdVg-04IdVg-08IdVg-1.2Id

(A)

Vd(V)

Self-heating is usually modelled with a single thermo-electrical circuit Rtherm*Ctherm.

With temperature coefficients TcIpk,TcP1 known, there is only one thermal parameter to find >

Rtherm. This is done in the CAD, at high Pdc:

1Fit accurately Ids at the knee(current parameters), 2Adjust Rtherm to fit the slope Ids vs. Vds.

Accurately, thermal resistance can be found measuring junction temperature Tj with infrared

microscope. Tj=Rtherm.Pd+Tamb

Rtherm is not constant with temperature. For high dissipated power>10W

should be considered: Rtherm(T)=Rtherm(1+TcRtherm*DTj).

The thermal capacitance Ctherm model the thermal storage capacity of the structure.

We can have different Rtherm and Ctherm for the chip Rthermchip, Cthermchip and for

package Rthermpackage ,Cthermpackage for high power devices.

CW Pulsed:

The slope is positive

even at high Pdc!


LS Harmonics Evaluation

Pin,RF freq, Vds Constant.

1) Low RF-evaluation of Ids current source 2) High RF-capacitances Procedure for PS :

1 Calibrate input power at DUT (Pin=0 dBm GaAs, 10-14 dBm for GaN SiC) at the device terminal for fund. and

harmonics.

2 Calibrate losses of output cables,diplexer, etc. Keep attenuators directly at the bias tees, close to DUT!!! 3 Measure 1,2,3 harmonics sweeping Vgs(10pts), Vds (14V, 28V.?..for GaN, SiC; Vds=0.1;3V, GaAs)

A9

For LS & Harmonics modeling we need correct derivatives

Self-Heating, Dispersion, Memory effects, complicate the picture.

DC data for Ids derivatives are noisy! Solution:

1Power Spectrum Evaluation (PS)using Spectrum Analizer ,or LSVNA;

2Load Pull , Waveforms LSNA or

3 Combined Load Pull & LSNA Waveform Evaluation!!

-1.3 -1.1 -0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3-1.5 0.5

-20

0

20

-40

40

Vgs

dB

m(V

load[:

:,1])

Readout

m1

VGS

dB

m(P

out1

meas)

Readout

m2

dB

m(P

out2

meas)

dB

m(P

out3

meas)

dB

m(V

load[:

:,2])

dB

m(V

load[:

:,3])

m1Vgs=dBm(Vload[::,1])=21.836

1.943E-16m2VGS=dBm(Pout1meas)=21.384

-2.626E-5

-1.5 -1.0 -0.5 0.0-2.0 0.5

-20

-10

0

10

20

-30

30

Vgs

dB

m(v

2[::,2

])d

Bm

(v2

[::,3

])d

Bm

(v2

[::,1

])

Readout

m1

VGS

dB

m(P

ou

t2m

ea

s)

dB

m(P

ou

t3m

ea

s)

dB

m(P

ou

t1m

ea

s)

Readout

m2

m1Vgs=dBm(v2[::,1])=21.028

0.300m2VGS=dBm(Pout1meas)=20.393

0.300

PS: GaN C-band and X- band Measured and modeled

Accurate Modeling of

GaAs & GaN HEMT's for

Nonlinear Applications

Part II: A quick overview of the

Angelov-GaN model

parameter extraction

Innovations on EDA Webcasts

Agilent EEsof EDA

Dr. Roberto Tinti, Ph.D.

Product Manager, Device Modeling

May 7, 2013


Angelov-GaN Extraction with IC-CAP

May 7, 2013


46

• Parasitic Extraction

• DC Extraction

• AC (CV and SP) Extraction

• (LS Extraction / Verification)

• DC Measurements

• SP Measurements

• (Large Signal

Measurements)

Measure Extract

Recommended Extraction Flow

May 7, 2013


47

Update Measured Data

(inc. de-embedding)

Extract System Series

Resistance

Repeat until getting

medium level fit

Extract CV

parameters

Repeat until getting

medium level fit

Large Signal

Verification

DC Extraction (Forward Gate current)

May 7, 2013


48

Tips:

Measure Gate Forward Diode characteristics.

Sweep Vg up to the level where enough current flows to get Gate resistance.

Measure 3 Vds points around Vds=0 to check the device behavior.

DC Extraction (Drain current, Id-Vgs)

May 7, 2013


49

Set Range

Tips:

Measure Drain current with Gate Voltage sweep.

Include negative Vg region where Gate leak current is observed.

Include Gmmax point and falling down region.

Self Heating Effect Modeling

May 7, 2013


50

Slope at low power is

positive: Lambda

Slope at high power is

negative: RTH (Rtherm)

Pulsed IV measurements, when

available, can give isothermal

results, avoiding the self heating

effect. (Pulse width < 100-200 nsec)

However, dispersion problems may

be observed.

Negative slope at high dissipated power is due to self

heating of the device. This effect is modeled with a

thermal network.

Reference:

I.Angelov “Compact Equivalent Circuit Models for GaN, SiC,

GaAs and CMOS FET”, MOS-AK Baltimore Dec9

Use RTH (and CTH) to model the dynamic thermal effect.

SP Tuning Example capacitances

May 7, 2013


51

S-parametersTips:

Make sure the signal input level is not too high

Account for series resistance due to bias tees and cables

SP Tuning Example gate and collector resistances

May 7, 2013


52

SP Tuning Example

May 7, 2013


53

Parameter Extraction and Validation with Agilent

NVNA Data

May 7, 2013


54

ADS

Circuit / Amp

design

IC-CAP

Parameter extraction for

std. compact model

using NVNA data as target

NVNA-based device

characterization

NVNA

Dynamic Load-line

Waveform meas.

DC-IV, S-pars

Sync. Bias

Supply

Compact

Model (e.g.

Angelov)

Benefits:

•Best set of model

parameters for a fixed

empirical model

•Data under realistic

conditions of use

•Validation for free! 0 1 2 3 4 5 6 7 8 9

0

20

40

60

80

100

120

140

160

180

See [1]

Validation with NVNA Data with IC-CAP and ADS

May 7, 2013


55

Trade-off

LS vs SS fits

Tune parameters

for specific

applications

Extract breakdown

and other

parameters at

operating extremes

Explore model

limits

See [2,3]

Summary

• Complete Angelov-GaN extraction flow

• As a optional step, the Agilent NVNA can be used in conjunction with IC-CAP and ADS to verify and improve the accuracy of compact models, such as Angelov-GaN, extracted using traditional linear techniques (DC and S-parameters). The exclusive Harmonic Balance simulation link between IC-CAP and ADS enables model parameters optimization to match large signal data.

Acknowledgements

• Takashi Eguchi, Tanigawa Hirohaki, Agilent Technologies

• David Root and Franz Sischka, Agilent Technologies

References:

1. D. Root, “NVNA Measurements for Behavioral & Compact Device Modeling” IMS2012, WMB: Device Model Extraction from Large-Signal Measurements

2. F.Sischka, "Improved compact models based on NVNA measurements", European Microwave Week 2010, Paris, Workshop WFS06 (EuMC/EuMIC ) 'Silicon Characterization from MHz to THz'.

3. F. Sischka,, “Nonlinear Network Analyzer Measurements For Better Transistor Modeling, ” 2011 IEEE Conference on Microelectronic Test Structures, April 4-7, Amsterdam, The Netherlands

May 7, 2013


56

Where to find more information about today’s

content:

Angelov-GaN paper library at Chalmers University:

• Angelov-Model-Library-at-Chalmers

IC-CAP and Angelov-GaN extraction package:

• www.agilent.com/find/eesof-iccap

ADS and supported foundry libraries:

• www.agilent.com/find/eesof-ads

• www.agilent.com/find/eesof-foundries

Non-linear verification with Agilent NVNA

• Future Device Modeling Trends by David Root

• See also reference papers on slide 12

May 7, 2013


57

https://document.chalmers.se/doc/00000000-0000-0000-0000-000005D7518B









http://www.agilent.com/find/eesof-iccap



http://www.agilent.com/find/eesof-ads



http://www.agilent.com/find/eesof-foundries



http://cp.literature.agilent.com/litweb/pdf/5991-1629EN.pdf

Appendix

The Agilent IC-CAP W8533EP Angelov-GaN

Extraction Package

May 7, 2013


58

Toolkit Work Windows

May 7, 2013


59

Measure

Extract

Settings

VerilogA Dir and Work Dir

May 7, 2013


60

Choose VerilogA directory and Working directory.

VerilogA Model for Simulation

May 7, 2013


61

File Location: (ADS Install Dir)/veriloga

File Name: angelov_gan.va

angelov_gan.va

in ADS2009U1 (not supported)

in ADS2011.10 (supported)

in ADS2012.08 (supported)

Pad Open/Short Measurement

May 7, 2013


62

S11 S22

Measure &

data manage

OPEN measurement settings

SHORT measurement settings

Deembed

data

manage

De-embed

De-embedding Set

May 7, 2013


63

Open S-parameters

Short S-parameters

Different combinations of

OPEN/SHORT data can be

assigned for de-embedding

If you don't use the de-embedding function in the toolkit,

set Ideal Open and Short for the De-embedding Set.

RF S-Parameter Measurement

May 7, 2013


64

RF measurement settings

.mdm Data import and export

De-embedding

Function

List

Extraction Flow Function

Flow

Extraction Flow / Function Editor

May 7, 2013


65

Function Editor

Customize Extraction Procedure

• Modify Extraction Flow

• Modify Function Flow

• Add New Function (Function Editor)

Tuner Function

May 7, 2013


66

Measurement

v.s

Simulation Tuner

Slider

Extraction Result Viewer

May 7, 2013


67

Extraction

Result Viewer

IC-CAP

•Open and flexible modeling platform

•Turn-key model extraction kits for a

broad range of models

•Allow customization to standard

extraction routines with Python

•Control your entire modeling process

– Instrument control for efficient data

collection

– Seamless data transfer

– Extraction

– Link to design tools

May 7, 2013


68

You are invited

You can find more webcasts

www.agilent.com/find/eesof-innovations-in-eda

www.agilent.com/find/eesof-webcasts-recorded

Matthew Ozalas

Application Engineer

Agilent EEsof EDA

http://www.agilent.com/find/eesof-innovations-in-eda







http://www.agilent.com/find/eesof-webcasts-recorded





Documents

Presentation Title Arial 28pt BoldDr. Iltcho Angelov, Associate Professor, Chalmers University • Part II: Overview of the Angelov-GaN model parameter extraction Dr. Roberto Tinti,