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Presenter : Shau-Jay Hou
Tsung-Cheng LinKuan-Fu Kuo
112/04/18
EICE team
TraceDo: An On-Chip Trace System for Real-Time Debug and Optimization in Multiprocessor SoC
Xiao Hu, Pengyong Ma, Shuming Chen, Yang Guo, and Xing FangSchool of Computer, National University of Defense Technology,Changsha, Hunan, P.R. of China, [email protected]. Guo et al. (Eds.): ISPA 2006, LNCS 4330, pp. 806 – 817, 2006. © Springer-Verlag Berlin Heidelberg 2006
Traditional debug techniques using breakpoints and single stepping are hard to meet the requirements of debug and optimization problems related with temporal behavioral of the real-time programs in multiprocessors. In this paper an on-chip trace system TraceDo (Trace for Debug and Optimization) of a multiprocessor SoC (YHFT-QDSP) is introduced to overcome the debug challenge. Several novel methods including LS encoder, branch configuration bits and configuration instructions, have been presented in TraceDo to trace the program paths, data access and events with timestamps from four Digital Signal Processor (DSP) cores of YHFT-QDSP efficiently. The results of benchmarks show that TraceDo with LS encoder can improve the compression ratio of trace information by 27% than the best reference result on average. When using branch configuration bits, this value goes to 64%.
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Abstract
Debug and Optimization in multiprocessor SoC Traditional method
Breakpoint and signal steppingChange behaviorEasily damaged the mechanical part
Logic analyzerNot useful in higher integration SoC
Soft instruments and profilingIntrusive Consumes excessive system resources
This paper propose method TraceDo(Trace for Debug and Optimization)
On system YHFT-QDSP(銀河飛騰 -32位元微處理器 )Use configuration to controlLow area in chip
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What’s the problem?
embedding debugging architecture for SoCs is introduced [9] Triggers, filters and timestamps are mentioned to support debug of
multipleprocessors [12]. An onchip events monitor on system level is introduced in [17] CoreSight Frame of ARM core defines a multi-core debug and trace
solution in [2][3][4] The IEEE-ISTO NEXUS 5001 STD defines the basic multiple core
debug support for embedded processors and external tools [15][13] Framework of on-chip real time trace of multiprocessor [8]
Graph
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Related work
F Bit(follow bit)◦ indicates if there is another byte followed in this
message
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TraceDo-overview
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Trace Hardware
Path Trace Program Flow Change Model Branches and interrupts
。Direct branches to constant address(BC)。Conditional direct branches to constant address(IBC)。Indirect branches to target address in register(BR)。Conditional indirect branches to target address in register(IBR)。Interrupt to interrupt service routine
Configuration bits。Enable Bits。Force Bits。Degrade Bits
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Messages。Long Chart Message。Short Chart Message。Indirect Branch Message。Synchronization Message。Interrupt Message
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Data Trace and Event Trace Data Trace
。Data transfer by load/store。XOR compression。Synchronization message
Event Trace 。Pipelines stall。Cache missing and DMA busy。Record the counter of taken times or valid cycles of stalls at a
configurable interval
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Trace Messages Combination and Timestamps Two-level combination
。First level： Sort trace messages of three trace unit into trace FIFO
。Second level： Sort trace messages of FIFOs into trace port
Arbitrator。Control which message should be written into FIFO
FIFO。Eight input port。One output pot 。Eight two-port registers。Overflow Synchronization message
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Trace Port Transfer massages package to Emulator
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The configurable functions of trace are programmed through configuration registers. Access by JTAG instructions Also can access by CPU instrucions
NOP_config no-operation instruction High instruction ratio Use to communication with on-chip trace hardware
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Use Verilog-HDL models Benchmark
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Compression of path trace
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Compression of path trace by use degrade bit
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TraceDo is modular and scalable, and it record ： Program path Data access pipeline stall
With several novel methods, TraceDo can reduce the quantity of trace messages effectively and support the tradeoff between precision and bandwidth by configuration.
Future work Degrade Bits selected manually in benchmarks will be
selected by tools automatically16
