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Penn ESE370 Fall2012 -- DeHon 1
ESE370: Circuit-Level
Modeling, Design, and Optimization for Digital Systems
Day 12: October 1, 2012 Variation
Previously • Understand how to model
transistor behavior • Given that we know its parameters
– Vdd, Vth, tOX, COX, W, L, NA …
Penn ESE370 Fall2012 -- DeHon 2
CGC
CGCS
CGCB
But… • We don’t know its parameters (perfectly) 1. Fabrication parameters have error range 2. Identically drawn devices differ 3. Parameters change with environment
(e.g. Temperature) 4. Parameters change with time (aging)
Why I am more concerned with robustness than precision.
Penn ESE370 Fall2012 -- DeHon 3
Today
• Sources of Variation – Fabrication – Operation – Aging
• Coping with Variation – Margin – Corners – Binning
Penn ESE370 Fall2012 -- DeHon 4
Fabrication
Penn ESE370 Fall2012 -- DeHon 5
Process Shift • Oxide thickness • Doping level • Layer alignment • Growth and Etch rates and times
– Depend on chemical concentrations • How precisely can we control those?
• Vary machine-to-machine, day-to-day • Impact all transistors on wafer
Penn ESE370 Fall2012 -- DeHon 6
2
Systematic Spatial
• Parameters change consistently across wafer or chip based on location
• Chemical-Mechanical Polishing (CMP) – Dishing
• Lens distortion
Penn ESE370 Fall2012 -- DeHon 7
FPGA Systematic Variation
• 65nm • Virtex 5
Penn ESE370 Fall2012 -- DeHon 8 [Tuan et al. / ISQED 2010]
Penn ESE370 Fall2012 -- DeHon 9
Oxide Thickness
[Asenov et al. TRED 2002]
Penn ESE370 Fall2012 -- DeHon 10
Line Edge Roughness
• 1.2µm and 2.4µm lines
From: http://www.microtechweb.com/2d/lw_pict.htm
Optical Sources
• What is the shortest wavelength of visible light?
• How compare to 45nm feature size?
Penn ESE370 Fall2012 -- DeHon 11
Penn ESE370 Fall2012 -- DeHon 12
Phase Shift Masking
Source http://www.synopsys.com/Tools/Manufacturing/MaskSynthesis/PSMCreate/Pages/default.aspx
Today’s chips use λ=193nm
3
Penn ESE370 Fall2012 -- DeHon 13
Line Edges (PSM)
Source: http://www.solid-state.com/display_article/122066/5/none/none/Feat/Developments-in-materials-for-157nm-photoresists
Penn ESE370 Fall2012 -- DeHon 14
Intel 65nm SRAM (PSM)
Source: http://www.intel.com/technology/itj/2008/v12i2/5-design/figures/Figure_5_lg.gif
Penn ESE370 Fall2012 -- DeHon 15
Statistical Dopant
Placement
[Bernstein et al, IBM JRD 2006]
Random Trans-to-Trans
• Random dopant fluctuation • Local oxide variation • Line edge roughness • Etch and growth rates
– Stochastic process
• Transistors differ from each other in random ways
Penn ESE370 Fall2012 -- DeHon 16
Penn ESE370 Fall2012 -- DeHon 17
Source: Noel Menezes, Intel ISPD2007
Impact
• Changes parameters – W, L, tOX, Vth
• Change transistor behavior – W? – L? – tOX?
Penn ESE370 Fall2012 -- DeHon 18
€
IDS =µnCOX
2WL
⎛
⎝ ⎜
⎞
⎠ ⎟ VGS −VT( )2[ ]
4
Example: Vth
• Many physical effects impact Vth – Doping, dimensions, roughness
• Behavior highly dependent on Vth
Penn ESE370 Fall2012 -- DeHon 19
€
IDS =µnCOX
2WL
⎛
⎝ ⎜
⎞
⎠ ⎟ VGS −VT( )2[ ]
€
IDS = ISʹ′WL
⎛
⎝ ⎜
⎞
⎠ ⎟ e
VGS −VTnkT / q
⎛
⎝ ⎜
⎞
⎠ ⎟
1− e−VDSkT / q⎛
⎝ ⎜
⎞
⎠ ⎟
⎛
⎝ ⎜
⎞
⎠ ⎟ 1+ λVDS( )
Penn ESE370 Fall2012 -- DeHon 20
Vth Variability @ 65nm
[Bernstein et al, IBM JRD 2006]
Penn ESE370 Fall2012 -- DeHon 21
Impact of Vth Variation?
• Higher VTH? – Not drive as strongly – Id,sat∝ (Vgs-VTH)2 – Performance?
€
IDS =µnCOX
2WL
⎛
⎝ ⎜
⎞
⎠ ⎟ VGS −VT( )2[ ]
Impact Performance
• Vth Ids Delay (Ron * Cload)
Penn ESE370 Fall2012 -- DeHon 22
Impact of Vth Variation
Penn ESE370 Fall2012 -- DeHon 23
Think NMOS Vgs = Vdd
FPGA Logic Variation
• Xilinx Virtex 5 • 65nm
Penn ESE370 Fall2012 -- DeHon 24 [Wong, FPT2007]
• Altera Cyclone-II
• 90nm
[Tuan et al. / ISQED 2010]
5
Penn ESE370 Fall2012 -- DeHon 25
Impact of Vth Variation?
• Lower VTH? – Not turn off as well leaks more
€
IDS = ISʹ′WL
⎛
⎝ ⎜
⎞
⎠ ⎟ e
VGS −VTnkT / q
⎛
⎝ ⎜
⎞
⎠ ⎟
1− e−VDSkT / q⎛
⎝ ⎜
⎞
⎠ ⎟
⎛
⎝ ⎜
⎞
⎠ ⎟ 1+ λVDS( )
Penn ESE370 Fall2012 -- DeHon 26 Borkar (Intel) Micro 37 (2004)
2004
Operation
Temperature Voltage
Penn ESE370 Fall2012 -- DeHon 27
Temperature Changes • Different ambient environments
– January in Maine – July in Philly – Air conditioned machine room
• Self heat from activity of chip • Quality of heat sink (attachment thereof)
Penn ESE370 Fall2012 -- DeHon 28
€
IDS = ISʹ′WL
⎛
⎝ ⎜
⎞
⎠ ⎟ e
VGS −VTnkT / q
⎛
⎝ ⎜
⎞
⎠ ⎟
1− e−VDSkT / q⎛
⎝ ⎜
⎞
⎠ ⎟
⎛
⎝ ⎜
⎞
⎠ ⎟ 1+ λVDS( )
Self Heating
Penn ESE370 Fall2012 -- DeHon 29
Borkar (Intel) Micro 37 (2004)
Thermal Profile for Processor
Penn ESE370 Fall2012 -- DeHon 30
[Reda/IEEE Tr Emerging CAS v1n2 2011]
6
Temperature (on current?)
• High temperature – More free thermal energy
• Easier to conduct • Lowers Vth
– Increase rate of collision • Lower saturation velocity • Lower saturation voltage • Lower peak Ids slows down
• One reason don’t want chips to run hot Penn ESE370 Fall2012 -- DeHon
31
Temperature and Ids
Penn ESE370 Fall2012 -- DeHon 32
Temperature (leakage?)
• High temperature Lowers Vth
Penn ESE370 Fall2012 -- DeHon 33
€
IDS = ISʹ′WL
⎛
⎝ ⎜
⎞
⎠ ⎟ e
VGS −VTnkT / q
⎛
⎝ ⎜
⎞
⎠ ⎟
1− e−VDSkT / q⎛
⎝ ⎜
⎞
⎠ ⎟
⎛
⎝ ⎜
⎞
⎠ ⎟ 1+ λVDS( )
Voltage
• Power supply isn’t perfect • Differs from design to design
– Board to board? – How precise is regulator?
• IR-drop in distribution • Bounce with current spikes
Penn ESE370 Fall2012 -- DeHon 34
Aging
Hot Carrier NBTI
Penn ESE370 Fall2012 -- DeHon 35
Hot Carriers
• Trap electrons in oxide – Also shifts Vth
Penn ESE370 Fall2012 -- DeHon 36
7
NBTI • Negative Bias Temperature Instability
– Interface traps, Holes • Long-term negative gate-source voltage
– Affects PFET most • Increase Vth
• Partially recoverable? • Temperature dependent
Penn ESE370 Fall2012 -- DeHon 37
[Stott, FPGA2010] Another reason not to run hot.
Measured Accelerated Aging (Cyclone III, 65nm FPGA)
Penn ESE370 Fall2012 -- DeHon 38
[Stott, FPGA2010]
Coping with Variation
Penn ESE370 Fall2012 -- DeHon 39
Variation
• See a range of parameters – L: Lmin – Lmax
– Vth: Vth,min – Vth,max
Penn ESE370 Fall2012 -- DeHon 40
Penn ESE370 Fall2012 -- DeHon 41
Impact of Vth Variation
• Higher VTH – Not drive as strongly – Id,sat∝ (Vgs-VTH)2
• Lower VTH – Not turn off as well leaks more
€
IDS = ISʹ′WL
⎛
⎝ ⎜
⎞
⎠ ⎟ e
VGS −VTnkT / q
⎛
⎝ ⎜
⎞
⎠ ⎟
1− e−VDSkT / q⎛
⎝ ⎜
⎞
⎠ ⎟
⎛
⎝ ⎜
⎞
⎠ ⎟ 1+ λVDS( )
Penn ESE370 Fall2012 -- DeHon 42
Variation • Margin for expected variation • Must assume Vth can be any value in range
– Speed assume Vth slowest value
Pro
babi
lity
Dis
tribu
tion
VTH
Ion,min=Ion(Vth,max) Id,sat∝ (Vgs-Vth)2
8
Gaussian Distribution
Penn ESE370 Fall2012 -- DeHon 43
From: http://en.wikipedia.org/wiki/File:Standard_deviation_diagram.svg
Impact
• Given – Vth,nom = 250mV – Sigma 25mV
• What maximum Vth should expect to see for a circuit of – 100 transistors? – 1000 transistors? – 109 transistors?
Penn ESE370 Fall2012 -- DeHon 44
Class ended here
Penn ESE370 Fall2012 -- DeHon 45
Variation
• See a range of parameters – L: Lmin – Lmax
– Vth: Vth,min – Vth,max
• Validate design at extremes – Work for both Vth,min and Vth,max ? – Design for worst-case scenario
Penn ESE370 Fall2012 -- DeHon 46
Margining
• Also margin for – Temperature – Voltage – Aging: end-of-life
Penn ESE370 Fall2012 -- DeHon 47
Process Corners • Many effects independent • Many parameters • With N parameters,
– Look only at extreme ends (low, high) – How many cases?
• Try to identify the {worst,best} set of parameters – Slow corner of design space, fast corner
• Use corners to bracket behavior Penn ESE370 Fall2012 -- DeHon
48
9
Simple Corner Example
Penn ESE370 Fall2012 -- DeHon 49
Vthp
Vthn 150mV
150mV
350mV
350mV
What happens at various corners?
Process Corners • Many effects independent • Many parameters • Try to identify the {worst,best} set of
parameters – E.g. Lump together things that make slow
• Vthn, Vthp, temperature, Voltage • Try to reduce number of unique corners
– Slow corner of design space • Use corners to bracket behavior
Penn ESE370 Fall2012 -- DeHon 50
Range of Behavior
• Still get range of performances • Any way to exploit the fact some are faster?
Penn ESE370 Fall2012 -- DeHon 51
Pro
babi
lity
Dis
tribu
tion
Delay
Penn ESE370 Fall2012 -- DeHon 52
Speed Binning
Pro
babi
lity
Dis
tribu
tion
Delay
Discard Sell Premium
Sell nominal
Sell cheap
Midterm 1 • Contents should not be a surprise
– Identify CMOS/non-CMOS – Identify CMOS function – Any logic function CMOS gate – Noise Margins – Transistor Equations
• All regions and identify operating regions • variation
– Circuit quasistatic configuration and switching delay
Penn ESE370 Fall2012 -- DeHon 53
Admin
• HW4 • First midterm next Monday • Previous midterm
– Solutions linked to 2011 syllabus – Solutions linked to 2010 syllabus
• But only one midterm in 2010 so parts more advanced than where we are now
• Review on Sunday – Time?
Penn ESE370 Fall2012 -- DeHon 54
10
Idea
• Parameters Approximate • Differ
– Chip-to-chip, transistor-to-transistor, over time
• Robust design accommodates – Tolerance and Margins – Doesn’t depend on precise behavior
Penn ESE370 Fall2012 -- DeHon 55