PRINCIPLES OF VLSI SYSTEM PLANNING: A Framework for Conceptual Design

THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE

VLSI, COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING

Consulting Editor Jonathan Allen

Other books in the series:

Logic Minimization Algorithmsfor VLSI Synthesis. R.K. Brayton, G.D. Hachtel, C.T. McMullen, and Alberto Sangiovanni-Vincentelli. ISBN 0-89838-164-9.

Adaptive Filters: Structures, Algorithms, and Applications. M.L. Honig and D.G. Messerschmitt. ISBN 0-89838-163-0.

Introduction to VLSI Silicon Devices: Physics, Technology and Characterization. B. EI-Kareh and R.J. Bombard. ISBN 0-89838-210-6.

Latchup in CMOS Technology: The Problem and Its Cure. R.R. Troutman. ISBN 0-89838-215-7. Digital CMOS Circuit DeSign. M. Annaratone. ISBN 0-89838-224-6. The Bounding Approach to VLSI Circuit Simulation. C.A. Zukowski. ISBN 0-89838-176-2. Multi-Level Simulation for VLSI Design. D.O. Hill and D.R. Coelho. ISBN 0-89838-184-3. Relaxation Techniques for the Simulation of VLSI Circuits. J. White and A. Sangiovanni-Vincentelli.

ISBN 0-89838-186-X. VLSI CAD Tools and Applications. W. Fichtner and M. Morf, Editors. ISBN 0-89838-193-2. A VLSI Architecture for Concurrent Data Structures. W.J. Dally. ISBN 0-89838-235-1. Yield Simulation for Integrated Circuits. D.M.H. Walker. ISBN 0-89838-244-0. VLSI Specification, Verification and Synthesis. G. Birtwistle and P.A. Subrahmanyam.

ISBN 0-89838-246-7. Fundamentals of Computer-Aided Circuit Simulation. W.J. McCalla. ISBN 0-89838-248-3. Serial Data Computation. S.G. Smith, P.B. Denyer. ISBN 0-89838-253-X. Phonologic Parsing in Speech Recognition. K.W. Church. ISBN 0-89838-250-5. Simulated Annealing for VLSI Design. D.F. Wong, H.W. Leong, C.L. Liu. ISBN 0-89838-256-4. Polycrystalline Silicon for Integrated Circuit Applications. T. Kamins. ISBN 0-89838-259-9. FET Modeling for Circuit Simulation. D. Divekar. ISBN 0-89838-264-5. VLSI Placement and Global Routing Using Simulated Annealing. C. Sechen. ISBN 0-89838-281-5. Adaptive Filters and Equalizers. B. Mulgrew, C.F.N. Cowan. ISBN 0-89838-285-8. Computer-Aided Design and VLSI Device Development, Second Edition. K.M. Cham, S-Y. Oh, J.L. Moll,

K. Lee, P. Vande Voorde, D. Chin. ISBN: 0-89838-277-7. Automatic Speech Recognition. K-F. Lee. ISBN 0-89838-296-3. Speech Time-Frequency Representations. M.D. Riley. ISBN 0-89838-298-X. A Systolic Array Optimizing Compiler. M.S. Lam. ISBN: 0-89838-300-5. Algorithms and Techniquesfor VLSI Layout Synthesis. D. Hill, D. Shugard, J. Fishburn, K. Keutzer.

ISBN: 0-89838-301-3. Switch-Level Timing Simulation of MOS VLSI Circuits. V.B. Rao, D.V. Overhauser, T.N. Trick,

l. N. Hajj. ISBN 0-89838-302-1. VLSI for Artificial Intelligence. J.G. Delgado-Frias, W.R. Moore (Editors). ISBN 0-7923-9000-8. Wafer Level Integrated Systems: Implementation Issues. S.K. Tewksbury. ISBN 0-7923-9006-7. The Annealing Algorithm. R.H.J.M. Otten & L.P.P.P. van Ginneken. ISBN 0-7923-9022-9. VHDL: Hardware Description and Design. R. Lipsett, C. Schaefer and C. Ussery. ISBN 0-7923-9030-X. The VHDL Handbook. D. Coelho. ISBN 0-7923-9031-8. Unified Methods for VLSI Simulation and Test Generation. K.T. Cheng and V.D. Agrawal.

ISBN 0-7923-9025-3. ASIC System Design with VHDL: A Paradigm. S.S. Leung and M.A. Shanblatt. ISBN 0-7923-9032-6. BiCMOS Technology and Applications. A.R. Alvarez (Editor). ISBN 0-7923-9033-4. Analog VLSIImpiementation of Neural Systems. C. Mead and M. Ismail (Editors). ISBN 0-7923-9040-7. The MIPS-X RISC Microprocessor. P. Chow. ISBN 0-7923-9045-8. Nonlinear Digital Filters: Principles and Applications. l. Pitas and A.N. Venetsanopoulos.

ISBN 0-7923-9049-0. Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench. D.E. Thomas,

E.D. Lagnese, R.A. Walker, J.A. Nestor, J.V. Rajan, R.L. Blackburn. ISBN 0-7923-9053-9. VLSI Design for Manufacturing: Yield Enhancement. S.W. Director, W. Maly, A.J. Strojwas.

ISBN 0-7923-9053-7. Testing and Reliable Design of CMOS Circuits. N.K. Jha, S. Kundu. ISBN 0-7923-9056-3. Hierarchical Modeling for VLSI Circuit Testing. D. Bhattacharya, J.P. Hayes. ISBN 0-7923-9058-X. Steady-State Methods for Simulating Analog and Microwave Circuits. K. Kundert,

A. Sangiovanni-Vincentelli, J. White. ISBN 0-7923-9069-5. Introduction to Analog VLSI Design Automation. M. Ismail, J. Franca. ISBN 0-7923-9071-7.

PRINCIPLES OF VLSI SYSTEM PLANNING:

A Framework for Conceptual Design

by

Allen M. Dewey IBM

and

Stephen W. Director Carnegie Mellon University

~.

" KLUWER ACADEMIC PUBLISHERS Boston/Dordrecht/London

Distributors for North America: Kluwer Academic Publishers 101 Philip Drive Assinippi Park Norwell, Massachusetts 02061 USA

Distributors for all other countries: Kluwer Academic Publishers Group Distribution Centre Post Office Box 322 3300 AH Dordrecht, THE NETHERLANDS

Library of Congress Cataloging-in-Publication Data

Dewey, Allen M. (Allen Mark), 1956-Principles of VLSI system planning: a framework for conceptual

design / by Allen M. Dewey and Stephen W. Director. p. cm. - (The Kluwer international series in engineering and

computer science. VLSI, computer architecture, and digital signal processing)

ISBN-13: 978-1-4612-8029-3 DOl: 10.10071 978-1-4613-0693-1

e-ISBN-13: 978-1-4613-0693-1

1. Integrated circuits-Very large scale integration-Design and construction-Data processing. 2. Computer-aided design. I. Director, Stephen W. II. Title. III. Series. TK7874.D49 1990

621.39 '5-dc20 90-4215 CIP

Copyright © 1990 by Kluwer Academic Publishers

Softcover reprint of the hardcover 1st edition 1990

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photoco­pying, recording, or otherwise, without the prior written permission of the publisher, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachu­setts 02061.

Contents

List of Figures xi

List of Tables xv

Preface xvii

1 Introduction 1

1.1 Benefits of VLSI System Planning 5

1.2 VLSI System Planning Overview 7 1.3 Comparisons to Previous Related Efforts . 10

1.3.1 General Problem Solving Research 10

1.3.2 VLSI Design Research . 14

1.3.3 DSP Synthesis Research 15

1.4 Organization of Book. . 15

2 Alternatives Exploration 17

2.1 Formalizing Design Knowledge 18

2.2 Hierarchy: Controlling Complexity 23

2.3 Constraints .......... 26

2.3.1 Ordering Constraints . 26

2.3.2 Consistency Constraints 27

2.4 Delaying Design Decisions . . . 28

2.5 Backtracking: Changing Design Decisions 30

v

3 Design Assistance

3.1 Advice .....

33

34

3.1.1 Type of Design Advice. 35

3.1.2 Basis of Design Advice: Discrimination Factors 36

3.1.3 Ranking of Design Advice . . . . 37

3.2 Prediction................. 38

3.2.1 Taxonomy of Prediction Models.

3.2.1.1 Heuristic Models .

39

40

3.2.1.2 Analytical Models 43

3.2.1.2.1 Probability Theory 43

3.2.1.2.2 Graph and Information The-

ory ..... .

3.2.1.3 Simulation Models .. .

3.2.2 Invoking the Prediction Models .

4 General Software Architecture

4.1 User Interface ......... .

45

47

49

53

54

4.2 Conventional/ AI Software Integration ..... 55

4.2.1 Rule-Based Expert System Architecture 56

4.2.2 Data-Driven and Procedure-Driven Control 57

4.3 The Knowledge Base . . . . . . . . . . . . . 60

4.3.1 Blackboard Architecture. . . . . . . 60

4.3.1.1 Advice Knowledge Sources 62

4.3.1.2 Prediction Knowledge Sources 64

4.3.2 State and Context Switching

4.3.3 Controlling Search Time .

65

66

5 A DSP VLSI System Planner 69

5.1 Algorithmic and Architectural Issues 71

5.1.1 Filter Algorithms. . . . . . . 72

5.1.1.1 Time-Domain Characterizations 72

5.1.1.2 Frequency-Domain Characterization 74

5.1.1.3 Discrimination Factors 77

vi

5.1.2 Polynomial Approximation Techniques. 79

5.1.2.1 Discrimination Factors

5.1.3 Filter Architectures ...... .

81

84

5.1.3.1 Algorithm-Specific Architectures 85

5.1.3.2 Filter Structures . . . . . . . . . 87

5.1.3.2.1 Discrimination Factors 91

5.1.3.3 Pipelining............. 94

5.1.3.3.1 Discrimination Factors 95

5.2 Logical Level Issues. . 95

5.2.1 Adder Logic Designs 96

5.2.1.1 Discrimination Factors

5.2.2 Multiplier Logic Designs .....

99

101

5.2.2.1 Encoding Techniques . 102

5.2.2.1.1 Discrimination Factors 103

5.2.2.2 Array Designs . . . . . . . . . . 104

5.2.2.2.1 Discrimination Factors 105

5.2.2.3 Final Adder Designs .

5.3 Circuit and Physical Level Issues . . .

5.3.1 Layout Design Styles ..... .

5.3.1.1 Discrimination Factors

5.3.2 Fabrication Technologies. . . . .

5.3.2.1 Discrimination Factors

6 A DSP Prediction Methodology 6.1 Algorithmic Level Predictions ..

6.1.1 FIR-related Prediction Models

6.1.2 IIR-related Prediction Models.

6.2 Architectural Level Predictions

6.3 Logical Level Predictions

6.3.1 Basic Full Adder

6.3.2 Word Size . . . .

6.3.3 Adder Logic Prediction Models

Vll

106

107

108

110

112

. 112

117

120

120

121

123

124

125

127

128

6.3.4 Multiplier Logic Predictions.

6.4 Physical Level Predictions

6.5 Experimental Results. . .

7 Yoda: Sample Planning Session

7.1 Constraints and Delaying Decisions .

7.2 Advice and Consistency Constraints

7.3 Qualitative and Quantitative Advice

7.4 Context Switching and Subplans

7.5 Backtracking ........ 7.6 Invoking Prediction Models

8 Summary

8.1 Future Work

A Commercial Digital Filter ICs

A.1 TRW.

A.2 NCR.

A.3 Harris

A.4 Zoran

A.5 Inmos

A.6 Motorola.

B Software Implementation Details

B.1 Bicorporal Architecture ..... B.2 Alternatives Exploration Subsystem

B.2.1 Representing Plans . . . .

B.2.2 Representing Constraints

B.3 Design Assistance Subsystem .. B.3.1 Representing Knowledge Sources

B.4 Code Management ............

viii

129

130

133

137

139

141

144

145

147

149

153

. 156

157

158

162

164

166

168

171

175

175

176

177

178

178

181

182

Biblography

Index

IX

185

199

List of Figures

1.1 VLSI System Planning Methodology . . . . 4

1.2 New Planning Level of Design Abstraction. 5

2.1 Constructing a Plan 18

2.2 Design Process ... 18

2.3 Design Issues .... 19

2.4 A Simple Design Decision Tree 22

2.5 A Two-Dimensional Performance Space 23

2.6 Hierarchical Design Issues . 24

2.7 Creating Alternative Plans 29

3.1 Characterizing Design Advice 34

3.2 Types of Prediction Models 40

4.1 General Software Architecture. 54

4.2 Integrating Conventional/AI Software 58

4.3 Blackboard Structure .......... 61

5.1 Lowpass Frequency Response Specification. 76

5.2 Equiripple Approximation ....... 81

5.3 Algorithm-Specific Filter Architecture 86

5.4 Direct Transposed Structure . . 89

5.5 Cascade Transposed Structure. 89

5.6 Parallel Transposed Structure . 90

5.7 Nonpipelined Direct Transposed Structure. 94

Xl

5.8 Pipelined Direct Transposed Structure 94

5.9 Ripple Carry Adder Logic Design . . . 97

5.10 Lookahead Carry Adder Logic Design 98

5.11 Combinational Multipliers 101

5.12 Iterative Multiplier Array 105

5.13 Wallace Multiplier Array. . 106

5.14 Gate Array Layout Design Style . 108

5.15 Standard Cell Layout Design Style . 109

5.16 TTL Fabrication Technology 113

5.17 CMOS Fabrication Technology 113

6.1 Hierarchical Structure of Prediction Models 119

6.2 Sum-of-Products Full Adder. 125

6.3 Transmission Gate Adder . . 126

6.4 Modified Booth's Encoding Hardware 130

6.5 Filter Area/Speed Tradeoffs Using Different Multipliers135

7.1 Yoda Display . . . . . . . . . . . . 138

7.2 Entering Design Specifications. . . 139

7.3 Design Plans, Issues, and Options. 140

7.4 Creating Multiple Plans . . . . . . 141

7.5 Asking For Advice . . . . . . . . . 142

7.6 Example of Consistency Constraints 143

7.7 Example of Advice Ranking 145

7.8 Hierarchical Design Issues . 147

7.9 Example of Backtracking 148

7.10 Directly Invoking Logical Prediction Models. 149

7.11 Final Implementation Performance Predictions 151

8.1 Historical Perspective on Design Automation 155

A.1 TRW TDC1028's Digital Filter Architecture. 159

A.2 TRW TMC2243's Digital Filter Architecture 160

xii

A.3 NCR NCR45CF8E's Digital Filter Architecture . 163

AA Harris' CDSPlOO Digital Filter Architecture. 165

A.5 Zoran's Digital Filter Architecture ...... · 167

A.6 Inmos' Digital Filter Architecture ....... · 170

A.7 Motorola DSP56200's Digital Filter Architecture 172

B.1 Data Structure for a Plan ......... 177

B.2 Three-Tier Memory Management Scheme · 180

Xlll

List of Tables

1.1 Design Plan for a Digital Adder. ............ 2

5.1 Digital Filter Design Issues ... 70

5.2 Digital Filter Algorithms ..... 72

5.3 Polynomial Approximation Techniques 80

5.4 Filter Structures .. 88

5.5 Adder Logic Designs 97

5.6 Encoding Techniques. 102

5.7 Multiplier Array Designs. 104 5.8 Layout Design Styles ... 108

5.9 Fabrication Technologies . 112

6.1 Experimental Results - Area. 134

6.2 Experimental Results - Speed 134

6.3 Experimental Results - Power . 134

xv

Preface

This book describes a new type of computer aided VLSI design tool,

called a VLSI System Planning, that is meant to aid designers dur­

ing the early, or conceptual, state of design. During this stage of

design, the objective is to define a general design plan, or approach,

that is likely to result in an efficient implementation satisfying the

initial specifications, or to determine that the initial specifications

are not realizable. A design plan is a collection of high level design

decisions. As an example, the conceptual design of digital filters

involves choosing the type of algorithm to implement (e.g., finite

impulse response or infinite impulse response), the type of polyno­

mial approximation (e.g., Equiripple or Chebyshev), the fabrication

technology (e.g., CMOS or BiCMOS), and so on. Once a particu­

lar design plan is chosen, the detailed design phase can begin. It is

during this phase that various synthesis, simulation, layout, and test

activities occur to refine the conceptual design, gradually filling more

detail until the design is finally realized. The principal advantage of

VLSI System Planning is that the increasingly expensive resources

of the detailed design process are more efficiently managed. Costly

redesigns are minimized because the detailed design process is guided

by a more credible, consistent, and correct design plan.

However, as important as the conceptual design phase is, the

authors are not aware of any computer aids that can be used to help

the designer during this phase of design. Thus, the only way presently

to determine if a particular design plan will yield a design that meets

specifications is actually to carry out the detailed design process.

Unfortunately, as the complexity of the design grows, this "trial­

and-error" approach becomes increasingly cost prohibitive because

the number of possible design alternatives, as well as the cost of a

complete synthesis and fabrication cycle, grows dramatically.

It is this state of affairs that motivated us to undertake re-

xvii

XVlll

search that would lead to the development of a CAD tool to assist

the conceptual design phase. The result of this work is the con­

cept of VLSI System Planning, which models the practices of an

expert designer in providing guidance at the initial stage of the de­

sign process about the most promising design alternatives and giving

a preliminary indication of the estimated performance. The myriad

of details concerning the design decisions, the interdependencies be­

tween the decisions, and decisions' impact on performance that can

easily overwhelm a designer are now managed by the VLSI System

Planner. The designer is now better able to concentrate on analyzing

the information and constructing the desired conceptual design plan.

Since conceptual design is a new area of CAD research, we felt

it important to find a forum to disseminate the results of our work

to the technical community in a timely fashion, hence the motivation

for this book. In this book, we describe not only a general methodol­

ogy for VLSI System Planning, but we illustrate the concept with a

particular VLSI System Planner called Yoda. Yoda is aimed at pro­

viding help during the conceptual design of digitial signal processing

filters.

The work described in this book constituted the Ph.D. re­

search of the first author, under the supervision of the second author.

We gratefully acknowledge the financial support of the Semiconduct­

gor Research Corporation and TRW.

Allen M. Dewey

Stephen W. Director

Pittsburgh, PA

PRINCIPLES OF VLSI SYSTEM PLANNING: A Framework for Conceptual Design