NDA required until November 11, 2008

The World Leader in High Performance Signal Processing Solutions

DSP Processors

2

Analog Devices Processors – Broad Choice of DSPs

Blackfin®

Media Enabled, 16/32-bit fixed point

Micro + DSP

Networked Media

Automotive Infotainment

Automotive Vision

SHARC®

Floating Point

Motor Control

Industrial Control

Professional Audio

SigmaDSP®

Low-Cost

Audio, post

processing

Integrated Codecs

Algorithms

Easy to Use

(SigmaStudio)

BF561 BF60x BF592 BF512

BF514

BF516

BF518

BF535 BF522

BF524

BF526

BF504

BF506

BF531

BF532

BF534

BF536

BF523

BF525

BF527

BF538

BF539

BF537

BF533 BF542

BF544

BF547

BF548

BF549

Highest Performance

Lower Power

Blackfin Processor Portfolio

Low Standby

Lockbox™ Security

System Integration

(Flash, Mixed-Signal)

Multicore

600 MHz or Greater

Lowest BOM Cost

Baseline Connectivity

System-Level

Connectivity

Future

The New Blackfin ADSP-BF592

Best-in-class cost/performance

• 400 MHz for $3 at 10k

• Performance up to 400 MHz (dual MAC)

• Small Footprint 9x9mm – 5 MIPs/mm2

• Lowest pin count Blackfin 64 LFCSP

Low cost development tools

• $199 BF592 EZ-KIT Lite

• $150 ICE-100B Blackfin Emulator

• 90 day VisualDSP++ Test Drive

Blackfin BF592 Low-Cost, Low-Power Embedded Processor

Test and

Emulate

Interrupt

Controller

Watchdog

Timer

32 bit

Core Timer

PLL & Power

Management

400MHz Blackfin Processor Core

L1

Data

SRAM

32kB

Data

Scratchpad

SRAM 4kB

Instruction

ROM

64kB

Instruction

SRAM

32kB

DMA

Controller

I/O Signal Multiplexing

TWI SPORT0,1; SPI0,1; UART 16-bit PPI

ITU-656

3 x 32 bit

Timer/Counters

32 GPIO’s

L3

Boot

ROM

4kB

90nm LP process

16-bit PPI (ITU-R 656)

Dual SPORT

Dual SPIs

400 MHz maximum core

clock frequency

36kB data SRAM, 32kB

instruction SRAM

64kB L1 instruction ROM

VDK & RTL

4kB L3 boot ROM

<1mA static leakage current

(typ at 25C)

Fully software compatible

with BF5xx family

9mm x 9 mm 64 LFCSP

(QFN) package

-40°to +85°C

SHARC Processor Portfolio

21266 21362

21363

21364

21368

21369

21365

21366

21367

21483

21486

21487

21488

21489

21467

1ADSP-21363, 21364, and 21366 do not have hardware accelerators.

Automotive grade available.

21469 21261

21262

21371

21375 1

21478

21479

Higher Performance

Application-Specific Peripherals

Configurable Applications

I/O Interface

Low Cost

Audio Decoders in ROM

Hardware Accelerators

High Speed Interprocessor

Communication (Link Ports)

Performance > 2 GFLOPS

1

1

Future

Low Power

6

3rd & 4th Generation SHARC Comparison

7

Family 21364 21369 21371 21469 2147x 2148x

Performance 200 - 333MHz 266 - 400MHz 200 - 266MHz 400 - 450MHz 200 - 266MHz 300 - 400MHz

MMACS 400 –666MMACS 532 - 800MMACS 400 - 532MMACS 800 - 900MMACS 400 - 532MMACS 600 - 800MMACS

On-chip

SRAM

3Mbits 2Mbits 1Mbits 5Mbits 5Mbits (21479)

3Mbits (21478)

5Mbits (21489)

3MBits (21488)

External

Memory I/F

SRAM, Flash 32-bit SDRAM,

SRAM, Flash

32-bit SDRAM,

SRAM, Flash

16-bit DDR2,

SRAM, Flash

16-bit SDRAM,

SRAM, Flash (BGA only)

16-bit SDRAM,

SRAM, Flash (LQFP 24x24 only)

Key

Peripherals

6 SPORT, 2 SPI

PWM, SPDIF,

2 PCG

8 SPORT, 2 SPI,

2 UART, TWI,

PWM, SPDIF,

4 PCG

8 SPORT, 2 SPI,

UART, TWI

PWM, SPDIF,

4 PCG

8 SPORT, 2 SPI,

UART,TWI,PWM

SPDIF, 4 PCG,

2 Link Ports

8 SPORT, 2 SPI,

UART, TWI,

4 PWM, SPDIF,

4 PCG

8 SPORT, 2 SPI,

UART, TWI,

4 PWM, SPDIF,

4 PCG

Other

features

ASRC ASRC - ASRC,

FIR/IIR/FFT,

VISA Code

ASRC, WDT

RTC, Shifter,

FIR/IIR/FFT,

VISA Code

ASRC, WDT,

FIR/IIR/FFT,

VISA Code

Core Power (Max, 25oC)

960mW

(333MHz, 1.2V)

1430mW

(400MHz, 1.3V)

720mW

(266MHz, 1.2V)

773mW

(450MHz, 1.1V)

193mW

(266MHz, 1.2V)

617mW

(400MHz, 1.1V)

Package

Options

LQFP 20x20mm

BGA 12x12mm

LQFP 28x28mm

BGA 27x27mm

LQFP 28x28mm BGA 19x19mm LQFP 14x14mm

BGA 12x12mm

LQFP 14x14mm

LQFP 24x24mm

Max Ambient

Temp Option

+85oC 333MHz

+105oC 200MHz

+70oC 400MHz

+85oC 333MHz

+85oC 266MHz

+105oC 200MHz

+70oC 450MHz

+85oC 400MHz

+85oC 266MHz

+105oC 200MHz

+85oC 400MHz

Schedule Released Released Released Released X-grade : Oct ‘10

RTP : Mar’11 (QFP)

Apr’11 (BGA

X-grade : Now

RTP : Dec’10

Price (1K QTY) Lowest Cost Device

$29.15 (333MHz)

$19.69 (266MHz)

$13.27 (266MHz)

$28.50 (400MHz)

$7.99 (200MHz 21478 100QFP)

$10.35 (300MHz 21488 100QFP)

SHARC Products with optional ROM are not listed here

ADSP-214xx Features Comparison Table ADSP

21467

ADSP

21469

ADSP

21478

ADSP

21479

ADSP

21483

ADSP

21486

ADSP

21487

ADSP

21488

ADSP

21489

Max Core Frequency (MHz) 450 450 266 266 400 400 400 400 400

Core Voltage (V) 1.1 1.1 1.2 1.2 1.1 1.1 1.1 1.1 1.1

RAM (Mbit) 5 5 3 5 3 5 5 3 5

ROM (Mbit) 4 0 0 0 4 4 4 0 0

Audio Decoders in ROM Yes N/A N/A N/A Yes Yes Yes N/A N/A

ASRC Performance (up to) -128 db -128 db -128 db -128 db -128 db -128 db -128 db -140 db -128 db

DDR2 16-bit 16-bit N/A N/A N/A N/A N/A N/A N/A

SDRAM N/A N/A 16-bit 16-bit 16-bit N/A 16-bit 16-bit 16-bit

Asynchronous Mem Int 8-bit 8-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit

Link Ports 2 2 NO NO NO NO NO NO NO

Thermal Diode YES YES YES YES YES YES YES YES YES

Watchdog Timer NO NO YES YES YES YES YES YES YES

Real Time Clock NO NO YES YES NO NO NO NO NO

Shift Register NO NO YES YES NO NO NO NO NO

Package 324-Ball

CSP_BGA

196-ball CSP_BGA

(12 x 12 mm) 176-ld LQFP_EP (24 x 24 mm)

100-ld LQFP_EP

(14 x 14 mm) 100-ld LQFP_EP (14 x 14 mm)

Common Features VISA, 8 SPORTs, 2 SPIs, S/PDIF, UART, TWI, 4 PWMs, MLB, DTCP, MTM, 4 PCGs, 2 Timers,

DAI/DPI (SRUs), IDP/PDAP; FIR, IIR, and FFT HW acc, Direct DMA from SPORT to External Port

• Only available in 100-ld LQFP package

• Not available in 100-ld LQFP package

• Pin compatible packages

• Only 3 PWMs available in 100-ld LQFP package

• Automotive only

8

9

ADSP-21469 Block Diagram

450 MHz (1.1V)

SHARC5

Enhanced Core

5Mb

RAM DDR2 DRAM

225 MHz

Async

Mem I/F

Precision Clock

Generators (4)

SPDIF Rx/Tx

SPORTs (8)

Input Data

Port/PDAP

ASRC

DAI

Routing U

nit

SPI (2)

GPIO

GP Timers (2)

UART

DPI

Routing U

nit

DMA

Controller

JTAG Test & Emulation

Digital Audio Interface

Digital Peripheral

Interface

IOP Register

Control, Status, Data

8 Data

External Port

IRQ/ Flags

24 Addr

I/O Processor

TWI

FFT

Engine

Link Ports(2)

16

64

32

DAI Pins DPI Pins

20 14

Thermal

Diode

FIR

Engine

IIR

Engine

16/8 Data

DEVELOPMENT TOOLS

Anal

og

Devi

10

“Andromeda” Integrated Development Environment

Based upon the Eclipse IDE framework

• Extensible framework, tools and run-times

• Optimized for ADI processors

• Supporting unicore, homogeneous and heterogeneous multicore devices

Multiple Toolchain Support

• gcc toolchain

• Blackfin

• ARM (Linaro based)

• Proprietary toolchain

• DSPs

Blackfin

SHARC

• Code generation improvements

Assembly

ANSI C99, ANSI C++2003, Embedded C99

32 bit FRACT support

Advanced debugging capabilities

• MISRA-C (Motor Industry Software Reliability Association)

• Static code analysis

• Stack overflow detection

• Heap tracking

Windows and Linux host support

11 Anal

og

Devi

“Andromeda” IDE

12 Anal

og

Devi