Kautalya Mishra

MULTI-CYCLE DATAPATHCLOCKCTR

Unnecessary power is consumed by components that are not currently in use in an instruction cycle. This power can be reduced by appropriately turning off clocks that feed into them.

Ideally we would expect a good amount of power saving in all the components being clocked and also in the combinational elements the registers are feeding into.

MOTIVATION

CLOCK-GATING

CLOCK

CTRLCLKout

COMPONENTS CLOCK-GATED

1. MEMORY2. REGISTER FILE3. MEMORY DATA REGISTER4. INSTRUCTION REGISTER5. PC REGISTER6. ALUOUT REGISTER7. 16 BIT REGISTERS

CODE THE DATAPATH, CONTROL UNIT AND THE MEMORY IN VHDL

CONVERT THE VHDL FILE TO A VERILOG FORMAT USING LEONARDO SPECTRUM ~ TECHNOLOGY 180 nm

CONVERT THE VERILOG GATE LEVEL NET LIST TO A RUTGURS

MODE FORMAT USING THE POWERSIM TOOL

ESTIMATE POWER CONSUMED BY THE PROCESSOR WITH AND WITH CLOCK-GATING AND EVALUATE POWER SAVING

GENERATED A GATE LEVEL NETLIST IN DESIGN ARCHITECT

VHDL MODELSWITHOUT CLOCK-GATING

WITH CLOCK-GATING

CLOCK

CLOCK

CTR

DA

TA

IN D

AT

A

IN DA

TA

O

UT

DA

TA

OU

TREGISTER

REGISTER

POWER ESTIMATIONStarted off by attempting to estimate power

consumed by the processor as a whole using the POWERSIM tool but no results were obtained because of a segmentation fault.

Estimated power consumed by each component feeding in appropriate (not random!) input vectors that would have flown through in the datapath otherwise.

Output loading of an individual component is not considered

RESULTS COMPONENT

DYNAMIC POWER LEAKAGE POWER

CLK CLK-GAT

SAVING CLK CLK-GAT SAVING

regMDR 3.73 mW 0.22 mW +94.1% 3.69 uW 2.16 uW +41.46%

regIR 4.086 mW 2.44 mW +40.29% 10.79 uW 6.16 uW +42.91%

regA 2.87 mW 1.06 mW +63.07% 3.69 uW 6.12 uW -65.85%

regB 2.87 mW 1.06 mW +63.07% 3.69 uW 6.12 uW -65.85%

Register File

48.68 mW 19.17 mW +60.62% 107.87 uW 61.59 uW +42.91%

regALUOUT

7.56 mW 3.20 mW +57.67% 13.69 uW 21.26 uW -55.30%

regPC 6.49 mW 3.46 mW +46.69% 6.16 uW 10.78 uW -75%

Memory 69.17 mW 62.83 mW +9.17% 107.87 uW 123.19 uW -14.9%

--Power estimation done over the first 10 input vectors--

The leakage losses in some components can be expected as the component is in an off state longer. Some components show high leakage losses (like -75%) but that is only because of the small values of the leakage power.

TOTAL POWER SAVING

COMPONENTTOTAL POWER

CLK CLK-GAT SAVING

regMDR 3.73369 mW 0.22216 mW 94.04%

regIR 4.09679 mW 2.44616 mW 40.40%

regA 2.87369 mW 1.006612 mW 64.97%

regB 2.87369 mW 1.006612 mW 64.97%

Register File 48.78787 mW 19.23159 mW 60.58%

regALUOUT 7.57369 mW 3.22126 mW 57.47%

regPC 6.496116 mW 3.47078 mW 46.57%

Memory 69.27787 mW 62.95319 mW 9.13%

TOTAL 145.71340 mW 93.55837 mW 35.79%

POWER SAVING IN regMDR

CONCLUSION

Clock-gating is a very neat way of reducing power consumed in a processor. Its authenticity however would have to be verified over longer clock cycles and for varying technologies.