PRODUCT SPECIFICATION - Heilind Electronics · 2015-11-20 · product specification revision: ecr/ecn information: title: product specification for hyperjack™ 1000 magnetic poe

PRODUCT SPECIFICATION

REVISION: ECR/ECN INFORMATION: TITLE: PRODUCT SPECIFICATION FOR HYPERJACK™ 1000 MAGNETIC

POE PLUS PSE ICM 1X1

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DOCUMENT NUMBER: CREATED / REVISED BY: CHECKED BY: APPROVED BY:

PS-85759-001 A.Papaevangelou P.Butschbach S.Steinke


FOR 1x1 HYPERJACK 1000 MAGNETIC PoE PLUS POWER

SOURCING EQUIPMENT

INTEGRATED CONNECTOR MODULE (PSE-ICM)

SCOPE This specification defines the functionality as well as the mechanical and electrical interfaces to the Molex 85759-series family of HyperJack 1000 Magnetic PoE Plus PSE-ICMs.




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1.0 PRODUCT DESCRIPTION INTRODUCTION The PSE-ICM offers the simplest solution for the design of a single-port Power Sourcing Equipment (PSE) that complies with IEEE 802.3at for Power over Ethernet (PoE). The PSE-ICM is a module that contains the entire single-port PSE except the power supply. The PSE-ICM includes the RJ45 connector with up to two LED’s, gigabit Ethernet magnetics, and high-power PSE controller. Just connect a power supply and it's ready to run with complete autonomy. The modular approach of using a PSE-ICM can significantly accelerate product time-to-market by reducing risks. The issues that often cause expensive, last-minute design changes and schedule slips such as isolation, EMI, surge immunity, heat dissipation, signal integrity, and UL certification – are all greatly simplified when using the PSE-ICM. The PSE-ICM also includes a simple interface that allows a host processor to enable or disable it, and read its status. Additionally, its wide operating temperature range makes the PSE-ICM particularly well suited for industrial applications, or where no air circulation is available, such as inside a power injector.

PRODUCT NAME AND SERIES NUMBER

Single port PoE Plus PSE ICM 1x1 85759 Series See SD-85759-001 for information on dimensions, materials, plating, markings & product options.

FEATURES

Complete high-power PSE module

PSE-ICM Power Interface pinout: MDI-X (Vmain_neg on pair 1-2, Vmain_pos on pair 3-6)

Fully complies with IEEE 802.3at (backward compatible to IEEE 802.3af)

Fully autonomous operation

10/100/1000 Base-T magnetics

Temperature range: 0°C to 70°C, see section 4.4.4 for more details

Operating Voltages:

PoE+: 50V to 57V supply

PoE: 44V to 57V supply

Provides up to 30W PSE output

Total input-to-output resistance < 1.2Ω (from Power input to RJ45 output)

Reliable 4-point detection protocol

DC-disconnect sensing

Class-dependent cutoff current threshold

LED indication of PD powered state

Power budget set by external resistor

2250Vdc isolation SAFETY AGENCY APPROVALS

UL File Number……………………E355595




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APPLICABLE DOCUMENTS AND SPECIFICATIONS Molex sales drawing See SD-85759-001 for information on dimensions, materials, plating and markings.

Molex Packaging Spec

PK-85759-001

IEEE 802.3 Amendment

Data Terminal Equipment (DTE) Power via Media Dependent Interface (MDI) Enhancements IEEE 802.3at This specification is available from the IEEE, (www.standards.ieee.org/getieee802) IEC 60603-7-1 TIA-568-C FCC PART 68 1.1 ABSOLUTE MAXIMUM RATINGS (NOTE 1)

Maximum Voltages

VMAIN_POS (Note 2) -30V, 72V

RESET, MAX_CLASS/STATUS (Note 3) +3.6V, -0.3V

Maximum Currents

RESET, MAX_CLASS/STATUS (Note 3) ±2mA

LED's ±20mA

PHY, MDI Pins ±1A

Control Pins X1 to X6 ±700mA

Temperature Ranges

Operating (case temp) 0°C to 70°C

Storage -55°C to 70°C

ESD (Human Body Model)

PHY, MDI Pins 10kV

Other Pins 2kV

Table 1 – Absolute Max Ratings

http://www.standards.ieee.org/getieee802




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2.0 ELECTRICAL CHARACTERISTICS Minimum and Maximum values are guaranteed through design, test, or statistical correlation. Numbers in bold type represent limits over the operating temperature range; numbers in plain type represent performance at 25°C. Typical numbers represent the most likely values at 25°C and are included for reference purposes only.

Symbol Parameter Notes and Conditions

Min Typ Max Units

Power Supply

VMAIN_POS Supply voltage operating range

PoE+ (IEEE 802.3at), Note 12

50.0 57.0 V

PoE (IEEE 802.3af), Note 12

44.0 57.0

Supply voltage slew rate

Note 11 0.001 V/µs

IEE Supply current VMAIN_POS = 57V. No PD Connected

2.9 3.2 3.5 mA

VUVLO Undervoltage lock-out threshold

38.0 40.0 42.0 V

Detection

RGOOD_MIN Min valid signature resistance

15.5 17.2 18.9 kΩ

RGOOD_MAX Max valid signature resistance

26.5 29.4 32.0 kΩ

CGOOD_MAX Max valid signature capacitance

1.0 2.0 3.0 μF

ISC Short-circuit output current

VMAIN_POS = 57V 3.0 mA

VDET1 Output voltage, level 1

2.9 4.3 4.9 V

VDET2 Output voltage, level 2

7.2 8.9 9.5 V

VOC Open-circuit output voltage

8.0 10.0 V

Classification

VCLASS Class event output voltage

ICLASS = 0 to 50mA 16.0 17.5 19.0 V

ICLASS_LIM Short-circuit output current

73.0 mA

tCLE Width of class event 19.0 20.0 20.5 ms

tME Width of mark event 7.9 8.0 8.1 ms

VMARK Mark event output voltage

7.0 8.5 10.0 V




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Symbol Parameter Notes and Conditions

Min Typ Max Units

Inrush and Short-Circuit Protection

ILIM Current limit level (Note 6)

During inrush, and PD classes 0-3 after

400.0 425.0 450.0 mA

Only for class-4 PD after inrush

816.0 850.0 884.0 mA

tLIM Current limit timer Single overload event Note 7

53.0 54.0 59.0 ms

tINRUSH Delay before setting ICUT and ILIM

Note 6 69.0 70.0 71.0 ms

tED Error delay time 792.0 1000.0 1200.0 ms

ON State

RPORT Total input-to-output resistance

Note 8 1.0 1.2 Ω

tOVLD Overload time limit Single overload event

Note 7 50.0 54.0 75.0 ms

ICUT Cutoff current threshold

PD class = 0 or 3

367.0 375.0 385.0 mA

(Note 6) PD class = 1 100.0 112.0 114.0 mA

PD class = 2 201.0 206.0 210.0 mA

PD class = 4 624.0 638.0 652.0 mA

DC Disconnect Sensing

IMIN Disconnect current threshold

6.0 7.5 9.0 mA

tMPDO Disconnect drop-out time

346.0 350.0 354.0 ms

tMPS Disconnect validity time

9.0 10.0 11.0 ms

Digital Logic Levels (Note 3)

VOH MAX_CLASS/STATUS output high voltage level

IOUT = 0 to -1.5mA

2.8 3.4 V

VOL MAX_CLASS/STATUS output low voltage level

IOUT = 0 to 1.5mA

0.25 V

VIH RESET input high voltage level

2.5 V

VIL RESET input low voltage level

0.7 V




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Symbol Parameter Notes and Conditions Min Typ Max Units

LED’s

VF Forward voltage drop, IF = 20mA

Yellow LED. 2.0 2.5 V

Green LED. 1.75 2.35 V

Orange LED. 1.7 2.30 V

IO Luminous intensity, IF = 20mA

Yellow LED. 5 10 mcd

Green LED. 5 10 mcd

Orange LED. 5 10 mcd

Note 1: Absolute Maximum Ratings are limits beyond which permanent damage to the device may occur. Note 2: VMAIN_POS refers to the input pin for the positive rail of the power supply; VMAIN_POS refers to the voltage applied to the VMAIN_POS pin with respect to VMAIN_NEG. Note 3: Voltages on digital lines RESET and MAX_CLASS/STATUS are referenced to the VMAIN_NEG pin which is the digital return. Note 4: VPORT is the output voltage of the PSE-ICM. MDI pins 3 and 6 are the positive side of VPORT. MDI pins 1 and 2 are the negative side of VPORT. Note 5: IPORT is the output current of the PSE-ICM. Positive current flow comes out of MDI pins 3 and 6, and returns to MDI pins 1 and 2. Note 6: When the PSE-ICM first applies power to the PD, ILIM and ICUT start at 425mA and 375mA respectively. After time tINRUSH has expired, ILIM and ICUT are adjusted according to the class of the PD. Note 7: The time given is for a single overload event that persists until the PSE-ICM turns off the port. If multiple consecutive overload events occur, each less than 54ms in width, then the time limit is automatically shortened to prevent the MOSFET from overheating. A gap of at least 1 second between overload events is required for the timer to return to its full value. Note 8: Total input-to-output resistance is measured under the following conditions: MDI pin 3 tied to pin 6; MDI pin 1 tied to pin 2; and the power MOSFET is fully on. RPORT is the sum of two resistances: from VMAIN_POS to MDI pins 1 and 2; and from VMAIN_NEG to MDI pins 3 and 6. Note 9: The compliances shown apply to the PSE-ICM alone; compliance issues may arise when the PSE-ICM is used in a system due to factors not associated with the PSE-ICM, such as noise generated by other components in the system or PCB layout problems. Note 10: For details of ESD tests required, see Section 5.5

Note 11: Minimum rating condition for external supply to ensure stable operation during power up of the system. Note 12: input to output resistance losses to be considered for the expected VPort_PSE in the POWER_ON state.




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2.2 TYPICAL PERFORMANCE CURVES




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3.0 SYSTEM OVERVIEW

3.1 MAGNETIC WIRING SCHEMATIC DIAGRAM

The following is the magnetic wiring schematic diagram for the Ethernet and PoE terminals on the HyperJack PoE Plus PSE-ICM 1x1.

Figure 1 – PoE and Ethernet magnetic wiring schematic diagram with power connection and power protection components




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3.2 TERMINAL DESCRIPTION/FUNCTION FOR HYPERJACK 1000 POE PLUS PSE-ICM 1X1

Figure 2 – Terminal Description

3.2.1 PIN FUNCTIONS

CONTROL TERMINALS VMAIN_POS: Pin X1. Positive Voltage input from power supply. VMAIN_NEG: Pin X5. Negative Voltage input from power supply. Also serves as the return line for RESET and MAX_CLASS/STATUS. RESET: Pin X4. Tie the RESET input to VMAIN_NEG to force the PSE-ICM to turn off power to the PD. To reset the PSE apply VMAIN_NEG to this pin for at least >5ms. During normal operation the RESET pin is pulled up by internal resistor and should therefore be left floating. Do not connect RESET to VMAIN_POS it will damage the PSE. MAX_CLASS/STATUS: Pin X2. This is a dual-function pin that is referenced to VMAIN_NEG. Do not connect MAX_CLASS/STATUS to VMAIN_POS. When the power supply comes up, or RESET goes high, MAX_CLASS/STATUS is temporarily an input that senses the external max-class resistor (RMC). After sensing RMC the pin becomes a status output; high indicates that a PD is being powered, low indicates there is no PD connectors, or the PD is being denied power because its class is greater than the maximum class set by RMC.




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DNC: Pin X3. DO NOT CONNECT. This pin is for factory test purposes only. Leave this pin floating. ETHERNET TERMINALS VCC: Pin 1. Input used to dc bias voltage required by PHY transceivers. VCC connects to the centre taps of all internal Ethernet transformers on the PHY side. In most applications the VCC pin is connected to the positive supply rail that powers the PHY chip, but consult the PHY data sheet to be sure. Do not add components (e.g. resistors, chokes, ferrites) in series with the VCC pin unless the PHY data sheet recommends it.

GND: Pin 7. Return line for Ethernet data lines (MD1+/- through MD4+/-). GND is coupled to VCC with internal capacitors. Connect GND to digital ground plane for the PHY and keep it isolated from VMAIN_POS, VMAIN_NEG. Connection to chassis ground is at the discretion of the system designer. TD0+/-: Pins 8 & 9. Differential data lines from the transformer that connects to pins 1 and 2 on the RJ45 connector. TD1+/-: Pins 3 & 2. Differential data lines from the transformer that connects to pins 3 and 6 on the RJ45 connector. TD2+/-: Pins 4 & 5. Differential data lines from the transformer that connects to pins 4 and 5 on the RJ45 connector. TD3+/-: Pins 11 & 10. Differential data lines from the transformer that connects to pins 7 and 8 on the RJ45 connector. LED Terminal Detail The below image details the front of the connector and highlights the two LED locations on the HyperJack PoE Plus PSE-ICM 1x1. Note there is also a Non-LED version.

Figure 3 - Image of connector front face indicating LED's

Left LED Right LED




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Right LED, Pins 13 & 14: Option for non-integrated LED. Pins for the LED on the right side of the module (looking from the front with pins facing down). Left LED, Pins 15 & 16: Pins for the LED on the left side of the module (looking from the front with pins facing down). There are two primary options for the LED’s in the 85759 series connectors: 1: Two independent LED’s with external pins to customer PCB 2: One independent LED (Pins 15 & 16) and one integrated LED which is linked to PoE functionality to indicate power is being delivered by the PSE using the STATUS output (pin X2). Note on LED isolation: Section 4.4.2 of this document details the isolation requirements for the PSE-ICM, as part of that, the LED’s are defined as being part of the PHY side isolation group. If using the independent LED’s to indicate any user defined operation, great care must be taken to ensure that sufficient isolation is maintained. See Sales Drawing for detailed options on LED colours and Part Numbers.

Figure 4 - LED Schematics




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4.0 APPLICATION Power over Ethernet (PoE) has played a key roll over the past several years in the growth of VoIP, wireless computer networking, video surveillance systems, and many other markets. But the limitations of the IEEE 802.3af standard – particularly the 12.95W limit – have constrained some applications. That's why in 2009 the IEEE ratified the long-awaited 802.3at standard which includes several key improvements: higher power levels (a class 4 PD may consume up to 25.5W), an improved physical-layer classification protocol, and enhanced power management via a new layer-2 protocol called LLDP. These improvements have opened the door for a wave of new PoE applications which will mean substantial growth for the industry, but the PSE designer still faces some difficult challenges. New PSE controller chips are slowly emerging, but they still leave lots of work for the PSE designer because the higher power levels means that heat dissipation, PCB layout, and EMI are all more difficult. Additionally, the new 802.3at standard is even more complicated and confusing than the original. And of course, designers are under pressure to bring their products to market quickly to get ahead of the competition. The PSE-ICM offers the simplest solution to these headaches. It is a complete PSE front end, including Ethernet magnetics, and PSE controller in a space-saving package. Furthermore, it operates over a wide temperature range without forced air. The biggest advantage of the PSE-ICM is that it reduces risk. Projects often go over budget and fall behind schedule because of bugs discovered late in the development cycle. Some of the most common issues involve heat dissipation, EMI, isolation, signal integrity, UL certification, surge immunity, ESD, or production test issues. The PSE-ICM significantly reduces the impact of such issues. For example, if you use a PSE controller chip, you need other discrete components to go with it, such as the Ethernet magnetics, transient suppressor diodes, decoupling caps, common-mode terminations, etc. With a discrete approach, you have to connect a PD to the port and verify it gets detected and powered. But even that is not always sufficient to assure quality since some assembly defects can go undetected. For example, if one of the protection diodes isn't properly soldered, your product could be vulnerable to surges; the PD test would never detect this. So with the discrete approach the engineer usually ends up having to spend time and effort designing test fixtures and circuits, and writing test procedures and software. In contrast, the PSE-ICM is a fully tested module. Production test is greatly simplified because there just are not as many opportunities for assembly or handling defects to creep in. All that is required is to solder the PSE-ICM to your board properly, ensure the power supply is working. The PSE-ICM can even indicate status through the right LED at power-up to signal that it is working, without having to connect a PD. In summary, the PSE-ICM reduces the burden on designers, leaving them free to focus on the rest of system. Furthermore, the risk of discovering bugs and compliance issues late in the development cycle is greatly reduced, time-to-market is shortened, and production test is simpler.




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4.1 MODES OF OPERATION

4.1.1 DETECTION Not all network devices are designed to accept power via the network cable. The PSE must not apply power to such devices; therefore, the PSE must use a detection process to identify the devices that require power. The detection process defined by the IEEE looks for the presence of a detection signature composed of a resistor (RSIG) in parallel with a capacitance (CSIG). A valid PD will present this signature while VPORT is in the detection range, 2.8V to 10V. Figure 5 shows the ranges of valid and invalid signatures. The inner shaded zone represents the range of signatures the PSE must always accept as valid. Signatures in the outer shaded zone must always be rejected by the PSE as invalid. Figure 4 also shows the characteristic curve of the PSE-ICM; signatures outside this curve are rejected, while signatures inside are accepted. Since the curve doesn't touch either shaded region, it meets the IEEE requirements. The PSE-ICM determines RSIG by outputting two voltage levels (VDET1 and VDET2) and measuring the resulting current at each level. RSIG=ΔV/ΔI. One problem some early PSE controllers had was they could be fooled by an invalid signature, if it was connected at just the right instant during the detection cycle. The PSE-ICM eliminates these false detections by using a 4-point process as shown in Figure 4. It essentially does the normal 2-point process twice; the signature must be valid both times in order for the PSE-ICM to accept it.

4.1.2 CLASSIFICATION

After a valid PD is detected, the PSE must determine how much power it needs. PDs are categorized into five classes (0 to 4) according to their power requirements. (See Table 2) Figure 6 shows the classification process when a class 4 PD is present. A class event is when VPORT is in the classification range (15.5V to 20.5V). The PD responds by sinking a fixed current; the magnitude of this current indicates its class. If the PD presents a class 4 signature during the first class event, then the PSE-ICM performs a second class event as shown in Figure 6. This second pulse notifies the PD that the PSE-ICM is capable of supplying more than 12.95W (the max limit under the old 802.3af standard). The mark events (where VPORT = VMARK) are used to separate the class events. The PSE-ICM is told how much power is available from the supply by an external resistor RMC. (See the section Setting the Maximum PD Class.) If the PD is not asking for more power than is available, then the PSE-ICM will go to the inrush phase.




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Figure 5 – Detection Signature Range

Figure 6 – Detection / Classification Waveforms




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4.1.3 INRUSH When the PSE-ICM turns on the port there will be an inrush current as capacitors inside the PD charge up. The input capacitance of the PD after start-up is required to be at least 5μF, and can be up to several hundred μF. The PSE-ICM limits the inrush current so that the supply voltage doesn't sag. (See the section Current Limiting.) After a delay of tINRUSH the ICUT and ILIM thresholds are automatically adjusted according to the PD class, as shown in Figure 8.

Figure 7 – Current Limiting

Figure 8 – Inrush Timing




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4.1.4 CURRENT LIMITING During and after inrush, the PSE-ICM limits IPORT to ILIM as shown in Figure 7. The shaded zones indicate the IEEE 802.3at requirements. When a short circuit occurs IPORT can briefly spike to a high peak, but the PSE-ICM quickly brings IPORT inside the 400mA to 450mA pipe. (If the PD is class 4, then after inrush the pipe doubles to 800mA/900mA and ILIM increases to 850mA as shown in Figure 8.) During the short-circuit event the power dissipation in the MOSFET is very high, but PSE-ICM has two features that protect the MOSFET from overheating: First, the tLIM timer turns off the port if the short persists too long as shown in Figure 6. Second, when the port is turned off due to tLIM the PSE-ICM won't repower the PD for time (tED) which gives the MOSFET time to cool off. The tLIM timer also protects the MOSFET from cumulative heating caused by brief, repetitive shorts. The timer counts up quickly while current limiting, but counts down slowly when the short is removed, so the widths of the events accumulate in the timer, eventually causing the port to turn off.

4.1.5 CUTOFF CURRENT THRESHOLD. The maximum current a PD can draw without being turned off is just below ICUT. If IPORT exceeds ICUT for duration of tOVLD then the port turns off, as shown in Figure 6. The tOVLD timer accumulates (similarly to the tLIM timer described above) so if IPORT is just below ICUT the port may still turn off due to ripple current if the peaks exceed ICUT repetitively.

4.1.6 DISCONNECT SENSING The PSE-ICM uses the DC Maintain Power Signature (DCMPS) method for sensing when the PD has been disconnected. Figure 7 shows how it works. If the current drops below IMIN (nominally 7.5mA) for tMPDO then the PSE-ICM turns off power. However, if the current rises above IMIN for at least tMPS then the internal counter is cleared.

Figure 9 – Overload Timing




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Figure 10 – DCMPS Timing

4.2 INTERFACE OPTIONS

4.2.1 MAX_CLASS/STATUS PIN The MAX_CLASS/STATUS pin serves two functions: Max_Class input: Immediately after VMAIN_POS exceeds VUVLO or the RESET pin goes high (whichever comes last) the MAX_CLASS/STATUS pin temporarily becomes an input for sensing the max-class resistor (RMC).

STATUS output: After sensing RMC the MAX_CLASS/STATUS pin automatically becomes an output that indicates the on/off status of the port.

4.2.2 SETTING THE MAXIMUM PD CLASS The cost of the power supply is directly related to its output power rating. Therefore, one way to reduce costs is to use a power supply that is just big enough for the intended application. For example, suppose the PSE-ICM is to be used in an audio system to power a microphone PD; the microphone will never need more than 1W, so the power supply in the PSE can be quite small and inexpensive.

Figure 11 – Setting the Maximum PD Class

Max_Class /

Status

Vmain_neg




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But what if someone inadvertently connects a different kind of PD that needs more power, such as an IP phone? If the PSE turns on power to this PD, the power supply will be overburdened. Most power supplies simply fold back without any damage, but this scenario adds more work for the designer, since the design must be analysed and tested for these types of unintended cases. The PSE-ICM offers a convenient feature that eliminates this problem. By connecting a single resistor, as shown in Figure 11, the PSE-ICM is told which PD classes it should power. The recommended values of the resistor are given in Table 2. For example, if RMC=30.0k ±5% then the PSE-ICM will grant power to any PD of class 0-3, but deny power to a class 4 PD. In the microphone example given above, if RMC is set to 10.0k ±5% then only class 1 PDs will be powered and the power supply will never be overburdened if it is rated for at least 3.84W.

RMC Value PD Classes

Powered Max Power the PD May Draw

10.0 k ±5% 1 only 3.84W

20.0k ±5% 1 and 2 6.49W

30.0k ±5% 0 to 3 12.95W

Open 0 to 4 25.50W

Table 2 – Max Class Resistor Values

4.2.3 USING THE STATUS OUTPUT

In many PSE applications, the designer may want the host processor to know when the PD is receiving power. The circuit shown in Figure 12 accomplished this. MAX_CLASS/STATUS is high while the PSE-ICM is powering the PD, and low otherwise.




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Figure 12 – Using the Status Output

In many applications the host microprocessor must interface to other peripheral hardware, such as a management port, or a USB port. These interfaces must be earthed for safety, so the status signal must be isolated with an optocoupler. Note that the PSE-ICM requires a small FET to drive the LED inside the optocoupler. The LED can't be driven directly from the MAX_CLASS/STATUS pin because it's impedance would interfere with sensing the RMC resistor. (See section 4.2.2: Setting the Maximum PD Class.)

The circuit in Figure 12 can also be used to drive an LED that gives a visual indication when the port is on; simply omit the optocoupler and connect the indicator in its place, or connect the indicator LED in series with the optocoupler LED. This has been integrated into the PSE-ICM in some version. See Sales Drawing and for further details. The MAX_CLASS/STATUS pin pulses high briefly after VMAIN_POS is turned on, or RESET goes high; this is because the PSE-ICM is using the pin to sense the RMC resistor. The host processor can simply ignore this pulse, or interpret it as meaning that the PSE-ICM is up and ready to detect a PD.

4.2.4 THE RESET INPUT The RESET pin is used to force the PSE-ICM to turn off power to the PD. When RESET goes low, the PSE-ICM goes into a low-power quiescent state and does not attempt to detect the PD. Detection resumes immediately after RESET goes high again. Figure 13 shows how to use an optocoupler to interface to a host processor. RESET is pulled up to VMAIN_NEG+3.3V by an internal 4.99k resistor.




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Figure 13 – Using the RESET Input




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4.3 POWER SUPPLY SELECTION For a PSE to be fully compliant with IEEE 802.3at, it is critical that the power supply meets the following requirements: Output voltage: 54V to 56V is recommended. If the PSE is intended to power class 4 PDs then the supply voltage must be between 50V and 57V (per the IEEE requirement for a Type 2 PSE). However, if RMC resistor is used to restrict the PSE-ICM to PD classes 0-3 (a Type 1 PSE) then the supply voltage can be as low as 44V, allowing a standard 48V wall adapter to be used. Output Current: If the PSE is intended to power class 4 PDs then the power supply must be rated for at least 900mA. However, if the PSE is restricted to PD classes 0-3, then the supply can be rated for as little as 450mA. (Even if the PSE is restricted to operate only PD classes 1 or 2, the supply still needs at least 450mA to get through inrush without sagging.) See the sections Inrush and Setting the Maximum PD Class.

Isolation: The power supply must be isolated from input to output. The isolation rating must be at least 2250Vdc, or 1500Vrms @ 60Hz to meet the IEEE requirements. Ripple and noise: Switching noise generated by the power supply essentially comes out of the port as conducted emissions. Figure 14 shows typical limits. The IEEE specification applies to both normal-mode and common-mode noise. CISPR22 applies only to common-mode noise. If extra filter components are added be sure they meet the isolation requirement specified above.

Figure 14 – Conducted Emissions Specifications




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4.4 PCB LAYOUT GUIDELINES

4.4.1 PHY INTERFACE The data lines TD[0:3]+/- should be routed as controlled-impedance traces, preferably as differential pairs to reduce crosstalk. The traces should be designed for a differential-mode impedance of 100Ω. Internal routing layers are recommended to reduce EMI and avoid isolation issues. (See Section 4.4.2: Isolation.) The plane layers directly adjacent to the routing layers should be GND and/or the supply rail that connects to VCC. If some other supply rail is used for one of these planes, place a 0.1μF decoupling cap from that rail to GND near the PSE-ICM, and another cap near the PHY chip. Avoid routing signal traces over cuts or holes in the planes.

4.4.2 ISOLATION For compliance with IEEE 802.3at, the PCB must withstand at least 2250V DC for 60 seconds without breaking down. The test voltage is applied between the MDI pins (usually with all 8 pins tied together) and chassis. There are two groups of signals that must be isolated from each other:

o The PHY-side group: VCC, GND, TD[0:3]+/-, LED Pins and Shield. o The MDI-side group: MAX_CLASS/STATUS, RESET, DNC, VMAIN_POS,

and VMAIN_NEG and RJ-45 pins. Signals in the same group can be close together, but signals from the other group must be far enough apart to meet the isolation requirements. Figure 15 shows the minimum spaces between signals of different groups. The LED’s may be assigned to different groups. Normally the LED’s are driven by the PHY, so pins 13-16 are part of the PHY-side group. But if one of the LED’s is driven by the MAX_CLASS/STATUS pin (see Figure 9) then its two pins are part of the MDI-side group, extreme caution must be taken in this case. The DNC pin should be considered part of the MDI side group even though it should not be connected to anything; do not route signals from the PHY-side group near this pin.

Figure 15 – Recommended Minimum Spaces

The most effective way to isolate signals is vertically; routing each group on different layers. Vertical isolation is preferred because the required space is much smaller. Most PC boards




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are made from FR-4, which has a dielectric strength of at least 500V/mil. So the minimum dielectric thickness is (2250V)/(500V/mil) = 4.5 mils. However, during the lamination process the prepreg flows into the etched spaces between traces, the finished dielectric layer can be slightly pinched near the edges of traces. Therefore it is recommended to use at least 6 mils of prepreg between layers where signals from different groups can cross over each other. Figure 16 shows an example of a 6-layer board. The planes (VDD and GND) are assigned to layers 3 and 4 so that the stack-up is symmetrical (to avoid warping). The PSE-ICM is mounted on the top side, chassis ground is assigned to layer 1. The MDI side group is routed on the bottom layer.

Figure 16 – Example PCB Stack-up

In this example, the top and bottom prepreg layers separate signals from different groups, so these should be at least 6 mils thick. However, the middle prepreg and core layers can be thinner because they separate layers that are all in the same signal group (VDD is tied to VCC). If a surface layer must be used to route some of the signals, use the surface on the opposite side of the board from the PSE-ICM; in this way surface traces do not have to pass directly under the edge of the shield. Note: All dimensions given are guides and be taken literally, the user should exercise caution and best engineering practice to ensure that no isolation issues occur.




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4.4.3 HEAT DISSIPATION The worst case heat dissipation in the PSE-ICM is dominated by the load current. For example, if a class 4 PD draws 620mA (624mA is the minimum cut-off current for class 4) and the input-to-output resistance of the PSE-ICM is 1.2Ω, the power dissipation is 461mW. If VMAIN_POS = 57V and the PSE-ICM draws 3.5mA, that adds 200mW. Worst case power dissipation for the PSE-ICM is approximately 660mW. If both LED’s are driven with 10mA each, it adds approximately 40mW. Therefore the maximum total heat dissipation is approximately 701mW. Some of this heat is carried away by the CAT-5e cable, and some by air circulation inside the PSE enclosure. But most of the heat is conducted out via the pins on the bottom side of the PSE-ICM. Therefore, it is good practice to add as much copper as practical on these pins; excluding the data traces since it would affect the impedance, broad traces or sections of planes should be used for other signals, particularly VMAIN_POS, VMAIN_NEG, GND, VCC, and the shield pins.

4.4.4 SETUP FOR THERMAL TESTING To aid in product testing, below is the standardised test setup used to measure component temperature for the 85759 series connectors. This setup indicates locations for mounting thermocouples to ensure the product remains within the design temperature limits during operation. The test setup involves the placement of the 85759-0099 Evaluation Board into a modified plastic housing with no ventilation or active cooling. The thermocouples are mounted on key components within the product and on the external shield at the location identified in Figure 16. Test is conducted across the operating temperature range for the 85759 series PSE-ICM and the temperatures measured to ensure all components remain within their acceptable operating temperature range. DETAILS TO BE ADDED IN NEXT DOCUMENT REVISION




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PERFORMANCE

5.1 ELECTRICAL REQUIREMENTS

ITEM DESCRIPTION TEST CONDITION REQUIREMENT

1 Visual Inspection IEC 60512-1-1 Test 1a There shall be no defects that

would impair normal operation

2 Initial contact

resistance

(Low Level)

Mated connectors:

Max test voltage 20mV DC or AC peak,

test current100 mA DC or AC peak

Arrangement acc. IEC60603-7-5 / 7.2

IEC 60512-2-1 Test 2a

20 mΩ

MAXIMUM

[Initial]

3 Insulation

Resistance

Mate connectors with a voltage of

100 V DC ±15V DC between each

contact and screen to all others

IEC 60512-3-1 Test 3a Method A

500 MΩ

MINIMUM

4

HiPot

(Voltage Proof /

Isolation)

IEC 60950-1: 2001 Subclause 5.2.2.

2250V DC for 60 seconds. No breakdown




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5.2 MECHANICAL REQUIREMENTS


5 Insertion

and

withdrawal forces

Insert and withdraw a plug

Speed: 10 mm/s max

IEC60512-13-2-Test 13b

Maximum insertion and

withdrawal force:

30 N (shielded connector)

6 Effectiveness of

connector coupling

devices

Rate of load application 44,5 N/s max.

IEC60512-15.6-Test 15f 50 N for 60 s ± 5s.

7

Mechanical

operation /

Durability

(Half rated cycles)

Speed: 10 mm/s max.

Rest: 1 s min.

(when mated and when unmated)

Operations: 750

Locking device inoperative

IEC60512 Test 9a

Contact Resistance:

20 mΩ max.

(change from initial)

8 Vibration

f= 10 to 500 Hz

Ampl. = 0.35 mm

Accel. 50 m/s2

10 sweeps /axis

IEC60512 Test 6d

Contact disturbance:

Discontinuity 10 µs. maximum

No damage

Dielectric withstanding voltage:

no breakdown

Contact Resistance:

Max. change from initial

20 mΩ (shield: 100 mΩ)

9 Mechanical gauging IEC60603-7-5 Annex L Passing Go / No go test

10 Gauging continuity All signal contacts and screen specimens

IEC60603-7-5 Annex A

Contact disturbance:

10 µs maximum




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5.3 ENVIRONMENTAL REQUIREMENTS


11 Solderability

Solder time 3 ± 0.5 seconds

Solder bath method

Solder temperature:

260°C +0/-5°C

95 % of the immersed area

must show no voids

12 Rapid change of

temperature

-40°C to +70°C

25 cycles t=30 min

Recovery time 2h

IEC60068-2-14

Appearance:

No damage

Contact resistance:

20 mΩ

max. change from initial

Dielectric withstanding voltage:

no breakdown

Insulation resistance:

500 MΩ min.

13 Cyclic damp heat

Cycles: 21

Low temperature: 25° C

High temperature: 65° C

Cold subcycle: –10° C

Humidity: 93%

Mated and unmated

IEC60068-2-38

14 Flowing mixed gas

corrosion

4 days, mated state and unmated state

IEC60512 Test 11g

15 Electrical load and

temperature

500h @ 70°C

Current: with 0.5A and without current

Recovery period 2h

IEC60512 Test 9b

16 Damp heat steady

state

21 days

IEC60068-2-78




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5.4 TRANSMISSION CHARACTERISTICS

ITEM DESCRIPTION TEST CONDITION REQUIREMENT (ALL TYPES)

17 Insertion loss (dB) Mated Connectors ES-85740-001

1.0 MHz - 9.9 MHz: 0.4+0.1*log(F) 10.0 MHz - 49.9 MHz: 0.5+0.3*log(F/10) 50.0 MHz – 79.9 MHz: 1+1.4*log(F/80) 80.0 MHz – 100.0 MHz: 1.3+3*log(F/100)

18 Return loss (dB) Mated Connectors ES-85740-001

1.0 MHz to 9.9MHz: 27 10.0 MHz to 100.0 MHz: 27-17*log(F/10)

19 NEXT loss (dB) Mated connectors, pair to pair ES-85740-001

1.0 MHz to 5.9 MHz: 50 6.0 MHz to 49.9 MHz: 45-16*log(F/10) 50.0 MHz to 100.0 MHz: 25-30*log(F/100)

20 CMR (dB) Mated Connectors ES-85740-001

1.0 MHz to 9.9 MHz: 34 10.0 MHz to 79.9 MHz: 27 80.0 MHz to 199.9 MHz: 27-14.5*log(F/80) 200 MHz to 399.9 MHz: 21.5-39*log(F/200) 400.0 MHz to 1000.0 MHz: 10

21 OCL (µH min) PHY and Wire Side ES-85740-001

20mA bias current @ 100kHz, 100mV 350µH

F in MHz




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5.5 COMPLIANCE STANDARDS

ITEM DESCRIPTION TEST CONDITION REQUIREMENT (ALL TYPES)

22 Hi-Pot: Pulse IEC 60950-1: 2001 Subclause 6.2.2. 1.5kV 10/700µs

23 Surge Immunity IEC 61000-4-5 1kV

24 Electrostatic Discharge 1

IEC 61000-4-2: 2008 150pF, 330Ω, 10 discharges at 1 sec intervals.

ESD Test 1 Contact discharge to outer shield

Both polarities > 4kV

ESD Test 2 Contact discharge RJ45 contact with loaded 150m cable


ESD Test 3 Air discharge to mated RJ45 plug housing or contacts


ESD Test 4 Air discharge to open end of mated 0.5m cable


ESD Test 5 Contact discharge to front bezel while enclosed

> 27kV

25 Electrical Fast

Transient (EFT) 1 EN 61000-4-4

±700V / 15ms pulse package / 5kHz burst period / 300ms pulse package period / 60s at each voltage and polarity

26 Electrical Fast

Transient (EFT) 2 EN 61000-4-4

±1000V / 15ms pulse package / 5kHz burst period / 300ms pulse package period / 60s at each voltage and polarity

27 Conducted Emissions

EN 55022: 2006 + A1:2007 CISPR 22: 2005 (amended by A1:2005 and A2:2006)

28 Radiated Emissions CISPR 22: 2005 Class B

29 Basic PoE+ Function Detection, Classification, Power delivery

Connect Class 4 PD




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5.5 QUALIFICATION TEST SEQUENCE

ITEM DESCRIPTION GROUP

P GROUP

AP GROUP

BP GROUP

CP GROUP

DP GROUP

EP GROUP

FP GROUP

GP

1 Visual Inspection 1 7,12 8 4 4 6

2 Contact Resistance 2 5,9 3,5 2 5 3,5

3 Insulation Resistance 3 4 6 3 2 4

4 HiPot 4 6,14 7 3

5 Insertion Withdrawal 1,10

6 Effectiveness of Connector

Coupling 2,11

7 Durability (half rated cycles) 1,4

8 Vibration 1

9 Gauging 6

10 Gauging Continuity 7

11 Solderability 13

12 Rapid Change of Temperature 3

13 Cyclic Damp Heat 8 2

14 Flowing Mixed Gas Corrosion 2

15 Electrical Load and Temperature 1

16 Damp Heat Steady State 1

17 Insertion Loss 1

18 Return Loss 2

19 NEXT 3

20 CMR 4

21 OCL 5

22 HiPot: Pulse 2

23 Surge Immunity 3

24 ESD 4

25 EFT 1 5

26 EFT 2 6

27 Conducted Emissions 7

28 Radiated Emissions 8

29 Basic PoE+ Function Test 15 5 8 7 1,9

Group P to be completed on all samples before testing begins Where contact resistance measurements are not possible, Insertion Loss should be completed instead




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5.0 PACKAGING

Parts shall be packaged to protect against damage during handling, transit and storage. (Refer to sales drawings)

6.0 ESD PROTECTION The PSE-ICM contains ESD sensitive components. To avoid damage by an electrostatic discharge while handling the module, proper precautions and handling procedure are required. A protected work area must be provided whenever the PSE-ICM is handled. This protected area must be constructed, equipped and maintained with the necessary ESD protective materials and equipment to ensure that voltages are below the sensitivity level of the most ESD sensitive item handled in the work place. Reference: IEC61340-5-1 & 2: Technical Report Protection of electronic devices from electrostatic phenomena.

7.0 GAGES AND FIXTURES Arrangement for contact resistance test: Arrangement acc. IEC60603-7-5 / 7.2 Arrangement for vibration test: Arrangement acc. IEC60603-7-5 / 7.3

8.0 QUALITY ASSURANCE PROVISIONS The applicable Molex Inspection plan specifies the sampling acceptable quality level to be used. Dimensional and functional requirements shall be in accordance with applicable product drawings and this specification.

Documents

PRODUCT SPECIFICATION - Heilind Electronics · 2015-11-20 · product specification revision: ecr/ecn information: title: product specification for hyperjack™ 1000 magnetic poe