Production to - Analog Devices

DATE

EXTERNAL CLOCK INPUT MAXIMUM LEVEL UPDATE5/11/2021 7

PAGE

REVISION CHANGES

DESCRIPTION

M. BANCISORMAR-2020AS PER ECR-092850D

AS PER ECR-089480

NOV-2016

AUG-2019C M. BANCISOR

INITIAL RELEASE

AUG-2016

AUG-2016

AUG-2016

AUG-2016

AUG-2016

AS PER ECR-064863B

A AUG-2016 M. BANCISOR

M. BANCISOR

N/A

N/A

R. AMARILLE

N/A

M. BANCISOR

G. CELEDONIO

M. JOSE

N/A

N/A

TBD

02_043758

1:1 CodeID

Dno_template

Product(s): ad9363: NA

PACKAGE : N/A-lead N/A N/A-family

<User Define><User Define>

91

HW TYPE : Customer Evaluation Z

<User Define>

: Pitch-pitch StyleVendor Style

R. MACDONALD

REV

2REVISIONS

1

OWNED OR CONTROLLED BY ANALOG DEVICES.THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTSPURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. JP#USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER

8

CONNECTORFUNCTIONCODE DEVICE

2

2

6JUMPER TABLE

4

7

5

A

3

DATE APPROVED

D

B

DESCRIPTION

34

OFFON

5

57

OEM PART# HANDLER

6

C

B

8

SOCKET OEMBK/BD SPEC.P.O SPEC.

A

1

RELAY CONTROL CHART

3 14

C

NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, ORTHIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS

CHECKER

DESIGNER

PTD ENGINEER

TEST ENGINEER

DECIMALS

X.XXX +-0.005X.XX +-0.010

MASTER PROJECT TEMPLATE

TOLERANCES

+-1/32FRACTIONS

+-2SIZE

DDDD

SCHEMATIC

DRAWING NO.

SCALE CODE ID NO.SHEET OF

REV.

DA A

ENV C

L GSE

ODATE

ANGLES

UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES

TESTER TEMPLATE

TEMPLATE ENGINEER

HARDWARE SERVICES

HARDWARE SYSTEMS

COMPONENT ENGINEER

TEST PROCESS

HARDWARE RELEASE

* SEE ASSEMBLY INSTRUCTIONS

CONTROL

D

Released to

Production

BANK_501

INTERNAL LDO IS USED FOR 3V3

PLACE NEAR XC7Z010 (VCCO_MIO1)

ZYNQ BANK 501

STANDBY - 1 OR OPEN: OSCILLATION

USB PHYUSB TO UART

2 9

<DESIGN_VIEW>

: NAProduct(s): ad9363HW TYPE : Customer Evaluation Z

1:1

D02_043758

M. BANCISOR

10K

39

2.2UF DNI

10K

74LVC1G126GW39

0.1UF0.1UF

0.1UFFT230XQ-R

10K

0.1UF

10K

XC7Z010-1CLG225C4334

24MEGHZ

0.1UF

39

8.06K

4.7UF 0.1UF 0.01UF100UF

20K

USB3320C-EZK

1UF 1UF 1UF2.2UF

0.47UF

0.1UF

4.7K

47PF

47PF 10K 0.01UF

39

R107

C215

R79

R94

R95

R93C189

C188

U9

C186

R81

R80

U10

C164

R92

R74U4

R82Y1

C163

R77

U15

C159 C161 C162C158

R76

C140 C154 C168C165

C160

C190

C196

C187

C197

1V8

USB_UART_TXUART_TX

USB_OTG_CPEN

PS_MIO36_501_USB0_CLK

PS_MIO39_501_USB0_D7PS_MIO31_501_USB0_NXT

PS_MIO07_500_USB_RESET_BPS_MIO30_501_USB0_STP

USB_FS_SLEEP

1V8

PS-SRST#

PS_MIO07_500_USB_RESET_BPS_GPIO5PS_GPIO6

PS_MIO39_501_USB0_D7PS_MIO38_501_USB0_D6PS_MIO37_501_USB0_D5PS_MIO36_501_USB0_CLKPS_MIO35_501_USB0_D3

PS_MIO34_501_USB0_D2PS_MIO33_501_USB0_D1PS_MIO32_501_USB0_D0PS_MIO31_501_USB0_NXTPS_MIO30_501_USB0_STPPS_MIO29_501_USB0_DIRPS_MIO28_501_USB0_D4

1V8

PS_MIO29_501_USB0_DIR

USB_OTG_N

PS_MIO33_501_USB0_D1PS_MIO32_501_USB0_D0

1V8

1V8

1V8

VIN

VDD33_USB

1V8

1V8

1V8

VIN

USB_IDUSB_VBUS_OTG

USB_OTG_P

PS_MIO38_501_USB0_D6PS_MIO37_501_USB0_D5PS_MIO28_501_USB0_D4PS_MIO35_501_USB0_D3PS_MIO34_501_USB0_D2

PS_GPIO4

USB_UART_P

USB_UART_N

VIN_5V_USB_POWER

UART_RX12

5

2 4

12

4

1 10

PAD

113

14

3

2

B11

A14D15C11E15C12

D11A15

B13

B14C14A13

B15

E14

C10

D14

C13

B12D13

31

4

20

1615

8

29

28 30 32

26

918

2221

17

31

5423

6

24

1

719

12 PAD

25

213

27

10

1411

16

13

7

5

9

A12

15

6

3

8OE

GND

VCC

YA

GND

GND

GND

GNDGNDGNDGND

GND

GNDGND

GND

GND

PINSPARE

GND

PINSPARE

PINSPARE

GND

GND_FLAG

VDDI

O

DIR

VDD1

8

STP

VDD1

8

RESETB

REFCLK

XO

RBIAS

IDVBUSVBAT

VDD3

3

DMDP

CPEN

SPK_RSPK_L

REFSEL2

DATA7

N/C

REFSEL1

DATA6DATA5

REFSEL0

DATA4DATA3DATA2DATA1DATA0

NXT

CLKOUT

PINSPARE

GND

GND

GND

VDDSTANDBY

GNDOUTPUT

GND

VCCO

_MIO

1_50

1VC

CO_M

IO1_

501

VCCO

_MIO

1_50

1

PS_SRST_B_501

PS_MIO53_501PS_MIO52_501PS_MIO49_501PS_MIO48_501PS_MIO39_501PS_MIO38_501PS_MIO37_501PS_MIO36_501PS_MIO35_501

PS_MIO34_501PS_MIO33_501PS_MIO32_501PS_MIO31_501PS_MIO30_501PS_MIO29_501PS_MIO28_501

GNDGND

GND

RTS#TXD

CBUS3

GND

CBUS0CBUS1

VCC

RESET#

3V3OUT

USBDMCBUS2

USBDP

CTS#

GND

RXD

VCCIO GND

D

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

AC

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.

2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

Released to

Production

BANK_500

ZYNQ BANK 500

- DEBUG AS NORMAL.

VMODE[1]VMODE[0]

PLACE NEAR XC7Z010 (VCCO_MIO0)

- POWER UP PLUTO

1

0

MIO5

0

0

MIO4

CASCADED JTAG

QSPI FLASH

- INSERT THE JUMPER ON THE ADAPTER (JTAG BOOT)

- REMOVE THE JUMPER ON THE ADAPTER, SO YOU CAN TALK TO THE SPI FLASH

https://www.xilinx.com/support/answers/47596.html

MIO5 CAN BE SHORTED TO GND BY INSERTING A JUMPER ON THE JTAG ADAPTER

WHEN USING THE ADAPTER, AND WANTING TO HAVE JTAG BOOT (DEVICE DOESN'T BOOT U-BOOT, OR KERNEL):

QSPI

BOOT MODE

3 9

<DESIGN_VIEW>


1:1

D02_043758

M. BANCISOR

0.47UF10KDNI

XC7Z010-1CLG225C4334

20K

20K

20K

DNI

20K

0.1UF

33.333MEGHZ

0.01UF

PTS840 GKP SMTR LFS20K

0.1UF

10KDNI

00.1UF100UF 4.7UF

20K

0.1UF

20K

MT25QU256ABA8E12-1SIT240

20K

39

20K

C51R8 U4

U13

R119

R13

R83

Y2

R12

R84

R57

S1

R15

C47

C52

R9

C50

C46

C53

R120

C49

C48

R122

R14

R116 R121

UART_TXUART_RX

1V81V8

PG_1P3V

PS_GPIO3PS_MIO06_500_QSPI0_SCLKPS_MIO05_500_QSPI0_IO3PS_MIO04_500_QSPI0_IO2PS_MIO03_500_QSPI0_IO1PS_MIO02_500_QSPI0_IO0

USR_LEDUSR_BTN

PS_GPIO1PS_GPIO2

PS_MIO01_500_QSPI0_SS_BPS_GPIO0

1V8

1V8

1V8USR_BTN

1V8

1V8

1V8

1V8

PS_MIO02_500_QSPI0_IO0PS_MIO03_500_QSPI0_IO1

PS_MIO04_500_QSPI0_IO2PS_MIO05_500_QSPI0_IO3

1V8

PS-SRST#

PS_MIO06_500_QSPI0_SCLK

PS_MIO01_500_QSPI0_SS_B

1V8

A5

A2 A3

A4

A5 B1

B2

B3

B4

B5 C1

C2

C3

C4

C5 D1

D2D3

D4

D5 E1 E2 E3 E4 E5

D8

A6

C9C7

A8A7C8A9

A10 B5

D10

B6

B7

D6

D9

B10

D7

B9C6

3

4

2

1

143

25

GND

VDDSTANDBY

GNDOUTPUT

DNU

DNU

DNU

DNU

DNU

DNU

DQ3

DQ0DQ1

DNU

DNU

W#DQ2

DNU

S#

DNU

DNU

VCC

VSS

C

DNU

DNU

RESET#/DNU

DNU

DNU

GND

GND

GNDGND

GND

GND

GND

GND

GND

VCCO_MIO0_500VCCO_MIO0_500PS_POR_B_500

PS_MIO9_500PS_MIO8_500PS_MIO7_500

PS_MIO6_500PS_MIO5_500PS_MIO4_500PS_MIO3_500PS_MIO2_500

PS_MIO15_500PS_MIO14_500PS_MIO13_500PS_MIO12_500PS_MIO11_500PS_MIO10_500

PS_MIO1_500PS_MIO0_500

PS_CLK_500

GND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

Released to

Production

ON

VTTREFS3STATE

S0

VTT

ON

S5

DDR 3

HI

PLACE NEAR XC7Z010 (VCCO_DDR)

PLACE NEAR DDR3

HI

4 9

<DESIGN_VIEW>


1:1

D02_043758

M. BANCISOR

0.47UF0.47UF

0.47UF0.47UF 0.47UF0.47UF

0.22UF

120

10K10K

XC7Z010-1CLG225C4334

100UF

240

240

MT41K256M16TW-107 IT:P

0.01UF

10UF

10UF10UF

0

0

80.6

240 1K

4.7UF 4.7UF

4.7UF

4.7UF

0.01UF

0.01UF

0.01UF

0.01UF0.01UF

TPS51206DSQR

0.1UF

0.1UF 0.1UF 0.1UF 0.1UF 0.1UF0.1UF

100UF

120

120

120

120

120

120

120

120

120

120

120

120

120

120

120

120

120

120

120

120

120

120

120

C89C88

C59C56 C58C57

C81

R22

R222R221

U4

R41

U2C61

C79

C82C83

R43

R44

R142

R165

R40 R42

C86 C87

C55

C101

C102C63

C84

C62

C80U14

C96 C97C95C94C92C91

C60C54

C100

R21

R20

R27

R19

R18

R17

R16

R25

R23

R26

R24

R31

R32

R33R39

R34R28

R36

R35

R38

R37

R30

R29

DDR3_WE#

DDR3_RAS#DDR3_ODTDDR3_RST#

DDR3_DQS1_PDDR3_DQS0_PDDR3_DQS1_NDDR3_DQS0_N

DDR3_DQ9DDR3_DQ8DDR3_DQ7DDR3_DQ6DDR3_DQ5DDR3_DQ4DDR3_DQ3DDR3_DQ2

DDR3_DQ15DDR3_DQ14DDR3_DQ13DDR3_DQ12DDR3_DQ11DDR3_DQ10

DDR3_DQ1DDR3_DQ0

DDR3_DM1DDR3_DM0DDR3_CS#DDR3_CK_PDDR3_CK_NDDR3_CKEDDR3_CAS#DDR3_BA2DDR3_BA1DDR3_BA0

DDR3_A9DDR3_A8DDR3_A7DDR3_A6DDR3_A5DDR3_A4DDR3_A3DDR3_A2

DDR3_A14DDR3_A13DDR3_A12DDR3_A11DDR3_A10

DDR3_A1DDR3_A0

VTT_0P75

DDR3_CK_P

DDR3_A1

DDR3_A4

1V35

DDR3_DQS0_PDDR3_A6

DDR3_DM1

DDR3_DQS0_N

DDR3_WE#

DDR3_RAS#

DDR3_A8

DDR3_A14DDR3_A13

DDR3_RST#

DDR3_A11

DDR3_A9

DDR3_A7

DDR3_A2

DDR3_A5

DDR3_BA1

DDR3_A12

DDR3_A0

DDR3_A3

DDR3_BA2

DDR3_BA0

DDR3_A10

DDR3_CS#

DDR3_CKE

DDR3_CK_N

DDR3_CAS#

DDR3_ODT

DDR3_CK_P

DDR3_DQ5

DDR3_DQ7

DDR3_DQ4

DDR3_DQ6

DDR3_DQ3

DDR3_DQ1DDR3_DQ2

DDR3_DM0

DDR3_DQ0

DDR3_DQ8

DDR3_DQ10

DDR3_DQS1_P

DDR3_DQ9

DDR3_DQ11

DDR3_DQ14

DDR3_DQS1_N

DDR3_DQ12

DDR3_DQ15

DDR3_DQ13

VTT_0P75

VIN

1V35

1V8

VIN

DDR3_A5

DDR3_A6

DDR3_CK_N

DDR3_CS#

DDR3_ODT

DDR3_CKE

DDR3_CAS#

DDR3_RAS#

DDR3_WE#

DDR3_BA2

DDR3_BA1

DDR3_BA0

DDR3_A13

DDR3_A12

DDR3_A11

DDR3_A10

DDR3_A9

DDR3_A8

DDR3_A7

DDR3_A3

DDR3_A2

DDR3_A1

DDR3_A0

1V35

VTTVREF

VTT_0P75

1V35

1V35

1V35

VTTVREF

VTT_0P75DDR3_A14

DDR3_A4

A1

A2

A3

A7

A8

A9B1

B2

B3

B7

B8

B9C1

C2

C3

C7

C8

C9D1

D2

D3

D7

D8

D9

E1E2

E3

E7

E8

E9 F1

F2

F3

F7

F8

F9 G1

G2

G3

G7

G8

G9

H1H2

H3

H7

H8

H9

J1 J2

J3

J7

J8J9

K1

K2

K3

K7

K8

K9

L1

L2

L3

L7

L8

L9 M1

M2

M3

M7

M8

M9

N1

N2

N3

N7

N8

N9

P1

P2

P3P7

P8

P9

R1

R2

R3

R7

R8

R9

T1

T2

T3T7

T8

T9

E2

R5

L4K3

D3

A3

B1R2N3N2L3

C1

M1

E1

E4 F1 J2 M3

K1

L2

N1

P6

R4B3

R3H3J3R6

G2C2F2B2H2H1G1F3E3

D1

C3A4B4

C4A2D4

N6

M6

K2M2

J1N4

M5P5P4P3M4

R1

P1

6

8PA

D

9

4

35

7

210

1

VSS

A8

A14A13

RESET#

VSS

VDD

A6

A11

A9

A7

VDD

VSS

A4

A1A2

A5

VSS

VDD

BA1

A12/BC#

A0

A3

VDD

VSS

VREF

CA

NC

BA2

BA0

VSS

NC

ZQ

A10/AP

WE#

CS#

NC

CKE

VDD

CK#

CAS#

VDDODT

NC VSS

CK

RAS#

VSS

NC

VDDQ

DQ5

DQ7

DQ4

VDDQ

VREF

DQ

VSSQ

VSS

VDD

LDQS#

DQ6

VSSQ

VSSQ

DQ3

DQ1

LDQS

DQ2

VDDQ

VDDQ

VSSQ

LDM

DQ0

VSSQ

VSS

VDD

VSSQ

DQ8

UDM

VDDQ

VSSQ

VDDQ

DQ10

UDQS

DQ9

DQ11

VDDQ

VSSQ

DQ14

UDQS#

VSS

VDD

VSSQ

VSS

VDDQ

DQ12

DQ15

DQ13

VDDQ

GND

GND

GND

GND

GND

GND

GND

GND

PIN

SP

AR

E

PIN

SP

AR

E

PIN

SP

AR

E

PIN

SP

AR

E

PIN

SP

AR

E

GND

GNDGND

GND

GND

GND

PAD

VDD

S5

GND

S3 VTTREF

VTTSNS

PGND

VTT

VLDO

IN

VDDQSNS

GND

GND

GND

VCCO

_DDR

_502

VCCO

_DDR

_502

VCCO

_DDR

_502

VCCO

_DDR

_502

VCCO

_DDR

_502

VCCO

_DDR

_502

PS_DDR_WE_B_502PS_DDR_VRP_502PS_DDR_VRN_502

PS_DDR_RAS_B_502PS_DDR_ODT_502

PS_DDR_DRST_B_502PS_DDR_DQS_P1_502PS_DDR_DQS_P0_502PS_DDR_DQS_N1_502PS_DDR_DQS_N0_502

PS_DDR_DQ9_502PS_DDR_DQ8_502PS_DDR_DQ7_502PS_DDR_DQ6_502PS_DDR_DQ5_502PS_DDR_DQ4_502PS_DDR_DQ3_502PS_DDR_DQ2_502

PS_DDR_DQ15_502PS_DDR_DQ14_502PS_DDR_DQ13_502PS_DDR_DQ12_502PS_DDR_DQ11_502PS_DDR_DQ10_502

PS_DDR_DQ1_502PS_DDR_DQ0_502

PS_DDR_DM1_502PS_DDR_DM0_502

PS_DDR_CS_B_502PS_DDR_CKP_502PS_DDR_CKN_502PS_DDR_CKE_502

PS_DDR_CAS_B_502PS_DDR_BA2_502PS_DDR_BA1_502PS_DDR_BA0_502

PS_DDR_A9_502PS_DDR_A8_502PS_DDR_A7_502PS_DDR_A6_502PS_DDR_A5_502PS_DDR_A4_502PS_DDR_A3_502PS_DDR_A2_502

PS_DDR_A14_502PS_DDR_A13_502PS_DDR_A12_502PS_DDR_A11_502PS_DDR_A10_502

PS_DDR_A1_502PS_DDR_A0_502

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

Released to

Production

USER LED

PLACE NEAR XC7Z010 (VCC_INT)

ZYNQ

PLACE NEAR XC7Z010 (VCC_PAUX)PLACE NEAR XC7Z010 (VCC_PINT)

PLACE NEAR XC7Z010 (VCC_AUX)

VCCINT

VCCINT

GND/VCC

SHORT TO GND FOR JTAG BOOT

PLACE NEAR XC7Z010 (VCC_PLL)

PLACE NEAR XC7Z010 (VCCO_0)

HARDWARE REVISION DETECTION

ZYNQ BANK 00.05 PITCH JTAG AND UART CONNECTOR

REV C - 0.805V

REV A - X.XXVREV B - 0.9V

5 9

<DESIGN_VIEW>


1:1

D02_043758

M. BANCISOR

4.7UF4.7UF

4.7UF4.7UF

4.7UF

47UF

47UF

0.01UF

100UF100UF

100UF

470

L0805100OHM

LTST-S220TBKT

470

4.7K

0.1UF

0

100OHML0805

4.7K

4.7K

100OHML0805

4.7K

20K

47UF

XC7Z010-1CLG225C4334

XC7Z010-1CLG225C4334

10K

LTST-S220TBKT

DNI

FTSH-105-01-L-D

0.47UF

0.47UF 0.47UF

0.47UF0.47UF 0.47UF

0.47UF

0.47UF

0.47UF

BSS138LT1G

BSS138LT1G

DS2

R87

C71

C78C66

C73C67

C174 C85

C65

C99

P1 P1

C64 C76

E1

DS1

R48

R47

C98

R45

E5

R46

R11

E6R91

C77

U4

U4

R75

R66

C68

C74 C75

C90C70 C72

C69

C178

C93

Q1

Q4

VIN

JTAG_TCKJTAG_TDOPS_MIO05_500_QSPI0_IO3

1V8

1V8

VTTVREF

VCCPINT1V8

VCCPINT 1V8

VCCPINT

VCCPLL

VCCPLL

VCCPINT

1V8JTAG_TMS

JTAG_TDI

USR_LED

VIN

1V8

1V8

JTAG_TDO

1V8

1V8

1V8

1V8

1V8

JTAG_TCKJTAG_TDI

1V8

JTAG_TMS

UART_RXUART_TX

7

35

9

1468

2

10

C

A

A

C

A1 A11

C15 E7

F5K5H5G6

L6J6L10

J10

G10

F9E10

K9J8H9F4

R9P12P2N15N5M8

L11L5L1K14

K10K7K4J9J5

H10H6G

13G5

G3

F10E9E5D12D2C5B8

H8

G8

D5

G4

G9L7

L8

G7

H7

M7

F8

J7

H4J4E8

L9

K8

F6

K6

F7 E6

3

1

2

VREFP_0VREFN_0VP_0VN_0

VCCO

_0VC

CBAT

T_0

VCCA

DC_0

TMS_0

TDO_0

TDI_0TCK_0

RSVD

VCC3

RSVD

VCC2

RSVD

VCC1

RSVD

GND

PROGRAM_B_0INIT_B_0

GND

ADC_

0

DXP_0DONE_0CFGBVS_0

GND

GND

GND

GNDGNDGND

GND

GND GND

GND

GND

GND

VCCP

LLVC

CPIN

TVC

CPIN

TVC

CPIN

TVC

CPAU

XVC

CPAU

XVC

CINT

VCCI

NTVC

CINT

VCCI

NTVC

CINT

VCCA

UXVC

CAUX

VCCA

UXPS

_DDR

_VRE

F0_5

02

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GNDGND

GND

GNDGND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

Released to

Production

ZYNQ BANK 34,35



BANK_35

BANK_34

6 9

<DESIGN_VIEW>


1:1

D02_043758

M. BANCISOR

XC7Z010-1CLG225C4334

2.2K 2.2K

XC7Z010-1CLG225C4334

4.7UF 4.7UF

4.7UF 4.7UF47UF

47UF 0.01UF

0.01UF

0.1UF

0.1UF

0.47UF 0.47UF 0.47UF

0.47UF 0.47UF 0.47UF

0.47UF

0.47UF

R68 R97

C110

C105 C107

C106 C108

C103

C104 C120

C119C117

C118

U4

C111 C113 C115

C112 C114

C109

C116

U4

IO_L06_34_RX_D10

IO_L21_34_CTRL_OUT4IO_L22_34_CTRL_OUT7

IO_L18_34_TX_D6

PL_GPIO4

PL_GPIO1

CTRL_IN2IO_L24_35_SPI_DI

PL_GPIO3

1V8

IO_L09_34_TX_FRAMEIO_L10_34_EN_AGC

PL_GPIO0

IO_L08_34_CTRL_OUT1IO_L07_34_RX_FRAME

IO_L24_35_SPI_DOIO_L23_35_SPI_ENBIO_L23_35_SPI_CLK

CTRL_IN3

IO_L08_34_CTRL_OUT0

IO_L20_34_TX_D10

PL_GPIO2

IO_L16_34_TX_D2

IO_L06_34_RX_D11

IO_L04_34_RX_D7

1V8

1V8

1V8

CTRL_IN1CTRL_IN0

IO_L05_34_RX_D8

IO_L01_34_RX_D0IO_L03_34_RX_D4IO_L02_34_RX_D3

IO_L01_34_FB_CLK

IO_02_34_AD9361_CLKOUTIO_02_34_AD9361_RSTIO_L22_34_CTRL_OUT6

IO_L21_34_CTRL_OUT5IO_L20_34_TX_D11

IO_L04_34_RX_D6

IO_L19_34_TX_D9

IO_L15_34_TX_D0

IO_L13_34_CTRL_OUT2IO_L13_34_CTRL_OUT3IO_L12_MRCC_34_DATA_CLK

IO_L11_34_TXNRXIO_L11_34_ENABLE

IO_L03_34_RX_D5

1V8

IO_L05_34_RX_D9IO_L02_34_RX_D2

IO_L19_34_TX_D8IO_L18_34_TX_D7

IO_L17_34_TX_D5IO_L15_34_TX_D1IO_L16_34_TX_D3IO_L17_34_TX_D4

IO_L01_34_RX_D1

H11

M11

R12

L12N12

N14

N11

L13

K12

E13

M15N13

J11J13J14J15

P9P8R10

K11

F13

F11

F14E11

H15G15

F12E12

F15

K13

N9

L14

P13P14

M14L15

M9

M12

R13

H12

R8

G11H13G12H14G14

R11P11

R7

M10N8

P10

M13

N10

P7 R14

N7

J12

K15

P15R15

VCCO

_34

VCCO

_34

VCCO

_34

VCCO

_34

VCCO

_34

IO_L9P_T1_DQS_34IO_L9N_T1_DQS_34IO_L8P_T1_34IO_L8N_T1_34IO_L7P_T1_34IO_L7N_T1_34IO_L6P_T0_34IO_L6N_T0_VREF_34IO_L5P_T0_34IO_L5N_T0_34IO_L4P_T0_34IO_L4N_T0_34IO_L3P_T0_DQS_PUDC_B_34IO_L3N_T0_DQS_34IO_L2P_T0_34IO_L2N_T0_34

IO_L24P_T3_34IO_L24N_T3_34IO_L23P_T3_34IO_L23N_T3_34IO_L22P_T3_34IO_L22N_T3_34

IO_L21P_T3_DQS_34IO_L21N_T3_DQS_34

IO_L20P_T3_34IO_L20N_T3_34

IO_L1P_T0_34IO_L1N_T0_34

IO_L19P_T3_34IO_L19N_T3_VREF_34

IO_L18P_T2_34IO_L18N_T2_34IO_L17P_T2_34IO_L17N_T2_34IO_L16P_T2_34IO_L16N_T2_34

IO_L15P_T2_DQS_34IO_L15N_T2_DQS_34

IO_L13P_T2_MRCC_34IO_L13N_T2_MRCC_34IO_L12P_T1_MRCC_34IO_L12N_T1_MRCC_34

IO_L11P_T1_SRCC_34IO_L11N_T1_SRCC_34IO_L10P_T1_34IO_L10N_T1_34

GND

GND

VCCO_35VCCO_35IO_L5P_T0_AD9P_35IO_L5N_T0_AD9N_35

IO_L3P_T0_DQS_AD1P_35IO_L3N_T0_DQS_AD1N_35IO_L2P_T0_AD8P_35

IO_L2N_T0_AD8N_35IO_L1P_T0_AD0P_35IO_L1N_T0_AD0N_35

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

Released to

Production

MAX +10 DBM

HIGH

TX SMA CONNECTOR

RX SMA CONNECTOR

IF YOU REPLACE Y3 WITH A VC/TCXOPOPULATE R? TO BE ABLE TO TUNE

14.3K 1%

AD9363

D4, D9, D3 AND D10 SHOULD BE PLACED AS CLOSE AS POSSIBLE TO THE CONNECTOR.

NOTE: WHEN BOTH RF CHANNELS ARE USED THE MAXIMUM DATA RATE IS 30.72 MSPS.

EXT CLOCK INPUT

EXT CLOCK OUTPUT

RX U.FL CONNECTOR

TO USE RX2A:

- REMOVE R104 AND R69- POPULATE T2 AND RX2A

TX U.FL CONNECTOR

NO STUBS ARE ALLOWED.

TO USE TX2A POPULATE T3 AND TX2A

MAKE THE CLOCK INPUT PATH 50 OHM

MAKE THIS PATH 50 OHM

PS_GPIO6

LOW INTERNAL

CLOCK SOURCE

THE FREQUENCY USING AUXDAC1 OF AD9363

EXTERNAL

7 9

<DESIGN_VIEW>


1:1

D02_043758

M. BANCISOR

1K

10UF

39

BSS138LT1G

BSS138LT1G

240

LTC6957HMS-3#PBF0.01UF

ESD8472MUT5G

0.01UF

49.9

U.FL-R-SMT-1(01)

0.01UF

240

75

0

ESD8472MUT5G

TCM1-63AX+

DNI

DNI

ESD8472MUT5G

DNI

1UF

JCCEM001

TCM1-63AX+

18PF

0.001UF

0.001UF

1

10UF

18PF

0.001UF

1UF

18PF

100

0.001UF

0.1UF

330NH 330NH

18PF

47PF

1

0.001UF

14.3K

0.001UF

0.001UF

330NH

U.FL-R-SMT-1(01)

10UF

18PF

18PF

TCM1-63AX+

JCCEM001

ESD8472MUT5G

18PF

40MEGHZ

18PF

AD9363ABCZ

DNI

18PF

330NH

1K

ESD8472MUT5G

ESD8472MUT5G

TCM1-63AX+

0

18PF

0

0.1UF 0.1UF

2.2K

4.7K

2.2K

R67

C204

R102

U17

C179

R96

CLK_IN

C180

R98

R86

R103

R104

R10

R5

Q3

C207

C208

D7

D8

D3

T5

C129

RX2A

C194

R51

C134

L9

TX1A

RX1A

T2

L8

U5

C126

C121

L7

C122

C193

C125

R49

L1

R100

C205

C124

T1

D4

C133

C131

C132

C155

C175

R52

C128

C156

D10

CLK_OUT

C157

R99R85

Y3

Q2

D9

C130

C127

C167C166

TX2A

C206

R69

C176

T3

R101

CLK_SOURCE_SEL

3P3V_CLK

RX2A_N

IO_L03_34_RX_D4


PS_GPIO6

AD9363_AUXADC

1P3_TX1A

VDD_INTERFACE

VDDD_DIG

VDDA_TX_LO

AD9363_GPO_0

IO_L18_34_TX_D6IO_L17_34_TX_D5

IO_L05_34_RX_D8

VDDA_BB

VDDA_RX_LO

VDDA_TX_LO

VDDA1P1_RX_VCO

TX1A_N

TX1A_P

RX1A_N

RX1A_P

IO_L20_34_TX_D10

IO_L15_34_TX_D0

IO_L16_34_TX_D2

IO_L20_34_TX_D11

IO_L15_34_TX_D1

IO_L16_34_TX_D3

IO_L19_34_TX_D9

CTRL_IN0

TX2A_PTX2A_N

RX2A_PRX2A_N

1P3_TX2A

TX_VCO_1P1V_SUPPLY

VDDA_RX_SYNTH

VDDA_RX_TX

VDDA_RX_LO

VDD_GPO

RX1A_P

IO_L05_34_RX_D9

IO_L03_34_RX_D5

IO_L02_34_RX_D3

IO_L19_34_TX_D8

CTRL_IN1

IO_L17_34_TX_D4

VDDA_TX_SYNTH

TX_VCO_1P1V_SUPPLY

1P3_TX1A

IO_L24_35_SPI_DO

IO_L07_34_RX_FRAME

IO_L09_34_TX_FRAME1P8V_CLK

IO_L12_MRCC_34_DATA_CLK

IO_L13_34_CTRL_OUT2

IO_L11_34_TXNRX

AD9363_GPO_1

IO_L06_34_RX_D10IO_L06_34_RX_D11


CTRL_IN3CTRL_IN2

IO_02_34_AD9361_RSTIO_L23_35_SPI_CLKIO_L24_35_SPI_DIIO_L23_35_SPI_ENB

AD9363_AUXDAC1

IO_L01_34_RX_D0

IO_L01_34_FB_CLK

IO_L10_34_EN_AGCIO_L11_34_ENABLE

AD9363_GPO_3AD9363_GPO_2

TX2A_N

1P3_TX2A


AD9363_AUXDAC1

IO_L22_34_CTRL_OUT7

TX1A_N

IO_L18_34_TX_D7

RX1A_N

TX1A_P

TX2A_P

IO_L22_34_CTRL_OUT6

CLK_SOURCE_SEL

IO_02_34_AD9361_CLKOUT


IO_L21_34_CTRL_OUT5

RX2A_P

AD9363_AUXDAC2

VDDA1P1_RX_VCO

1P8V_CLK

G1

C12

104

5

2

9

1

11

36 12

8

7

5

1

K5

J12L4

F7

D5

E4

L11

M10

H10H2

G4

D12

M4

D7

B6

E7

J4

K7

E12

A9A10

E10

J8

F8

J11

M3

K12

G8

A8

K11

M8

E2

M2

K1L1

E1F1

A2A1

M9

C1

A5

G3

D10

K8

D11E11

J6L6

B3

J1

H8

H7M6L8K2

F12

K4 B10

K3E3B9 F2D3 J3D2 H12

B8

M5

M7

G2

H1

M1

J7

J9

A3

B5

G5

F5

D6C6

J5

F9

C5

A7

K6

C3

J10

H9

G6L5

K9

B7

K10

F4

J2F3C10 L2

A11

H5

D1

H11

G7

B11

H3

F10

F6

A4 C11

G12F1

1C9C8

3

3

5 1

6

1

3

L9H6 L7L3B2B1A12A6

4

2

M12

C4

C7C2B12

G11

E6

L10

L12

E8D8E9D9

D4

E5G9

H4

B4

G10

4

4

2

M11

2

6

GND

GND

XTALN

NC

TX1B_NTX1B_P

TX1A_NTX1A_P

VSSA

TX_MON1

VSSA

NC

RX1A_NRX1A_P

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA SPI_DO

AUXADC

RBIAS

VSSA

VSSA

RX1C_N

VSSD

P1_D0/RX_D0_N

P1_D2/RX_D1_N

P1_D4/RX_D2_N

P1_D6/RX_D3_N

P1_D8/RX_D4_N

SPI_ENB

RESETBVD

DAP3

_BB

VDDA

1P3_

TX_S

YNTH

VSSA

RX1C_P

P1_D1/RX_D0_P

P1_D3/RX_D1_P

P1_D5/RX_D2_P

P1_D7/RX_D3_P

P1_D9/RX_D4_PP1_D10/RX_D5_N

CLK_OUT

SPI_CLKSPI_DI

VDDA

1P3_

RX_S

YNTH

VSSA

RX1B_N

VDD_

INTE

RFAC

E

DATA_CLK_NVS

SD

TX_FRAME_N

P1_D11/RX_D5_P

VSSD

VSSA

VSSA

TXNRX

VSSA

VSSA

RX1B_P

VSSD

DATA_CLK_P

FB_CLK_N

TX_FRAME_P

RX_FRAME_PRX_FRAME_N

ENABLEEN_AGC

CTRL_OUT7

VDDA

1P1_

RX_V

CO

RX_VCO_LDO_OUT

VSSA

VDDS

1P3_

DIG

VSSD

FB_CLK_P

VSSD

P0_D10/TX_D5_N

VSSD

CTRL_OUT4CTRL_OUT5CTRL_OUT6

VSSA

VDDA

1P3_

RX_V

C_LD

O

RX2B_N

P0_D0/TX_D0_N

P0_D2/TX_D1_N

P0_D4/TX_D2_N

P0_D6/TX_D3_N

P0_D8/TX_D4_N

P0_D11/TX_D5_P

CTRL_OUT3CTRL_OUT2CTRL_OUT1

VDDA

1P3_

TX_L

O_B

UFFE

R

VDDA

1P3_

RX_L

O

RX2B_P

VSSD

P0_D1/RX_D0_P

P0_D3/TX_D1_P

P0_D5/TX_D2_P

P0_D7/TX_D3_P

P0_D9/TX_D4_P

CTRL_IN2CTRL_IN3

CTRL_OUT0VD

DA1P

3_RX

_TX

VDDA

1P3_

RX_R

F

RX2C_N

VSSA

VSSA

VSSA

VSSA

VSSA

VSSA

CTRL_IN1CTRL_IN0

TEST/ENABLE

AUXDAC2

VSSA

RX2C_P

VSSA

TX_VCO_LDO_OUT

VDDA

1P3_

TX_V

CO_L

DO

VDDA

1P3_

TX_L

O

VDD_

GPO

GPO_0GPO_1GPO_2GPO_3

AUXDAC1

VSSA

VSSA

VSSA

VDDA

1P1_

TX_V

CO

TX2B_PTX2B_N

TX2A_PTX2A_N

VSSA

TX_MON2VS

SA

NC

RX2A_PRX2A_N

GNDGND

GND

GND

GND

GND

GND

GND

NC

GND

GND

GND

NC

GND

NC

GND

GND

GND

GND

GND

GNDGNDGND

GND

NC

GND

E/DGND

VDDOUT

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

SD1

VDD

OUT1OUT2

GNDOUTSD2

FILTB

GND

IN-IN+

V+

FILTA

GND GND

GND

GND

GNDD





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

Released to

Production

USB CONNECTORS

POWER + DATA USB

CURRENT LIMIT DATA = 1A

USING POWER USB IF AVAILABLE

1V8 RAIL POWERS THE AD9363DUAL INDUCTORS USED BECAUSE THE

2A @ 1.8V

D2 ENABLED BELOW 3.53

PL:

POWER SEQUENCE:

SELECTOR

PS:

RF (1V3)AD9363:

--------->2ND

VCCO_DDR

1V3-------->

VCCPINT

---

---

1V81ST 1V0

10MS DELAY

SECOND START 1.8V PS

VCCO_MIO0, VCC_MIO1VCCPAUX, VCC_PLL

USB

VCCINT

---VDD_INTERFACE (1V8)

VCC0_34, VCCO_35

3RD---------> 1V35SLEW LIMIT

VCCAUX, VCCO_0

THIRD START 1.35V PS

2A @ 1.35V

1.2 MHZ

CURRENT MONITOR

POWER SELECTORINRUSH AND OVERCURRENT PROTECTION

EXT POWER & USB FS

SECONDARY

PRIMARY

D1 DISABLED BELOW 3.25

---->

90 OHMS FIFFERENTIAL

DLW21HN900SQ2L

CURRENT LIMIT POWER = 1A

8 9

<DESIGN_VIEW>


1:1

D02_043758

M. BANCISOR

47UF

2.2UF

0.1UF

2.2UF

ADP198ACBZ-11

0.1UF

0.5A 470

DNI

47590-00012.2UF

8.06K

LTC4415EDHC#PBF

DNI

270NH

100K

10UF

5.6NF

47590-0001

SP3004-04XTG

1KDNI

10UF

0.0033UF

10UF

22UF

1.5UH

10K

47UF

180PF

100UFADP2114ACPZ

10

17.8K

14.3K

0.047UF

0.1UF

47UF

4.7K

1UF

4.7K

23.2K

27.4K

10UF10UF

DNI

10UF

1.5UH

100UF

10UF

10K

46.4K

4.7K

100K

150PF

10UF470

27.4K

100

2.2UF

DNI

1K

0.1UF

SP3004-04XTG

90OHMS AT 100MEGHZ 0.1UF

600OHM AT 100MEGHZDNI

600OHM AT 100MEGHZ

DNI

0.1UF0.1UF

800OHMS AT 100MEGHZ

600OHM AT 100MEGHZ

0.1UF

600OHM AT 100MEGHZ

24.9K

47UF

E3

C211C172C171

P2

C182

C184D1

C183

U16

L6

R55C1

77

C210

L3

R60

C181

R56

R89 C149

C145

R61

C148 R62

C153

R63

C139

C7

R54

C152

L2

R90

C143

R65

C136

R64

C144

C151

U6

C138

C137C135

C150

C147

R50

C146

C141

R59

R53

C142

L5

R78

R73

R70

R71

R72

P3

F1

R58

D2

C214C213C212

E9

L10

E11

E10

R88

C209C185

U8

VIN_5V_USB_DATAUSB_VBUS_OTG

USB_ID

VIN_5V_USB_POWER

USB_OTG_CPEN

EN_DAT_USB

VIN_5V_USB_POWER

VIN_5V_USB_DATA

VIN_5V_USB_POWER

EN_DAT_USB

EN_POW_USB

USB_OTG_P

FB_1P8V

VINFB_1P8V

COMP_1P8V

FB_1P35V

FB_1P35VPG_1P8V

ADP2114_VIN

1V35

COMP_1P35V

PWR_CLK

VIN

VIN

COMP_1P35V

VIN

VIN

COMP_1P8V

ADP2114_VIN

PG_1P35V

1V8

ADP2114_VIN

PG_1P8V

VIN

EN_POW_USB

USB_OTG_N

1V8

USB_UART_N

VIN_5V_USB_POWER

USB_UART_P

45

3

32

1

131

B2

B1

SH3SH2SH1

54

23

SH2

2

2

21

2726

PAD22

1

1814

201

12

1

17

13

34

8

2

6

5

24

7

31

23

30

911

21 19

15

25

10

16

2832

29

1 15

910

2

786

PAD

3

4

5

16

14

1211

SH3

1

SH1

A2A1

14

2

4

23

GND

GND

PGND

VCC

I/O1

I/O4

I/O3

I/O2

GNDVCC

I/O1

I/O4

I/O3

I/O2

GND

GND

GND

GND

PGND

GNDGND

GNDGNDGNDGNDGND

GNDGNDGNDGND

GNDGNDGND

GNDGND

PAD

OUT2OUT2

STAT2_NWARN2_N

WARN1_NSTAT1_N

OUT1OUT1

IN2IN2

EN2_N

CLIM2

CLIM1

EN1IN1IN1

ENGND

VOUTVIN

GND

GND

GNDGND

GND

GNDGND

GNDGND

GNDGND

GND

VIN6VIN5VIN4

VIN3VIN2VIN1

VDD

PAD

PGND

4PG

ND3

PGND

2PG

ND1

GND

SS2FB2 V2SET

SW4SW3

COMP2

PGOOD2

SW2SW1

COMP1

PGOOD1

EN2

SS1FB1 V1SETEN1

OPCFG

SYNC_CLKOUTFREQSCFG

GND

GND

GND

GNDGND

GND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

Released to

Production

FIRST START 1V PS

BALL B9 & B10

BALL F12

TEST PADS5V

BALL K3

JTAG & UART

RESET ZYNQ

POWER

BALL E2 & F2

POWER MANAGEMENT SECTION

3A @ 1V

M9, M10

A9, A10

BALLS E3, D3,

BALL J3

BALL K4

9 9

<DESIGN_VIEW>


1:1

D02_043758

M. BANCISOR

N/A2.2UF

46.4K

N/A

0.01UF

7001953N/AN/A

1K

N/A

ADM7160ACPZN1.8

1UF1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF1UF

1UF1UF

1UF

ADM7160ACPZN3.3

100OHML0805

0.01UF

10K

1UH

N/AN/A

0.1UF

10UFL0805100OHM

7002112

10UF

7001953

0.01UF

10UF

7002112N/A

N/A

N/AN/AN/A7001953

0.01UF

0.01UF

N/A

N/A

N/A10UF

N/A

7001953

N/AN/A

N/A

N/AN/A

N/A

N/AN/A

17.8K

A-00

7002112

N/AN/A7001953

7001953

47UF

0.1UF

0.1UF

0.01UF

N/A

A-00N/A

N/AN/A

7001953

N/A

10UF

10UF

N/AN/AN/A

N/A

N/A

N/AN/A

N/A

N/A

N/A

N/A

N/A

A-00

A-00

A-00

N/A

N/A

7001953

0.01UF

7001953

0.01UF

7001953

7002112

N/A

N/A

N/AN/AN/A

N/A N/A

N/AN/AN/A

N/A

N/A

27.4K

0.1UF

0.1UF

N/AN/A

7001953

0.1UF10

ADP2164ACPZ

0.1UF 0.1UF

N/A

0.01UF

ADP1754ACPZ-1.3

ADP1754ACPZ-1.3

47UF

10UF

47UF

100OHM

A-007002112

10UF

N/A7002112

N/A

0.01UF

N/A

0.1UF

0.01UF

47UF47UF

L0805

N/A7001953

N/A

N/A

N/A7002112A-00N/A

N/A

0.01UF

N/A7002112A-00N/AN/A

0.1UF

N/A

0.1UF

0.01UF

7001953

L0805

N/AA-007002112N/A

10UF

100OHM

0.1UF 0.1UF

L12N

MIO0

C26

R7

C198

C170C169

C192

C36

C35

C34

C30

C28

C37

C29

C31

C45C38

C200C199

C123

VDD_GPO

GPO3

L4

R6

U3

C21

C202C201 C203

E8C195

E7 U11

ADC

GND4

R3

DAC2

DAC1

GPO2

GPO1

GPO0

C173

E2

C12

C41

C3

U12

C5

C191

U7

1P8V_CLK

1P3V_B

1P3V_A

1V35

1V8

1P0V AD9361_CLKOUT

U1

E4

C18

R4R2

C15

C25

C1

C10

C22

C2

C24

C43

C23

C16

C20

C42

C6

C40

R1

PG_1P3V

RX

TMS

GND3

TX

JTAG_BOOT

MIO49

MIO53

MIO09

MIO11

MIO10

L24N

MIO48

GND1

L10P

C11

TCK

TDO

TDI

C8

C14

C19

C13

C9

C17

C32

C39

C44C33

C4

C27

L9N

L7N

GND2

1V8_2

UART_TX

UART_RX

VDDA_TX_SYNTH

1P3_SUPPLY_B

VDD_GPO

PL_GPIO2

PL_GPIO1

PS_GPIO0

VIN

VDDA_RX_LO

PG_1P3V

VDD_GPO

AD9363_GPO_0

PG_1P0V

SYNC

3P3V_CLK

PL_GPIO3

PL_GPIO4

VDDA_TX_LO

1P3_SUPPLY_B

VDDA_RX_SYNTH

VDDA_RX_TX

PG_1P35V

VDDA_BB

1P3_SUPPLY_A

AD9363_GPO_1

PG_1P3V

1P8V_CLK

AD9363_AUXDAC2

AD9363_AUXADC

PS_GPIO6

1P3_TX2A

VDDD_DIG

1P3_TX1A

IO_02_34_AD9361_CLKOUT

PG_1P3V

JTAG_TDI1P8V_CLK

VCCPINT

JTAG_TCK

1V35

1V8

JTAG_TMS

PG_1P35V

VIN

VDD_INTERFACE

VCCPINT

PG_1P3V

FB0

1P3_SUPPLY_A

PS_MIO05_500_QSPI0_IO3

PS_GPIO5

PS_GPIO4

PS_GPIO3

PS_GPIO2

1V8

PL_GPIO0

PS_GPIO1

AD9363_AUXDAC1

AD9363_GPO_2

JTAG_TDO

AD9363_GPO_3

PG_1P3V

1V8

PWR_CLK

VIN3P3V

6

3

41

2 5 PAD

6

3

41

2 5 PAD

11103

12

1415 9

16

65

2

10

7

1211

13

8 6

14

153

1

14 1

2

1

4 13

101115

321

7

5

2 5

PAD8

PAD

9

12

13

1

164

PAD87

2

4

61

9 2

16

SENSE

VOUT

NC

SS

GND

PG

EN

VIN

PADGNDGNDGND

GND

GNDGNDGNDGNDGND

GND

GND

GNDGND

GNDGND

GND

GNDGND GNDGNDGND

GND GND GND GND GND

PADNC

VOUTEN

GND

VIN

GNDGND

GND

GND

GND

GND

GND

GND

SYNC

PADPGNDGND

SW

PGOOD

RT

FBTRKENVIN

PVIN

GND

GND

GNDGND GNDGND

PADNC

VOUTEN

GND

VIN

GND

SENSE

VOUT

NC

SS

GND

PG

EN

VIN

PADGNDGNDGND

GND

GNDGND

GND

GNDGND

GNDGND

GND

GND

GND

GND

GND

GND

GNDGND

GNDGND

GND

GND

GND

GND

D





AC


2

SCALE

DDDSIZE

D

REV

SHEET

1

1

A

234

35

8

D

7

678

A

B

C C

D

5

4

APPROVED

B

6

DESCRIPTION

REVISIONS

OF

OL GE


EAN

V

OF ANALOG DEVICES.

SCHEMATIC

S

PTD ENGINEER

DESIGN VIEW

REV DATE

Released to

Production

Documents

Production to - Analog Devices