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Prof Jess Role @UEAB 2008
Prof Jess Role @UEAB 2008
• A decoder is a circuit which takes an n-bitnumber as input and uses it to select (set to1) exactly one of its 2n outputs
Decoders
Prof Jess Role @UEAB 2008
Prof Jess Role @UEAB 2008
3 input to 8 output decoderE B2 B1 B0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q70 0 0 0 0 1 1 1 1 1 1 10 0 0 1 1 0 1 1 1 1 1 10 0 1 0 1 1 0 1 1 1 1 10 0 1 1 1 1 1 0 1 1 1 10 1 0 0 1 1 1 1 0 1 1 10 1 0 1 1 1 1 1 1 0 1 10 1 1 0 1 1 1 1 1 1 0 10 1 1 1 1 1 1 1 1 1 1 01 X X X 1 1 1 1 1 1 1 1
B0
B1
B2
E
Q0Q1Q2Q3Q4Q5Q6Q7
Prof Jess Role @UEAB 2008
EncodersAn encoder performs the opposite function to a decoder,
it produces a binary output that indicates which input is active.
There are often PRIORITY encoders because they encode the most significant input.
Eg. A 4 input priority encoder.D0 D1 D2 D3 Q0 Q1 V0 0 0 0 0 0 0 1 0 0 0 0 0 1X 1 0 0 1 0 1 X X 1 0 0 1 1X X X 1 1 1 1
D0
D1
D2
D3
Q0
Q1
V
DataInputs
EncodedOutputs
OutputValid
Prof Jess Role @UEAB 2008
Decoder: input code word, enable inputs, mapping to output code word
Prof Jess Role @UEAB 2008
Display requires BCD to 7-segment decoder
Prof Jess Role @UEAB 2008
2-to-4 decoder:EN=1, I0=1, I1=0 activates Y1
Prof Jess Role @UEAB 2008
Truth table for 2-to-4 binary decoder
Prof Jess Role @UEAB 2008
Shaft encoder (Gray code)
Prof Jess Role @UEAB 2008
DIP for Gray code from mechanical encoding disk
Prof Jess Role @UEAB 2008
Signal naming conventions74x138 3-to-8 decoder
G must be 100 to decode
Prof Jess Role @UEAB 2008
Logic diagram74x138 3-to-8 decoder
Prof Jess Role @UEAB 2008
Truth table74x138 3-to-8 decoder
Prof Jess Role @UEAB 2008
Logic symbols for 74x138 3-to-8 decoder
Prof Jess Role @UEAB 2008
5-to-32 Decodercascading
74x138 3-to-8 decoders
Prof Jess Role @UEAB 2008
G input to construct a 4-to-16 decoder using74x138 3-to-8 decoder
Prof Jess Role @UEAB 2008
ENCODERS6.5
Prof Jess Role @UEAB 2008
Binary Encoders
For n=3 2n=8
Input: I0, I1, … I7
Output: Y0, Y1, Y2
If IY=1 Y2Y1Y0=Y
Prof Jess Role @UEAB 2008
Binary encoder
Prof Jess Role @UEAB 2008
Request encoder
Only one input signal can be active at a time
Prof Jess Role @UEAB 2008
Logic equations for a priority encoder
H7 = I7
H6 = I6•I7’
H5 = I5•I6’•I7’
…
Then the outputs are generated bybinary encoding of the H signals(only one of which can be High).
Prof Jess Role @UEAB 2008
Logic symbol for a generic8-input priority encoder
If I5, I2, and I0 are on, the output is 101
Prof Jess Role @UEAB 2008
74x148 8-Input Priority Encoder
Active-low I/O
Enable Input
“Got Something”
Enable Output
Prof Jess Role @UEAB 2008
Truth table for a 74x148 8-input priority encoder
Inverted inputs:only highestLOW bitmatters
Prof Jess Role @UEAB 2008
Truth table for a 74x148 8-input priority encoder
Note Got Something (GS) and Equal (EQ_L) outputs.
Prof Jess Role @UEAB 2008
Cascading Priority Encoders
32-input priority encoder
Prof Jess Role @UEAB 2008
Next: Three-state Devices,Multiplexers and Demultiplexers, EXORs
Summary
Decoders map an n-bit signal to one of 2n signals.
Encoders map one of 2n signals to an n-bit signal. Some encoders can only have one input line active. Priority encoders can have several.
Most MSI modules have additional control I/O lines.Many eight-bit SSI devices can be combined for wider words.
Prof Jess Role @UEAB 2008
Prof Jess Role @UEAB 2008
Comparators
A comparator is a circuit which compares two input words and produces 1 if they are equal and 0 if they are not equal.
Based on the Exclusive-OR gate, which returns 0 if its inputs are equal and 1 if they are unequal.
A NOR gate decides whether to return 1 for equality or 0 for inequality.
Prof Jess Role @UEAB 2008
Prof Jess Role @UEAB 2008
ComparatorsA B EQL LES GTR
A2 A1 B2 B1 A=B A<B A>B0 0 0 0 1 0 00 0 0 1 0 1 00 0 1 0 0 1 00 0 1 1 0 1 00 1 0 0 0 0 10 1 0 1 1 0 00 1 1 0 0 0 1 (NB Bits reversed)0 1 1 1 0 1 0 (A2 & B2 are LSBs)1 0 0 0 0 0 11 0 0 1 0 1 01 0 1 0 1 0 01 0 1 1 0 1 01 1 0 0 0 0 11 1 0 1 0 0 11 1 1 0 0 0 11 1 1 1 1 0 0
Prof Jess Role @UEAB 2008