Prof. Sandip Kundu

ECE 353 Lab B

(part 1 – Overview)

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Brief Intro of Instructor

@UMass for 9 years Previously

• Principal Engineer @ Intel• 1997-2005

• Member of Research Staff at IBM Research• 1988-1997

Research Interests• Processor Design: 242• VLSI Circuit Design: 558. 559• VLSI Testing: 654• Design for Manufacturability: 697

Authored multiple books and research papers

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Class Information

http://ece353.ecs.umass.edu Labs B and D Office hours during Lab B and D

• Tu 10AM-11AM• Or send email for appointment

Grading• Lab B and Lab D equal weight (each 50% of 35% of final grade)

• Will grade demo and code/report • Final exam (30% of grade) – 50% of questions from Lab B/D

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Outline

Lab B Overview• Next Lecture Review of Design with Verilog for Lab B

Hands-on Lab B • We will provide information about common issues to watch out for

Demo by UGAs• We will go through a functional system so that you can see the end result

in class

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In this lab, you will…

Design and implement a serial MIDI receiver• Essentially a serial port for the MIDI device that will read a MIDI signal • Interpret its content • Display the note number in binary on seven LEDs. • MIDI signal from PC (soundcard)

• Musical notes played using PC keyboard & MIDI OX (“the world's greatest all-purpose MIDI Utility” is free at www.midiox.com). The notes played on the computer’s keyboard will cause MIDI serial data to be sent serially out the MIDI OUT connector.

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In this lab, you will… (contd.)

be Coding in Verilog Hardware in an Altera Complex Programmable Logic Device (CPLD)

MAX 7000S (part number EPM7064SLC44-10) Using ALTERA Quartus II software tools for synthesis Wire up and program on board Debug - functional simulation (wave forms) Debug of board - logic analyzer

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Review MIDI

Musical Instrument Digital Interface Developed in 1980s Common hardware interface and protocol Allows electronic musical devices to communicate with each other MIDI messages are transmitted asynchronously

• Like UART – Universal Asynchronous Receiver Transmitter• UART is more flexible with many more parameters

time

bit 0 bit 1 bit n-1

nochar

start stop...

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MIDI Specification

Groups of bytes, typically three Each byte with START and STOP bit Status byte – code for Note On, Off, other ctrl, ChID – MSB bit is on (1) Data bytes – MSB bit is off (0)

• 2nd B: Note On or Off message with note number• 128 different notes, 10 octaves

• 3rd B: Note On or Off with velocity (how hard is instr. pressed)

STOPbit

Idle MSBLSB

STARTbit

0 1 2 3 4 5 6 7

1

0

Data word

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Decoding of a MIDI Message

In your work you will be decoding MIDI 31,250 bits/s fixed baud rate, bit time (BT) 32us With START & STOP a MIDI msg is 10BT, 320us

• You see this with wave form • Consecutive frames separated by undefined time

idle

@1.5 BT

idle

@8.5 BT

stop startstart

8 bits

stop start stop

8 bits 8 bits

@2.5 BT

frame 3frame 2frame 1

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Decoding of MIDI (contd.)

Board has a 4MHz clock that you need to divide (or count) Before a frame, signal line is high The receive must wait for 0 and detect neg edge Now start sampling 8 bits (payload) in the middle

• See below at 1.5BT, …8.5BT• Stop at 9.5 BT, that is the STOP bit

Repeat for each byte

idle

@1.5 BT

idle

@8.5 BT

stop startstart

8 bits

stop start stop

8 bits 8 bits

@2.5 BT

frame 3frame 2frame 1

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Decoding of MIDI (contd.)

Sampled value at 9.5BT is not logic 1?• A MIDI receiver sets a flag “Framing Error”• You can implement if you want (not required)

Sampling at least once per bit but commonly more times and vote• A voter has a number of inputs and generates an output based on e.g.,

majority or plurality of inputs• TMR (Triple Modulo Redundancy) voter would vote 1 if 2 out of 3 inputs

are 1• A 5 input majority voter would need 3 out 5

• A plurality voter needs a plurality (not majority)

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How it Works, Circuit Schematic

The MIDI OX sw transforms keyboard into an electronic music keyboard.

MIDI signal is generated by the PC. • MIDI OX will send a MIDI Note On

message • Cable terminated with an opto-isolator.

The CPLD will be clocked by a 4MHz crystal oscillator, from which you may have to derive local clock for sampling.

Output of CPLD drives 7 LEDs to display the note number.

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Programming through JTAG

JTAG - Joint Test Action Group: IEEE 1149.1 standard entitled: Standard Test Access Port and Boundary-Scan Architecture • test access ports used for testing printed circuit boards (and chips) using

boundary scan. • Used also for programming embedded devices.

• Most FPGAs, PLDs are programmed via a JTAG port.

JTAG ports commonly available in ICs• Boundary scan, scan chains, mbist, logic bist connected• Chips chained together with Jtag signals and connected to main JTAG

interface on PCB

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Design in Verilog

A quick overview provided next Lecture• Focus is on methodology for proper design and coding

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More Details

Please consult course website Also check deliverables for the Lab in the Lab review document Next

• Practical advise and demo video by the UGAs