Professor N Cheung, U.C. Berkeley Lecture 19EE143 F2010 V DD GND Select mask (dark field & clear field) P-well mask (dark field) Note body contacts: p-well

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

VDD

GND

Select mask(dark field & clear field)

P-well mask(dark field)

Note body contacts:• p-well to GND• n-substrate to VDD

CMOS Inverter Layout

PMOSW/L=9/2

NMOSW/L=3/2

Active(clear field)

Gate(clear field)

Contact(dark field)

Metal(clear field)



Visualizing Layouts and Cross-Sections with SIMPLer

SIMPL is a CAD tool created by Prof. Neureuther’s group

• allows IC designers to visualize device cross-sections corresponding to a fabrication process and physical layout.

A Berkeley undergraduate student, Harlan Hile, created a mini-version of SIMPL (called SIMPLer) for EE40.

• It’s a JAVA program -> can be run on any computer, as well as on a web

server.• A 3D version SIMPL-GL can be accessed at

http://cuervo2.eecs.berkeley.edu/Volcano/simpl_gl/main.htm













Define active areas; etch Si trenchesFill trenches (deposit SiO2 then CMP)

Twin Well + STI CMOS Process

Form wells (implantation + thermal anneal)

Grow gate oxideDeposit poly-Si and pattern gate electrodes

Implant source/drain and body-contact regionsActivate dopants (thermal anneal)

Deposit insulating layer (SiO2); planarize (CMP)Open contact holes; deposit & pattern metal layer



9

3D view of a CMOS inverter after contact etch.



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Well Engineering

P-tub

N-tub

Twin Tub



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Twin Well CMOS Process Flow



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C(x)

x

Conventional well (depth and profilecontrolled by diffusion drive-in)

Retrograde well (depth and profilecontrolled by implantation energy and dose)

Retrograde Well

- formed by high energy (>200keV) implantation



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1) Very low thermal budget for well formation (no need for diffusion drive-in)

2) Retrograde Well is formed AFTER field oxidation small lateral diffusion and localized high conc under FOX

Conventional vs Retrograde Well



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Example: Formation of Channel Stop and Retrograde Wellin a single step

Channel stopRetrograde well



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Multiple Implants for Well Engineering



N Cheung EE243 Sp2010 Lec 116

Channel Engineering

ShallowOxide TrenchIsolation



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Generic Silicon-on-Insulator (SOI) CMOS Process Flow



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SOI Process Flow (continued)



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Smallest featureprintable bylithography

SiO2

CVD oxide CVD oxide

n+ n+ n+ n+

poly-Si gate

Thermal gate oxide

Oxide spacer

AngledImplantn+ pocket

NormalS/D implant

TiSi2

Self-Aligned Channel V-gate by Optical Lithography(SALVO) Process

* Sub-50nm channels



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or

SALVO Process Flow

Chang et al, IEDM 2000

See Homework Problem



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SUMMARY OF IC PROCESS INTEGRATION MODULE

•Self aligned techniques: channel stop, Source/Drain, LDD, SALICIDE•How to read process flow descriptions and cross-sections•Generic NMOS Process with LOCOS•Generic CMOS Process with LOCOS and single well•Modified Processes: •Shallow Trench Isolation (STI), Twin Wells, Retrograde Well, SOI CMOS

Documents

Professor N Cheung, U.C. Berkeley Lecture 19EE143 F2010 V DD GND Select mask (dark field & clear field) P-well mask (dark field) Note body contacts: p-well