The Foundation provides awards for research in the sciences and engineering. The awardee iswholly responsible for the conduct of such research and preparation of the results for publication. The Foundation, therefore, does not assume responsibility for such findings or theirinterpretation.

The Foundation welcomes proposals on behalf of all qualified scientists and engineers, andstrongly encourages women, minorities, and persons with disabilities to compete fully in any ofthe research-related programs described here. In accordance with federal statutes, regulations andNSF policies, no person on grounds of race, color, age, sex, national origin, or disability shall beexcluded from participation in, denied the benefits of, or be subject to discrimination under anyprogram or activity receiving financial assistance from the National Science Foundation.

Facilitation Awards for Scientists and Engineers with Disabilities provide funding for specialassistance or equipment to enable persons with disabilities (investigators and other staff,including student research assistants) to work on an NSF project. See the programannouncement, or contact the program coordinator at (703) 306-1636.

The National Science Foundation has TDD (Telephonic Device for the Deaf) capability, whichenables individuals with hearing impairment to communicate with the Foundation about NSFprograms, employment, or general information. To access NSF TDD dial (703) 306-0090; forFIRS, 1-800-877-8339.

Catalog of Federal Domestic Assistance Number 47-070; Computer and Information Science andEngineering.

Preface iii

Preface

The Computer and Information Science and Engineering (CISE) Directorate, under the direction of an AssistantDirector, consists of the following six divisions and offices: Advanced Scientific Computing (ACS) Division, Computerand Computation Research (CCR) Division, Cross-Disciplinary Activities (CDA) Office, Information, Robotics andIntelligent Systems (IRIS) Division, Microelectronic Information Processing Systems (MIPS) Division, and theNetworking and Communications Research and Infrastructure (NCRI) Division.

The Microelectronic Information Processing Systems Division (MIPS) supports research on novel computing andinformation processing systems including signal processing. Emphasis is on experimental research, technology-relatedresearch and particularly the critical link between conceptualization and realization for integrated systems. Technologiesinclude VLSI, ULSI, OPTICAL, OPTO-ELECTRONIC, INTER-CONNECTION and other emerging technologies.The focus is on research pertaining to hardware systems and their supporting software, including: experimental researchinvolving these new systems; infrastructures, environments, tools, methodologies and services for rapid systemsprototyping; design methodologies and tools; technology-driven and application-driven systems architectures; and fabri-cation and testing of systems. For signal-processing systems, research on algorithms and architectures relating to thesenew technologies that have promise for real-time computing is emphasized.

The purpose of this Summary of Awards for the MIPS Division is to provide the scientific and engineering communitieswith a summary of those grants awarded in Fiscal Year 1996. This report lists only those projects funded using FiscalYear 1996 dollars and hence does not list multi-year awards initiated prior to Fiscal Year 1996.

Similar areas of research are grouped together for reader convenience. The reader is cautioned, however, not to assumethat these categories represent the totality of interests of each program, or the total scope of each grant. Projects maybridge several programs or deal with topics not explicitly mentioned herein. Thus, these categories have been assignedadministratively and for the purpose of this report only.

In this document, grantee institutions and principal investigators are identified first. Award identification numbers,award amounts, and award durations are enumerated after the individual project titles. Within each category, the awardsare listed alphabetically by state and institution.

Readers wishing further information on any particular project described in this report are advised to contact the principalinvestigators directly.

Bernard Chern John R. Lehmann Division Director Acting Division Director

Microelectronic Information Processing Systems Division

Table of Contents v

Table of Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vThe MIPS Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiMIPS Staff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ixSummary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

Design Automation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1The Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Awards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Design Automation - Generic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Design Automation - Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Manufacturing Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Computing Systems Research . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Program Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Awards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Technology Driven Microarchitectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Application Driven Computing Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Scalable Parallel Computing Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Signal Processing Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31The Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Awards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Analog (Mixed Analog/Digital) Signal Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33One-Dimensional Digital Signal Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Image and Multidimensional Digital Signal Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Statistical Signal and Array Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

vi Table of Contents

Experimental Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51The Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Awards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Storage Hierarchies and Input/Output Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53General Purpose Computing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Application Specific Computing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Prototyping Tools and Methodology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65The Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Awards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Education. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Index of PYI, NYI, CAREER, and PFF Investigators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Index of Principal Investigators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Index of Institutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Introduction vii

Microelectronic Information Processing Systems

The MIPS Division

The area of Computing Systems, which involves the structure of computers, is central to MIPS. This is acore area of computer science and engineering and in the 1990's encompasses much more than just hardware.Computing systems deals with computer architecture, hardware implementation, system software (operatingsystems and compilers), networking, and data storage systems. The advent of gigabit networks, highperformance microprocessors and parallel systems is dramatically impacting research on systems levelarchitecture of high performance computing systems.

The emphasis in MIPS is on REAL SYSTEMS i.e. physically realizable. Special weight is placed on design,prototyping, evaluation, and novel use of computing systems and on the tools needed to design and build them.This involves technology driven and application related research, experimental research and theoreticalstudies. The MIPS programs support research on: high level design (design automation and CAD tools);systems level architecture studies; experimental systems research projects which build and evaluateHARDWARE/SOFTWARE SYSTEMS; signal processing algorithms and systems; knowledge of applications;methodologies, tools and packaging technologies for rapid prototyping at the system level; and infrastructureneeded to support MIPS' educational and research activities, e.g. MOSIS.

The Programs

Design Automation Program

Supports research aimed at obtaining fundamental knowledge about the complete design cycle for integratedcircuits and systems from conception through manufacturing and operational test. Emphasis is on integratingall aspects of the cycle, and automating the design and testing processes.

Prototyping Tools and Methodology Program

Supports research on technologies, tools, and methodologies needed for the prototyping of experimentalinformation processing systems and for Microelectronics Education. Issues that arise in rapid systemprototyping are explored, including use of new packaging techniques such as multichip modules, and suchsystems issues as interfacing and standards. Support is also provided for new prototyping services. Basicresearch necessary to model, simulate, measure, automate and improve the microfabrication process issupported. Microelectronics Education support includes workshops, conferences, development of curriculumand courseware materials, and educational support services such as those for FPGA's and fabrication (MOSIS).

Computing Systems Research Program

Supports basic research on computing systems and methods for their design. Computing Systems deals withcomputer architecture, hardware implementation, systems software, networking, and data storage. Researchis encouraged on the fundamental aspects of computing systems architectures and scientific design methodsthat better utilize existing or emerging technologies, support systems software or address important applicationswhose computational requirements cannot be met by conventional architectures. The program emphasizesphysically realizable systems and, when necessary, limited proof-of-concept prototyping.

viii Introduction

Signal Processing Systems Program

Supports research on circuit theory and analog and digital signal processing. The emphasis is on modern signalprocessing, stressing the impact of VLSI, including areas such as: signal representation, filtering, novelalgorithms, special-purpose hardware, and real-time computing.

Experimental Systems Program

Supports research experiments that involve building and evaluating information processing and computingsystems. These are goal-oriented projects usually undertaken by teams of designers, builders, and users. Thebuilding of a system must itself represent a major intellectual effort, and offer advances in our understandingof information systems architecture by addressing significant and timely research questions. The systemprototypes being built should be suitable for exploring applications and performance issues.

Basic research in Computer Architecture and Computing Systems is supported by the National Science Foundationprimarily through three programs in the CISE Directorate: the Computing Systems Research Program and theExperimental Systems Program in the MIPS Division; and the Computer Systems Program in the CCR Division. Thefollowing pie chart shows the relative support through these three programs.

Computing Systems Research (MIPS) (29%)

Experimental Systems (MIPS)(63%)

Computer Systems (CCR) (8%)

MIPS Staff ix

Division of Microelectronics Information Processing Systems

MIPS Staff (October 1996)

Bernard Chern Division Director bchern@nsf.gov

John R. Lehmann Deputy Division Director jlehmann@nsf.gov

Program Program Director NET Address

Design Automation Robert B. Grafton rgrafton@nsf.govComputing Systems Research Michael J. Foster (Acting) mfoster@nsf.govSignal Processing Systems John H. Cozzens jcozzens@nsf.govExperimental Systems Michael J. Foster mfoster@nsf.govPrototyping Tools and Methodology Joseph Cavallaro jcavalla@nsf.gov

MIPS Staff (July 1997)

John R. Lehmann Acting Division Director jlehmann@nsf.gov

John R. Lehmann Deputy Division Director jlehmann@nsf.gov

Program Program Director NET Address

Design Automation Robert B. Grafton rgrafton@nsf.govComputing Systems Research Michael J. Foster (Acting) mfoster@nsf.govSignal Processing Systems John H. Cozzens jcozzens@nsf.govExperimental Systems Michael J. Foster mfoster@nsf.govPrototyping Tools and Methodology Michael J. Foster (Acting) mfoster@nsf.gov

All persons can be reached on the World-Wide-Web through: www.nsf.gov

The address and telephone number for all of the above:

National Science Foundation4201 Wilson Blvd.

Arlington, Virginia 22230

(703) 306-1936

x Summary

MICROELECTRONIC INFORMATION PROCESSING SYSTEMS DIVISION(FY 1996)

Experimental Systems Design Automation

Other Manufacturing OtherTest

Storage Hiearchiesand

Input/Output Systems Application Specific Design Design Computing Automation Automation General - Applications - Generic

Purpose Computing

Design Automation

Experimental Systems

Computing Computing Systems Systems Research Research Other

Prototyping Signal Tools Processing and SsystemsMethodology Technology

Scalable Driven Parallel Microarchitectures Computing

Prototyping Tools and Methodology Systems Application Driven

Infrastructure Computing Education Systems

Signal Processing SystemsAnalog (Mixed Analog/Digital)

Prototyping Signal Processing - Microelectronic

Prototyping Other One-Dimensional - MEMS, SFF, Digital Signal

MCM Statistical Processing Signal and Array Processing

Image and Multidimensional Digital Signal Processing

Summary xi

Summary

Number Dollars ofAwards

Design Automation 57 $4,822,155Design Automation - Generic 30 $2,884,139Design Automation - Applications 13 $1,240,502Manufacturing Test 9 $589,086Other 5 $108,428

Computing Systems Research 36 $4,227,08Technology Driven Microarchitectures 14 $1,316,462Application Driven Computing Systems 6 $612,379Scalable Parallel Computing Systems 15 $2,278,404Other 1 $19,835

Signal Processing Systems 55 $4,749,798Analog (Mixed Analog/Digital) Signal Processing 4 $533,903One-Dimensional Digital Signal Processing 7 $946,480Image and Multidimensional Digital Signal Processing 18 $1,959,287Stistical Signal and Array Processing 11 $595,963Other 15 $714,165

Experimental Systems 38 $9,059,525Storage Hiearchies and Input/Output Systems 5 $1,956,829General Purpose Computing 10 $2,258,447Application Specific Computing 20 $4,755,568Other 3 $88,681

Prototyping Tools and Methodology 24 $3,093,033Prototyping

Microelectronic 15 $1,626,579MEMS, SFF, MCM 6 $1,059,990

Education 2 $56,464Infrastructure 1 $350,000

This summary data includes funds designated for special Foundation initiatives, and equipment matching funds from the Office of Cross-DisciplinaryActivities. It does not include program funds use to support Intergovernmental Personnel Act employees, their travel costs, or costs of travel of reviewpanelists and site visitors.

Design Automation 1

Design Automation(Formerly Design, Tools and Test)

Dr. Robert B. Grafton, Program Director (703) 306-1936 rgrafton@note.nsf.gov

The Program

The Design Automation Program supports long-term, basic research in Electronic Design Automation (EDA) and those areas whereVLSI design technology is applicable; for example, systems-on-a-chip, embedded systems, and multi-technology (optical, micro-electro-mechanical, etc.) systems. It investigates the scientific methodologies, intellectual processes, abstractions, search paradigms,and information models used in VLSI design. Research covers all phases of the complete EDA design cycle for integrated circuits andsystems, from conception through manufacturing test. Goals of the program are:

& Promote discovery, integration, and dissemination of new knowledge in design automation.& Explore models and methods for design and test in radically new technologies.& Support research enabling the US to uphold its world leadership in VLSI Design.& Facilitate a smooth flow of ideas and results to industry and other researchers.

The technology of VLSI circuits changes rapidly. It is now possible to put millions of transistors on a chip and operate at speeds in thehundreds of MHz range. The demand for computing systems of great complexity, performance and trustworthiness is high. VLSIchips and systems of the future will be complex and incorporate technologies ranging from traditional CMOS to optical andmechanical (MEMS). This is causing a re-evaluation of the abstractions on which today's CAD systems are based. Paradigm shifts indesign are needed. New abstractions are needed to permit the designer to better manage the complexity of the design. Newmethodologies need to be developed to cope with technological advances, which make physical phenomena especially important.Design re-use and need for deeper design-space exploration are changing the nature of the design cycle and require new approaches.New tools must be more rapidly disseminated.

Of primary importance to research on a new generation of CAD tools is rebuilding the link betweenCAD researchers and the systems industry. Internships and collaborative research are stronglyencouraged.

Research proposals should contain an explanation of the research strategy and how success will effect the design process, or how itwill be measured in the context of a design project. Specifically, proposals should explain the motivation for the work generated by aparticular application or innovative target. Related work in industry as well as academia, and the methodology to be used in carryingout and evaluating the research needs to be discussed.

Topics in research can be positioned in a three-dimensional space where the three axes represent the traditional EDA area, theapplication domain, and the enabling implementation technology. This framework provides a way to assess the potential impact anddifficulty of the problems addressed.

Design Automation 3

Awards

Design Automation - Generic

Auburn University; Richard O Chapman: CAREER: Formally Verified, Efficient Tools for High-Level Synthesisand Hardware-Software Codesign; (MIP-9623604);$145,312; 60 months; (Support from: ExperimentalProgram to Stimulate Competitive Research, DesignAutomation Program - Total Grant $281,354.

This is a program of research and educationcentered on development of efficient, formallyverified CAD tools for high-level synthesis andcodesign of digital systems. The notion here is todevelop CAD tools which are, themselves, formallyverified and guaranteed to synthesize correctdesigns. The aim is to produce code running on anembedded processor and custom hardware on fieldprogrammable gate arrays. The tools are designedto partition a design into hardware and softwarecomponents, to generate microprocessor code, andto do high-level synthesis. Verification is done byproviding semantic models for the representationlanguages used in the system (behavioralspecification, register- transfer level description,gate-level circuit, machine code) and proving thatthe tools produce designs whose meanings arerefinements of the meanings of their specifications. Theoretical and practical classroom courses whichcompliment this research are being developed.

University of Arkansas; Mitchell A. Thornton; Designand Implementation of OBDD VariableOrdering/Reordering; (MIP-96 33085); $57,681; 24months.

This research is on the design andimplementation of ordered binary decision diagram(OBDD) variable ordering and reordering methods. The work explores the use of memory-efficient datastructures, called Decision Diagrams (DD), todescribe the behavior of Boolean functions. Beingdeveloped is a methodology for finding an orderingof the Boolean function variables so that the DD hasminimal size. This research exploits the use ofconditional probabilities for the purposes of variableordering and dynamic reordering. Efficienttechniques for computation of the spectrum of aBoolean function using its OBDD representation asinput are being used. Software is being developedto manipulate OBDDs as well as compute theprobability values.

California Institute of Technology; Erik K Antonsson:Structured Design Methods for MEMS; (MIP-9529675);$211,584; 24 months; (Support from: Design AutomationProgram, Prototyping Tools and Methodology Program -Total Grant $260,048).

This research is on developing structured designmethods for Micro-Electrical- Mechanical Systems(MEMS). The focus is on MEMS fabrication processsimulation and mask-layout synthesis. In analogy topresent-day VLSI design, tools to permit rapid,accurate, conservative mask layout synthesis ofMEMS are being explored. The objective for thetools is to enable a MEMS designer to specify a micro-mechanical function (e.g. a mechanical springwith particular characteristics), and have a systemautomatically generate the information (mask- layout,and other fabrication instructions) to create the shapethat exhibits the desired function. This includesrefining and extending the 3-D anisotropic etchsimulation methods. Prototype software design toolsare being developed.

Stanford University; Giovanni De Micheli: Logic Synthesisof Low-Power Circuits; (MIP-9421129 A001); $69,514; 12months.

This research is on techniques and tools forautomated logic design of low-power, semi-customcircuits. Digital circuits are specified as models inhardware description languages that can be readilycompiled into finite-state machines. The latter aredescribed by transition diagrams or by synchronouslogic networks. These models are then used to solvelogic synthesis problems in encoding sequentialcircuits, restructuring logic networks, and librarybinding. Tools for a comprehensive EDA system forlow-power design are being developed.

University of California - Los Angeles; Jason Cong: NYI:Performance Optimization in Layout and Logic Synthesis ofVLSI Systems; (MIP-9357582 A003, A004); $67,500; 12months.

This research investigates methodologies andefficient algorithms for performance-driven layoutdesign and logic synthesis of high-speed, high-complexity VLSI systems. The research onperformance-driven layout focuses on interconnectdesign and optimization at each stage of layout design

4 Design Automation

process, including the development of accurateinterconnect models which enable efficient layoutoptimization algorithms, efficient algorithms forcircuit partitioning and clustering, interconnect-driven floorplan and placement, interconnecttopology design with buffer insertion, simultaneousdevice and interconnect sizing, and clock layoutoptimization. The research on performance-drivenlogic synthesis mainly focus on synthesis andmapping for field-programmable gate-arrays(FPGAs), including optimal or near-optimalalgorithms for structural and functional gatedecomposition, minimum-delay technologymapping, trade-off of delay and area in technologymapping, combined retiming, technology mapping,and re-synthesis for clock period minimization, andautomatic pipelining.

University of California - Los Angeles; Andrew BKahng: NYI: Synthesis of High-Speed, High-ComplexityVLSI Systems; (MIP-9257982 A004); $62,500; 12 months.

This research develops a body of knowledge incircuit theory, device physics, and computationaltechniques for VLSI CAD that addresssemiconductor industry needs, as well as futureresearch and tool development. Ongoing researchincludes algorithms for timing/power optimization,layout-driven re-synthesis, and clock distribution forstructured-custom, complex ASIC and mixed-signaldesign methodologies. Other ongoing thrusts aretoward topics in data management, e.g., couplingextraction with timing/signal purity analysis tasks; new models of layout tools for constraint-drivenlayout flows; and search-optimization technologies. Two new topics are also being developed. One ismulti-layer constrained area routing, which bringsinto convergence various technology trends whichinclude: scaling issues related to design complexityand process technology, electro-migration, signalpurity, power, thermal and EMI. The second is developing metrics of solution quality and algorithm performance.

University of California - San Diego; Chung-KuanCheng: Research on Circuit Partitioning; (MIP-9315794A003); $26,391; 12 months; (Support from: ComputingSystems Research Program, Design AutomationProgram - Total Grant $52,783).

This project is an investigation into a newgeneration of hierarchical partitioning methodsmotivated by the need to:1. cope with high circuit complexity,2. improve a system's performance, and3. control intermodule delay.

The principal investigator is extending partitioning research by adopting different circuitmodels including petri nets, data flows, and statemachines, by improving the efficiency andeffectiveness of the methods, and by derivingtheoretical results on variations of partitioningformulations. Partitioning methods are being appliedto netlist mappings for various hardware emulationmachines and VLSI design problems.

University of California - San Diego; Kenneth Y Yun:CAREER: Design Methodologies and Tools for 1 GHz andBeyond; (MIP-9625034); $215,000; 48 months.

This research explores systematic designmethodologies to handle timing and communication inmixed synchronous - asynchronous designs. Formaland automated techniques for managing the designprocess for independently synchronized domains on aVLSI chip are being developed. Specific researchfocuses on: mixed- timing design methodologies andcomponents; specification formalism for mixed-timing interfaces, performance driven synthesis andtechnology mapping techniques for mixed-timingcircuits; hierarchical timing verification techniquesthat check the validity of assumptions used forsynthesis and technology mapping, and techniques toestimate and analyze system performance. Theeducation plan provides an environment to nurturestudents; open-ended problem solving skills;incorporated research activities for undergraduates;opens research opportunities to underrepresentedgroups; and develops industrial internships in thegraduate research program.

University of Southern California; Massoud Pedram: NYI:Low Power VLSI Design; (MIP-9457392 A002); $31,250; 12months; (Support from: Computing Systems ResearchProgram, Design Automation Program - Total Grant$62,500).

This research investigates modeling andestimation of power consumption as well astechniques for minimizing power at the various levelsof design abstraction (layout, logic, register- transferand behavioral levels). Principles and methods toguide the design of power efficient electronic systemsare being explored; and the impact of availability oflow-power design techniques on chip, module, andsystem level designs is being assessed. Topics beinginvestigated include: spatio-temporal powerestimation; state assignment for low power; powerdissipation in boolean networks; commonsubexpression extraction; and FPGA synthesis for lowpower.

Design Automation 5

Colorado State University; Tom Chen, Charles WAnderson, Anneliese VonMayrhauser: Behavioral LevelDesign Verifications Using Software Testing Techniquesand Neural Networks; (MIP-9628770); $314,313; 36months.

A structured methodology for validating andverifying behavioral models is being explored. Themethodology is adapted from a set of software testand validation criteria, which are based on controland data flow properties of the behavioral modelunder test. The test criteria are measured by a setof coverage metrics which indicates the types andthe locations of untested portions in the model. The methodology includes an adaptive test datageneration technique using neural networks. Giventhe untested portions in the model, effective testdata are generated and identified by neural networksto exercise the untested portions. Tools which willprovide designers with a quantitative confidenceindex at the end of their testing and verificationefforts are being developed.

University of Colorado - Boulder; Gary Hachtel, FabioSomenzi, Michael Lightner: An Integrated VHDL-basedSynthesis and Verification System for VLSI Systems;(MIP-9422268 A001); $250,000; 12 months.

This project is on synthesis and verification ofdigital systems. The computational basis for thework is the binary decision diagram (BDD) datastructure and extensions. In low power circuitdesign, new ideas in BDD technology are beingused for synthesis algorithms, and to estimate powerconsumption via probablistic behavior of circuits. Decomposition concepts, such as tearing, to assessproperties of very large circuits are beinginvestigated. In verification, approximateexploration ideas are being examined for use inchecking equivalence of very large circuits. Hierarchical verification capabilities, where parts ofthe circuit are modeled - bit level and word level,are being examined. To provide a soundconnection between high level synthesis and highlevel verification, as well as to validate high levelVHDL descriptions, refined comparisons ofnon-deterministic systems, such as bi-simulationequivalence, testing equivalence, and pre-orders arebeing explored.

University of Colorado - Boulder; Gary Hachtel, FabioSomenzi: U. S. -Germany Cooperative Research on EfficientData Structures for Computer-Aided Design;(INT-9514775); $3,300; 24 months; (Support from:Western Europe Program, Design Automation Program -Total Grant $9,240).

This award supports Professors Gary Hachtel andFabio Somenzi, and a graduate student, all from theUniversity of Colorado, to collaborate in computerscience research with Professor Christoph Meinel andothers of the Department of Computer Science andComplexity Theory and VLSI-Design of theUniversity of Trier, Germany. They are working inthe area of computer-aided circuit design, focusing onthe synthesis and verification of digital systems using`binary decision diagram` data structures. Togetherthey will explore new classes of these efficient datastructures and their behaviors in specific applications. Previous work by the group - Trier on Ordered BinaryDecision Diagrams (OBDDs) has focused primarilyon the theoretical foundations and the connection withcomplexity theory. The US group has been motivatedby real problems of electrical engineering such assequential circuit verification, optimization andtesting. The plan for collaboration will transfer andcombine the complementary knowledge andexperience of the two groups. The resultingsynergism should result in contributions to boththeoretical and practical aspects of circuit design.

University of Delaware; Phillip Christie: Statistical Analysisof Interconnect-Limited Systems; (MIP-9414187 A002,A003); $28,749; 12 months; (Support from: ComputingSystems Research Program, Design Automation Program -Total Grant $57,499).

The growth in size and complexity of moderncomputers is matched by the need for more accuratemodels of their internal wiring structure. The task ofmodeling this complexity is ideally suited to a recentdevelopment in statistical physics called the re-normalization group. It has the power to attack thewiring optimization problem because it takes this onevery difficult problem and breaks it up into a verylarge number of much simpler problems. Rather thanattempting to attack the entire range of partitioningand placement requirements from the transistor levelto the back-plane, an optimization procedure needonly be found for a highly restricted wire length range. Once this has been derived, the procedure isrenormalized for all other length scales in a mannerwhich generates a system-wide solution. This projectwill investigate how such an approach may be used todevelop much better estimates of interconnect-limitedsystem performance and how this theory leads to newoptimization algorithms. In contrast to other theories

6 Design Automation

the predictions made by this technique will growever more accurate as the systems grow larger andmore complex.

University of South Florida; Peter M Maurer: Improvingthe Performance of Digital Logic Simulation;(MIP-9403414 A001); $64,946; 12 months.

This research is on compiled simulation ofsynchronous and asynchronous circuits. A digitallogic simulation algorithm, called the InversionAlgorithm, is being investigated. This is a veryefficient algorithm, yet capable of simulating anydigital circuit. Basic extensions are being made tothe algorithm. These involve including unit andmulti-delay timing models, a logic model withunknown value, new gates, new types of functions,as well as bit-parallel simulation. Further, it isbeing redesigned so as to reduce both thecomplexity of the simulation and the number ofevents processed during simulation. Additionalactivities include extending the existing model to amultiple processor implementation, and to handleasynchronous sequential circuits. Application ofthe Inversion Algorithm to hierarchical simulationand incremental compilation is being explored.

Northwestern University; Prithviraj Banerjee: ParallelAlgorithms for Synthesis and Test; (MIP-9696164);$42,0000; 12 months.

This research is on developing circuit design andtest algorithms that run on parallel computers. These include efficient, asynchronous, portableparallel algorithms for;1. synthesis of combinational circuits, and2. test generation and fault simulation.

Algorithms are being written using anenvironment that makes it possible to port CADapplications across a wide range of MIMDmachines. In addition they are designed to allow amaximum overlap of computation andcommunication. The algorithms are being tested onseveral parallel platforms.

Northwestern University; Majid Sarrafzadeh: AlgorithmDesign for VLSI Layout; (MIP-9527389); $130,772; 24months.

This project is on algorithmic approaches toVLSI. Problems are being investigated are:1. Literal minimization in logic synthesis using an

approach based on term intersection graphs.2. Gate level placement problems using minimum

floating Steiner trees.

3. Budget assignment in timing driven placement.4. Clock tree design using a gated design which

minimizes activity, hence power consumption.A coherent design system, incorporating above

stages, is being developed.

University of Illinois - Urbana-Champaign; C. L. Liu:Research in Computer-Aided Design of VLSI Circuits;(MIP-9222408 A004); $55,600; 12 months.

The research is on algorithms for high levelsynthesis and layout of VLSI CAD designs. Algorithms for complex, large industrial type designproblems are being developed. Research topicsinclude:1. high level synthesis with testability as a goodness

measure,2. timing driven placement algorithms for FPGAs, 3. routing in which cross talk is considered.

For the first problem, the effect of registerallocation and functional unit binding on the testabilityof the circuit is being examined. Then the schedulingstep is being examined. Research on the secondproblem is based on the notion of a "neighborhoodgraph" which is used in guiding an iterativeimprovement algorithm that produces placementswhich satisfy given timing constraints. An integerprogramming approach is being used for the thirdproblem, to avoid parallel long wires that are closetogether in the routing solution.

Purdue University; Kaushik Roy: Logic and CircuitSynthesis for Low-Energy Computing Using Principles ofAdiabatic Switching; (MIP-9633516); $45,146; 18 months.

This research is on adiabatic logic design for verylow energy consumption circuits and systems. Theprimary idea is to use principles of adiabatic switchingas the basis for circuit design. Energy recovery usingthis notion is a relatively new idea, although theconcept of reversible logic and zero-energy computingcan be tracked back to he early 1970s, the attempt torealize the concept in electronic circuits is a newendeavor. An adiabatic logic, using both fullyreversible and partially reversible logic, is beingdeveloped. It is based on standard CMOS technologywith a switching power supply. Basic logic gates,registers, and memories for recovered energyoperations, are being developed. Tools for powermanagement, such as techniques to utilize theredundant signals generated from reversible logicgates, are being developed. The circuits and thepower supply are being fabricated and tested.

Design Automation 7

University of Notre Dame; Edwin H Sha: High-LevelDesign Methodologies for Time-Optimal andMemory-Optimal Systems; (MIP-9501006 A001); $25,000.

This research is on optimization algorithms forsynthesis of multi- level loops, which occur in timeand memory critical parts of scientific computingapplications. The nested loops are modeled asmulti-dimensional data-flow Graphs (MDFG); andalgorithms taking advantage of the multi-dimensionality are being designed. By consideringthe multi-dimensional iteration space and theiteration body simultaneously, the transformationand optimization techniques are able to optimizethroughput and memory requirement - the behaviorlevel. Research topics include: graphtransformation and optimization; data scheduling;and co-design. Polynomial-time algorithms forvarious graph models are being developed. Thisavoids exponential integer linear programmingapproaches.

Massachusetts Institute of Technology; SrinivasDevadas: NYI: Formal Methods for Hardware andSoftware Verification; (MIP-9258376 A005); $62,500; 12months.

This research is on methodologies for design oflarge-scale digital systems containing bothapplication-specific and re-programmable hardware,where most (or all) of the circuitry will be on asingle chip. A design methodology that optimizespower dissipation of the embedded system, whilemeeting area and performance constraints, is beingdeveloped. Methods to generate small, dense codeto reside on the chip, and verification methods thatguarantee design correctness are being explored.

University of North Carolina - Charlotte; Dian Zhou:NYI: Performance-Driven VLSI Designs; (MIP-9457402A002); $32,750; 12 months; (Support from: SignalProcessing Systems Program, Design AutomationProgram - Total Grant $65,500).

This research merges two efforts inasynchronous circuit compilation. These are thework of Gopalakrishnan on the language "hopCP"and its use in verification; and the work ofBrunvand on asynchronous circuit compilation. Thegoal is to enhance the expressive power as well asthe semantic clarity of concurrent hardwaredescription languages for asynchronous circuits andsystems. The research effort includes: findingextensions to the formal basis for compiling fromHDL's to circuit designs; exploring formal

characterizations and the optimizations used inasynchronous circuit compilation; and studying theperformance of implemented circuits with regard to avariety of parameters.

Portland State University; Malgorzata Chrzanowska-Jeske: Pseudo-Symmetric Binary Decision Diagrams(PSBDDs); (MIP-9629419); $183,550; 36 months.

This research is on a data structure,Pseudo-Symmetric Binary Decision Diagrams(PSBDDs), for completely specified Booleanfunctions. The structure of an OBDD for a totallysymmetric function is used as a model for PSBDDs. The Shannon expansion is used to generate thevertices of PSBDDs. There is a join operation whichcombines two adjacent vertices such that the functionis represented as a pseudo-symmetric network insteadof a binary tree. The research consists of: a)developing a PSBDD package with four types ofsymmetry; b) investigating the best heuristic forvariable ordering, and ordering sets of symmetricvariables; c) comparing mapping results for largefunctions between PSBDDs and BDDs; d) developingstrategies for efficient generation of PSBDDs forincompletely specified functions; e) developingdiagrams using Davio I and Davio II expansions; andf) suggesting new architectures forCellular-Architecture type FPGAs which aredesign-automation friendly.

Carnegie-Mellon University; Edmund M Clarke:Automatic Verification of Finite-State Concurrent Systems inHardware and Software; (CCR-9217549 A003); $75,000; 12months; (Support from: Design Automation Program,Software Engineering - Total Grant $150,000).

Logical errors in sequential circuit designs andcommunication protocols have always been animportant problem. The most widely used method forverifying such systems is based on extensivesimulation and can easily miss significant errors whenthe number of possible states is very large. Thisresearch deals with developing an alternative approachbased on a technique called temporal logic modelchecking. In this approach specifications areexpressed in a propositional temporal logic, andsequential circuits and communication protocols aremodeled as state transition systems. An efficientsearch procedure is used to determine automatically ifthe specifications are satisfied by the transitionsystem.

8 Design Automation

Texas A & M University; Dhiraj K Pradhan, Duncan MH Walker, Wolfgang Kunz: Novel Methods inComputer-Aided Circuit Design and Testing UsingRecursive Learning; (MIP-9406946 A002); $108,731; 12months.

This research investigates modeling andestimation of power consumption as well astechniques for minimizing power at various levelsof design abstraction (layout, logic, register- transferand behavioral levels). Principles and methods toguide the design of power efficient electronicsystems are being explored; and the impact ofavailability of low-power design techniques on chip,module, and system level designs is being assessed. Topics being investigated include: spatio-temporalpower estimation; state assignment for low power;power dissipation in boolean networks; commonsubexpression extraction; and FPGA synthesis forlow power.

University of Texas - Austin; Margarida Jacome:CAREER: Design Assessment and Reuse; (MIP-9624231);$220,050; 48 months.

This research is on design reuse and designprocess assessment. Design reuse can be in anypart of the design cycle from initial phases (capture,processing, and organization of design information),to final phases (matching, retrieval and actual reuseof design information). Mechanisms for supportingthis activity are being explored. Attention is beingpaid to maximizing opportunities for reuse, andassessing the impact on productivity of the reuseinfrastructure. Issues being addressed include thecharacterization and representation of design objectsand design processes, automatic capture, indexing,retrieval and reuse of design information. Thesecond investigation is developing a framework,including risk assessment and planning tools, fordesign process assessment. Metrics or measuringmanagement objectives and parameters of thedesign process are being identified andcharacterized. Results of the research are beingtested and validated in the design of large embeddedsystems.

University of Utah; Erik L Brunvand, GaneshGopalakrishnan: The Design of Asynchronous Circuitsand Systems with Emphasis on Correctness and ProvenOptimizations; (MIP-9215878 A002); $5,000.

This research merges two efforts inasynchronous circuit compilation. These are thework of Gopalakrishnan on the language hopCP andits use in verification; and the work of Brunvand on

asynchronous circuit compilation. The research is:1. enhancing the expressive power and semantic

clarity of concurrent hardware descriptionlanguages for asynchronous circuits and systems

2. extending the formal basis for compiling fromHDL's to circuit designs;

3. formally characterizing and improving theoptimizations used in asynchronous circuitcompilation; and

4. studying the performance of implemented circuitswith regard to a variety of parameters.

University of Utah; Ganesh Gopalakrishnan: AMulti-Paradigm Verification System Tailored for the DesignRefinement Cycle; (MIP-9321836 A002); $15,000.

The design of a VLSI system involves multipledesign representations; and the design must gothrough several iterations aimed at meeting manyperformance and cost constraints. Verification thatthe design meets constraints is necessary. Thisresearch is developing rigorous verification methodsthat span multiple design representations,accommodate design revisions, and provide incisivepartial verification methods (e. g. verificationfocussed on the "corners" of the behavioral space) thatfit within designers' time budgets. These ideas arebeing validated by verifying the real asynchronousdesigns.

University of Utah; Chris J Myers:CAREER: DesignMethods and Tools for Mixed-Timed Systems;(MIP-9625014); $210,000; 48 months.

This research investigates formalization andautomation techniques for design of asynchronoussystems. Techniques for managing multiple,independently synchronized domains under amethodology in which timing and communication canbe explicitly specified, synthesized, and verified arebeing explored. Specific tools and techniques beingdeveloped for the design of mixed-timed systemsinclude: a performance and power optimizingcompiler; a synthesis tool to producetechnology-independent circuits; a technologymapping tool that takes the implementation and mapsit to high- performance gate libraries; and a timingverification tool. In addition, new design methods arebeing developed to produce: high-performancemixed-timed data paths, and an interface betweensynchronous and asynchronous modules.

The PI's education plan includes;1. curriculum emphasis on communication skills,2. development of new computer engineering

courses,3. promoting interdisciplinary activities,4. incorporating research activities into the

Design Automation 9

curriculum through class and summer projects,and

5. fostering interaction with industry throughstudent summer internships.

University of Virginia - Charlottesville; Gabriel Robins:NYI: New Directions in High-Performance VLSI Layout;(MIP-9457412 A003); $62,500; 12 months.

Realistic formulations of performance-drivenlayout are the focus of this research. Accuratemodels of circuit delay are being sought. Thesemodels include technology parameters, such ascapacitance, resistance, inductance, etc. Theapproach is to study delay-optimal trees to define anenvelope of achievable routing performance. Methods for constructing near-optimal layouts arebeing investigated. Additionally, the routingproblem is being recast as one of constructinglow-delay routing graphs where cycles are allowed. This can have the advantage of designs beingtolerant to certain types of open faults due tomanufacturing defects or electro-migration.

University of Washington; Steven M Burns: NYI: A DesignLanguage for Asynchronous Circuit Synthesis;(MIP-9257987 A004); $62,500; 12 months.

The long term goal of this project is to find amechanism for capturing the complete design of anasynchronous digital system. Thus, this research is onmechanisms for representing design decisions, andfinding ways to construct transformations of fromhigh-level descriptions to a low-level design. Research includes:1. developing algorithms for technology mappings

of speed-independent circuits;2. exploring methods to formally verify correctness

of design transformations;3. finding methods for analyzing timing of

asynchronous systems; and4. development of a rapid prototyping facility

(MONTAGE) for field-programmable gate arrays.

Design Automation - Applications

University of California-Santa Barbara; Forrest Brewer:Production Language Based High-Level Synthesis;(MIP-9320752 A002); $56,002; 12 months.

The overall goal of this research is to create anew class of synthesis tools which address the designof complex controller-data path machines underconstraints of pre-defined interfaces. Because theresults will be integrated with commercial EDAdesign tools, a design output format, which can besimulated and allows automated re-design of selectedportions of the design, is being developed. In asecond task, approximate sequential reachabilityanalysis is being used to design and implementalgorithms for optimizing and partitioning controllerdesigns. The third task is to explore schedulingalgorithms for both the control and data-path portionsof the design. Finally, an optimizing compiler isbeing built. It contains algorithms which solveencoding issues for high performance designs, andperforms re-scheduling of the data-path operations tominimize required resources while maintainingdesign behavior.

University of California-Santa Barbara; MalgorzataMarek-Sadowska: Research on Layout and Logic Design;(MIP-9419119 A001); $103,000; 12 months; (Supportfrom: Prototyping Tools and Methodology Program, Design Automation Program - Total Grant $143,000).

This research is on layout driven synthesis,which is at the intersection of logic synthesis andphysical design. The approach is to determinealgorithms and methodologies for restructuring logicnetworks in synthesized digital systems. Threetopics, which address the problems inherent indesigning and testing in dense, high speed, circuitsare being investigated. Topics include:1. Incremental restructuring of Boolean networks2. Logic synthesis for testability;3. Logic synthesis for low power,4. XOR/AND representation of Boolean functions;

and5. Tools for field programmable gate arrays.

New techniques are being applied to partitioning,routability correction, improving testability,automation of engineering change, free scan insequential circuits, multilevel synthesis, and FPGArouting.

10 Design Automation

Georgia Institute of Technology; Giorgio Casinovi:Computer-Aided Simulation of Optoelectronic IntegratedCircuits; (MIP-9523436); $142,142; 24 months.

The integration of electronic and photonicdevices on the same chip offers performanceadvantages in terms of speed, bandwidth, immunityto interference, power dissipation andinterconnection density. This research exploresalgorithms and tools for simulation of optoelectronicIntegrated Circuit (OEIC) designs. The goal is tosimulate equally accurately both optical andelectronic devices in the same circuit. Both lumpedand distributed-constant elements are included in themodel. Existing models for optoelectronic devicessuch as light emitters, detectors, and electro-opticmodulators are being refined and incorporated in thesimulator. New models are being developed foroptical interconnect and for those optoelectronicdevices for which no models suitable for time-fordomain simulation currently exist. A simulationenvironment, capable of handling circuits withoptical and electronic devices is being constructed.

University of Illinois - Urbana-Champaign; Rajesh KGupta: Architecture and Synthesis Techniques forEmbedded Systems; (MIP-9501615 A001); $10,000.

This research is on synthesis techniques formicro-electronics- based "embedded systems". Anembedded system is one designed for a specificfunctionality under stringent constraints on its timingperformance and cost. Design automationtechniques are being developed for use in aframework where the designer can assess tradeoffsbetween various embedded system architectures anddesigns. The main capabilities of this frameworkare;1. timing analysis for both execution delay and rate

constraints,2. embeddable software and runtime system

generation, 3. software size-performance tradeoffs, and4. cost- performance analysis of architectural

alternatives.This work is exploring system partitioning and

transformation techniques to build systemimplementations that "guarantee" constraintsatisfaction while optimizing system developmentcost.

University of Illinois - Urbana-Champaign; NareshShanbhag:CAREER: Design of Giga-Scale CMOSCommunications Systems: An Integrated Approach;(MIP-9623737); $220,000; 48 months.

The research objective is to developmethodologies for the design of giga-scale CMOSsystems. A focus is high bit rate digitalcommunications. The approach transcendsboundaries between algorithmic, architectural, logic,circuit and technological aspects of the VLSI designmethodology. The research has two parts. The firstis an investigation of fundamental limits on powerarea speed and reliability in giga-scale computation. Activities include finding achievable bounds on thepower dissipation, area, speed and reliability for anygiven algorithm and implementation technology.

In the second part, algorithms, architectures, andsystems for design of high-bit rate communicationssystems are being investigated. This includesdeveloping power, area, and speed-optimal VLSIalgorithms and architectures for high-bit rate digitalcommunications and signal processing applications. As an application, systems for 155.52 Mb/stransmission over twisted-pair wiring for ATM andIMTV, and wireless spread-spectrum systems arebeing built.

University of Massachusetts Amherst; Israel Koren:Topological and Physical Layout Design Techniques forYield Enhancement; (MIP-9305912 A001); $70,000; 12months.

This research is on design tools which cancompensate for manufacturing yield losses due to thecomplexity of the logic. Preliminary results haveshown that yield can be enhanced by the technique ofreducing the sensitivity of the chip to point defects. Yield optimization algorithms and techniques whichare applicable to the last two stages of design -topological/symbolic, and physical layout are beingexplored. Physical layout strategies for yieldenhancement in the channel routing and compactionphases for standard cell designs are beinginvestigated. Yield enhancements in topologicaldesigns are being illustrated through PLA-baseddesigns.

Design Automation 11

Michigan Technological University; Jeffrey O Coleman:RIA: Convex-Programming Design of Signals and Systems;(MIP-9409686 A001); $2,500; (Support from: SignalProcessing Systems Program, Design AutomationProgram - Total Grant $5,000).

The PI is creating a special-purposeprogramming language in which optimizationproblems can be specified in a natural and direct way. The focus is on developing associated translationsoftware to convert such a specification into aparticular canonical form for numerical optimizationusing recently developed, ultra-efficient,interior-point algorithms. The canonical form is alinear-matrix- inequality (LMI) program, where eachconstraint takes the form of a requirement that alinear (plus a constant) matrix function of theoptimization variables be positive definite.

Control theorists have recently demonstrated thata tremendous variety of common (and uncommon)constraints can be put into this generic form. Often,however, the required LMI constraints are not relatedto the underlying problem in an intuitive way. Software to translate specifications in a "comfortablelanguage" to sets of LMIs is being developed in orderto make these powerful optimization techniques easyto apply. The language is being applied to realproblems in communication and signal-processingcircuit designs.

University of Michigan Ann Arbor; Karem A. Sakallah,Trevor N Mudge, Edward S Davidson: Timing Issues inthe Design of Digital Systems; (MIP-9404632 A001);$116,678; 12 months; (Support from: Computing SystemsResearch Program, Design Automation Program - TotalGrant $175,017).

This research is on a timing verification andoptimization framework for designing an entiredigital system (e. g. a microprocessor). Theresearch builds on a widely used model forsynchronous timing analysis and an efficient methodfor estimating gate and wire delays. The model isbeing extended to include relevant functionalinformation in order to enhance accuracy. Components of the framework are: designdecomposition to isolate critical elements; a pathdelay calculator; algorithms for finding synchronizercomponents; clock analysis algorithms; a symbolicsequential timing verification component; a hybridtiming-logic simulator; and design optimizers.

Princeton University; Sharad Malik: NYI: DesignAutomation for Embedded Systems; (MIP-9457396 A002);$60,000; 12 months.

High fabrication costs and decreasing time-to-market for products require an increase of theprogrammable component of integrated circuits. Thischanges circuit design from just gates in an array, toa combination of instructions running on a coreprocessor coupled with a gate array. Gates, as basicunits of computation on silicon, are well understood;but use of embedded instructions as basic units ofcomputation on silicon is not. Three problems are thefocus of this research. First is performance analysisof embedded software, with examination of pathanalysis and micro-architecture modeling. Second ispower analysis of embedded software, withdevelopment of an instruction level power model. Third is retargetable code generation for digitalsignal processors, with the application of codegeneration problems to expression trees for DSPs.

State University of New York - Stony Brook; Michael MGreen: NYI: Improved Circuit Simulation Using Resultsfrom Circuit Theory; (MIP-9457387 A002); $31,250; 12months; (Support from: Signal Processing SystemsProgram, Design Automation Program - Total Grant$62,500).

This research is applying the principalinvestigator's previous work in the area of nonlinearcircuit theory to make major enhancements to theway designers simulate analog circuits. Inparticular, improvements to the continuation methodsof solving dc operating points of circuits are beingmade guaranteeing that all of a circuit's operatingpoints will be found during a single analysis. Moreover, continuation methods are being applied tosensitivity analysis of circuits; for example, bymaking observations of a continuation curve, adesigner could determine whether a circuit is prone toa latch up condition. Erroneous models are thoughtto be a major source of convergence problems anderroneous results in circuit simulation. Anotherenhancement to circuit simulation includes checkingthe accuracy of transistor models by verifying that allmodels satisfy passivity and the no- gain condition.

12 Design Automation

University of Utah; Erik L Brunvand, GaneshGopalakrishnan, Alan L Davis: Application-DrivenAdvancement of Asynchronous Design Methods;(MIP-9622587); $157,076; 12 months.

This is an investigation into the application ofasynchronous circuit design tools to a large, realisticexample. The project is being carried out inconjunction with the Avalanche parallel architectureproject - the University of Utah. The Cache andCommunication Control Unit (CCCU) of theAvalanche multiprocessor, which is designed as asynchronous system, is being implemented as aself-timed system using the original specification forthe Avalanche CCCU. To do this, problems inself-timed circuit design are being deeplyinvestigated, with a particular focus on automatingthe design of high-performance self-timed systems. Chips embodying the designs are being fabricatedthrough MOSIS, tested and evaluated.

University of Virginia - Charlottseville; Joanne Dugan,Barry W Johnson: Innovative Dependability AnalysisTechniques in an Advanced Design Environment;(MIP-9528258, A001); $209,354; 24 months.

This research explores the relationships betweenmodels used to refine the system design, to assess thereal-time behavior of the system, and to assess thefault tolerance. These relationships are beingcombined to develop tools for system- level modelingwith dependability analysis of the design. Theapproach builds on two recently developed tools,ADEPT (Advanced Design Environment PrototypeTool) and DREDD (Dependability and Risk

Evaluation using Decision Diagrams). Advanced techniquesfor dependability analysis of embedded computer systems arebeing put into the ADEPT design environment. There, adynamic fault tree model is automatically generated from theADEPT system design model. The fault tree models uses acombination of Markov techniques, combinatorial approachesand binary decision diagrams. It can model permanent andtransient hardware faults, unrelated and related software,automatic recovery and reconfiguration management,sequence dependencies and other dynamic behavior.

University of Washington; Andrew T Yang: NYI:Modeling and Simulation of Advanced Microelectronics andOptoelectronic Circuits and Systems; (MIP-9257279 A004);$62,500; 12 months.

This research is on design of deep submicrontechnology, <0.5 um, circuits. Effects that werepreviously disregarded are now important in design. For example, reduced power supply voltage andhigher operating frequency lead to more noise, signalintegrity problems, and devices that appear moreanalog. Furthermore manufacturing process controlhas not kept up with reduction in dimensions, leadingto designs that are vulnerable to process variations. Topics include:1. a computer aided design methodology for

improving product yield in manufacturing2. substrate power supply switching noise modeling

and simulation; and3. reduction of interconnect and substrate RC

networks from post layout extraction. Algorithms for solving these problems are being

developed.

Manufacturing Test

Stanford University; Edward J McCluskey: Research onReliable Computers; (MIP-9107760 A003); $150,002; 12months.

This research is on techniques for reducing theoccurrence of run-time errors in circuits and systems. Emphasis is on preventing the introduction of faultsinto the system through verification and synthesistechniques, and on improving the detection anddiagnosis of faults causing run-time errors so that thefaults can be removed from the system. Topics beingpursued are:1. finding synthesis methods that automatically

synthesize a synchronous, register-transfer level(RTL) hardware specification from a behavioral

VHDL language specification;2. determining what coverage of multiple stuck-at

faults or bridging faults can be expected orguaranteed by a test for delay faults in anarbitrary circuits;

3. investigating methods for utilizing the use ofoutput waveform characteristics in delay testing;and

4. constructing fault models and methods fordetecting intermittent failures.

Design Automation 13

University of California-Santa Cruz; Frankie J Ferguson:PYI: Hierarchal Test Pattern Generation forManufacturing Defects; (MIP-9158491 A007); $48,530; 12months.

Two approaches to manufacturing testmethodologies are being explored. These are the useof both high level and low level fault models togenerate tests that detect virtually all plausiblemanufacturing defects. The research vehicle is adefect modeling tool, "Carafe" (circuit and realisticfault detector), which determines the most likelyfaults to occur in a CMOS circuit. First, Carafe isbeing modified to include algorithms for location ofthree dimensional defects, and locate shorts that arebetween nodes on different layers. Second, it isbeing used to investigate physical design fortestability at both the chip and logic cell levels. Third, Carafe is being used to develop algorithms forfault isolation and diagnosis.

University of California-Santa Cruz; Tracy Larrabee; PYI: Sequential and Combinational Test PatternGeneration for Realistic Faults Using Boolean Satisfiability;(MIP-9158490 A007); $37,500; 12 months.

This research is based on an automatic testpattern generation (ATPG) system (called Nemesis)that generates a test pattern for a given fault by firstconstructing a formula representing all possible testsfor the fault, and then applying a Booleansatisfiability algorithm to the resulting formula. Thismethod separates the formula extraction from theformula satisfaction thus providing flexibility andgenerality. A testing system, based on Nemesis, thatwill generate tests detecting all realisticmanufacturing defects in both combinational andsequential ICs is being developed.

University of Iowa; Irith Pomeranz: NYI: A New SearchStrategy for Design Automation; (MIP-9357581 A003);$41,880; 12 months.

This research explores a design strategy,"Incremental Dynamic Optimization BasedLearning". This is a general purpose approach toobtaining high quality solutions to synchronous,sequential VLSI designs. This strategy is based onscaling down a design problem, by reducing circuitsize, while retaining critical details. Optimalsolutions are found for a sequence of small designs,common features are extracted, and these are scaledup to a solution for the original problem. Thismethod permits exploration of the tradeoff betweenspeed of creating a design and its quality. Additionally, tradeoffs between two methods for test

generation and diagnosis are being explored. Theseare: three valued logic (which is fast) and stateenumeration (which is accurate, but slow). Applications to very large circuits are being made.

University of Massachusetts - Amherst; PremachandranMenon: Delay-Verifiable Combinational and Non-ScanSequential Circuits; (MIP-9320886 A001); $29,999; 12months.

This research explores the concept of a delay-verification test set, which detects the presence ofany path delay faults that can affect the timing of thecircuit. The approach is to find necessary andsufficient conditions for delay verifiability; i. e. theexistence of a complete delay-verification test set. Algorithms for the synthesis of area-efficient, delay-verifiable circuits and the generation of delayverification test sets are being developed. A secondtopic being explored is a design and test methodologyfor sequential circuits without scan latches infunctional paths. A method, based on clocksuppression, is being used to generate transitions onstate variables for delay testing. State assignmenttechniques to improve delay-fault testability withoutscan and clock suppression are being investigated.

Princeton University; Niraj K Jha: High-Level Synthesisfor Hierarchical Testability; (MIP-9319269 A002, A003);$81,050; 12 months.

This research explores efficient hierarchicaltestability techniques for controller-data pathsystems. Module level test sets, derived for anysuitable fault model, are used with high level designsynthesis. The resulting test sets are combined into asystem level test set which provides complete (ornearly complete) test coverage of all the embeddedmodules. These testability techniques are beingembedded into algorithms for design of schedulingand allocation circuits. Key design criteria are lowpower and testability.

University of North Carolina - Charlotte; Rafic Z Makki:New Approaches to the Testing of Digital IntegratedCircuits; (MIP-9406931 A001); $3,580; (Support from:Africa, Near East and South Asia Program, DesignAutomation Program - Total Grant $7,160).

This research explores test methods formanufacturing test of CMOS integrated circuit (IC)chips based on monitoring of the dynamic portion ofthe power supply current (iDDT). Since an iDDTpulse is created any time a CMOS circuit switchesstates, the monitoring of iDDT provides observability

14 Design Automation

into the switching behavior of the circuit. This,combined with standard test methods, can provideimproved testability of manufactured IC chips. Newaccurate fault models based on actual physical testsas opposed to simulation alone, and new designmethods for enhancing iDDT-testability are beinginvestigated. The methods are being incorporatedinto a design-for-testability tool, and are beingevaluated on real designs.

Case Western Reserve University; Daniel G Saab: AnAdaptive Approach to Automatic Test Pattern Generation;(MIP-9528931); $131,545; 24 months.

This research investigates the generation ofmanufacturing tests for highly sequential VLSIcircuits. The approach is based on combining thebest features of deterministic and simulation basedtechniques. Deterministic techniques are mainlyused to identify untestable and redundant

faults, and to correct the direction ofthe simulation.

Simulation based test vector generationexamines a set of test vectors to determine a new testsequence to detect some faults. This process, while

accurate and fast, generates longer than necessary testvectors. The technique being explored is detecting andcorrecting the genetic search, using deterministic ATPG. This process involves an intricate exploration of the power ofa switch-level logic and fault simulator in an combination witha genetic algorithm and the deterministic ATPG during thetest generation process. The technique is being applied todesign problems such as, circuit partitioning, initial test setfinding, and circuit initialization- structure to determineperformance and quality of generated test sets.

University of Wisconsin-Madison; Charles R Kime:Built-In Self-Test for Random Pattern Resistant Faults;(MIP-9319742 A002); $65,000; 12 months.

This research is on techniques for testing circuitshaving random pattern resistant faults. The focus ison methods for synthesizing random pattern testablecircuits. The synthesis algorithms being developedinclude algorithms for design of random patterntestable two level and multi-level combinationallogic; extensions to some classes of sequential logicare also being investigated. Two methods beingpursued are weighted cellular automaton, and fixedbit biased pseudo-random pattern generator.

Other

Tufts University; Karen P Lentz: Compression andInteraction Algorithms for Modeling and SimulationEnvironments; (MIP-9528194); $8,998; 18 months;(Support from: Design Automation Program, SoftwareEngineering Program - Total Grant $17,996).

This is a research planning grant developingmodeling and simulation aigorithms to assess systemperformance and to recreate events so as to interpretcause- effect relationships. The research planningactivities focus on investigating the potential fordeveloping accurate, general purpose modelingtechniques that include compressing multipleexperiments (variations of effects on the model)while allowing internal observation to expose theperturbations that caused the outcome. The grantresources are being used to contact other researchersinvolved in related efforts; and to investigate issuresinvolved in expanding existing concurrent algorithmsto areas beyond digital logic modeling andexperimentation.

University of Cincinnati; Ranganadha R Vemuri, HaroldW Carter: Innovation in VLSI Systems Education:Integration of High Level Synthesis, Analysis and TestGeneration Research Results into Undergrad MinorCurriculum in VLSI Systems Engineering;(CDA-9634462); $65,000; 36 months; (Support from:Design Automation Program, CISE InstitutionalInfrastructure - Total Grant $249,042).

This CISE Educational Innovation awardsupports the integration of research in high-levelVLSI synthesis, performance analysis and test vectorgeneration into the undergraduate curriculum inVLSI systems engineering. The model curriculumwill contain topics on the development of high-levelfunctional and behavioral modeling of VLSI designs,use of high-level VLSI synthesis techniques andtools, developing and using performance modelsthroughout the design process, and generation ofdesign verification tests. Curriculum supportmaterial will include mini-books on these topics, termproject modules, and, most importantly, free softwaretools for high-level synthesis, performance analysis

Design Automation 15

and test generation. All of the curriculum materialwill disseminated through the Internet and theWorld-Wide-Web.

University of Virginia - Charlottesville; Gabriel Robins:Joint Research Between VLSI CAD and MEMS Areas: TheFifth Physical Design Workshop; April 15-17, 1996; Reston,Virginia ; (MIP-9531666); $12,500; 12 months.

The Micro-Electro-Mechanical Systems(MEMS) process technology has matured to the pointwhere it is possible to fabricate a chip with bothelectrical and mechanical pomponents on it. However, tools and design methodologies arelacking. This workshop brought together designresearchers from the VLSI CAD and MEMS designfields to discuss and develop ideas for a new designmethodology for combined MEMS/VLSI structures.

Virginia Polytechnic Institute and State University; DongHa; Infrastructure for VLSI Circuit Testing: Developmentof a Fault Simulator and Test Generators for IndustrialCircuits; (MIP-9632625); 24 months; (Support from:CISE Institutional Infrastructure, Design AutomationProgram - Total Grant $154,746).

VLSI chip testing tools, produced in researchprojects - the Virginia Polytechnic University, arebeing developed and enhanced. The tools areintended to support teaching and research inacademia. These tools include, a combinationalcircuit automatic test pattern generator (ATPG), asequential fault simulator, a sequential ATPG forboth synchronous and asynchronous sequentialcircuits, and two parsers for analyzing circuit designsin the languages VHDL and EDIF. A benchmarkcollection of industrial type circuits is beingdeveloped. The tools are being developed so thatthey;

1. are easy to install and use,2. Are maintenance free,3. provide a variety of options to support research

and teaching activities, and4. have source code that is easy to read, modify and

extend. The tools and their source code are being

distributed freely to universities for research andteaching.

University of Washington; Gaetano Borriello: Workshopon Future Research Directions in CAD for ElectronicSystems: "Putting the 'D' Back in CAD"; (MIP-9634523);$21,930; 6 months.

This workshop is on evaluating priorities foracademic electronic design automation (EDA)research, with the intention that the results of themeeting aid in refocusing the field on its roots. Bothfuture priorities for research and education, as well asareas that are already well-served by the EDAindustry and are unlikely to require major newmethodological or technological breakthroughs areconsidered. The workshop report includes:1. a statement of the most pressing problems to

solve within the next decade,2. recommendations regarding the style and kind of

research to be conducted and suggestions to thecommunity as to how to implement thesesuggestions, and

3. viewpoints on increasing the impact of the EDAfield on education in electrical and computerengineering.

Computing Systems Research 17

Computing Systems Research(Formerly Microelectronic Systems Architecture)

Dr. Michael Foster. Acting Program Director(703) 306-1936 mfoster@note.nsf.gov

Program Description

The Computing Systems Research (CSR) program is concerned with developing a fundamental understanding of computing systems,including their design, architecture, implementation, and evaluation. Computing systems include computer architecture, hardwareimplementation, supporting system software (e.g., compilers and operating systems) for new architectures, interconnection networks,storage and I/O architectures, and novel computing structures and technologies that hold the promise of radically new computingsystems for the next century. Research in computing systems seeks higher levels of performance and more advanced computational or information processingcapabilities by enhancing the structure and organization of computing systems with innovative architectural concepts, and byimproving the interaction of their underlying hardware and software components. The basic technological domains involved inadvanced computing systems include:

& design and evaluation of instruction set architectures and the organization of central processing units, including datapaths, arithmetic units, controller design, and processor pipelines;

& memory systems, including addressing, register files, virtual memory support, multilevel cache memories, highperformance frame buffers, and pipelined memory structures;

& computer system interfaces to communications networks and other high speed peripherals, including direct memoryaccess mechanisms;

& multilevel storage structures, including disk architecture, disk caches, and mass storage systems;& interconnection structures among processors, memories, and input/output channels;& compiler and operating system support for novel architectures;& fault tolerant and redundant hardware structures, including fault detection and correction mechanisms, design for

testability and reliability;& high-performance input/output systems, including smart sensors, actuators, and special underlying systems for graphics

and visualization; (9) the design of heterogeneous distributed computing systems, including global architecture, nodearchitecture, and supporting software; and

& embedded systems, in which hardware, software, and I/O are integrated into an application. In addition, new generationsof computer architectures or special purpose computing systems often demand specialized system software andapplication library co-development, and such specialized system software are part of computing systems research.

Within these technical domains, the CSR program concentrates on research issues that contribute to extending performance,programmability, scalability, and reliability of computing systems. Typical issues which are addressed include: methodologies forsystem design that map system specifications to physical realizations; design and analysis of components of computing systems; andbenchmarking of performance, programmability, scalability, reliability, composability, and predictability. The CSR programencourages studies on the impact of new hardware and software technologies, as well as the impact of new applications andalgorithms on computing systems architecture. The styles of research employed include theoretical studies, simulations, limited proof-of-concept prototyping, and measurement of existing systems. The CSR program emphasis is on the design and evaluation ofphysically realizable systems. Successfully completed research projects are expected to pursue advanced experimental systems designthrough the Experimental Systems Program.

Computing Systems Research 19

Awards

Technology Driven Microarchitectures

California Polytechnic State University; Joy SShetler:CAREER: Computing Systems Research Educationand Research; (MIP-9624967); $200,000; 48 months.

This project establishes an active research effortin Computing Systems Research that enhances theundergraduate curriculum in Computer Engineering,Computer Science and Electrical Engineering, andintroduces students to new computer architectures,new technology and microelectronic systems. Theideas developed will be incorporated into themicroprocessor and computer architecture curriculumalong with new cooperative learning techniques. The focus of the research component is to devise andtest Instruction Level Parallelism (ILP) techniquesand mechanisms. Programmable Logic Devises,such as FPGAs, are used to implement rapid systemprototyping of custom computer designs and are alsoused to implement custom components inreconfigurable architectures. Engineers andcomputer Science students are taught with highlyparticipatory "active learning" methods such ascooperative learning which stimulate student interestand learning. By introducing students to teamworkin the engineering classroom, learning is enhanced,fruitful networking relationships are developed andstudents are able to adapt easily into other teamenvironments. The rapid- prototyping platformdeveloped for this effort is used for several upperdivision computer architecture and microprocessorcourses and the cooperative learning pedagogy servesa national model.

University of California - Davis; Matthew Farrens: NYI:Award: High Performance Single Chip VLSI Processors;(MIP-9257259 A005); $61,665; 12 months.

The research is to investigate variousconfigurations of decoupled architectures and toextend the concept into the field of parallelprocessing. It is anticipated that, with severaldecoupled processors communicating viaarchitectural queues called Multiple InstructionStream Computer (MISC), it will function as a typeof dynamic superscalar processor, providingsignificant performance gains. The MISCarchitecture uses multiple asynchronous processingelements to separate a program into streams that canbe executed in parallel, and integrates a conflict-freemessage passing system into the lowest level of theprocessor design to facilitate low latency intra-MISC

communication. This approach allows for increasedmachine parallelism with minimal code expansion,and provides an alternative approach to singleinstruction stream multi-issue machines such assuperscalars and VLIWs. The relationship betweenoptimal processor configuration and transistor countis also being investigated. The goal is to define thedesign points at which a change to multipleprocessors becomes advantageous.

University of California - San Diego; Chung-Kuan Cheng:Research on Circuit Partitioning; (MIP-9315794 A003);$26,392; 12 months; (Support from: Computing SystemsResearch Program, Design Automation Program - TotalGrant $52,783).

This project is an investigation into a newgeneration of hierarchical partitioning methodsmotivated by the need to:4. cope with high circuit complexity,5. improve a system's performance under I/O pin

count constraints, and6. control intermodule delay in order to optimize

system performance.The principal investigator proposes to extend

previous partitioning research by adopting differentcircuit models including petri nets, data flows, andstate machines, by improving the efficiency andeffectiveness of the methods, and by derivingtheoretical results on variations of partitioningformulations. He plans to apply partitioningmethods to netlist mappings for various hardwareemulation machines and to find potential applicationsof these methods to VLSI design problems

University of California - Santa Cruz; Anujan Varma:NYI: High-Speed Interconnection and SwitchingTechnologies; (MIP-9257103 A006); $62,500; 12 months.

This research aims to develop architectures andprotocols for highspeed interconnection withincomputer systems. Typical applications to beconsidered include interconnection of processorsubsystems among themselves for multiprocessorconfigurations, and the interconnection of processorsto I/O subsystems. The focus is on high-speedcrossbar switches as the interconnection means. Thestructure of these switches as well as mechanisms forconnection setup, routing, and flow-control acrossmultiple cascaded switches are being studied.

20 Computing Systems Research

Photonic switch architectures obtained by combiningdimensions of switching, such as wavelength andspace, are under investigation.

University of Southern California; Massoud Pedram:NYI: Low Power VLSI Design; (MIP-9457392 A002);$31,250; 12 months; (Support from: Computing SystemsResearch Program, Design Automation Program - TotalGrant $62,500).

This research investigates modeling andestimation of power consumption as well astechniques for minimizing power at the various levelsof design abstraction (layout, logic, register- transferand behavioral levels). Principles and methods toguide the design of power efficient electronicsystems are being explored; and the impact ofavailability of low-power design techniques on chip,module, and system level designs is being assessed. Topics being investigated include: spatio-temporalpower estimation; state assignment for low power;power dissipation in boolean networks; commonsubexpression extraction; and FPGA synthesis forlow power.

George Washington University; Hyeong-Ah Choi: WDMBroadcast Networks and Massively Parallel Computers;(MIP-9628468); $50,000; 12 months.

This is a career advancement award to applytheoretical methods from the study of interconnectionnetworks to the study of all-optical broadcastnetworks. The goal of the research is to developnew scheduling algorithms to improve theperformance of broadcast networks that usewavelength division multiplexing. The schedulingalgorithms will take into account an arbitrary set ofsystem parameters that change with technology. Theresearch will provide insight into the user of multiplewavelengths and tunable devices in optical networks.

Iowa State University; Sachin Sapatnekar: CAREER:Gate-Level Performance Optimization of Pipelines andGeneral Sequential Circuits; (MIP-9502556 A002); $5,000.

This project is concerned with performanceoptimization of high- speed synchronous digitalcircuits It addresses the application of timingoptimizations to pipelines and general sequentialcircuits in high-performance systems. The core ofthe research effort is directed towards the method ofretiming at the gate level. Retiming is a sequentiallogic optimization technique that repositions memoryelements, namely, edge-triggered flip-flops andlevel-triggered latches, within a circuits to optimize

the timing behavior of the circuit. The use ofretiming optimization methods, chiefly device sizing,is also being investigated.

Under the educational part of this project, the PIis incorporating CAD techniques in theundergraduate program from the sophomore level bythe use of CAD tools in teaching. At the graduatelevel, he is involved in developing courses, thesupporting existing courses, and in advising graduatestudents. He is also exposing undergraduates to hisresearch for a better appreciation of the state of theart, and to motivate them towards higher education. he is also contributing towards outreach activities byfocusing towards distance education through teachingcourses to sites in the state of Iowa via television,and around the country through the medium ofsatellite.

University of Michigan - Ann Arbor; Karem A Sakallah,Trevor N Mudge, Edward S Davidson: Timing Issues inthe Design of Digital Systems; (MIP-9404632 A001);$58,339; 12 months; (Support from: Computing SystemsResearch Program, Design Automation Program - TotalGrant $175,017).

This research is on a timing verification andoptimization framework for designing an entiredigital system (e. g. a microprocessor). Theresearch builds on a widely used model forsynchronous timing analysis and an efficient methodfor estimating gate and wire delays. The model isbeing extended to include relevant functionalinformation in order to enhance accuracy. Components of the framework are: designdecomposition to isolate critical elements; a pathdelay calculator; algorithms for finding synchronizercomponents; clock analysis algorithms; a symbolicsequential timing verification component; a hybridtiming-logic simulator; and design optimizers.

Rutgers, The State University; Miles Murdocca:Development of a Methodology for Implementing HardwareDataflow Graphs Using Reconfigurable OpticalInterconnects; (MIP-9224707 A002); $10,000.

In this project a system is being built to translatea dataflow language into hardware and implement thehardware on an optical gate array. The system iscomprised of three components: a compiler totranslate a dataflow language such as ID into adataflow graph; a method for converting dataflowgraphs into hardware described by a hardwaredescription language, along with a simulator; and asynthesis program for mapping HDL descriptionsonto an optical gate array. The optical gate arrayconsists of planes of electronic gates, with the planes

Computing Systems Research 21

interconnected by free-space optics. An advantageof this kind of gate array is quick reconfiguration ofthe optical interconnections which allows dataflowgraphs to be changed quickly. This project isapplicable to the development of advanced integratedengineering cells for manufacturing. Because ofnoise immunity and lack of electromagneticinterference, optical computation is well-suited to thefactory floor. Reconfigurable optical computers ofthe type under development in this project may allowhigh-speed computation to be inserted intomanufacturing processes in new ways.

State University of New York - Buffalo; Chunming Qiao:RIA: Reducing Communication Latency with PathMultiplexing in Optically Interconnected MultiprocessorSystems; (MIP-9409864 A001); $10,000.

This project develops an innovative approach toall-optical TDM communications in multiprocessorsystems. The proposed approach is an extension ofa previously developed connection paradigm forreducing control latency in reconfigurable opticalinterconnection networks. Using the proposedapproach, a connection is established during a set oftome slots along the path which are dependent oneach other, so that no time-slot interchanging isrequired and simple switching devices can be used. As a result, the overall communication latency aswell as the complexity of the network can bereduced. Thus, a near term impact of this research ison the design of high-performance, low-complexityoptical interconnection networks suitable formultiprocessor systems. The research also haslong-term impact on the advancement of technologiessuch as Asynchronous Transfer Mode (ATM) andWavelength-Division Multiplexing (WDM) as theemerging technologies for computercommunications.

North Carolina State University - Raleigh; Thomas MConte;CAREER: New Paradigms for Instruction-LevelParallel Processors; (MIP-9625007); $200,000; 48 months.

This CAREER proposal addresses newparadigms for exploiting and teaching instruction-level parallelism (ILP). Statically-scheduledmicroarchitectures achieve high performance byrelegating to the compiler the responsibility fordetecting and scheduling ILP. Drawbacks to thisapproach include a lack of object code compatibilitybetween generations, the reliance on programprofiles, and the erosion of the individualcompilation model. This research will develop new

paradigms for ILP that remove the drawbacks byenlisting the OS, the linker, the assembler, theinstruction encoding and the microarchitecture. Theeducational plan will introduce the compiler's role inthe undergraduate curriculum as the sophomore andsenior levels by developing two courses:"Introduction to Machine Language Programming"will be modified to include an awareness ofperformance issues and the role of the compiler; anda senior level course will be developed to teachback-end ILP compiler optimization. An importantfeature of this proposal is the training of graduatestudents in a fundamentally and technologicallysignificant area of ILP. The research andeducational activities will use the TINKERInstruction Set Architecture that has been constructedby the principal investigator and his students.

North Carolina State University - Raleigh; Wentai Liu:VLSI Delay Vernier Architectures and Applications;(MIP-9531729, A001); $214,300; 37 months.

This project is concerned with two performanceenhancing techniques of VLSI systems that havedeveloped from wave pipelining: delay vernierarchitectures and non-zero skew designmethodologies. Many high performanceapplications require extremely fine timing resolutionor very high data sampling rates. Examples includehigh speed network transceivers, A/D converters,phase-locked and delay-locked loops, and ATE pinelectronics. Normally, expensive circuittechnologies and very high frequency clock signalsare used to satisfy these performance requirements. However, the proposed delay vernier structures arecapable of achieving a very high time resolutionusing CMOS technologies and relatively slow clocksignals. This research will focus on refining andextending delay vernier architectures and designtechniques so that their usefulness is maximized. The effectiveness of the architecture in a number ofapplications will be evaluated. Also, somereal-world factors, such as process variation andnoise, will be investigated. The non-zero skewdesign approach allows the VLSI systems designer totake advantage of intentional skew to optimize clockdistribution for a particular set of propagation delays,and thereby greatly improve system throughput. Acritical necessity for these systems in the ability tocreate precise clock skews. This research will focusvery strongly on the delay vernier technique, since itcan provide this required ability. Finally, prototypessystems will be built for several promisingapplications.

22 Computing Systems Research

Carnegie-Mellon University; David F Nagle:CAREER:The Architect's Workload Suite Helping ArchitectsUnderstand Software Systems' Impact on Future ComputerDesign; (MIP-9624700); $200,000; 48 months.

Effective computer architecture requires acarefully selected set of workloads that arerepresentative of the target design's softwareenvironment. However, it is becoming increasinglydifficult for computer architects to obtain workloadsthat accurately characterize today's complex softwaresystems. The Architect's Workload Suite (AWS)project seeks to address this problem by developing acollection of commercial, public domain, andnext-generation software systems that architects canuse as a source of representative workloads. Usingon-chip performance counters and custom tools, eachworkload in the AWS will be accompanied byWorkload Characterization Worksheet thatsummarizes its architectural requirements includingmemory-system, branch-prediction, instruction-levelparallelism, course-grained parallelism, and operatingsystem support. Workload summaries will allowresearchers to carefully screen the AWS workloads,selecting a set that is appropriate for their work. Inaddition to the workload suite, this work isdeveloping several hardware/software analysis tools. The first, based on Trap-driven simulation,characterizes and evaluates memory systems. Thesecond, a modified version of DECs ATOm analysistool, generates accurate software traces of the entiresystem's activity, including OS and applicationworkloads. Together, the workloads, theircharacterization worksheets and the tools will helparchitects determine how best to support futuresoftware systems.

University of Pittsburgh; Rami Melhem: Time DivisionMultiplexing of Optical Interconnection Networks;(MIP-9633729); $187,016; 36 months.

The goal of this research is to study, design andevaluate control mechanisms for time-multiplexingoptical interconnection networks in multiprocessorapplications. Such mechanisms decouple therelatively slow network control from the high opticaldata transmission bandwidth. The research willassess the advantages, capabilities and limitations oftime-division multiplexing. Specifically, modelswill be developed to specify the communicationrequirements of applications, to express and measurethe communication locality present in communicationloads, and to estimate the communication cost inmultiplexed interconnection networks. Differentcontrol protocols will be simulated and tested ontraces collected from actual parallel applications, andon synthetic traces generated with the help of thecommunication locality model. Centralized,distributed and pipelined control strategies will beimplemented and compared. This project ismotivated by several observations. First, withoutmultiplexing, the control overhead of establishingend-to-end connections in a network may beprohibitive. Second, applications exhibitcommunication locality which amplifies the benefitsof multiplexing. Third, the high bandwidth ofoptical paths allows for multiplexing with minimaleffect on the transmission rate on individualconnections. Finally, the nature of massivelyparallel programs allows compilers to determine,with current technology, the multiplexing sequencesthat satisfy most of the communication requirements.

Application Driven Computing Systems

University of Illinois - Urbana-Champaign; Benjamin WWah: Global Optimization and Parallel Processing ofNonlinear Problems in Engineering Applications;(MIP-9632316); $300,000; 36 months.

The objective of this project is to develop anefficient nonlinear optimization method - NOVEL:Nonlinear Optimization Via External Lead - and thesupporting hardware/software to solve large-scalenonlinear optimization problems in operationsresearch, digital signal processing, andneural-network learning. Such a method will allowmany important application problems in these areasto be solved better as well as faster than existing

methods. The method first transforms nonlinearconstrained optimization problems using Lagrangemultipliers into unconstrained optimization problems. This transformation allows both constrained andunconstrained problems to be solved in a unifiedframework. The key idea of the method is to use auser-defined trace to pull a search out of a localoptimum (a local saddle point in constrainedoptimization and a local minimum in unconstrainedoptimization) without having to restart it from a newstarting point. The proposed method has a goodbalance between global search and local search. Inglobal search, NOVEL relies on two counteractingforces: local gradient information that drives the

Computing Systems Research 23

search to a local optimum, and a deterministic tracethat leads the search out of a local optimum once itgets there. The effect of the trace on the searchtrajectory is expressed in terms of the distancebetween the current position of the trajectory and thatof the trace. Good starting points identified in theglobal-search phase are then searched moreextensively using pure local searches. The proposedresearch consists of four aspects: refinement of theNOVEL method, parallel processing, extension tomixed-nonlinear optimization problems, andapplications of the methods developed to solveproblems in operations research, digital signalprocessing, and neural-network learning.

Massachusetts Institute of Technology; Kai-Yeung Siu;NYI: Analysis and Design of Artificial Neural Networks;(MIP-9696144); $31,250; 12 months; (Support from:Signal Processing Systems Program, Computing SystemsResearch Program - Total Grant $$62,500).

Artificial neural networks present a new modelfor massively parallel computation and a promisingparadigm for solving large scale optimizationproblems. This research is exploring the advantagesof neural network-based models over conventionalmodels for computation, and a novel design ofneuromorphic computing architectures forapplications in signal and image processing. Atheoretical framework is being established to derivetight tradeoffs between the number of elements andthe number of layers in neural networks. The resultsshould answer some of the key open questions in theanalysis of neural networks using classicalmathematical tools such as rational approximationtechniques and harmonic analysis.

Western Michigan University; Xiaobo Hu: ArchitecturalDesign Exploration for Real-Time Embedded Systems;(MIP-9612298); $151,177; 36 months.

Advances in both hardware and software designhave enabled system designers to develop large,complex embedded systems. Such systems maycontain a mixture of software programs running ongeneral purpose or special-purpose processors,high-speed memory systems, and application specifichardware devices. One of the key tasks in designingthese systems is to find a "best" system architectureincluding determining the "right" partition betweenhardware and software components and selecting the"right" hardware components. The focus of thisproject is to develop a viable methodology as well asa set of tools to assist system designers in thisarchitectural design exploration task. The researchproposed performs design exploration at the system

level. At this level, a system is specified as acollection of task graphs and an implementation isdescribed by an interconnection of hardwarecomponents and an assignment of processes to thehardware components. Though the problem sharessome similarities with the hardware synthesisproblem, many different issues need to be addressedin order for this approach to be effective. One of theissues is identifying and estimating appropriateparameters to be included in the exploration processsuch that system timing performance can beadequately predicted. The project emphasizesdesign exploration for embedded systems withreal-time constraints. Such systems can be found inmany applications, such as navigation and landingcontrol of aircraft, networks and communications. Attributes that are useful for guiding designexploration will be devised so as to efficientlyanalyze the timing behavior of a large number ofimplementations with respect to the system timingspecifications and hence permit exploration of a widerange of design options. Other issues includingsensitivity analysis and component reuse will also beaddressed. To properly handle conflictingperformance requirements including both functionaland non-functional attributes, an approach based onimprecise value functions from utility theory will bepursued. Furthermore, the design explorationproblem is formulated as a multi-attributeoptimization problem. Techniques from theevolutionary computation field will be investigated inorder to tackle the exponential nature of theoptimization problem.

University of Rhode Island; Qing Yang: Exploring theDesign Space for High Performance and Low Cost MemoryHierarchies; (MIP-9505601 A001); $10,000.

The main objective of this research is toinvestigate the issures related to hardware designsand performance evaluations of a number ofinnovative cache design techniques. These designtechniques are currently being developed forsingle-chip general purpose processors andmultiprocessors. Specifically, the focus of theresearch includes: 1) minimization of area cost ofon-chip caches by CAT--caching address tags: 2)maximization of cache hit ratios by evenlydistributing data across cache sets with the help of afew tag bits that change frequently during programexecutions; 3) investigation of potential impacts ofthe new CAT cache designs for various cacheconfigurations as well as multiprocessor caches; and4) devising analytical models, and performingtrace-driven simulations and execution-drivensimulations for evaluating implementation costs,performances, and design trade-offs of variousdesigns.

24 Computing Systems Research

Texas A & M University; Nitin H Vaidya: Bit/ByteBounded Error Control Codes for Byte-Organized Systems;(MIP-9423735 A001); $49,952; 12 months.

The principal goal of this project is to designerror control codes for "byte-organized" systemsusing a new error control model. In a byte-organizedsystem, the hardware is partitioned such that eachpart produced a subset of hits in the output. Forexample, a memory may be organized as one byte percard. In this case, each card produces a byte in thememory word. For such systems, a new errorcontrol model called the bit/byte bounded model isbeing developed. Briefly, this model can bedescribed using two parameters, say t and u. Thecodes designed using the bit/byte bounded model cantolerate up to t bit errors confined to a must u bytes. Unlike the existing approaches, the bit/byte boundedmodel can interpolate between the traditional bit and1 byte error models. Also, the proposed model canbe used to reduce the number of checkbits by tradinga small amount of error control capability.

University of Wisconsin-Madison; ParameswaranRamanathan: Guaranteed Performance Communication inDistributed Real-Time Systems; (MIP-9526761); $70,000;12 months.

This project is exploring new communicationmechanisms that go beyond the deadline guaranteesof previous work in real-time and non-real-timemessage streams, using models of real-timecommunication that can represent tolerance todeadline misses. For real-time message streams,these models suggest new techniques for providingservice guarantees on the frequency or clustering ofmissed deadlines. for non-real-time messagestreams, the models will be used to develop supportmechanisms that minimize average delivery delaysubject to the constraints of the real-time streams. Simulation and analytic methods are being used toevaluate competing techniques.

Scalable Parallel Computing Systems

University of California - Los Angeles; Milos DErcegovac: Arithmetic Algorithms and Structures forLow-Power Systems; (MIP-9314172 A002); $98,395; 12months.

The objective of the proposed research is thedevelopment of numerical computing systems whichoperate with a small amount of electrical power. Itconcentrates on arithmetic structures and algorithmsand models power consumption by the number ofsignal transitions. These low-power structures areessential for the development of future computingsystems. The proposed research will further theunderstanding of the effect of number representation,algorithm, and implementation on the powerdissipation of numerical computation structures. Moreover, methods and technique for the design oflow-power structures will be developed, as well aslow-power designs for specific operations, such asadders, comparators, multipliers, and dividers.

University of Delaware; Phillip Christie: StatisticalAnalysis of Interconnect-Limited Systems; (MIP-9414187A002, A003); $28,750; 12 months; (Support from:Computing Systems Research Program, DesignAutomation Program - Total Grant $57,499).

The growth in size and complexity of moderncomputers is matched by the need for more accuratemodels of their internal wiring structure. The task of

modeling this complexity is ideally suited to a recentdevelopment in statistical physics called the re-normalization group. It has the power to attack thewiring optimization problem because it takes this onevery difficult problem and breaks it up into a verylarge number of much simpler problems. Ratherthan attempting to attack the entire range ofpartitioning and placement requirements from thetransistor level to the back-plane, an optimizationprocedure need only be found for a highly restrictedwire length range. Once this has been derived, theprocedure is renormalized for all other length scalesin a manner which generates a system-wide solution. This project will investigate how such an approachmay be used to develop much better estimates ofinterconnect-limited system performance and howthis theory leads to new optimization algorithms. Incontrast to other theories the predictions made by thistechnique will grow ever more accurate as thesystems grow larger and more complex.

University of Florida; Jih-Kwon Peir: CAREER:Decoupling and Reforming Tag and Data Arrays forHigh-Performance Memory Hierarchy Systems;(MIP-9624498); $200,000; 48 months.

The project investigates issues in memoryhierarchy design and proposes solutions to bridge theincreasing performance gap between the processorand memory. By observing the unequal time needed

Computing Systems Research 25

to perform cache tag access/comparison and to accesscache data, this path imbalance can be exploited toachieve a more performance optimal cache design. The basic idea is to use an additional tag array recordthe status and location of the recently used lines inthe cache data array. By recording the cache linelocations in this subset of the tag array, the dataaccess is decoupled from the tag access/comparisonpath for a shorter overall cache access time. In amultiprocessor system, cache coherence activitiesincur extra traffic to the heavily-loaded snooping busand impose additional latency in accessing the data. By observing that references to the same memorylocation are often ordered at the software level,frequently rendering cache coherence activities areunnecessary and can be deferred until at the propersynchronization point. The infrastructure required,including a multiprocessor tracing facility,multiple-issue out-of-order execution processormodels, and various memory hierarchy models, willbe developed in this project. These tools will beenhanced with graphical user interfaces and used forinstructional purposes to provide students withhands-on experience in evaluating differencearchitectural design tradeoffs.

Georgia Institute of Technology; UmakishoreRamachandran: The Quest for a Zero Overhead ParallelMachine; (MIP-9630145); $235,442; 36 months.

The primary goal of this project is todemonstrate the viability of cost- effective parallelcomputing techniques for two application domainsthat make computing ubiquitous. The first one isparallel databases embodying a clients/serverparadigm used in data mining/data warehousingapplications. The second one is the physicalsimulation of virtual multimedia environments thathas potential use in several everyday situations. Thechallenge in this domain is to perform realisticphysical simulation in real time of multiple actors(some real and some synthetic), each with severaldegrees of freedom. This research will investigatethe system architecture issues in the design of parallel(cluster) servers engineered with commodityprocessing and network components for supportingsuch applications. A shared address space across thecluster is an attractive abstraction from theperspective of programming such applications. However, accessing and caching data from thisshared address space can be expensive in terms ofobserved latencies in a cluster. Therefore, clevertechniques that hide the communication overheadsfor accessing the shared address space are imperativeto achieving good performance. The ultimate goalsis to make the cluster server appear as though the

applications incur zero overhead for communication. Specific research issues to be addressed in thisresearch include (a) mechanisms for realizing sharedaddress space across the cluster, (b) mechanisms forsupporting variable granularity, caching, explicitcommunication, and synchronization (within theframework of shared space) tailored to the needs ofthese applications, (c) hardware assists necessary tomake clusters appealing as cost-effective parallelmachines, and (d) detailed performance evaluationsof cluster servers under such multimedia anddatabase workloads.

Purdue University; Jose A Fortes: Data DistributionIndependent Parallel Processing; (MIP-9500673 A002);$91,253; 12 months.

This project is exploring the possibility of aparallel programming paradigm that isdata-distribution independent (DDI) in the sense thatthe user would not be required to program or eveninvoke data communication routines (hereon calledmodules). The need for data redistribution wouldeither be eliminated or transparent to the user. Theemphasis this work is on the systematic design ofcomputational modules so that either there is no needto redistribute input data or, when this cannot beachieved, the cost of (automatic) redistributionisminimized. In this context, source-to-sourceprogram transformations, called modular mappings,and properties that allow commutative parallelprocessing are being explored as techniques andconcepts that enable DDI computation. The extentto which a DDI paradigm could replace existingapproaches, complement them or merely apply tospecial application domains is unclear and this is oneof the issues under investigation. In addition,hardware and architecture features that support DDIcomputation on both general and special purposeaprallel processors are being investigated. Theexperimental validation is being done in the contextof three application areas and programimplementations on a fine-grain distributed memorySIMD machine (Maspar MP-1 with 16 thousandprocessors) and a coarse- grain distributed memoryMIMD machine (Intel Paragon with 140 processors). The areas of interest are dense linear algebra, sparselinear algebra and symbolic compute algebra whichcan be applied to numerous scientific andengineering computing problems. For these threeareas, DDI modules are being developed as well asentire programs built of several modules. Performance comparisons are being made betweenDDI implementation and their non-DDI counterparts.

26 Computing Systems Research

Iowa State University; Prasant Mohapatra: HardwareMulticast Routing Techniques for Scalable ParallelComputers; (MIP-9628801, A001); $167,486; 36 months.

Multicast communication is an essential featurein parallel computers. It benefits several parallelapplications and is useful for shared memory,distributed memory, and distributed-shared memorysystems. Multicasting also helps in supporting aclass of communication patterns known as collectiveoperations. Multicasting can be supported by eitherhardware or software approaches. However, thehardware approach is significantly faster than thesoftware approach. Most vendors of parallelcomputers are either unaware of it or have madeunsuccessful attempts at implementing deadlock-freehardware multicasting schemes. This project isconcerned with efficient hardware multicast routingtechniques for meshes and switch-based parallelcomputers. Several implementation details, such asstart-up latency, router delays, and multiplemulticasts, will be addressed in this project. Theprimary objectives of the research will include theminimization of the total communication latency byreducing the number of start-up steps required formulticasting in meshes. For switched-basedsystems, this project will examine alternative switchdesigns to support efficient deadlock-freemulticasting. Finally, an effort will be made todesign low-cost routers that support multicastoperation. Two primary constraints will be observedduring this research. First, the cost and complexityof the algorithms will be minimized. Second, the PIwill focus on techniques that not only supportdeadlock-free multicast operations but also enhancethe performance of node-to-node unicastcommunications.

Johns Hopkins University; Robert Cypher: Techniques forFault-Tolerant Communication in Parallel Computers;(MIP-9525887); $153,756; 36 months.

The project studies techniques for performingefficient communication in parallel computers thathave faulty components. Parallel computers with alarge number of identical processors have a greatpotential for fault-tolerance. The main challengethat must be overcome in order to exploit thispotential for fault- tolerance is the fact that faults alsoaffect communications between processors. Hardware faults in processors, routers, andcommunication links force messages to take newpaths that avoid the faulty components. In addition,the mapping of computations from faulty processorsto nonfaulty ones changes the pattern of

communication. As a result, faults can have a majorimpact on the performance, and even correctness, ofthe communication subsystem in a parallel computer. Specifically, the project focuses on the following twokey issues; creating efficient, deadlock-free routingalgorithms for parallel computers with faultycomponents, and developing efficient mappings ofcommunication-intensive real-time applications toparallel computers that contain faults. This researchwill result in more efficient use of parallel computersand a better understanding of how their inherentpotential for fault-tolerance can be utilized.

Boston University; Mark G Karpovsky: SoftwareImplemented Fault Tolerance in Multicomputers;(MIP-9630096); $220,003; 36 months.

The main objective of this proposal is to developan integrated approach for increasing thedependability of parallel computers. For detectionand diagnosis of hardware faults at the local (node)level, this approach will combine off-line built-in selftesting, on-line concurrent checking, and softwaretechniques implementing path and algorithmic-basedchecks. The aim of this proposal is to develop asystematic method for generating and placing checksinto the implementation of an application. Forautomating the verification process and placement ofchecks in programs, an interactive tool, VERIFY,will be developed. For estimating the coveragefactor provided by these techniques, a softwarefault-injection tool will be created. Efficient and fastreconfiguration algorithms will be developed foravoiding single and multiple faulty nodes and links. A user transparent software layer will be created forimplementing the proposed algorithms. This will bewritten on top of the existing system software thatresidents in every node of parallel computingsystems.

The Software Object-Oriented Fault-InjectionTool (SOFIT) will be ported on the nCUBE andTandem SeverNet. The recovery time overhead willbe estimated in the presence of single and multiplefaults injected by SOFIT into the nodes and links ofthe nCUBE and SeverNet when programs are beingexecuted. A dependability evaluation study will beperformed. The objective of this research is to showthat this integrated approach can be used successfullyfor improving the reliability of the nCUBE andSeverNet by an order of magnitude.

Computing Systems Research 27

University of Michigan Ann Arbor; Peter M Chen:CAREER: Measuring and Improving Memory's Resistanceto Software Corruption; Relational Instruction;(MIP-9624869); $200,000; 48 months.

System designers have long assumed thatmemory cannot reliably store permanent data becauseof memory's volatility and vulnerability to softwarecorruption. Memory's unreliability slows systemperformance by forcing some applications to writedata through to disk and hurts reliability for forcingapplications that care about performance to throwaway 30 seconds of data on a crash. The primaryresearch goals of this CAREER plan are 1) to enablememory to reliably store permanent data even in thepresence of operating system or database errors; and2) to measure how often software faults corruptmemory, both with and without extra protection.

The primary education technique of thisCAREER plan is relation instruction: spending timeand effort relating with students personally. Thisplan suggests several simple ways, such as grouplunches, to do this effectively with large,undergraduate classes; prior experience attests tohow caring for students in a personal mannermotivates them to learn.

StateUniversity of New York - Geneseo; Rong Lin:Reconfigurable Architectures with Shift Switching for NovelParallel Arithmetic Schemes; (MIP-9630870); $110,370; 36months.

This research will investigate a novel VLSIarithmetic design approach using reconfigurablearchitectures with shift switching, aimed at achievingan innovative design methodology which could leadto a substantial improvement on both speeds andareas for several arithmetic devices including parallelcounters, parallel compressors, parallel multipliers,precharged CMOS adders/comparators, prefixparallel counters, as well as elementary functionevaluations. The proposed technique will employenhanced reconfigurable buses, i. e. busescontaining shift switches with buffers properlyinserted. It possesses the following new features. First, when specified digital signals are propagatingthrough shift switching buses, the desired modulooperations can be performed directly, whichsimplifies the traditional model of this basicarithmetic computation. Second, after passingthrough each shift switch, the state signals areinverted alternatively in two mutually inverted forms(n and p), which minimizes the load of transistorsand maximizes the speed of circuits. The researchwill focus on the development of enhancedreconfigurable bus-based VLSI schemes forimportant arithmetic operations. The goals are to

investigate:1. shift switching parallel compressors and

conditional compressors;2. efficient partial product reduction schemes; 3. application-specific array processors for

realization of some optimal arithmeticalgorithms;

4. various shift switching parallel counter schemesand their applications; and

5. shift switching with precharge CMOS dominologic and its applications in designing arithmeticdevices and asynchronous arithmetic devices.

Pennsylvania State University; Chita R Das:Application-Driven Network Performance Evaluation;(MIP-9634197); $224,496; 36 months.

Prior research on multiprocessor interconnectionnetworks has primarily focused on the networktopology, switching mechanism, and message routingalgorithm to maximize network performance. Verylittle work has been done to study the impact of thecommunication properties of parallel applications. Communication pattern, message generationfrequency, and message size are the three attributesto quantify any communication. The proposedresearch is aimed at characterizing thesecommunication workloads and analyzing their impacton multiprocessor performance.

The research has two major phases. In the firstphase, traffic profiling of a wide range of parallelapplications will be conducted by collectingexecution traces from parallel machines and alsofrom an execution-driven simulator. Thecommunication traces will be analyzed to determinedifferent types of traffic patterns, rate ofcommunication, and volume of communication. Thesecond phase of the project will use these realistictraffic properties for the performance analysis ofinterconnection networks via simulation and analyticmodels. In-depth simulation of known unicast andcollective routing algorithms on various topologieswill be performed with these workloads. Analyticalmodels capturing wormhole switching, virtualchannel flow control, routing mechanism and therealistic workloads will be developed. The maincontribution of the project is characterizingapplication workloads to be used for differentarchitectural and algorithmic research. For example,evaluation with these workloads will quantify theactual performance advantages of adaptive routingalgorithms, will identify the potential bottlenecks ofexisting communication mechanisms, and willprovide insight for developing application-specificrouting algorithms. Next, the new mathematicaltools will be more accurate in predicting the realistic

28 Computing Systems Research

communication traffic. The techniques and toolsdeveloped in this research can be used in understanding and evaluating the interplay between parallelarchitectures and algorithms to maximize theperformance of existing machines and to designbetter machines in the future.

Pennsylvania State University; Ali R Hurson: Research inMultithreaded Dataflow and Hybrid Architectures;(MIP-9622836); $161,997; 36 months.

The overall objective of the research is theinvestigation of architectural features forcost-effective, mainstream computing based onmultithreading. In this vein, this research will focusin two directions; investigation of multithreadeddataflow paradigm, and the adaptation of the resultsto hybrid dataflow-von Neumann architecture. Thedataflow model is ideally suited for multithreadedarchitecture since it facilitates instruction levelcontext switching and fine-grained parallelism. Aclear understanding of the issues in supportingmultiple threads in dataflow environment will permitus to adapt them to hybrid dataflow/control flowarchitectures. Hybrid systems present the mostinteresting opportunities in the area ofmultiprocessing - they directly address problems thatwill be faced by future superscalar processors, suchas long memory latencies, context switchingoverheads, multiple active instruction streams, fastand efficient support for task synchronization.

Initially, this project will investigate the use ofcache memories for multihreaded dataflowarchitecture, and compiler techniques for improvingthe performance of such machines. This project willthen study architectural support for multithreadingincluding support for thread management, threadscheduling, communication and synchronizationamong threads. Simultaneous multithreading in thecontext of dataflow and hybrid architectures will thenbe investigated. Finally, this project will explore thesuitability of the most significant architecturalfeatures for use with convectional RISC technology.

Texas A & M University; Laxminarayan N Bhuyan:Cache Coherence in Wormhole Networks; (MIP-9622740);$85,960; 12 months.

This project is investigating the use of wormholenetworks in supporting cache- coherentmultiprocessors. Cache coherence gtraffic,characterized by fixed length messages that arrive in

bursts, is generated by an execution-driven simulator. This traffic is used to evaluate alternative messagescheduling schemes, adaptive routing schemes,virtual channels, and interface designs. Newcoherence and synchronization schemes are beingdeveloped and evaluated as part of this research.

The project is divided into three phases. In thefirst phase the effect of congestion in theinterconnection network in performane ofcache-coherent multiprocessors is being investigated. The second phase emphasizes the development oftechniques to reduce cache coherence traffic andinvalidation time. The third phase is thedevelopment of new protocols that use wormholenetworks effectively.

University of Texas - Arlington; Krishna M Kavi, BehroozShirazi: Research in Multithreaded Dataflow and HybridArchitectures; (MIP-9622593, A001); $120,496; 12 months.

The overall objective of the research is theinvestigation of architectural features forcost-effective, mainstream computing based onmultithreading. In this vein, this research will focusin two directions; investigation of multithreadeddataflow paradigm, and the adaptation of the resultsto hybrid dataflow-von Neumann architecture. Thedataflow model is ideally suited for multithreadedarchitecture since it facilitates instruction levelcontext switching and fine-grained parallelism. Aclear understanding of the issues in supportingmultiple threads in dataflow environment will permitus to adapt them to hybrid dataflow/control flowarchitectures. Hybrid systems present the mostinteresting opportunities in the area ofmultiprocessing - they directly address problems thatwill be faced by future superscalar processors, suchas long memory latencies, context switchingoverheads, multiple active instruction streams, fastand efficient support for task synchronization.

Initially, this project will investigate the use ofcache memories for multihreaded dataflowarchitecture, and compiler techniques for improvingthe performance of such machines. This project willthen study architectural support for multithreadingincluding support for thread management, threadscheduling, communication and synchronizationamong threads. Simultaneous multithreading in thecontext of dataflow and hybrid architectures will thenbe investigated. Finally, this project will explore thesuitability of the most significant architecturalfeatures for use with convectional RISC technology.

Computing Systems Research 29

University of Washington; Arun K Somani: Extent andEffects of Error Propagation and Recovery Mechanisms inCache Memory Systems; (MIP-9630058); $180,000; 36months.

Commercial microprocessor systems are beingoperated at higher and higher clock rates. Fasterclocks impact the time that is available to fetch datafrom cache memory, and increases the probability oftransient error occurrence in cache memory systems. Besides data reading error, an error may also occur inthe processor subsystem, and it may write erroneousdata into the cache memory. Error-correcting codesallow detection and recovery from some of theseerrors within the code word limits. Fast error

detection allows damage containment and reduces therecovery time, which otherwise could be very expensive intime. The goals of this project are: (1) to study the extent oferror propagation due to transient faults in computer systemwhen a fault originates either in a processor register or a cachelocation; and (2) to develop techniques and hardware supportneeded for early detection and recovery from such errors incomputation tasks with low overhead and low performanceloss. The proposed techniques will cover a broad spectrumfrom only detection to full error recovery. This research willidentify architectural features which, when provided incommercial microprocessors, will make them suitable for usein fault-tolerant applications. The intent is to keep theperformance impact in the normal operation to a minimal.

Other

Princeton University; Douglas W Clark: Workshop onCritical Issues in Computer Architecture Research, May 21,1996, Philadelphia, Pennsylvania; (MIP-9634380);$19,835; 6 months.

The last decade has seen extraordinarytechnological, intellectual, and market developmentsthat have shifted many assumptions underlyingresearch in computer architecture. Promisingavenues for future research will doubtless lead indirections different from those of the past. Thisproject will convene a group of approximately 15experts from industry and academe, who will discussthis and related issues in a one-day workshop. Theproposed date is May 21, 1996, the day before thestart of the ACM/IEEE international ComputerArchitecture Symposium to be held in Philadelphia,PA. The product of the workshop will be a finalreport published on the World Wide Web.

Signal Processing Systems 31

Signal Processing Systems(Formerly Circuits and Signal Processing)

Dr. John H. Cozzens, Program Director(703) 306-1936 jcozzens@nsf.gov

www.cise.nsf.gov/mips/CSPhome.html

The Program

The Signal Processing Systems (SPS) program supports basic research in the areas of digital signal processing, analog signalprocessing, and supporting hardware and software systems. This research is typically driven by important applications and emergingtechnologies. Signal processing is a highly active research area, with topics ranging from theory to Very Large Scale Integrated(VLSI) circuit implementations and applications. Although signal processing is typically driven by advances in technology,discoveries in this field also serve as a catalyst for new technological innovations. A taxonomy of research areas, based on signalcharacteristics, applications, and/or technology, include:

One-Dimensional Digital Signal Processing (1-D DSP) - the representation of time-varying signals (e.g., audio, EKG,etc.) in digital form, and the processing of such signals;& (adaptive) filtering and equalization& filter design, theory, and analysis, both linear and nonlinear& multirate processing and wavelets& time-frequency representations

Statistical Signal and Array Processing (SSAP) - the use of statistical techniques for the processing of signals thatmay arise from multiple sources;& cyclostationary signal processing& higher order statistics& (statistical) array processing& nonstationary and time-frequency

Image and Multi-Dimensional Digital Signal Processing (IMDSP) - the acquisition, manipulation, and display ofmulti-dimensional data using digital technology;& image analysis, filtering, restoration, and enhancement& image and video coding& vector quantization

Analog Signal Processing (ASP) - the processing of data without conversion to sampled-digital form;& analog-to-digital conversion& analog circuits and filters

Other research areas delineated in the SP EDICS listing that are selectively supported by this program are:& Underwater Acoustics Signal Processing - & VLSI Signal Processing - & Emerging Techniques -

Signal Processing Systems 33

Awards

Analog (Mixed Analog/Digital) Signal Processing

University of California - Berkeley; Paul R Gray, RobertG Meyer: Research in High-Frequency Analog ElectronicCircuits for Communication Systems; (MIP-9412940A001); $136,403; 12 months.

The field of electronic telecommunicationshas experienced explosive growth in the past tenyears, both in terms of its commercial importance andin terms of the research effort devoted to it inacademic and industrial laboratories. It appears thatradio-based digital communications will play a muchlarger role than might have been anticipated,complementing data communications on wire pairswith fiber media which are coming into increased usefor data communications backbones. As in the past,reducing the cost of electronics associated with VLSItechnology will be critical.

This research is directed at exploring new waysto use silicon integrated circuit technology toimprove the performance, reduce the powerdissipation, and reduce the cost of components forcommunication systems of various kinds. Theprimary emphasis of this research is on datacommunications and Personal CommunicationsSystems (PCS) using radio and free-space opticalmedia. Particular emphasis is placed on circuittechniques applicable to implementation of RF, IFand baseband mixed signal communications circuitswith low power and low operating voltage. Specifictopics for investigation are: limits-to-phase noiseperformance in power-optimized monolithic voltage-controlled oscillators; investigation of new parallel-architecture sampling demodulators; limits-to-distortion performance in MOS samplingdemodulators; the use of passive-sampling FIRswitched capacitor filters for low-power, high-frequency filtering and CDMA despreading;optimization of the sensitivity in fiber opticcommunication receivers; the application ofBiCMOS technology for the particular needs of high-speed communications; and modeling of active andpassive IC components for RF design.

Harvard University; Woodward Yang: NYI: VLSI Designfor High Performance Signal Processing and Computation;(MIP-9257964 A004); $62,500; 12 months.

The focus of this research is on the developmentof innovative VLSI design methodologies that willfacilitate the next generation of high performancesignal processing and computing systems. A varietyof analog, digital, and mixed signal circuitry will beimplemented for use in high performance computingapplications including object recognition, smartsensors, adaptive neural networks, and programmableanalog filters.

Northeastern University; Lisa McIlrath: CAREER:Development of a New Program in Integrated AnalogSystems Design at Northeastern University; (MIP-9623907);$210,000; 48 months.

The focus of this Career Development plan is thedevelopment of a new broad-based program in thedesign of integrated analog systems at NortheasternUniversity. The research component of this planinvolves the development of analog processingcircuits to be used in integrated circuits containingarrays of sensors or display elements. The mainfocus of this research is on applications related toelectronic imaging. The two main thrusts are;1. to develop high quality imaging arrays with

CMOS technology, and,2. to devise focal-plane computational imagers for

extracting useful information from the imagedata.The functions performed by the focal plane

processors, which include temporal and spatialdifferencing and spatial filtering, will haveapplications in fields ranging from imagecompression and enhancement to machine visionproblems such as tracking and inspection.

The educational component of this planaddresses the need to interest and train moreengineers in the field of analog design. The majorinitiatives of this plan include developing anextended analog design project for second and thirdyear undergraduates; incorporating moreundergraduates into on-going research; creating aseminar series bringing outside speakers on campus

34 Signal Processing Systems

to increase students' awareness of the importance ofanalog design in real world systems; and developingan advanced graduate course in analog systems aimedboth at our graduate research students as well as atengineers in industry who need to deepen theirunderstanding of design principles and techniques.

Washington State University; Terri S Fiez: NYI: HighPerformance Analog Signal Processing for Mixed-ModeIntegrated Circuits; (MIP-9257112 A003); $125,000; 24months.

The focus of this research is the development ofhigh performance analog architectures and circuitsfor mixed analog-digital IC's. Emphasis is placed on

improving the immunity of the analog circuits to digitalswitching noise and in obtaining accurate, high speed analogcircuit performance with the newly emerging 3.3 Volt powersupply standard. (Current-mode circuits will be examined asa way of overcoming these limitations and this research willyield a general understanding of the advantages andlimitations of current-mode circuits as compared tovoltage-mode circuits. The current-mode circuits will be usedto implement area efficient, high-order sigma-delta A/Dconverters.)

One-Dimensional Digital Signal Processing

University of California - San Diego; James R Bunch:Stability of Algorithms in Signal Processing;(MIP-9625482); $131,830; 36 months.

The method of Least Squares has been employedsuccessfully to solve problems in many scientificdisciplines, including signal processing. The classof fast Recursive Least Squares Algorithms wasintroduced in order to address certain desirableperformance traits, such as computationalcomplexity, tracking, and misadjustment. Althoughthese algorithms have evolved over many years andare widely used in signal processing, a commonapproach addressing the issue of algorithmic stabilityhas been lacking. This research provides an analysisthat fills this critical void in the research anddevelopment of these algorithms. Descriptivedefinitions of stability are being examined which areconsistent with current and previous algorithmicanalyses. The effects of the forgetting factor - theextent to which prior information is weighted - withrespect to matrix perturbation theory and the controland propagation of arithmetic roundoff errors arebeing studied. This research is also providing usefuland insightful gains in the important areas of filtermisadjustment, filter tracking, the conditioning of theauto-correlation matrix, and the usefulness of thefilter output.

This research program joins the science ofNumerical Analysis with the science of SignalProcessing, providing tools by which algorithms forsignal processing can be better designed and used, sothat they will give more accurate results.

University of Delaware; Gonzalo R Arce, Neal CGallagher: Weighted Myriad Filters and Their Applicationsin Communications; (MIP-9530923); $105,013; 12 months.

Linear Filtering theory has been largelymotivated by the characteristics of Gaussian randomprocesses. In the same manner, research in myriadfiltering theory is motivated by the statisticalproperties of alpha-stable processes which describean important class of processes, impulsive in nature,that obey a Generalized Central Limit Theorem; thusthese processes can arise in practice as a result ofphysical principles. The foundation of myriadfiltering algorithms lies in the definition of thesample myriad as the location estimate of a class ofalpha-stable distributions. The main goals of thisresearch are;1. To study the theoretical properties of the sample

myriad and to exploit its geometrical structurefor the development of efficient computationalalgorithms,

2. To solve the optimal "weighted myriad" filteringproblem - the problem analogous to the design ofthe optimal FIR (Wiener) filter and the optimalweighted median filter,

3. To develop adaptive filtering algorithms for thesimple design of weighted myriad filters forapplications where the statistical characteristicsof the underlying signals may be unknown orvarying, and,

4. To extend the filter formulation to the casewhere the signals are complex or multivariate,providing us with the tools needed to developrobust CDMA multiple access detectors. This work can have a significant impact on

applications requiring robust estimation and filtering. This is particularly the case in mobile and personal

Signal Processing Systems 35

communication systems, to be deployed in the nearfuture, where the underlying statistics of the noiseand interferences closely follow the models used inthis research rather that the traditional models used inpractice today. The results of this research can alsobe applied to a wide range of problems includingremote sensing imaging of the environment andnon-destructive evaluation of materials.

Ohio State University; Peter Clarkson: Robust ParameterEstimation in the Detection of Cardiac Arrhythmias;(MIP-9220769 A002); $79,637; 12 months.

This research is concerned with improving theefficiency and robustness of parameter estimationschemes employed by implantable and portabledevices for cardioversion and defibrillation. Thegoal of the research is to replace the ad-hocestimation schemes used in present generationdevices by robust estimators that produce optimalminimum variance estimates for a wide range ofunknown error distributions, and which maintainclose-to-optimal performance in the presence ofparameter fluctuations. These objectives arepursued through estimation schemes that are basedon the application of Order Statistic (OS) operationsto the data.

Carnegie-Mellon University; Virginia L Stonick: PYI:Practical Approaches to Optimal Adaptive Filtering of RealTime Non-Linear Systems; (MIP-9157221 A008); $47,500.

This research addresses the use of numericaloptimization methods to develop real-time adaptivefilters for estimating, identifying, or predictingtime-varying and potentially nonlinear processes. The first phase of this work will be devoted to thedevelopment, analysis, and simulation of an optimaladaptive infinite-impulse response (IIA) filteringalgorithm for telecommunications using homotopycontinuation methods to perform the necessarynonlinear optimization. This research will increaseour understanding of IIA filter structures in time-varying environments, and will ultimately lead totheir more widespread use.

Drexel University; Athina P Petropulu: PFF: SignalReconstruction and Applications to Communications,Ultrasound Image Processing, and EarthquakeEngineering; (MIP-9553227, A001); $105,000; 12 months.

The goal of the project is twofold: research inthe area of signal reconstruction, and teaching insignal processing, both components emphasizing theinterdisciplinary aspect of signal processing. Themain thrust of the research is the reconstruction of asignal with unknown statistical description thatpropagates through a system with unknown

characteristics, solely from the system's output (blinddeconvolution). Higher Order Statistics arepowerful mathematical tools being employed in thisproblem, capable of revealing a wealth ofinformation about the signal/process (e.g., phase,presence of nonlinearities), and at the same timesuppressing noise. The theoretical developments ofthis work will be applied in the areas of digitalcommunications, medical diagnostics and earthquakeengineering, and are expected to bring newknowledge to these fields. In the area of teachingthe goal is to develop and maintain a new systemscurriculum, highlighting principles that unitedifferent engineering disciplines. Towards this goal,a state-of-the-art multimedia signal processinglaboratory will be developed, and new courses willbe designed.

University of Pittsburgh; Patrick Loughlin; CAREER: Joint Density-Based Methods of Applied NonstationarySignal Processing; (MIP-9624089); $205,000; 48 months.

While the Fourier transform is an indispensabletool in signal processing and Linear Time-Invariant(LTI) systems analysis, as well as a staple of theelectrical engineering curriculum, many natural andman-made processes are not time-invariant but rather exhibit frequencies that change over time (e.g., FMcommunication systems, the Doppler effect, speechand other biomedical signals). The conventionalshort-time, or "quasi-stationary," extensions of LTIconcepts for studying such processes is ofteninadequate; for example, depending upon theshort-time analysis interval length selected,dramatically different results can be obtained for the same process, particularly when the signal containsboth transients and harmonics. Accordingly, there isa need, both in engineering practice and pedagogy,for the development of new methods for time- varying (or nonstationary) signal processing. Thisresearch involves the development and application ofa general method of nonstationary signal processingthat surmounts the limitations of methods based onthe extension of LTI concepts to time-varyingsituations. The principle objectives of this research are to:1. Develop new joint density-based methods for

nonstationary signal processing (e.g., scale);2. Apply these new methods to challenging,

practical problems in biomedical signal analysisand machine health monitoring (which fall underthe biotechnology and manufacturing FederalStrategic Areas); and,

3. Develop a general educational framework fornonstationary signal processing based on thenew methods, via new instructional laboratorycourses and research opportunities for collegeundergraduate and graduate students.

36 Signal Processing Systems

William Marsh Rice University; Richard G Baraniuk:NYI: Signal Analysis and Processing in MatchedCoordinate Systems; (MIP-9457438 A002); $62,500; 12months.

This research aims to extend current methods oftime-frequency and time-scale analysis by developinga general theory for signal analysis and processing inalternative coordinate systems. Specific tools under

investigation include optimal, signal- dependenttime-scale representations, information measures fortime-frequency and time-scale analysis, andoperator-based, generalized coordinate systems. Test signals are being drawn from problems inmachine health monitoring, magnetic resonanceimaging, and dispersive signal processing.

Image and Multidimensional Digital Signal Processing

Stanford University; Robert M Gray, Richard A Olshen:Tree-structured Image Compression and Classification;(MIP-9311190 A004); $80,054; 12 months.

Tree-structured vector quantization is anapproach to image compression that applies ideasfrom statistical clustering algorithms andtree-structured classification and regressionalgorithms to produce compression codes that tradeoff bit rate and average distortion in a near optimalfashion. This research is examining the explicitcombination of these two forms of signal processing,compression and classification, into singletree-structured algorithms that permit a trade offbetween traditional distortion measures, such assquared error, with measures of classificationaccuracy such as Bayes risk. The intent is toproduce codes with implicit classificationinformation, that is, for which the stored orcommunicated compressed image incorporatesclassification information without further signalprocessing. Such systems can provide direct lowlevel classification or provide an efficient front endto more sophisticated full-frame recognitionalgorithms. Vector quanitization algorithms forrelatively large block sizes are also being developedwith an emphasis on multiresolution compressionalgorithms. In order to improve the promisingperformance found in preliminary studies orcombined compression and classification, it will benecessary to use larger block sizes or, equivalently,more context. Multiresolution or hierarchialquantizers provide a simple and effective means ofaccomplishing this. Other related issues are beingexplored, including improved prediction methods forpredictive vector quantization and image sequencecoding.

University of California - San Diego; Pamela C Cosman:CAREER: Multiresolution Region-Based ImageCompression; (MIP-9624729); $222,500; 48 months.

Image Compression reduces the number of bitsrequired to represent an image, and thereby allowsimage and video information to be stored moreefficiently, or to be transmitted much faster from oneplace to another. Some compression methodsdegrade the quality of the image. The researchportion of this CAREER plan involves designingcompression methods which examine the content ofan image in order to control or eliminate thedegradation for some portions of the image. Theintent is to increase the visual quality or scientificutility of the images. This work also involves thedesign of multiresolution methods for region-basedimage and video compression, and the developmentof novel methods for quality evaluation for suchcodes. Dividing an image into regions can allow acompression algorithm to employ different encodingstrategies in different portions of the image, and canallow some regions to be represented at higherquality or finer resolution than others. Methods forsegmentation, bit allocation, and code selection atdifferent levels of resolution will be examined in thecourse of our investigations.

The main objects of the education plan are topromote interactive and hands-on learning, to behighly accessible and supportive to students whom Iadvise, and to facilitate interdisciplinary as well asacademic/industrial discourse.

Signal Processing Systems 37

Georgia Institute of Technology; Ronald W Schafer, S. JMcGrath, Mark A Clements, James H McClellan,Thomas P Barnwell: Infrastructure and Research Programfor Signal Processing in Multimedia Systems;(MIP-9205853 A006); $171,177; 12 months; (Supportfrom: Signal Processing Systems Program, CISEInstitutional Infrastructure - Total Grant $295,895).

The objective of this proposal is to establish aninfrastructure for signal processing in multimediasystems. Equipment will be acquired, installed, andintegrated into an existing research environmentconsisting of networked UNIX workstations andminicomputers. This equipment will provide thecapabilities to acquire multimedia signals, includingimage, video, speech, audio, text, and fax; store andaccess these signals on high-speed, high-capacitydisk storage subsystems; process them using customhigh-speed, real-time, DSP microcomputer-basedprocessors, hosted by UNIX workstations;communicate a variety of these signals betweenworkstations over a high-speed fiber network; andoutput the processed signals at their intendeddestinations. Special-purpose systems - an HDTVworkstation, and a custom DSP multiprocessor - willbe integrated into the infrastructure to allow forreal-time processing of high-resolution videosequences and images. The goal of thisinfrastructure is to build an environment in which theDSP algorithms, which will play a major role in thegrowth of multimedia technology, may be developedin such a fashion as to lead directly to real-timeimplementations of those algorithms. Thecompanion part to this infrastructure is a program ofresearch based on this environment, to be conductedin areas with immediate and urgent application to theproblems facing multimedia information systems. This includes real-time video encoding, concentratingon the problems of inter- and intra-frame redundancyelimination. Advances in this area will lead toaffordable applications in a host of areas such asvideo mail, video messaging, real-time videocommunications, and interactive learning andpresentations.

University of Illinois at Urbana -Champaign; YoramBresler: PYI: Statistical Techniques in Inverse Problems;(MIP-9157377 A004, A005); $100,000; 12 months.

This research falls into four broad areas: imagereconstruction, reconstruction of time-varyingdistributions, sensor array processing, andvisualization of multiparameter data. In the area ofimage processing, the principal objective is todevelop the theory and associated computationalalgorithms for superresolution image reconstructionfrom partial and noisy data, using statistical models. For the second area, the goal is to develop optimumsignal acquisition schemes subject to physical oreconomic constraints, and the associated efficientreconstruction algorithms, for imaging spatial datathat is time varying during the acquisition process. In the area of sensor area processing, several issuesare being addressed including the design ofcomputationally efficient algorithms for the(sub)optimal solutions of model fitting problems,wideband source location, and imaging with sensorarrays. Finally, in the last area, the goal is to addressthe effective fusion, display, and visualization ofmulti-parameter spatially-related data, such as isacquired in multispectral, or multi-modality remotesensing and diagnostic imaging.

University of Illinois - Urbana-Champaign; Michael TOrchard: NYI: Optimal Motion Compensation for VideoCompression; (MIP-9357823 A003); $62,500; 12 months.

Efficient compression of video sequences shouldexploit the high interframe redundancy due to thesmoothness of motion fields in typical scenes. Current video coding algorithms use very simplisticmotion models, limiting the degree to which motion-induced redundancy can be exploited in videocoding. This research is investigating improvedmethods for estimating motion in video sequences,and compensating for that motion to achieveincreased coding efficiency. Methods are beingconsidered which estimate motion at the encoder,requiring transmission of motion overhead, and thosewhich estimate motion directly at the decoder. Thegoal is to provide a unifyied framework for these twoapproaches to motion estimation, and to develophybrid algorithms taking advantage of the bestfeatures of both approaches.

38 Signal Processing Systems

University of Notre Dame; Ken D Sauer: Model BasedTomography: A Comprehensive Approach to IterativeImage Reconstruction; (MIP-9300560 A002); $70,201; 12months.

Low dosage transmission medical imaging,emission medical imaging, and nondestructive testingof materials are all examples of tomographicreconstruction problems which can benefit greatlyfrom improved reconstruction techniques. Thisresearch introduces a strategy for the development ofcomputationally efficient reconstruction algorithmswhich directly search for the statistically optimal fitto measured data. This approach exploits the wideavailability of digital computation and storage tosubstantially improve reconstruction in demandingapplications. The research has three essentialcomponents;1. a general measurement system model which

characterizes the physical measurementapparatus for both the transmission and emissionproblems, and can be extended to includenonlinear effects such as scattering,

2. a new class of computationally tractable imagecross section models which preserves imagedetail while suppressing noise artifacts, and,

3. A fast numerical algorithm, known asGauss-Seidel, which serves as a basis forefficient and accurate multiscale reconstructionmethods.Algorithmic techniques are being evaluated

using data collected from the NondestructiveEvaluation Section at the Lawrence LivermoreNational Laboratories.

Johns Hopkins University; Jerry L Prince: PFF:Three-Dimensional Image Processing; (MIP-9350336A002); $100,000; 12 months.

This program has two major components:research and teaching in image processing, bothhaving a focus on three-dimensional data. Theresearch component is divided into two major thrusts:1. the development of new methods for estimating

motion in three dimensions fromthree-dimensional data sets. The first aiminvolves optimizing data acquisition methodsgiven a prior stochastic description of the motionand assuming the use of a certain optical flowmethod. The second aim explores the theory ofthree-dimensional vector tomography and itsimplementation using a magnetic resonancescanner.

2. The estimation of shape from three- dimensionaldata sets. This topic focuses on active surface

methods: the definition of new active surfaces,the algorithms and their convergence properties,and the use of active surface methods for 3-Dimage registration. The teaching component of this grant has two

main objectives:1. to develop a state-of-the-art signal and image

processing laboratory, and,2. to develop new courses and textbooks on image

reconstruction.The overall goal is to provide a comprehensive

educational program at the cutting edge of signal andimage processing

Northeastern University; Eric Miller; CAREER: AnIntegrated Approach to the Study of Inverse Methods inElectrical Engineering; (MIP-9623721); $204,092; 48months.

The objective of this CAREER award is todevelop a fully integrated career plan designed tomeet the educational needs of students in theElectrical and Computer Engineering (ECE)Department of Northeastern University. Theunderlying theme behind all aspects of this work isthe study of inverse problems, a topic which is allbut absent at the undergraduate level and not oftenconsidered even in the graduate school despite theubiquity of these problems in many fields of engineering and the applied sciences. In the area ofeducations activities, two projects are envisioned. Atthe undergraduate level, a capstone design course inthe general area of signal processing is beingdeveloped and implemented. At the graduate level, acourse devoted to the study of the theoretical andpractical issues surrounding linear inverse problemsis being developed. In the area of research, we areexploring the use of statistical and multiscale signalprocessing methods for solving non-linearelectromagnetic inverse scattering problems. Thesealgorithms will incorporate scattering models based upon a Green's function formulation of the vectorHelholtz equation. A statistically-based,multi-grid-type algorithm for extracting image andtarget information (number of targets, locations, andclassifications) is being developed. Theincorporation of detailed, physical models directlyinto the data processing algorithms makes thesetechniques directly applicable to a wide range ofproblems including radar signal processing for imageformation and target detection/ classification, remotesensing, microwave medical imaging, and geophysical exploration.

Signal Processing Systems 39

Medico-Technological Research Institute; John J Wild:Detection of Differential Sonic Energy Reflection by SoftTissues; (MIP-9634543); $49,950.

The objective of this work is to provide acapability of obtaining a significantly increasedresolution for abnormal foci (tumors and knots) incellular biological tissues by ultrasonic detection. An ultrasonic transducer array with specialelectroding is being designed, tested and its operationevaluated. This work will look at the electrodepatterns and the measurement of the actual beamcharacteristics using a biological phantom. Electronic circuitry is being developed for increasedsensitivity in data acquisition and detection.

Stevens Institute of Technology; Alan L Stewart, Roger SPinkham: Self-Adjoint Operators and Models ofSpace-Variant Visual Acuity; (MIP-9405081 A003);$78,524; 12 months.

Current theories of visual processing are theoriesof local responses. Even models of space-variantacuity concentrate on properties of the local receptivefields, with the rationalization that the visual systemis approximately homogeneous within any smallneighborhood. The response of the entire visualfield is pieced together from models of localresponses.

The theory of integral operators allows theexperimentla study of human acuity to be united withcomputational model is visual processing. Their usein this context leads to simpler and more intuitiveproofs of key theorems which relate thresholdassessment to eigenvalue problems. At the sametime, everyday experimental concepts, such asthreshold sensitivity, take on new elegance whenplaced within the theory of integral operators.

Rensselaer Polytechnic Institute; William A Pearlman:New Techniques for Audio, Image, and Video Compression;(NCR-9523767); $184,546; 36 months; (Support from:Signal Processing Systems Program, CommunicationsResearch, Network Infrastructure - Total Grant$369,092).

The goal of this research is to investigate moreeffective techniques for digital audio, image, andvideo data compression. For audio, the intention isto employ more efficient entropy-constrained,conditional and unconditional, quantization in thecoding of the critical subbands of the MPEG audiostandard. The dependence of the subbands is nextexploited using set partitioning in hierarchical trees(SPIHT) as done originally in embedded, wavelet,zerotree coding of images. The resulting embedded

coding allows delivery of different qualities ofservice with a single compressed bit stream. Anewly developed SPIHT procedure, which obtainedprobably the best-to-date monochrome, still imageresults (lossy or lossless) and with extremely fastencoding and decoding, is utilized for audio and alsofor color image and video coding. The extremelyfast execution of the SPIHT coding procedure makesit especially suitable for video, where a requirementof real-time coding becomes an insurmountableobstacle for other procedures. Both lossy andlossless coding are investigated, as they fit naturallyinto the SPIHT framework. Other investigationsinvolve the use of information theoretic criteria tocreate optimal adaptive subband compositions andthe use of trellis coded quantization (TCQ) in blockdiscrete cosine transform (DCT) and lappedorthogonal transform (LOT) coding.

Rensselaer Polytechnic Institute; Badrinath Roysam;Real-Time Processing and Multi-Spectral ImagingEquipment for Intraocular Image Processing; (MIP-9634206); $21,521; 6 months.

This research involves two components. Thefirst component is an extension of prior work underNSF grant MIP-9412500 on the development ofalgorithms for automatic generation of retinalvasculature maps, and real-time feature-based determination of retinal position from intra-oculardigital video image sequences. Specifically, aTMS320C80 video signal processor chip will be used to achieve fully transparent image tracking byreducing the time required to establish a trackinglock to a small number of video frame intervals. Thesecond component to this research is to modify thefundus imaging system acquired under the previousaward to achieve simultaneous imaging in the nearinfrared and visible bands using a pair of low-lightvideo cameras. This instrumentation will be used toinvestigate real-time algorithms for artificiallysuperimposing computed vasculature landmarks onlate-phase Indocyanine Green angiograms. Thisresearch will result in the development of real-timeimage processing hardware and software technologyfor enabling the development of novelinstrumentation for laser retinal surgery and relatedapplications. It is motivated by the need to reducethe currently high failure rate (approaching 50%) ofcurrent procedures. This project is an application ofhigh-performance computing technology to enablenew advances in ophthalmology and related problems in biology and medicine. In addition to reducing thefailure rate, this technology is expected to reduce thecost of laser retinal surgery by eliminating the needfor repeated corrective procedures.

40 Signal Processing Systems

Rensselaer Polytechnic Institute; John W Woods: MotionCompensated Object Based Video Coding; (MIP-9528312);$119,126; 12 months.

This research program investigates an advancedvideo compression approach for applications such asmultimedia, video on networks, video conferencing,and video on demand. It is a novel combination ofobject-based coding usually used for very low ratesand 3-D subband/wavelet waveform-based coding,usually reserved for higher rates.

In this method, the motion field is firstsegmented into objects which make up the imageframe, and move at different velocities. Theboundaries of these objects are coded using a type ofcontour coding which preserves the shape of theedge. This contour coding is performed as an updateon the object boundaries found for the previousframe. Finally the interior of these space-timeobjects is coded using the waveform coding methodbased on motion compensated 3-D subband filtering. The overall goal is an efficient unified set of videocompression algorithms scalable from video phoneup to HDTV.

Rochester Institute of Technology; Edward R Dougherty:Model-Based Design of Optimal Nonlinear Filters forBinary Images; (MIP-9520139); $55,240; 12 months.

All translation-invariant binary image filterspossess morphological representations. Hence,finding an optimal filter involves finding thestructuring elements that yield a filter havingminimum error - in our case, mean-absolute error(MAE). This observation leads to automated designprocedures for restoration and enhancement filterswhen treating both the observed (corrupted) and idealimages as random set processes. A key designaspect is postulation of image models for the idealand observed processes. This research concernsfilter robustness relative to modeling assumptions: towhat degree is filter performance degraded relative todeviations from the design assumptions? Ourapproach is to assume parameterized ideal andobserved image processes and to consider the effectsof applying an optimal filter for a given parametervector to images corresponding to different parametervectors. The design of enhancement algorithms is anintegral part of the manufacture of electronic officeequipment. This time-consuming (up to a year), andperformance is limited by the ability of a humanbeing to consider only a relatively small number ofpossible algorithms. Recently, enhancementalgorithms have been automatically designed byhigher-level algorithms that use statistics inconjunction with mathematical models of images and

imaging systems, thereby significantly cutting designtime while at the same time producing betterenhancement. The present research investigatesdesign from various image models. It also addressesthe "robustness" question: since a designedenhancement algorithm is based on modelingassumptions, practical application requires that wehave a reasonable idea of how it will perform onimage data that differs to varying degrees from thedata on which it has been designed.

University of North Dakota; Richard R Schultz:CAREER: Integration of Image Processing Education andResearch; (MIP-9624849); $225,690; 48 months.

The research component of this program has twomajor thrusts:

1. an investigation of the mathematical andcomputational aspects of the multiframe, bilinearimage- recovery problem; and

2. the development and application of solutions forproblems in the areas of high-resolutiontransmission electron microscopy, and ground-and space-based astronomy.Theoretical advances in this program are

providing a unified approach to many imagingproblems in which intensity data are recorded,including those for which satisfactory solutions havenot been previously discovered. Collaborations withmaterials scientists on problems such as the study ofatomic scale processes in solid batteries are providingexciting applications for which new methodsdeveloped in this program are being used to enhancethe resolving and information-gathering powers ofelectron microscopes.

Through the teaching component, an educationalprogram is being established with emphasis on:1. the development of a multidisciplinary

laboratory in which faculty and students frommany departments jointly explore problems inremote sensing and imaging;

2. the development of multidisciplinary courses inremote sensing and imaging in which studentsfrom many departments are included, and theeducations goals for each student - ranging fromtheoretical foundations to specific applications -are tailored to his or her individual needs; and

3. the use of a strong research-teaching exchange inwhich cutting-edge technology is used in theclassroom and laboratory as a tool to excite,motivate, and retain enthusiasm in the students

Signal Processing Systems 41

University of Pennsylvania; Eero Simoncelli; CAREER:Visual Information Processing; (MIP- 9624855); $210,000;48 months.

This CAREER award provides support for theconstruction of a research and education program invisual information processing. This field isinherently interdisciplinary, and includes portions ofcomputer science, electrical engineering, appliedmathematics, psychology, and neuroscience. Yet,educational curricula often do not cross thesedisciplinary boundaries. One objective of thisresearch is the construction of an educationalcurriculum, starting next year with the introductionof two innovative foundational courses. The first, anundergraduate lecture course entitled "Foundations ofVision: Perception and Computation," will cover abroad range of material in vision science, fromperceptual psychology, to single-cell physiology, tocomputational theories of visual processing. Thesecond, a graduate lecture/laboratory course entitled"Fundamentals of Image Processing and ComputerVision," will cover basic tools, both theoretical andapplied, that are common to these two fields. Thesecond objective of this research is the study of a setof basic and applied research issues in visual imageprocessing. The research will be based on the familyof "steerable pyramid" image representations, andwill include the use of this representation in anadaptive context, rotation-invariant pattern matching, noise removal and enhancement, representation oftexture and orientation content, and differentialrecovery of three-dimensional scene structure.

University of Washington; Eve A Riskin: NYI: VectorQuantization Codebook Processing and Organization;(MIP-9257587 A004); $62,500; 12 months.

New ways to use Vector Quantization (VQ)other than strictly for data compression are beinginvestigated, and are being applied to applicationssuch as image processing, halftoning, progressivetransmission, and immunity against communicationchannel noise. In many applications, both VQ andmany image processing operations are applied tosmall subblocks of an image. The image processingstep can be applied ahead of time to each vector in aVQ codebook, with the processed vectors storedalong with the codebook. If the computationalcomplexity of the VQ encoder is lower than that ofthe image processing step, this reduces thecomputational complexity. This approach is beingapplied to halftoning, edge detection, and histogramequalization. In a progressive transmission system,the received image is reconstructed as an increasinglybetter reproduction of the transmitted image as bitsarrive. Ways to organize and order a VQ codebook

so that it can be used for direct progressivetransmission of full search VQ are being studied. Inan ordered VQ, the VQ codeword index is correlatedwith the codeword location in the input space. Thisordinal mapping feature of clustering codewords withsimilar indexes to obtain additional reproductionvectors for the decoder is being exploited. Extentions to progressive transmission of orderedVQ indexes over noisy communication channels arebeing included.

University of Wisconsin - Madison; Truong Nguyen; TheStructure, Design and Application of M-band SymmetricWavelets and Filter Banks; (MIP-9626563); $151,666; 12months.

The wavelet transform with symmetric basisfunctions is emerging as a next-generation standardfor still-image compression. Wavelet methodsoutperform the current JPEG standard at lowbitrates, and degrade gracefully with decreasing bitrate. The new M-channel symmetric wavelets areused in image and video coders, with particularattention to quantization strategies and motion compensation. This research is addressing the theory,design, and application of orthogonal andbiorthogonal linear-phase M-channel filter banks andM-band symmetric wavelets. Multirate filter banksare the fundamental building blocks for subband andwavelet decompositions, as well as frequency-domain/time-domain multiplexing. Theoreticalquestions being addressed by the research include thestructure of linear-phase M-channel filter banks andwavelets, including a comprehensive theory ofpermissible lengths, minimal structures for parametrization and fast computation, and mappingsfor two-dimensional signal processing. Criteria forwavelet filter design are also being addressed,including vanishing moments, smoothness andnonnegativity of the scaling function, and unequallength filters. The investigators are studyingapplications of the above to perceptually-based datacompression of image, video and seismic data,multicarrier modulation, and multiscale featuredetections. They are also investigating the use of theM-band wavelet transform for multitone modulation. The frequency partitioning properties of theM-channel filter bank enable high efficiency forchannels such as twisted-pair copper wire and hybridfiber-coax, with reduced susceptibility tonarrow-band interference.

42 Signal Processing Systems

Statistical Signal and Array Processing

Stanford University; Iain M Johnstone, David L Donoho;Mathematical Sciences: Adaptive Estimation: New Tools,New Settings; (DMS-9505151 A001); $70,000; 12 months;(Support from: Signal Processing Systems Program,Computational Mathematics, Statistics - Total Grant$190,000).

This research is developing statistical theoryand computational tools in the general area ofadaptive methods for representing and analyzingsignals, images and other objects, and is showinghow to tune them so they are noise-cognizant andstable. Underlying the approach are:1. the idea of oracles, which know perfectly well

how to ideally adapt representations;2. the idea that the goal of adaptation in the

presence of noisy data is to quantify how closelyrealizable procedures (which do not haveprivileged information about the object) canmimic an oracle; and,

3. the design of procedures coming as close aspossible to the oracle.The research is also developing methods for

comparing different adaptation schemes bycomparing oracles of different kinds, for exampletime-frequency oracles and time-scale oracles. This isan outgrowth of our earlier results on wavelets,where this approach was used to show that waveletshave a property of being nearly-ideally spatiallyadaptive. In addition a computational environment isbeing developed for implementing and systematicallytesting such approaches.

As a further outgrowth of earlier work onwavelets, a number of improvements and extensionsof wavelet shrinkage, for example in the directions ofclassification, confidence bands, correlated data andselection of orthogonal bases, are being explored.These efforts may have two spin-offs. First, some ofthe results may be stimulating and/or useful to thecommunity of "inventors of adaptive procedures" insignal, image, speech, and time/frequency, andrelated communities. Second, the theoretical workmay stimulate statisticians to take more interest inmaking further contributions in such directions.

University of Colorado-Boulder; Clifford T Mullis, LouisL Scharf; Statistical Signal Processing and CommunicationWithin Subbands; (MIP-9529050); $61,789; 12 months.

The efficient use of bandwidth for multimediainformation transmission depends on the efficient useof imperfect channels, such as coaxial cables and

optical fibers. This means redundant informationmust be removed and what remains must be codedfor reliable transmission. This research isaddressing the problems of redundancy removal(source coding) from the point of view ofmultichannel filterbanks; it is also addressing theproblem of efficiently implementing filterbanks indigital electronics.

Specifically, we are studying applications ofundersampling operators, oversampling operators,and tight frames to source coding, channel codingand halftoning. The aim of this research is todevelop efficient state variable realizations for tightframes and related maps, and to determine thecomputational complexity and performancecharacteristics of these realizations. Of particularinterest are sum of all-pass realizations formultichannel filterbanks. The results will produceinsights and design rules for implementing sourcecoders and channel coders in state variablefilterbanks that have good numerical properties.

University of Florida; Jian Li; NYI: SAR Image Formationand Processing Techniques for Environmental Monitoring;(MIP-9457388 A002); $45,347; 12 months.

This research shows the advantages of usingSynthetic Aperture Radar (SAR) to detect, analyze,and quantify environmental changes. There are threefoci.1. Improve SAR image formation with a phased

array airborne or spaceborne radar. EfficientSAR image formation techniques are beingdeveloped by appropriately designing thetransmitted waveforms of the phased array radar. The trade-offs between nonparametric andparametric techniques are being studied.

2. Research on the SAR image understanding andground truth evaluation. Statistical clusteringalgorithms and various feature extractionschemes that adequately incorporateelectromagnetic phenomena are being developedand evaluated.

3. Research on the detection, analysis, andquantification of environmental changes throughrepeated SAR imaging of critical regionsincluding the environmentally fragile Floridawetlands. Change detection techniques are beingdeveloped to quantify and document subtleenvironmental changes from these images.

Signal Processing Systems 43

Purdue University; Michael D Zoltowski; Closed-FormAngle Estimation with Circular Arrays/Apertures forMobile/Cellular Communications and Surveillance Radar;(MIP-9320890 A002, A003); $28,770.

The digital communications industry is currentlyinvesting enormous resources towards thedevelopment and experimental verification ofprototype antenna arrays to be deployed on mobilecommunication vehicles, including the commercialautomobile of the future, as a means ofdiscriminating amongst signals co-located infrequency based on their respective spatial locations. Given the small aperture on a mobilecommunications unit, the Uniform Circular Array(UCA) geometry is ideal due to its rotationalinvariance with respect to azimuth. This research isbased on a recent development of a simple, closedform algorithm, UCA-ESPRIT, for use inconjunction with a UCA that provides automaticallypaired source azimuth and elevation angle estimates. To date, the algorithms for 2D arrival-angleestimation have required expensive spectral searches,iterative solutions to multidimensional optimizationproblems, or ad-hoc schemes for pairing directioncosine estimates with respect to each of a number ofdifferent array axes. UCA-ESPRIT is fundamentallydifferent from ESPRIT in that it is not based on adisplacement invariance array structure but rather isbased on phase mode excitation and hinges on arecursive relationship between Bessel functions.

A theoretical performance analysis ofUCA-ESPRIT is being conducted. This provesextremely useful for predicting its performance in amobile communications environment. Novelstrategies for incorporating mutual coupling effectsare also being developed. The real worldperformance of UCA-ESPRIT is being assessed withexperimental data from a prototype circular antennaarray currently being built at the PolytechnicUniversity of Madrid for mobile sea communicationswith the INMARSAT satellite system. Adaptationsof UCA-ESPRIT for filled circular arrays are beingdeveloped.

University of Minnesota; Kevin M Buckley; PYI: DigitalSignal Processing for Hearing Aids and SourceLocalization; (MIP-9057071 A004); $37,500.

In the general area of Source LocalizationEstimation (SLE), this research will;1. continue SLE algorithm performance

evaluation(s),2. investigate algorithm improvements based on

considerations of analytical performanceexpressions derived during the course of thisproject, and,

3. address the combined issue of robust estimationand high resolution in the presence modelingerrors.In the area of acoustical/biomedical digital signal

processing, specifically hearing aids, effort will bedirected towards the specification of algorithmconstraints and appropriate cost functions,incorporating robustness and real- time testing bothin the laboratory and in the field. Adaptive methodswill be examined for use in active noise cancellationof undesired nonstationary noise.

University of Pennsylvania; Saleem A Kassam; Arrays forHigh Resolution Imaging and Efficient Digital Filtering;(MIP-9321856 A003); $64,462; 12 months.

Many imaging systems use arrays of individualelements to sense the propagating field produced byan object. Through signal processing techniquessuch as beamforming, an image of the object maythen be formed. In addition to such passive arrays,imaging systems may use active arrays to bothilluminate an object with a radiated field and torecord the reflected field. Examples of imagingarray systems occur in radio astronomy, sonar,microwave imaging and ultrasound imaging.

This research is aimed at developingfundamental new results for array design andassociated signal processing, based on recentdevelopments on the characterization of arrayperformance in linear imaging. Active imagingsystems (e.g., ultrasound imaging arrays) are aparticular focus of this investigation, although someof the proposed work also addresses passive arrays. Using the idea of the "coarray", this work willconsider how to deploy array elements (andassociated hardware) in the most efficient way toobtain large array apertures and high resolutions. The results will allow minimum redundancy activearrays and minimum complexity active arrays to bespecified. This research on arrays includes a studyof their characteristics under real operatingconditions and will extend to some experimentalwork with an acoustic array system.

University of Texas - Austin; Guanghan Xu, Dim-LeeKwong; Development of Advanced Signal ProcessingAlgorithms for On-Line Temperature Profile Measurementin Semiconductor Manufacturing; (MIP-9400732 A003);$79,980; 12 months.

This research is directed towards thedevelopment, implementation, and demonstration ofadvanced model-based signal processing algorithmsfor real-time measurement of wafer temperatureprofile in Rapid Thermal Processing (RTP). RTP

44 Signal Processing Systems

cluster tools are strategically important for submicronsemiconductor manufacturing because of trendstowards reduced thermal budget and tightenedprocess control requirements on large diametersilicon wafers. Despite its significant advantages,commercial versions of RTP modules for variouschemical vapor deposition applications are notavailable.

This project is developing advanced model-based signal processing algorithms, which whencoupled with the acoustic thermometry andacoustic/pyrometer approaches, accurately measurethe wafer temperature profile at fast acquisition ratesand with a minimum number of sensors. This entailsalgorithm development, implementation, andvalidation using real data from commercial RTP toolsat UT-Austin and SEMATECH.

University of Texas at Austin; Guanghan Xu; CAREER:Development and Implementation of Antenna ArrayProcessing Techniques for Wireless Communications;(MIP-9502695 A001); $41,301.

Array signal processing techniques weretraditionally limited to military applications. Researchers recently found that these techniquescould be applied to significantly expand channelcapacity and improve quality of wirelesscommunication systems through exploitation ofspatial diversity. Despite significant researchactivities in array processing during the last decade,conversion of military technology to commercialtechnology has not been cost-effective. This researchis developing innovative antenna array processingtechniques and fast implementation schemes forvarious wireless communication systems. Theprogram scope is not limited to algorithmdevelopment, theoretical analysis, and simulationstudies; our ultimate objective is to implement theresulting algorithms in real hardware.

Industries specializing in digital signalprocessing and its applications intelecommunications have experienced rapid growthdue to a high demand for information access andprocessing. To respond to such a growth, newcourses in these areas and innovative teachingmethodologies must be developed so students canquickly adapt to various challenges. Plans include;1. the development of several new courses in these

areas including undergraduate laboratorycourses,

2. the continued involvement of undergraduatestudents in industry sponsored projects,

3. the design of more computer projects,4. the creation of opportunities for minority

students and students with disabilities, and,5. the development of a multimedia teaching

method drawing on advanced technology, e.g.,live audio, video, and graphical illustrations andreal hardware demonstrations.

William Marsh Rice University; Don H Johnson; AdaptiveReceivers for Uncertain, Time-Varying Channels;(NCR-9628236); $60,000; 36 months; (Support from:Signal Processing Systems Program, CommunicationsResearch - Total Grant $186,542).

Analysis based upon the "typicality" of the datahas become one of the primary theoretical andpractical concepts in modern information theory. The so-called "Type" (appropriate histogramestimators of the amplitude distribution) have notonly been shown to be sufficient statistics for bothclassification and compression, but have also beenshown to converge exponentially fast to the trueunderlying distribution. Because type-baseddetectors make no a priori assumptions about thechannel characteristics and measure the quantitiesneeded to provide asymptotically optimal reception,these detectors can theoretically achieve the sameexponential error rate as the clairvoyant receiver thatknows the channel characteristics perfectly and usesthem optimally.

The goal of this research is to develop anonparametric adaptive communications receiverstrategy by exploiting results from the theory ofuniversal classification and data compression. Theapproach will be extended to deal with intersampledependencies and colored noise by using channelmeasurements in an optimally effective way. Twotechniques drawn from data compression work,context trees and Lempel-Ziv (universal) coding, arebeing examined to determine which representschannel-induced dependencies most efficiently andwhich is most adaptable. By merging systems basedon these two theories, a receiver that adapts tounknown, time-varying channels will be developed. It will be demonstrated that this receiver can be usedin multiuser channels, both wireless and optical fiber,with little modification. The research will developthe theoretical underpinnings of this adaptivereceiver strategy, and will develop a completesoftware implementation of the receiver, using as testdata actual communication channel recordings.

Signal Processing Systems 45

Brigham Young University; A. L Swindlehurst; Analysisand Development of Algorithms for Antenna Array BasedCommunications Systems; (MIP-9408154 A001); $49,343;12 months.

Communication systems employing antennaarrays are required in situations where multipleco-channel signals are present simultaneously. Thespatial discrimination provided by multiple antennaelements allows spectrally overlapping signals to beindividually extracted. Such systems have typicallybeen proposed in the context of military applications,but important commercial applications have recentlygained attention. It has been proposed that antennaarrays be used in land-based mobile radio systems toprovide enhanced spatial discrimination and henceincreased capacity. Such arrays could potentiallyprovide frequency reuse in adjacent cells, or within acommunication cell itself.

This research is examining signal copy,interference cancellation, and source localizationusing antenna arrays, with emphasis on scenarios thatmight be encountered in mobile radiocommunications (e.g., multipath fadingenvironments, signal formats such as analog FM IS-3AMPS, GSM, IS-54 offset QPSK, IS-95 CDMA,etc.). This research focuses on the development andanalysis of algorithms that exploit all availabletemporal and spatial information. Conventionaltechniques for Direction Finding (DF) and SignalCopy (SC) rely on either spatial or temporal structurein the data, but typically not both. Three differenttechniques that exploit both spatial and temporalsignal structure for improved DF/SC are beingstudied;1. iterative blind-least-squares,2. decision directed algorithms array-based

equalization of multipath channels, and,3. optimal joint DF/SC with parametric array

uncertainty.Finally, special emphasis is being placed on the

use of real mobile cellular radio data to test theeffectiveness of the algorithms developed.

George Mason University; Geoffrey C Orsak; AdaptiveReceivers for Uncertain, Time-Varying Channels;(NCR-9628294); $57,471; 36 months; (Support from:Signal Processing Systems Program, CommunicationsResearch - Total Grant $149,995).

Analysis based upon the "typicality" of the datahas become one of the primary theoretical andpractical concepts in modern information theory. The so-called "Type" (appropriate histogramestimators of the amplitude distribution) have notonly been shown to be sufficient statistics for bothclassification and compression, but have also beenshown to converge exponentially fast to the trueunderlying distribution. Because type-baseddetectors make no a priori assumptions about thechannel characteristics and measure the quantitiesneeded to provide asymptotically optimal reception,these detectors can theoretically achieve the sameexponential error rate as the clairvoyant receiver thatknows the channel characteristics perfectly and usesthem optimally.

The goal of this research is to develop anonparametric adaptive communications receiverstrategy by exploiting results from the theory ofuniversal classification and data compression. Theapproach will be extended to deal with intersampledependencies and colored noise by using channelmeasurements in an optimally effective way. Twotechniques drawn from data compression work,context trees and Lempel-Ziv (universal) coding, arebeing examined to determine which representschannel-induced dependencies most efficiently andwhich is most adaptable. By merging systems basedon these two theories, a receiver that adapts tounknown, time-varying channels will be developed. It will be demonstrated that this receiver can be usedin multiuser channels, both wireless and optical fiber,with little modification. The research will developthe theoretical underpinnings of this adaptivereceiver strategy, and will develop a completesoftware implementation of the receiver, using as testdata actual communication channel recordings.

Other

University of Arizona; Richard J Greenberg, Robert GStrom; Image Processing Teaching: Curriculum MaterialsDevelopment; (ESI-9553841); $75,000; 12 months;(Support from: Instructional Materials Development,Signal Processing Systems Program - Total Grant$399,774).

Image processing has been shown to be apowerful medium for engaging diverse learners,whose needs have not been met in the past, in the

study of science and mathematics. The technique isan effective and engaging way to study theapplications of science and mathematics to real-worldsituations as represented by digital imagery. Itbrings science research to the classroom; science islearned as science is done. In this project, studentsand teachers are lead into exploration, inquiry andanalysis using real data sets and state-of-the-artcomputer tools. These supplemental materials,useful in middle and high schools are based on

46 Signal Processing Systems

successful materials developed in teacherenhancement programs and provide a context forchanging traditional classroom structure to a learningcommunity. Teachers are supported by on-lineservices and a network of professional developmentopportunities. Subject specific CDROMs areproduced in physics, biology and Earth science. Thestandards-based activities are designed to meetspecific learning goals and lead to creativestudent-generated products for performance-basedassessment of student achievement. Students alsolearn about mathematical concepts that underlieimage processing such as coordinate systems, slopeand intercept, measurement and statistics.

University of California - Berkeley; Kjell A Doksum;Mathematical Sciences: Topics in Nonparametric Analysisand Model Building; (DMS-9625777); $30,000; 12 months;(Support from: Signal Processing Systems Program,Statistics - Total Grant $72,000).

With the advent of computer data bases ofunprecedented size and complexity and with thedramatic increase in computer power, it has becomeincreasingly more desirable and possible to developmore flexible models, concepts, and procedures thatcan be used to study relationships between variablesand to construct models without relying on rigidglobal assumptions. Much of the recent work instatistics have addressed this need for more generaland flexible methods.

This research addresses the question of howintuitive and concise linear model concepts andtechniques can be extended to nonparametricsettings. Nonparametric counterparts of suchcommonly used linear model ideas as regressioncoefficients, correlation coefficients, coefficient ofdetermination, and principal components areconsidered. The research also studies nonparametrictechniques for model diagnostics that can be used fordimensionality reduction and to address the questionof adequacy of particular models. Both asymptoticand finite sample properties are studied, and theproblem of developing reliable data-based methodsfor smoothing parameter selection for functionals andcurves is addressed.

University of California - Los Angeles; A. N. Willson;Circuits and Systems for Signal Processing;(MIP-9632698); $294,216; 36 months.

A major research area, one evolving out of theprincipal investigator's long-term work in nonlinearcircuit theory, is the development of a rigorousstability theory for the operating points of dctransistor circuits. A complete solution (necessary

and sufficient conditions for dc operating pointstability in nonlinear circuits) seems almost withingrasp, and this research project seeks to obtain it. Research on low-power circuits encompasses thedesign of new low- power clock buffers, schemes forimplementing circuits to achieve charge recovery ona databus and the investigation of techniques for thedesign of low-power practical circuits such as Viterbidecoders for CDMA digital cellular applications.

Another project concerns the development ofnew techniques for multiplierless digital filter design,including the design of novel multiplierless adaptivefilters. Work will continue on new techniques forIIR filter pipelining, a topic that shows great promisein providing more economical structures (in terms oflower power-dissipation and IC-area requirements)for DSP systems. In addition, research will continuein the area of video compression, where a techniquefor rate-distortion optimization is being developed. Finally, recent circuit design experience has madeevident the need for advances in logic simulation. The principal investigator's research has alreadyproduced several simple ways to improve simulationefficiency and it is expected that major improvementswill be forthcoming through further vigorous pursuitof this project

Colorado State University; Richard A Davis, Peter JBrockwell, Murray Rosenblatt; Mathematical Sciences:Time Series Models and Extreme Value Theory;(DMS-9504596 A001); $10,000; 12 months; (Supportfrom: Signal Processing Systems Program, Statistics -Total Grant $70,000).

The research is concerned with problems ofestimation and research for time series models whosetheory is not yet fully understood. The standardlinear Gaussian models for time series datainadequately describe many of the time seriesobserved in practice. It is therefore important todevelop techniques for estimation and predictionbased on more general models. Efficient estimationprocedures and prediction techniques for non-causaland non-invertible ARMA processes are beingdeveloped, and a study of the theory and applicationof continuous-time linear and non-linear ARMAprocesses is being made. Extreme value theory forlinear and non-linear models is also investigated.

Signal Processing Systems 47

University of Colorado- Boulder; Delores M Etter;Workshop on Future Research Directions for SignalProcessing Research, August, 1996, Durango, CO;(MIP-9614719); $56,740; 12 months.

Today, all areas of technology use signalprocessing. The applications range from adaptivecoding of speech signals, to analysis of medicalimages, to echo- canceling in cellular telephones. The successful implementation of signal processingalgorithms in both software and hardware is a resultof research into various aspects of signal processing,including analysis, modeling, synthesis, algorithmdevelopment, tool development, and implementation. This workshop in intended to bring together adistinguished group of research scientists andeducators to explore the expanding role of signalprocessing within applications that include thetelecommunications infrastructure and the expandinginformation highway.

The workshop will meet for 3 1/2 days to assessand document recent advances and current and futureresearch directions in signal processing. During thistime we expect to prepare recommendations forresearch activities and to initiate a debate on thefuture directions of the field from among the researchcommunity. Participants will be drawn fromacademia, industry, and companies whose productsinclude significant signal processing components. The goal of the meeting will be to develop a visionstatement for the field and determine areas whichhave the potential for high payoff in terms ofapplication areas. The participants will also discussways of integrating signal processing research resultsand applications into the undergraduate engineeringcurricula - "the integration of research and education. " Another important topic will be the discussion ofways to promote public awareness of the pervasiverole of signal processing.

Iowa State University; Dianne H Cook; Using CAVETechnology to Explore High-Dimensional Data;(DMS-9632662); $15,000; 24 months; (Support from:Signal Processing Systems Program, ComputationalMathematics, Statistics - Total Grant $50,000).

Virtual Reality offers the construction andrealization of an artificial 3-Dimensional (3-D) worldthat has important potential use in scientific areas. Statistics is the science of making sense ofcomplicated data. For example, typicalenvironmental data sets may contain thousands ofdata values on hundreds of variables. Graphicalmethods are needed for exploring and determiningrelationships among variables such as tree crownhealth, topography, temperature, population densityand atmospheric pollutants.

This research explores visualization methods forexamining high-dimensional data with low-dimensional projections with CAVE Virtual Realitytechnology. Dynamic graphical methods forexploratory data analysis are examined in a 3-Dimmersible environment. The methods are based ongenerating motion graphics from continuoussequences of 3-D projections of high-dimensionaldata. Interactive user control is considered in theform of controlling the path of the 3-D sequences inthe data space.

University of Maryland - College Park; K. J. Ray Liu;NYI: High Performance Computing for Signal Processing;(MIP-9457397 A002); $31,250; 12 months; (Support from:Prototyping Tools and Methodology Program, SignalProcessing Systems Program - Total Grant $62,500).

There are three major architectural models usedin high-performance signal/image processing:1. VLSI- signal processing - high- throughput

VLSI architectures for low-costapplication-specific implementations used inapplications such as communication systems,speech, video/HDTV, and radar;

2. parallel signal processing on massively parallelcomputers - parallel algorithms for complexsignal/imaging systems used in computer vision,medical imaging, and the processing of vastamounts of data in deep space exploration;

3. distributed signal processing on high-speednetworks - used in applications such asdocument image processing, multimedia,automatic signal processing in manufacturing,and medical signal/image processing. This research will focus on the development of

efficient algorithms and architectures for eacharchitectural model, and in comparative studies of theadvantages and disadvantages of these differentcomputing schemes. The goal is to investigatewhich signal/image processing problems can becarried out optimally under different computing andcommunication schemes.

Massachusetts Institute of Technology; AlexanderSamarov; Topics in Nonparametric Analysis and ModelBuilding; (DMS-9626348); $20,000; 12 months; (Supportfrom: Signal Processing Systems Program, Statistics -Total Grant $59,000).

With the advent of computer data bases ofunprecedented size and complexity and with thedramatic increase in computer power, it has becomeincreasingly more desirable and possible to developmore flexible models, concepts, and procedures that

48 Signal Processing Systems

can be used to study relationships between variablesand to construct models without relying on rigidglobal assumptions. Much of the recent work instatistics have addressed this need for more generaland flexible methods.

This research addresses the question of howintuitive and concise linear model concepts andtechniques can be extended to nonparametricsettings. Nonparametric counterparts of suchcommonly used linear model ideas as regressioncoefficients, correlation coefficients, coefficient ofdetermination, and principal components areconsidered. The research also studies nonparametrictechniques for model diagnostics that can be used fordimensionality reduction and to address the questionof adequacy of particular models. Both asymptoticand finite sample properties are studied, and theproblem of developing reliable data-based methodsfor smoothing parameter selection for functionals andcurves is addressed.

Massachusetts Institute of Technology; Kai-Yeung Siu;NYI: Analysis and Design of Artificial Neural Networks;(MIP-9696144); $31,250; 12 months; (Support from:Signal Processing Systems Program, Computing SystemsResearch Program - Total Grant $$62,500).

Artificial neural networks present a new modelfor massively parallel computation and a promisingparadigm for solving large scale optimizationproblems. This research is exploring the advantagesof neural network-based models over conventionalmodels for computation, and a novel design ofneuromorphic computing architectures forapplications in signal and image processing. Atheoretical framework is being established to derivetight tradeoffs between the number of elements andthe number of layers in neural networks. The resultsshould answer some of the key open questions in theanalysis of neural networks using classicalmathematical tools such as rational approximationtechniques and harmonic analysis.

TERC Inc; Susan J Russell; Investigations in Number,Data, and Space: An Elementary Mathematics Curriculum;(ESI-9050210 A008); $600; 12 months; (Support from:Instructional Materials Development, Signal ProcessingSystems Program - Total Grant $549,820).

TERC will develop a comprehensivemathematics curriculum for grades K-6 based oninvestigations in number, data, and space, andemphasizing depth and understanding. Thecurriculum will stress mathematics as apattern-finding science, make the discipline moreaccessible to both students and teachers, and build

teachers' knowledge of how students learnmathematics. TERC will design, evaluate, anddisseminate ten curriculum modules for each gradelevel. Each module will focus on a set of related anddevelopmentally appropriate investigations whichintroduce key mathematical content within acompelling context. The teaching is built into theprint materials (through scenarios depicting analyticwork in classrooms), and into videotapes of effectivemathematics teaching in action. Evaluation of theproject will include formative research, as well as anexamination of the impact of the curriculum onstudents and teachers. Investigations will bedisseminated through publications aimed specificallyat elementary school educators. The curriculum willbe published by Dale Seymour Publications, who hasmade a major financial commitment to the project.

Michigan Technological University; Jeffrey O Coleman;RIA: Convex-Programming Design of Signals and Systems;(MIP-9409686 A001); $2,500; (Support from: SignalProcessing Systems Program, Design AutomationProgram - Total Grant $5,000).

The PI is creating a special-purposeprogramming language in which optimizationproblems can be specified in a natural and direct way. The focus is on developing associated translationsoftware to convert such a specification into aparticular canonical form for numerical optimizationusing recently developed, ultra-efficient,interior-point algorithms. The canonical form is aLinear-Matrix-Inequality (LMI) program, where eachconstraint takes the form of a requirement that alinear (plus a constant) matrix function of theoptimization variables be positive definite.

Control theorists have recently demonstrated thata tremendous variety of common (and uncommon)constraints can be put into this generic form. Often,however, the required LMI constraints are not relatedto the underlying problem in an intuitive way. Software to translate specifications in a "comfortablelanguage" to sets of LMIs is being developed in orderto make these powerful optimization techniques easyto apply. The language is being applied to realproblems in communication and signal-processingcircuit designs.

University of Minnesota; Keshab K Parhi; NYI: DedicatedVLSI Digital Signal and Image Processors; (MIP-9258670A004); $62,500; 12 months.

Research efforts are directed towards the designof dedicated, high-performance digital signal andimage processors. The emphasis is on real-timeprocessing, where samples are processed as they are

Signal Processing Systems 49

received from the source, as opposed to being storedin buffers and then processed in batch. Design ofalgorithm topologies for recursive signal processingalgorithms were once considered a major challenge. Using the relaxed look-ahead technique, newconcurrent algorithms and topologies for adaptiveLMS and lattice filters, cascade and lattice recursivedigital filters, and predictive speech and image codershave been developed. Design of concurrenttopologies for wave digital filters, decision-feedbackequalizers, and adaptive differential vector quantizersare being pursued. The decoding speed in Huffmanand arithmetic coders (used for lossless compression)is limited due to the feedback. For the Huffmandecoder, the codeword length multiplicity constraintis being exploited to design codes where multiple bitscan be simultaneously decoded in parallel. Theperformance of these decoders is further improved bythe use of conditional coding. Novel approaches fordesign of parallel arithmetic coders are also beingpursued.

State University of New York - Stony Brook; Michael MGreen; NYI: Improved Circuit Simulation Using Resultsfrom Circuit Theory; (MIP-9457387 A002); $31,250; 12months; (Support from: Signal Processing SystemsProgram, Design Automation Program - Total Grant$62,500).

This research is applying results in the area ofnonlinear circuit theory to enhance the simulation ofanalog circuits. Improvements to the continuationmethods of solving dc operating points of circuits arebeing made to guarantee that all circuit operatingpoints are found during a single analysis, and arebeing applied to sensitivity analysis of circuits. Erroneous models are thought to be a major source ofconvergence problems and erroneous results incircuit simulation. Another enhancement to circuitsimulation includes checking the accuracy oftransistor models by verifying that all models satisfypassivity and the no-gain condition.

Earmark Inc; Elisabeth Perez-Luna; Intersections: Art,Science and Technology -- A Radio Project; (ESI-9634183);$8,000; 12 months; (Support from: Informal ScienceEducation, Prototyping Tools and Methodology Program,Signal Processing Systems Program - Total Grant$25,000).

This project will examine the implications of theintersection of art, science, and technology asrevealed by the events occurring around thecelebration of the fiftieth anniversary of the firstgeneral electronic computer, ENIAC-50. Thefinished product will be radio programming and

audio material that presents the coming together ofscientists, artists, and other participants inPhiladelphia. It will build on the previous researchand explorations in both of these fields towardfinding commonalties and ways in which each hasinfluenced the other. The finished product will bebroadcast for the general public and also can be madeavailable to scientists and educators in the field asresource material for courses, seminars, and lecturesas they explore the intersections of science and artand implications this has for research and education.

Brown University; Harvey F Silverman; ParallelArchitectures for Speech Recognition: NonlinearOptimization of Expectation-Maximization (EM) Trainingof Hidden Markov Models (HMMs) in a ReconfigurableEnvironment; (MIP-9509505 A001); $45,859; 12 months.

This research focuses on one of the strategicareas of national concern, that of high performancecomputing. It involves the development, constructionand testing of new architectures for high-speedcomputing. The idea is to combine general-purpose,RISC-based processing nodes, each with multipleField-Programmable-Logic-Array (FPLA) basedcoprocessor systems. This kind of system has thehardware properties of a general-purpose computer,but the advantage of performance more akin to thatof a special-purpose engine. In particular, the 20-node Armstrong III system has been built, isoperational, and provides nearly two-orders ofmagnitude improvement over current advancedworkstations. The hardware system, combined withits configuration compiler, a program thatautomatically translates a C function subroutine toboth machine code and to the hardware design of thereconfigurable coprocessors, are the basic buildingblocks for this class of architectures.

This project is unique in that not only has thehardware/software system been built, but it is alsobeing tested on real applications. The training of amodern hidden markov model based speechrecognition system requires hundreds of hours, evenwith recent variants developed at Brown andelsewhere. The reduction of this training time to tenor so minutes allows progress in this area to be madeat a faster rate and/or that expensive nonlinearoptimization techniques may now be applied to theproblem. Also, this means that data from a lesscumbersome sensor system (the microphone arraysystems in place and being developed at Brown) canbe suitably incorporated into a more robust speechrecognition system.

Experimental Systems 51

Experimental Systems

Dr. Michael J. Foster, Program Director(703) 306-1936 mfoster@nsf.gov

The Program

The Experimental Systems program supports research projects that involve building, evaluating, and experimenting with a computer orinformation-processing system. These are goal-oriented projects generally undertaken by teams of designers, builders, and users. Thebuilding of the system must itself represent a major intellectual effort, and offer advances in our understanding of information systemsarchitecture. A system supported by the Experimental Systems program will usually include both hardware and software components.

Research on information processing systems involves interaction among diverse elements such as hardware architectures, computationalmodels, compilers, operating systems, applications, performance evaluation tools, and user interfaces. Building and evaluating realexperimental systems is the only way to understand these interactions in large systems; other techniques, such as simulation and analysis,have only limited uses in understanding the system issues in such a complex environment. Software simulators, for instance, do notprovide the computing speed needed for large experiments, nor the needed performance incentives for porting large application systemsfor experimentation. Without real experimental systems, important areas of information systems architectures cannot advance.

A successful proposal to the Experimental Systems program should demonstrate the feasibility and utility of the project. Feasibility canbe shown by describing prior proof-of-concept prototypes or simulation studies that indicate that the proposed system can be built andwill meet its design goals. Utility can be shown by demonstrating that building the system will provide substantial advances in computersystem architecture, or that the system is inherently useful. Details of the measurement and evaluation procedures that will demonstratethe benefits of the system in an application should be given in the proposal.

The system to be built must be novel in some way, and the impact of the novel aspects of the system upon its architecture must be evaluatedduring the course of the research. To justify construction, the new system must be potentially superior to existing systems in the chosenapplication area. Ideally, building the system would provide new knowledge of systems architecture, open up new application areas, and/orcontribute to our knowledge about system building techniques. An appropriate project might be a system built using a new architectureor technology, which addresses an application in a new way. An inappropriate project would be one in which the research uses, simplyas a platform, a special purpose machine whose design, fabrication, and evaluation are straightforward. The novel aspects of anexperimental system may fall into several different areas; the system might feature application of a new technology, new architecture, ornew techniques for performance measurement and evaluation to a computationally stressing problem. Examples of technologicalinnovation are massively parallel analog systems, or applications of opto-electronics. Architectural innovations might include new parallell/O structures, hardware-software codesign, or limited modifications to commodity processors. New evaluation techniques might includeinstrumentation for performance evaluation or debugging. These innovations might be applied to produce high-performance computers,intelligent sensors, or signal processing architectures, for example.

To justify support under this program, a proposal should show that system building is necessary for answering significant and timelyresearch questions. The research issues should be such that the best way to address them is to build the proposed system and measure itsperformance. Building for its own sake is discouraged; analysis and simulation should be performed in sufficient detail before a proposalis sent to the Experimental Systems program. Furthermore, off-the-shelf hardware should be employed in the building stage wheneverthe research goals do not require custom construction.

By encouraging the design, construction, test, and evaluation of novel information processing systems, NSF hopes to achieve several goals:

* Settle major research issues and add to fundamental knowledge in information processing;

* Guide university research in computer science and engineering toward meaningful problems of industrial interest;

* Strengthen the system-building expertise in our research institutions;

* Educate a new generation of researchers in experimental systems research.

Potential applicants are encouraged to discuss their research ideas with the program director prior to formal submission.

52 Experimental Systems

Optical Science and Engineering

During the 1996 Fiscal Year the Experimental Systems program participated in an initiative on Optical Science and Engineering(OS&E). Optical Science and Engineering is an enabling field with demonstrated contributions to many technologies and diverseareas of science and engineering: in the use of optics and optoelectronics in information and communications, in the development ofnovel materials and devices, in the control of chemical reaction pathways, in the elucidation of quantum processes with laser light, inmetrology for precision manufacturing processes, in optical instrumentation advances and their profound influence in the physical,biological, and environmental sciences, and in the development of an educated and skilled workforce.

Experimental Systems 53

Awards

Storage Hierarchies and Input/Output Systems

California Institute of Technology; Paul Messina: ScalableI/O Initiative; (CDA-9415797 A001); $50,000; 12 months;(Support from: Experimental Systems Program, CISEInstitutional Infrastructure, Operating Systems andSystems Software - Total Grant $300,000.

This award supports the infrastructure for theScalable I/O national project. This national projectwill investigate many of the issues surrounding thescalability of Massively Parallel Processing (MPP)System input and output systems. The nationalproject consists of 18 application groups involvingmore than 30 researchers.

The equipment provided by this award consistsof I/O nodes for an MPP and a small MPP forcrashable experimentation. The infrastructure willbe available to all of the application groups for theirexperimental research needs.

University of Southern California; Michel Dubois:Hardware Prototyping of Shared-Memory MultiprocessorArchitectures on RPM; (MIP-9633542); $794,566; 48months.

This project is conducting research inmultiprocessor architecture by using a rapidprototyping engine for multiprocessors (RPM) thatconsists of commodity processors and memoriesinterconnected with programmable logic. The mainpurpose of RPM is to demonstrate the feasibility,complexity, performance, and cost-effectiveness ofvarious selected multiprocessor architectures, byallowing accurate hardware prototypes to beconstructed. The prototype can include input/output,and can run production operating systems andapplication codes. Prototype architectures evaluatedas part of this project include cache-coherentNUMAs and cache-only machines with varyingcache and memory protocols, and several softwaredistributed shared memory machines with fine-grainhardware support. Expected outcomes of the researchinclude accurate measurements of the performance ofvarious architectures, as well as the demonstration ofa new methodology for rapid and cost-effectiveprototyping of computer systems.

North Carolina A & T State University; Kelvin S Bryant:Performance Tools and Compiler Support for Parallel I/OSystems; (MIP-9625083); $200,000; 48 months.

This award supports a unified program ofresearch and education in parallel input-outputsystems for high-performance computing. Researchactivities will include development of tools for I/operformance evaluation, applying the tools tocharacterize I/O performance of scientific codes, andprovision of compiler support for parallel I/O. Educational activities span the needs of graduate andundergraduate students, and include outreach to K-12and the community. These include development of agraduate course, augmentation of undergraduatecurricula, and workshops for participants outside theuniversity.

Texas A & M University; A. L. Narasimha Reddy:Scalable Storage Server for Multimedia and ScientificApplications; (MIP-9624310); $200,000; 48 months.

This project is building a high-performancedistributed storage system using communicationswitches and workstations. Data to be stored will bedistributed across the workstations and will beretrieved using the communication network betweenthe workstations. Research issues to be addressedinclude identification of hardware and softwarebottlenecks, limits to system scaling, scheduling ofmultimedia I/O in a distributed system, and theimplications of I/O on switch architecture. Education is a part of this project; plans include agraduate course on I/O systems, an undergraduatelaboratory in computer architecture, and use of themachine developed during the research as a testbedfor the graduate course.

William Marsh Rice University; Willy Zwaenepoel:Reliable Main-Memory Storage Systems; (MIP-9521386);$712,263; 24 months.

This project investigates the use of non-volatilesemiconductor memory (such as flash memory) as astorage system to replace some of the functionscurrently assigned to disks. A board (eNVy)incorporating a large (128MB) flash memory is beingdesigned at Rice University; concurrently, alog-structured file system (Rio) that can use the flashmemory board as a cache between main memory anddisk is being developed at the University of

54 Experimental Systems

Michigan. In later stages of the project theseresearch prototypes will be integrated. Researchissues in hardware development include spacereclamation (garbage collection), and tradeoffsbetween memory size, performance, and memory

lifetimes. Research issues in file system developmentinclude optimization of the sizes of cache and main memory,algorithms for compression of data in the cache, protection ofmemory from software faults, and exploration of file systemindex structures. Integration of the prototypes will provideinsight into the protability of these techniques to new systems.

General Purpose Computing

Stanford University; Michael J Flynn, Bruce A Wooley, S. Simon Wong, Giovanni De Micheli, R Fabian W Pease:Sub-Nanosecond Arithmetic II; (MIP-9313701 A002);$330,000; 12 months.

This project is attempting to speed up computerarithemtic by several orders of magnitude using acombination of algorithmic, circuit, and packagingtechniques. CAD tools to automate the applicationof these techniques are also being developed underthe project. Specific research problems include thedevelopment of a package capable of passing largenumbers of signals with 100 picosecond rise times,and the integration of wave pipelined data paths intoan overall system.

University of California - Berkeley; David E Culler: ANext-Generation Infrastructure for Integrating Computingand Communications; (CDA-9401156 A004); $200,000; 12months; (Support from: Experimental Systems Program,CISE Institutional Infrastructure - Total Grant $263,630.

This award provides support for the developmentof Titan, a computing system consisting of anintegrated ensemble of computing andcommunication elements, organized to provide theuser with a number of services. These services willinclude multimedia capabilities in delivery vehicles;storage and communication; large computing power;large storage space; innovative parallel languages,debuggers, and libraries; and high accessibility fromboth mobile and fixed locations. The experimentalfacilities requested include workstations and serversconstituting the backbone of the distributed systemproviding cycles to the user, ATM switches forlinking workstations and servers, a video editingsystem, a massive storage unit, and equipment forlinking the network to the currently available CM-5parallel computer.

The proposed research projects fall into threeareas: network and communications; distributed

supercomputer projects which are mainly concernedwith providing parallel computing to every userthrough a combined architecture, operating systems,and programming language effort; and multimediaservices which requires integrating systems support,software support, and artificial intelligence tools tocreate, store, play, edit, search, input, and outputmultimedia objects. The networking, multimedia,and computing aspects of Titan form will form theinfrastructure for a number of computationallyintensive applications.

University of Illinois - Urbana-Champaign; JosepTorrellas: NYI: Increasing the Performance of ScalableShared-Memory Multiprocessors; (MIP-9457436 A002);$87,500; 12 months.

Scalable shared-memory machines are apromising way of attaining large-scalemultiprocessing without surrendering muchprogrammability. Achieving high performance fromthese machines, however, is challenging becausemany complex architecture and architecture-softwareimplementation issues that have been only partiallystudied considerably impact the performance of themachines. The objective of this research is tocontribute in three areas to help make shared-memorymultiprocessors the preferred source of computingpower. The three thrusts of this project are to: studythe optimal division of responsibilities among thehardware, compiler, and operating system to maintaincache coherence in scalable share-memorymultiprocessors; design algorithms and hardware toeffectively support multiprogramming of parallelprograms in scalable shared-memorymultiprocessors; and optimize the management ofmemory hierarchies and the interaction of theoperating system with the architecture.

Experimental Systems 55

Princeton University; Kai Li, Margaret R Martonosi,Douglas W Clark, Edward W Felten, Richard J Lipton:SHRIMP: Architectural and Systems Support forInexpensive, High-Performance Multicomputers;(MIP-9420653 A001); $450,000; 12 months.

This project is building a high-performancemultiprocessor from commodity desktop computersystems and off-the-shelf interconnects. Commercial Intel Pentium workstation boards, eachwith attached memory, disk, and I/O, are attached toa Paragon backplane. Communication uses a newmechanism called virtual memory-mappedcommunication, which disguises interprocessorcommunication as write operations to memory. Thenode interface maps physical pages in the memoriesof individual nodes to each other, so that a write toone mapped page results in messages to other nodesthat share the mapped page. The operating systemson the individual nodes use their ordinary virtualmemory mechanism to support virtual page mapping. In addition to this word-by-word communication,DMA transfers are available, with control registerslocated in the address space of individual processes. This allows high bandwidth communication thatmaintains user-level protection. Research to beaddressed in the project includes the achievement ofhigh-bandwith low-latency communication betweenprocesses, the structure of an I/O system supportedby the new communication mechanism, andperformance evaluation of the resulting system.

New York University; Zvi M Kedem: CollaborativeResearch: High Performance Parallel Processing:Fault-Tolerant Computing on a Network of Workstations;(CCR-9411590 A001); $25,000; 12 months; (Supportfrom: Experimental Systems Program, Computer SystemsArchitecture - Total Grant $71,233).

This project deals with both theoretical andprototyping research in parallel processing to harnessthe power of workstation clusters. The primarytechniques will be based on aggressive scheduling,evasive memory and dispersed data management. The formal work expands the previous results of thePIs in asynchronous computing in several directions:4. Extend the models to fine-grained programs.5. Permit the inclusion of architecture specific

characteristics into the theoretical framework.6. Techniques to distinguish inconsistencies in

memory states as viewed by different processorsresulting from time-outs, interrupts and failures(or indefinite postponement of a computation).

7. Techniques to allow non-deterministicexecutions.

8. Model input/output operations of fault-tolerant

programs. The experimental part of the project will build a

scaled version to execute parallel programs onclusters of workstations. The prototype will addressissues related to the eager scheduling of threads, theimplementation of evasive memory and datamanagement. The prototype will attempt to evaluatethe effectiveness of the environment in terms ofefficiency.

This project is conducted jointly by P. Dasgupta of Arizona State University and Z. Kedemof New York University.

University of Washington; Susan Eggers; SimultaneousMultireading; (MIP- 9632977); $200,859; 24 months;(Support from: Experimental Systems Program,rototyping Tools and Methodology - Total Grant$519,164).

This is a project to develop and extend supportfor multithreaded computation on superscalarprocessors. The intention is to provide highprocessor utilization despite increasing memorylatency. In simultaneous multithreading, multiple independent threads will issue instructions to asuperscalar processor's functional units in a singlecycle. The objective of this project is to fully definethe low-level architecture for simultaneousmultithreading, including scheduling, registerarchitecture, pipeline design, and speculativeexecution. The project is developing compiler andoperating systems support for multithreadedexecution on the new processor architecture. Aprimary goal is to maximize multiple threadperformance without increasing single thread latency.Most measurements are from detailed simulations,using simulators and compilers provided byindustrial partners.

University of Washington; Lawrence Snyder, CarlEbeling: Chaotic Routing: Study and Implementation;(MIP-9213469 A005); $1,000; 18 months.

The chaotic router for multiprocessor systemsavoids congestion in message routing by deroutingpackets chosen at random at congested nodes of anetwork. The routers can thus adapt to varyingmessage traffic. In this project, the router is beingimplemented and its performance is being measuredwithin a testbed that approximates a realmultiprocessor.

56 Experimental Systems

University of Wisconsin - Madison; Max G Lagally: DNAComputation on Surfaces; (CCR-9613799); $50,000; 12months; (Support from: Experimental Systems Program,Theory of Computing, Computational Biology Activities,ARPA - Total Grant $300,000).

1. This multi-disciplinary project concentrates ondeveloping computation at the molecular level, viamanipulation of DNA strands on surfaces. Anexperimental demonstration of DNA-basedcomputation by Adlemana. has changed the view of what computation is,b. offers the potential for unprecedented computing

power at the molecular level, andc. raises fundamentally new research problems in

chemistry, computer science, and materialscience.This project represents a concerted attack on

these problems which involves close collaborationbetween chemists, material scientists, and computerscientists.2. This research will help answer two majorquestions on DNAcomputation. First, doescomputation at the molecular level have the potentialto provide computing power that is orders ofmagnitude greater than foreseeable extrapolations ofcurrent technology? Second, is this type ofcomputation suited to solving NP-hard problems(problems that are well beyond the limits of currenttechnology?3. The potential for huge computing power rests on

the use of DNA strands to encode informationand the manipulation of these strands in amassively parallel fashion, involving as many as2¬70 (2 to the 70th power) distinct strands. Thepremise of this project is that surface-basedchemistry is a critical technology in approachingthis scale. With this approach, DNA strands areimmobilized on a surface, thus allowing a muchgreater degree of control in chemical processesthat manipulate the DNA than is achievable viathe test tube based methodology of Adleman. While surfacebased chemistry is the basis forrecent strides in combinatorial chemistry, thisproject is the FIRST to fully exploitsurface-based manipulation of DNA strands forthe purposes of DNA computation.

4. Scaling up current surface chemistry toapproach the requirements of DNA-basedcomputation requires high-quality research at theinterface of materials science and chemistry. Improvements in the nanoscale morph ology andchemical makeup of the surface is key toensuring that a high density of information canbe obtained and reliable chemical manipulationsperformed. Good surface attachment chemistryand control of chemical ``operations'' orenzymatic processes are also extensively

developed. This project should result insignificant advances in the state of- the-art insurface chemistry and should provide a solidbasis for predicting the limits of surfacebasedDNA computation.

5. An eventual goal of DNA-based computation isto perform massivelyparallel searches foroptimal solutions of NPhard problems. However, the differences between DNAbasedcomputation and conventional technologyrequire that radically new algorithms bedeveloped for this paradigm. Tempering thepotential for unprecedented parallelism (up to2¬70 simultaneous operations) is extremely slowand errorprone nature of the operationsthemselves. Novel strategies for generating andsearching solution spaces for NPhard problemsare investigated. These strategies embodysound algorithmic principles that can be appliedto a range of problems. Using a combination ofanalysis and simulations, the effectiveness ofthese strategies are tested on selectedapplications. This work provides new ways ofattacking NPhard problems that, while designedfor a hypothetical DNA based computer, arevaluable for massively parallel computingparadigms, other than the DNA-based paradigmstudied here.

6. Thus this comprehensive program will provide adeep understanding of the potential andlimitations of DNAbased computation, fromboth the chemical and algorithmic viewpoints.

University of Wisconsin - Madison; Gurindar S Sohi,James E Smith: Prototyping Multiscalar Processors;(MIP-9505853 A001); $229,962; 12 months; (Supportfrom: Experimental Systems Program, Computer SystemsArchitecture - Total Grant $309,962.

This project is evaluating a new architecturalparadigm that can extract and exploit the parallelismin sequential code. This new approach uses bothsoftware scheduling in the compiler, as in VLIW, andhardware scheduling at run-time, as in superscalararchitectures. The compiler segments code intolarge blocks of instructions that form subgraphs ofthe control-flow graph, though not necessarily basicblocks. The compiler appends synchronizationinformation to each block that describes whichregisters must be shared with blocks. The compilerappends synchronization information to each blockthat describes which registers must be shared withother blocks. The blocks or tasks are passed toseparate identical parallel execution units, each ofwhich executes its task sequentially. Tasks arescheduled optimistically, so that some tasks may beexecuted by a unit when they would not be executed

Experimental Systems 57

in a sequential system; in such cases, the tasks are"squashed," which means that their results are notwritten to memory or registers. At the end of eachtask, it blocks until the system determines that thetask will not be squashed; at that time results arecommitted. The collection of execution unitsappears logically to be one unit, with a single registerfile. Shared register values are passed on aninter-execution-unit network, and tasks that needshared values block until the values are produced.

During the first two years of this award isdevoted to compiler design for the new architecture,to comparison with other architectures usingsimulation, and to conceptual refinement of thearchitecture. During later years, work is expected tofocus on implementation.

University of Wisconsin - Madison; David A Wood, PeiCao, James R Larus, Mark D Hill: Tornado: Fine-GrainDistributed Shared Memory for SMP Clusters;(MIP-9625558); $684,126; 24 months.

This project is exploring the cluster approach tosymmetric multiprocessing, in which bus-basedmultiprocessors are interconnected using a morescalable network. Using the Tempest parallelprogramming substrate, the project is buildingclusters that extend the shared memory model withfast references to recently used locations across acluster. The key issue is achieving goodperformance without resorting to extensive customhardware.

The project encompasses design and someimplementation of a high-speed Tempest system.

Application Specific Computing

University of California - San Diego; Henry D. I.Abarbanel: Synchronization and Communication inNonlinear Optical Systems; (NCR-9612250); $315,800; 36months; (Support from: Experimental Systems Program,Networking and Communications Research Program,Optical Communications Systems, Office ofMultidisciplinary Activities - Total Grant $1,069,701).

The is a joint effort through subcontracts, with RajRoy, Georgia Institute of Technology, and StevenStrogatz, Cornell University

The researchers will investigate synchronizationof chaotic lasers for purposes of using chaos as acarrier for new modes of communication includingmultiplexing information bearing signals and privatecommunications using chaotic carriers as well asmethods for optical channel equalization usingnonlinear properties of the fiber. The program willinclude experiments on Nd:YAG and Erbium Dopedlasers, analysis of synchronization methods andinnovative communications techniques, andmathematical analysis of synchronization of a fewand assemblies of chaotic oscillators with applicationto optical communications.

A "group meeting" workshop will be heldsemi-annually and each year we will invite experts inoptics, optical engineering, and opticalcommunications to provide additional research

expertise to broaden the horizons of the students,postdoctoral fellows, and faculty involved in thisproject

University of California - San Diego; Michael J Bailey,Ramesh C Jain: Making Rapid Prototyping Viable forRemote Use on the National Information Infrastructure;(MIP-9420099 A001); $318,305; 12 months.

This project is working to make rapidprototyping and reverse engineering facilitiesavailable over wide-area computer networks. Itincludes several research thrusts along with anintegration effort to ensure that the facilities will beusable remotely with little on-site intervention. Theproject has four major thrusts:1. development of algorithms for checking

consistency of geometric descriptions;2. development of new languages based on

constructive solid geometry for communicatinggeometric descriptions;

3. connection of rapid prototyping equipment to awide rear network, with device drivers andserver software to allow remote access;

4. connection of a 3D scanner to the network forremote access.

58 Experimental Systems

University of California - Santa Cruz; Richard Hughey,Kevin Karplus: Multi-Purpose Parallel Process forBiosequence Analysis; (MIP-9423985 A001, A002);$176,576; 12 months.

This project is building an application-specificcomputer system for biosequence comparison. Thearchitecture is suitable for a wide range of sequencecomparison methods, including the Smith- Watermanalgorithm, BLAST, profile searches and dictionarymethods. In addition, the architecture is beingintegrated with software for the statistical analysis ofsequences using techniques such as hidden Markovmodels.

The core of the architecture is a linear array ofSIMD processing elements, each with a small localmemory. A single chip can contain 64 of theseelements, so a board with 20 chips will hold 1280processors. The processing elements have beentuned to sequence comparison by incorporating asingle cycle add-and-min instruction and a data-pathfor quickly recording the results of the instruction. Software, I/O, and algorithms have been consideredin the design of this architecture; the resultingbalanced implementation should result in highperformance at low cost.

National Academy of Sciences; Ronald D Taylor:Assessment of Optical Science and Engineering;(ECS-9414956 A002); $6,500; 12 months; (Support from:Graduate Fellowships, Experimental Systems Program,Spectroscopy, Metals, Ceramics, And ElectronicMaterials, Quantum Electronics, Plasmas, andElectromagnetics, Instrumentation and InstrumentDevelopment - Total Grant $47,500).

The Board on Physics and Astronomy, incollaboration with the National Materials AdvisoryBoard, has established a committee to carry out amajor study of the field of optical science andengineering (OS&E), a diverse interdisciplinary areaof scientific and technological activity that is playingan increasingly area of scientific and technologicalactivity that is playing an increasingly important rolein driving economic growth. OS&E is emerging as akey enabling element for a host of applications thataddress critical national needs such as manufacturing,information technology, health care, transportation,environment, and education. It is also a vital area offrontier scientific research. The purpose of the studyis to define the field of optical science andengineering, assess the state of the art in research andtechnology, project the future impact of OS&E onnational needs, identify institutional and educationalinnovations needed to optimize the contributions ofOS&E to national needs, identify how public policyinfluences the ability of the field to meet these needs,

and examine trends in private and public researchactivities as compared to those in other countries. The study is being supported jointly by NSF, NIST,and ARPA. The Foundation of the report will bebased on the conduct of 5 major workshops; eachworkshop would be organized according to nationalneeds and would address issues that cross OS&Escientific and technical disciplinary boundaries.

University of Hawaii; Eun Sok Kim, Mehrdad G Nejhad,Junku Yuh, Stephen Y Itoga: Rapid Prototyping: VirtualRapid Prototyping System for Piezoelectric Micro Systems;(DMI-9420378 A001); $110,000; 12 months.

This award is to develop a virtual rapidprototyping system for piezoelectric micro systems(PMS). This is an area of Micro ElectromechanicalSystems (MEMS), where actuator or sensor devicesare built to the scale of a human hair. PMS's moveand either are driven by or produce electrical signals. Some examples are microphones, pumps, or motors. The rapid prototyping system that will be developedused computer simulation to design the PMS devices,design the special processes to make them, and doperformance tests on the virtual prototype. As partof the program this interdisciplinary team will buildthese devices using this system and compare theirvirtual system predictions with experimental data. The technological impact of this virtual rapidprototyping system will be reduced cost and lead timeby providing the engineering tools to design both thePMS devices and the processes to make them. Thismeans new competitive PMS-based products can bedesigned for commercial and industrial applications. This award will also build the research and humanresource infrastructure to be competitive in this areaof technology.

Massachusetts Institute of Technology; Robert Berwick; High Performance Computing for Learning; (IRI-9217041); $20,000; 12 months; (Support from: Roboticsand Machine Intelligece, Knowledge Models & CognitiveSystems, Linguistics, Human Cognition & Perception,Experimental Systems Program, CISE InstitutionalInfrastructure - Total Grant $636,944).

The Grand Challenge Application Groupscompetition provides one mechanism for the supportof multidisciplinary teams of scientists and engineersto meet the goals of the High PerformanceComputing and Communications (HPCC) Initiativein Fiscal Year 1992. The ideal proposal provided notonly excellence in science: focussed problem withpotential for substantial impact in a critical area ofscience and engineering) but also significantinteractions between scientific and computational

Experimental Systems 59

activities, usually involving mathematical, computeror computational scientists, that would have impactin high-performance computational activity beyondthe specific scientific or engineering problem area(s)or discipline being studied. In the award to Berwick,Bizzi, Bulthoff, Jordan, Wexler, Poggio, Rivest,Winston, and Yang at MIT, the research project -High Performance Computing for Learning - hasbeen designed explicitly to push the HighPerformance Computing algorithmic andarchitectural envelope via a CM-5 and VLSI testbedand to address many of the HPCC goals. It willadvance new algorithms and software for a broadclass of optimization and learning problems, testedon and directly driving operating system andarchitectural changes on the CM-5 (working with oneof the CM-5's key architects). The learning problemsaddressed are essentially an entire class ofmodeling/optimization problems that intersect withnearly all HPCC Grand Challenge Problems.

Massachusetts Institute of Technology; John L Wyatt,Ichiro Masaki: Cost-Effective Hybrid Vision System forIntelligent Highway Applications; (MIP-9423221 A001);$1,247,000; 24 months.

The goal of this project is a new cost-effectivearchitecture for machine vision, which will beevaluated for intelligent highway applications. Components of three smart image sensors are beingdeveloped and integrated into a heterogeneous visionsystem. The smart sensors use analog, digital, andmixed signal techniques to perform 3 dimensionalmeasurement for adaptive cruise control, lanedetection, and time-to-collision measurements. Allof these tasks are intended for machine visionsystems within intelligent vehicles, and will be testedin intelligent vehicle applications within the laterstages of the award. MIT is performing basicresearch on the first versions of all of these cameras,while later development, integration, and testing willbe carried out by industrial partners.

University of Michigan - Ann Arbor; A. Galip Ulsoy,Yoram Koren, Kang G Shin: Hierarchical Controller forReal-Time Quality Control in Machining; (DMI-9313222A003); $30,000; 12 months; (Support from: Robotics andMachine Intelligence, Experimental Systems Program,Manufacturing Machines and Equipment - Total Grant$151,628).

The award is for the design and development ofan experimental, modular, open-architecturemachining system controller for prismatic androtational parts that enhances part quality by an orderof magnitude while sustaining high machining rates.

The approach would enable integration ofunderutilized results of the prior work of variousresearchers as well as generating new results. Thehypothesis of the research is that informationembedded in the control-loop error signals can beeffectively used to improve part quality andmachining system performance. A hierarchicalcontroller structure is proposed consisting ofcompensators at the machine tool servo, process, andpart inspection levels. Intelligent integration ofhardware and software components of the controlleris proposed here by combining expertise in machinetools, machining processes, sensors, control theory,software architecture, and real-time computing.

The hierarchical, open-architecture controller isexpected to have a major impact on manufacturingpractice and research. Potential benefits forindustrial users include reduction of partmanufacturing cycle times, reduction of indirectinspection costs, controller improvement costs, andthe cost of using sensors. Implementation of futuremachining research results would also be facilitatedby the availability of such a controller.

Cornell University; Herbert B Voelcker: MassivelyParallel Computation for Mechanical Manufacturing andDesign; (MIP-9317620 A002); $402,326; 12 months.

Solid modeling is a critical enabling technologyfor mechanical CAD/CAM because it providesgeometrically complete representations of parts andproducts, and enables important manufacturingprocesses to be modeled. Today's industrial systemsoperate far below the technology's potential becausesolid modeling requires enormous computingresources, and because current algorithms andrepresentations cannot handle several importantapplications.

This project is designing new implementationsof ray-casting representations for the solid modelsused in mechanical CAD, and extending the modelsto new applications. New implementations forray-casting engines are being developed, using bothcustom hardware and software running on massivelyparallel machines. Using the new hardware, newapplications of ray representations are beingexplored, including the solution of boundary-valueproblems, computation of medial axis transforms,methods for representing mechanical tolerances, andrepresentation of solid objects.

60 Experimental Systems

State University of New York - Stony Brook; Arie EKaufman: Scalable Architecture for Real Time VolumeRendering; (MIP-9527694 A001); $194,063; 12 months.

This research deals with the development of anew scalable volume visualization architecture andits associated algorithms. The architecture, calledCube-4, exploits parallelism and pipelining toachieve real-time rendering of high-resolution imagesfrom volume data. The architecture is based on analgorithm for ray casting of a volume buffer ofvoxels which is stored as a skewed distributedmemory to support conflict-free access to voxelstructures. It performs interpolation of sampledpoints, shading, and compositing to generate thepixel values. Computations are done using limitedcommunication between processors, so that thearchitecture is scalable over a wide range ofperformances and image resolutions. This projectencompasses algorithm development, architectureresearch, and construction of a reduced-resolutionprototype.

University of North Carolina - Chapel Hill; Henry Fuchs,John W Poulton: ImageFlow: Real-Time Image-BasedRendering; (MIP-9612643); $483,131; 12 months.

Depth images are used as rendering primitives inthe high-performance graphics engine that is beingconstructed in this project. A depth image is a two-dimensional image that includes depth relative to aviewpoint, in addition to color and other properties. From a small number of depth images, each of whichrepresents an arbitrarily complex scene from a singleviewpoint, an image can be computed for anyviewpoint within the neighborhood of the originalviewpoints. This image-based rendering approachoffers advantages in realism and distributing therendering computation among processors thatgenerate depth images and those that reproject themto new viewpoints.

The project is using the existing PixelFlowgraphics engine to test the image- based renderingideas. During the first part of the project, algorithmsfor acquiring and pre-processing depth images willbe investigated. At the same time, the PixelFlowmachine will be enhanced for image acquisition andstorage. This will permit software for image-basedrendering to run in real-time on the PixelFlowmachine, performing the following operations:determination of reference images to be used assources of depth pixels, warping of reference imagepixels to the screen space, evaluation color, area, andother parameters for each pixel, and blending of

pixels to form the final reference image. In laterstages of the project, hardware support may bedeveloped and evaluated for some of theseoperations.

University of North Carolina - Chapel Hill; John WPoulton, Henry Fuchs: Scalable Graphics: From Personalto Supercomputer Visualization Engines; (MIP-9306208A007); (Support from: ARPA - Total Grant $803,641).

The object of this project is to build andexperiment with a new graphics engine that willeliminate the current limits to scalability incommercial graphics systems. The work centers ona new graphics engine architecture called imagecomposition, which is radically different from theorganization of today's commercial systems. Inimage composition, rendering is distributed over anumber of identical processors. Each renderergenerates a full-screen image, but for only a fractionof the primitives in the scene. The system thenmerges these images over a high-speed network toform a single image of all primitives. Since eachsubimage is independent, and since the images can bemerged on a distributed network whose throughputscales linearly with the number of subimages,performance of the entire system can be scaled uparbitrarily by adding more processors.

University of Oregon - Eugene; Zary Segall, Stephen FFickas: Collaborative Research: Architecture, Design andImplementation of Mobile Computers; (MIP-9403573A001); $194,615; 12 months.

This is a joint effort between two universities forrapid prototyping of mobile computers. The projectsinvolve teams of students who over the course of asemester design the hardware, software, andpackaging of mobile computer systems, and fabricateprototypes by combining standard electronic partswith custom fabricated cases and interconnectharnesses. This project focusses primarily on mobilecomputing for the diagnosis of telecommunicationsnetworks. Mobile computer systems that includestationary and mobile computers, interface devices,and software, are being designed and fabricated forthese applications. The project goal is to systematizethe prototyping process in several ways: by providingan integrated design tool that can simultaneouslyrepresent electronic, thermal, and mechanicalconstraints; by providing modular templatearchitectures for mobile computers; and by reportingon experience in the co-design of software, mobilehardware, and stationary hardware in a mobilecomputing system.

Experimental Systems 61

Carnegie-Mellon University; L. Richard Carley, David JAllstot, Rob A Rutenbar, Donald E Thomas: Design ofUltra-Low Power IC's; (MIP-9408457 A001); $300,000; 12months.

This project combines analog circuit design andCAD to produce digital circuits that can operate atsubstantially reduced voltages, which will result inlower power consumption. The project hasintroduced the QuadRail logic family, which allowsvoltage control of transistor thresholds to maintainconstant logic thresholds. Use of this family permitslower supply voltages because of the tighter controlof device thresholds. However, use of this familyrequires optimization of individual digital cells, newdevice layout methods, and new strategies forfloorplanning, placement, and routing. The researchin this project is exploring all of these optimizationareas, and is producing a battery powereddemonstration system for speech signal processing.

Carnegie-Mellon University; Susan Finger, Lee Weiss,Daniel P Siewiorek, Andrew P Witkin: Rapid DesignThrough Virtual and Physical Prototyping; (MIP-9420396A001, A002); $159,962; 12 months; (Support from:Experimental Systems Program, Integration Engineering -Total Grant $510,211).

This project is creating an experimental systemusing the Internet that will allow students in designcourses to use rapid prototyping services. Threeparticipant institutions, Carnegie-Mellon University,the University of California at Berkeley, andStanford University are participating in the project. Each has developed individual technologies forvirtual and physical prototyping, which currentlystand alone. Bringing these technologies togetherwill result in exciting new capabilities. Partnershipswith industrial partners and a Federal laboratory arealso anticipated. This project addresses key issues inprototyping, and is creating a network ofinterconnected services to support the rapid design,test, and manufacture of mechanical,electro-mechanical, and electronic products.

Carnegie-Mellon University; Ralph Hollis, MahadevSatyanarayanan, Mark H Kryder: HPCC: A DistributedArchitecture for Rapidly Reconfigurable Assembly Systems;(DMI-9527190 A001); $290,000; 12 months; (Supportfrom: Experimental Systems Program, ManufacturingMachines and Equipment, Integration Engineering - TotalGrant $539,953).

This research aims to improve assembly inproduct manufacturing. Assembly is a difficult andtime-consuming process to automate, especially when

small tolerances are necessary. This architecture foragile assembly is a strategic framework usingagent-based robotic elements that are precise,modular, and extensible. These elements form setsof leased self-contained software/hardware modulesthat can be programmed and operated over theInternet, and can be brought together to formminiature agile factories for assembly. Such ascheme requires a combination of intelligentnetworked communication, distributed computingresources using high-performance processors, anddistributed sensor/actuator subsystems of noveldesign. Design and construction of a prototypeminiature factory according to the principles of agileassembly architecture will be carried out to validatethe research and provide a unique and powerfulreconfigurable platform for assembly research andevaluation by industry. Partial assembly of magneticstorage disk drives will serve as a testbed.

This work aims to advance knowledge in threemain areas:1. seamless wide area and local area networking of

distributed agents emphasizing high quality ofservice;

2. modular precision robotic assembly elementscontaining high-performance embeddedprocessors; and

3. a comprehensive software environment formodeling, simulation, and programming of theminiature factories.The results of the research could allow

manufacturers to develop a capability forgeographically distributed design and deployment ofassembly systems while providing drastically reducedchangeover times, higher quality, and a new level ofmanufacturing system portability.

Carnegie-Mellon University; Daniel P Siewiorek:Collaborative Research: Architecture, Design andImplementation of Mobile Computers; (MIP-9403473 A002,A003); $210,000; 12 months.

This is a joint effort between two universities forrapid prototyping of mobile computers. The projectsinvolve teams of students who over the course of asemester design the hardware, software, andpackaging of mobile computer systems, and fabricateprototypes by combining standard electronic partswith custom fabricated cases and interconnectharnesses. This project focusses primarily on mobilecomputing for the diagnosis of telecommunicationsnetworks. Mobile computer systems that includestationary and mobile computers, interface devices,and software, are being designed and fabricated forthese applications. The project goal is to systematizethe prototyping process in several ways: by providingan integrated design tool that can simultaneously

62 Experimental Systems

represent electronic, thermal, and mechanicalconstraints; by providing modular templatearchitectures for mobile computers; and by reportingon experience in the co-design of software, mobilehardware, and stationary hardware in a mobilecomputing system.

Carnegie-Mellon University; D. Lansing Taylor, Scott EFahlman: High Performance Imaging in BiologicalResearch; (DBI-9217091 A007, A009); $100,000; 12months; (Support from: Knowledge Models and CognitiveSystems, Robotics and Machine Intelligence,Neuroscience, Experimental Systems Program, CellBiology - Total Grant $600,000).

The Grand Challenge Application Groupscompetition provides one mechanism for the supportof multidiscipinary teams of scientists and engineersto meet the goals of the High PerformanceComputing and Communications (HPCC) Initiativein Fiscal Year 1992. The ideal proposal providednot only excellence in science: focussed problemwith potential for substantial impact in a critical areaof science and engineering) but also significantinteractions between scientific and computationalactivities, usually involving mathematical, computeror computational scientists, that would have impactin high-performance computational activity beyondthe specific scientific or engineering problem area(s)or discipline being studied.

This is a project to research and develop anAutomated Interactive Microscope (AIM). TheAIM will combine the latest technologies in lightmicroscopy and reagent chemistry with advancedtechniques for computerized image processing, imageanalysis, and display, implemented onhigh-performance parallel computers. Thiscombination will produce an automated, high-speed,interactive tool that will make possible new kinds ofbasic biological research on living cells and tissues. While one milestone of the research will be to showthe proof-of-concept of AIM, the on-going thrust willbe continued development as new technologies ariseand the involvement of the biological community.

Pennsylvania State University; Robert M Owens, Mary JIrwin: Architecture, Algorithms and Software in the Designof a Massively Parallel, Fine Grain Processor;(MIP-9408921 A001, A002); $180,326; 12 months.

This project is investigating the design,implementation, and use of a family of family ofmassively parallel computers that use one processorper digit. A first generation design, completed in an

earlier project, contains 16,384 fine grain processorson a single board. The processors contain a smallnumber of parallel logic circuits and a configurationmemory that controls the logic and interconnect. The entire machine is programmed for a problem bysetting all configuration registers to transform themachine into a special-purpose computer for theproblem. By improving the density of processors onchips and the speeds of interconnect and interface,this project is increasing the operation rate of themachine by a factor of 4 to 10. In addition to thedesign and implementation of architectures, thisproject is developing both high and low levelprogramming tools for the machines. Finally,algorithms for solving compute intensive problemson these machines are being developed and tested.

Brown University; Harvey F Silverman: A Large-Scale,Intelligent Three-Dimensional Microphone-ArraySound-Capture System; (MIP-9314625 A005); $16,964.

This is a joint project between Brown andRutgers to build a large microphone array withassociated processors for beam forming. Applications are direction finding, echo cancellation,and speaker differentiation in telconference systems,multimedia educational systems, and largeconference centers. Groups of microphones sharemicrophone modules that perform A/D conversionand low-level processing. The microphone modulesare linked over a high speed serial network (possiblyoptical) to a multiprocessors signal processing systemfor the higher level processing. The resulting systemis being evaluated in an experimentalteleconferencing facility.

Experimental Systems 63

Other

National Institute of Standards and Technology; JudsonFrench: Purchase of Optoelectronic Prototypes by the U. S. Broker - Interagency Transfer; (ECS-9530730 A001);$50,000; 12 months; (Support from: ExperimentalSystems Program, Quantum Electronics, Plasmas, andElectromagnetics - Total Grant $150,000).

The Joint Optoelectronic Project (JOP) is a jointprogram entered into by the U. S. and JapaneseGovernments to provide prototyping services forexperimental optoelectronic devices and modules. The goals of the project are to establish a jointresearch project in optoelectronics to improve theavailability of novel prototype optoelectronicmaterials, devices, circuits and modules by providingusers with access to leading edge optoelectronicfabrication facilities, to stimulate research activitiesin optoelectronics for computing in both the U. S. and Japan and to encourage effectivecommercialization. The funds provided in thisaward will be used to help support U. S. userparticipation in the JOP. It is anticipated that thenovel, custom-designed optoelectronic devices andmodules obtained using the broker facility willadvance device and systems research activities withinthe academic community.

Salk Institute for Biological Studies; Terrence JSejnowski: Workshop on Neuromorphic Engineering; June25, 1995 - July 8, 1995; Telluride, Colorado; (IBN-9511637A001); $5,000; 12 months; (Support from: InteractiveSystems, Experimental Systems Program,Neuroengineering, Computational Neuroscience,Computational Biology Activities - Total Grant $48,880).

Recently a new field of engineering hasemerged, referred to as neuromorphic engineering,that is based on the design and fabrication ofartificial neural systems, such as vision chips,head-eye systems, and roving robots, whosearchitecture and design principles are based on thoseof biological nervous systems. A two-weekworkshop on neuromorphic engineering will be held

to bring together young investigators and more establishedresearchers from academia with their counterparts in industryand national laboratories, working on both neurobiological aswell as engineering aspects of sensory systems andsensory-motor integration. Formal lectures will be given, butthe primary focus will be hands-on experience with researchtools for all participants. The workshop will serve as a bridgebetween the engineering world of artificial neural systems andthe neuroscience community. The workshop will provide anenvironment for intensive interactions between members ofthese two communities - merging engineering principles withexperimental results from neuroscience. The interaction ofthese two disciplines should have significant impact both onthe development of new technologies (new artificial neuralsystems) and on our understanding of how the nervous systemis designed.

University of Washington; Lawrence Snyder: Conferenceon Experimental Research in Computer Science, June20-21, 1996, Arlington, Virginia; (MIP-9634389); $33,681;6 months.

This award supports a conference to assess thecurrent status and future prospects for experimentalcomputer science research in the United States. Thegoals are to highlight progress in experimentalresearch, largely using selected projects funded bythe ES program, to discuss issues of importance tothe fields practitioners in panel sessions, and tofurther an awareness of experimentation amongpolicy makers. Researchers, policy makers,administrators, and leaders from academia, industry,and government will attend. A proceedings will bepublished.

Prototyping Tools and Methodology 65

Prototyping Tools and Methodology(Formerly System Prototyping and Fabrication)

Dr. Michael Foster. Acting Program Director(703) 306-1936 mfoster@note.nsf.gov

The Program

Vision and Goals

The Prototyping Tools and Methodology (PTM) program addresses rapid prototyping technologies. The goal is todevelop and integrate the tools and technologies needed for rapid and efficient design and fabrication of products,processes and systems. The PTM program consists of three principal elements. The first (systems prototyping)supports fundamental research on rapid system prototyping methodologies, tools, environments, etc. with particularinterest in the informational infrastructure needed for prototyping systems (virtual prototyping). The second(microfabrication) supports research related to advancing the state of the art in the modeling and control aspects ofthe fabrication (physical prototyping). The third element (education) provides assistance to microelectronicseducation through support of MOSIS and administrative oversight for its involvement in microfabrication foreducational institutions.

Strategies

Strong interaction exists with the educational VLSI community through the MOSIS service. Every yearapproximately 5000 students in over 180 classes design custom VLSI chips to be fabricated through the MOSISservice. Special workshops are conducted at NSF, such as the 1996 Workshop on Integration of Education andResearch in Microelectronics, to monitor and refocus the educational MOSIS program. Additionally, a series ofworkshops on emerging research in advanced manufacturing are sponsored. The 1995 NSF Workshop on StructuredDesign Methodologies for Micro-Electromechanical Systems (MEMS) brought together outstanding researchersfrom university and industry to address research directions.

Key Research Problems

Initiatives in this program include research in rapid prototyping for advanced manufacturing. New tools andtechnologies for virtual prototyping coupled with innovative services and an updated infrastructure that allowsdistributed rapid prototyping over high speed networks are of particular interest. Projects include new languages formachine and process design, and CAD/CAM integration, as well as projects encompassing modeling, simulation,model validation, and design tools and techniques. Research dealing with the application of useful VLSI designparadigms to SFF (Solid Free-form Fabrication) and MEMS (Micro-ElectroMechanical Systems) are alsoaddressed.

Prototyping Tools and Methodology 67

Awards

Prototyping

Microelectronic

University of California - San Diego; Chung-Kuan Cheng; Research on Rapid Prototyping Systems Using FieldProgrammable Devices; (MIP- 9529077); $175,479; 12months.

Rapid prototyping systems composed ofprogrammable gate arrays present many technicalchallenges affecting system utilization andperformance. The objective of this research is thedevelopment of engineering methodologies whichaddress these currently unresolved technical issues. Current rapid prototyping systems suffer severalshortcomings, including engineering bottleneckscaused by time- consuming mapping processes,inadequate performance for real-time emulation of high-speed systems, and high cost resulting frompoor system utilization due to the severe /IO limit ofprogrammable devices. The proposed researchtargets these key areas. Both hardware and CADalgorithm issues will be addressed. The proposedproject will contribute to identify the bottlenecks ofcurrent prototyping systems and discovering novelsolutions. This research will contribute to fastermapping processes, low cost - high utilizationsystems, and real-time emulation.

University of California - Santa Barbara; MalgorzataMarek-Sadowska: Research on Layout and Logic Design;(MIP-9419119 A001); $40,000; 12 months; (Support from:Prototyping Tools and Methodology Program, DesignAutomation Program - Total Grant $143,000).

The proposed research is on layout drivensynthesis, i. e. the intersection of logic synthesisand physical design. The focus is on restructuringlogic networks in synthesized digital systems. Fourtopics, which meet the goals of improving routingefficiency or power consumption, are beinginvestigated. These are:4. Incremental logic resynthesis to control wiring,5. Coupling wiring with logic restructuring and

finding optimizations to eliminate wiringoverflows.

6. Use of generalized Reed-Muller forms toanalyze logic as an aid to: - designing celllibraries and for technology mapping, -developing new multi level optimizationtechniques, - designing networks of provably

good testability.7. Develop new methods for power optimization, at

the technology independent and technologydependent levels in logic synthesis, and also findbetter routing tools to handle power constraints.

University of Florida; Mark E Law: PFF: A Multi-disciplinary Approach to IC Process Modeling Using theSUPREM-IV Modeling Tool; (MIP-9253735 A004);$100,000; 12 months.

This multidisciplinary research focuses on thedevelopment of silicon models for point defectbehavior, which are vital to understanding dopantdiffusion. Models are being developed andparameterized for the effect of silicidation and stresson point defect kinetics. These models are thenimplemented in SUPREM-IV, a standard integratedcircuit process modeling tool that utilizes advancedfinite element techniques. This is a PresidentialFaculty Fellow (PFF) Award initially awarded inFiscal Year 1992.

Southern Illinois University - Carbondale; RalphEtienne-Cummings:CAREER: VLSI Implementation ofComputation Sensors for Visual Information Processing;(MIP-9624141); $200,000; 48 months.

This proposal describes the design andimplementation of VLSI vision systems for real-timedynamic tasks. The two part career plan developssmart application specific and general purpose visualcomputational sensors which may be used with otherintelligent systems to realize solutions to variousrobot vision and image processing problems. Thethree part research tasks are:1. the development and implementation of compact

VLSI algorithms for image acquisition, edgedetection and motion detection;

2. applications of these algorithms to specificproblems such as image velocitometry, targettracking and rudimentary line-following auto-navigation and

3. development of a general purpose VLSIcomputational sensor which performs imageacquisition, edge detection and 2D optical flowmeasurement in a single compact system.

68 Prototyping Tools and Methodology

The goals of the educational component of thisproposal include inclusion of VHDL tools intointroductory undergraduate digital design courses,and the development of VLSI courses in imagingtechnology and mixed digital/analog signalprocessing with fabrication and testing requirements.

University of Illinois - Urbana-Champaign-Urbana; FaridN Najm:CAREER: Reliability Engineering for IntegratedCircuits; (MIP-9623237); $200,000; 48 months.

A methodology is to be developed which allowsdesigners to do reliability prediction and reliabilitybudgeting using a high-level functional description ofthe design. Prediction models at the gate andfunction level will be developed and verified usingobserved data. Under reliability budgeting aspecified failure rate, or mean-time-to-failure, for thewhole chip may be partitioned to provide reliabilitytargets for smaller pieces and thus lower levels ofabstraction. The work leads to the development of anew course in "Reliability Engineering for IntegratedCircuits", which will provide a software environmentwhere ICs may be subjected to stress test experimentsin virtual environment at various design stages usingobservational data.

University of Notre Dame; Jay B Brockman: CAREER:Concurrent Optimization of Cell Libraries and FabricationProcesses; (MIP-9625152); $200,000; 48 months.

This research proposes to develop techniques forconcurrent optimization of both the circuit celllibraries and the fabrication process. A keyadvantage of the proposed approach is that it allowsboth the circuit designer and fabrication processengineer to work towards the common goal ofmaximizing yield, which will in turn reduce productcost. A second advantage is that through concurrentengineering, this approach can significantly reduceproduct development time. Provisions have beenmade for validating proposed techniques in anindustrial setting. The research component of thisproposal is also complemented by an extensiveeducation plan for integrating studies in concurrentdesign into the undergraduate curriculum.

University of Kentucky; Charles E Stroud: RIA:Self-Testing, Diagnostic and Repair Configurations forField Programmable Gate Arrays; (MIP-9409682 A001);$10,000.

This research is directed at system level testingby developing algorithms and circuit configurationswhich can be loaded into FPGA's to provide

self-testing, fault diagnostic and repair capabilities. Once faults in an FPGA have been detected andidentified, reconfiguration algorithms would then beused to remap the system function into the FPGAwhile avoiding the existing faults. It is conjecturedthat by using this approach, development ofapplication-specific system diagnostic software fortesting the FPGA system function can be avoided.

University of Maryland - College Park; K. J. Ray Liu:NYI: High Performance Computing for Signal Processing;(MIP-9457397 A002); $31,250; 12 months; (Support from:Prototyping Tools and Methodology Program, SignalProcessing Systems Program - Total Grant $62,500).

There are three major architectural models usedin high-performance signal/image processing:1. VLSI- signal processing - high- throughput

VLSI architectures for low-costapplication-specific implementations used inapplications such as communication systems,speech, video/HDTV, and radar;

2. parallel signal processing on massively parallelcomputers - parallel algorithms for complexsignal/imaging systems used in computer vision,medical imaging, and the processing of vastamounts of data in deep space exploration; and

3. distributed signal processing on high-speednetworks - used in applications such asdocument image processing, multimedia,automatic signal processing in manufacturing,and medical signal/image processing. This research focuses on the development of

efficient algorithms and architectures for eacharchitectural model, and in comparative studies of theadvantages and disadvantages of these differentcomputing schemes. The goal is to investigatewhich signal/image processing problems can becarried out optimally under different computing andcommunication schemes.

University of Maryland - College Park; Linda Milor: AStatistical Modeling Methodology for Submicron MOSDevices and Circuits; (MIP-9501912 A001); $10,000.

The performance of an integrated circuit dependson the designers' choices and the process engineers'decisions during the manufacture of the device. Typically the choices and decisions are independentof each other with little awareness of the interplay ofthe two engineering domains.

This research develops methods for raising thedesigners' awareness of the effects of circuitimplementation parameters and to sensitize processengineers to the impact of processing decisions onthe performance of the final circuit. A statistical

Prototyping Tools and Methodology 69

model is developed to correlate device and processparameters, primarily to establish circuit performancevariations on spatial and process dependencies inreplicated circuits. Circuit simulators are used tosolve the resultant (huge) set of nonlinear differentialequations.

Michigan Technological University; Ashok K Goel, EstherT Ososanya: Experimental Validation of Interconnectionand Transistor Delay Models for the GaAs-Based IntegratedCircuits; (MIP-9223989 A004); $10,000; 12 months.

During the last few years, GaAs technology hasemerged rapidly from basic research to device andcircuit development. It is crucial to know theexpected propagation delays in an integrated circuitbefore it is fabricated. To meet this objective,numerical models have been developed that addresscrosstalk and propagation delays in the parallel andcrossing VLSI multilevel interconnections as well asfor the transverse delays in the GaAs MESFETs andGaAs/AlGaAs MODFETs. In addition todetermining the crosstalk and propagation delays, themodels can be utilized to achieve the optimization ofthe device and interconnection dimensions and otherparameters for minimum crosstalk and delays. Validation of these numerical models by comparisonof the modeling results with actual experimentalobservations is critical if they are to be incorporatedinto GaAs CAD tools. This research effort focuseson the following set of objectives:1. design and fabrication of several GaAs-based

logic circuits to retain the ability to alter thevarious design parameters;

2. application of the interconnection and the GaAsMESFET delay models recently developed forthe determination of propagation delays in theseGaAs-based logic circuits;

3. experimental measurements of propagationdelays in these circuits and comparison withdeveloped delay models;

4. modification of the interconnection andtransistor delay models, as required; and

5. experimental validation of the final models.

Cornell University; Geoffrey M Brown: Data AcquisitionSystems with User Configurable Hardware; (MIP-9530811,A001); $162,295; 24 months.

This project develops a new class of dataacquisition systems with user configurable hardware. The primary development effort is the creation ofsoftware tools which will enable scientists andengineers who are not skilled hardware designers toutilize such systems. Some of the primary researchissues are the development of techniques for

specifying and analyzing timing behavior betweenfixed and configurable hardware and thedevelopment of techniques for designing robustinterfaces.

A typical application of this work is areconfigurable data acquisition card consisting of afixed analog section and a configurable digitalsection built from one or more field programmablegate arrays (FPGAs) and static RAM chips. Existingdata acquisition cards are generally used by scientistsand engineers who are not skilled hardwaredesigners; however, the currently available tools forFPGAs require significant digital design experience. For a reconfigurable data acquisition card to beuseful, it is necessary that the configuration toolsaccept as input high level programming languagewhich is accessible to a competent programmer. Any custom hardware necessary to interface theanalog sections or host CPU must be provided in theform of libraries which can be conveniently linked tothe user's code.

State University of New York - Binghamton; JiayuanFang: NYI: Analysis and Modeling of High-SpeedInterconnects in Electronics Packaging; (MIP-9357561A003); $74,000; 12 months.

This research is concerned with the analysis andmodeling of electrical performance of high-speedinterconnects in electronics packaging. Thefinite-difference time-domain (FDTD) method,which is a full-wave solution of Maxwell's equationsin three dimensions, is used to simulate signalpropagation through interconnects. Topics pursuedare:1. Development of a computational scheme for

conformed finite-difference grid to modelcomplex-shape interconnects. The objective ofthis scheme is to enhance the resolution andaccuracy of numerical solutions whilemaintaining the computation efficiencyassociated with the regular rectangularfinite-difference grid.

2. Analysis and modeling of electrical properties ofinterconnection discontinuities in electronicspackaging. Issues involved in this topic include:modeling of electrical characteristics ofinterconnection discontinuities over thefrequency range from dc to tens of gigahertz;evaluation of impacts of parasitics associatedwith interconnection discontinuities on thepropagation of high-clock rate signals; anddevelopment of design guidelines for typicalinterconnection discontinuities in highperformance electronics packaging.

70 Prototyping Tools and Methodology

North Carolina State University - Raleigh; Paul DFranzon: NYI: Advanced Interconnect and DisplayApproaches; (MIP-9357574 A003); $62,500; 12 months.

The primary focus of this work is to resolveissues dealing with the design and implementation ofhigh bandwidth reconfigurable interconnect systemsbased on Micro ElectroMechanical Systems (MEMS)which are commonly referred to as Micromachines. Different guided-wave optical and holographicfree-space optical switch elements are beingimplemented and compared in terms of bandwidth,switch reconfiguration rate, and range ofprogrammability. Application to data switching, andprogrammable interconnect devices for rapidprototyping are being addressed with attention toboth technological and system-wideperformance/cost design issues. Comparisons aremade with conventional technologies. Also beinginvestigated is the application of some of the opticalMEMS elements to advanced image projection.

University of North Carolina - Charlotte; Dian Zhou:NYI: Performance-Driven VLSI Designs; (MIP-9457402A002); $32,750; 12 months; (Support from: PrototypingTools and Methodology Program, Design AutomationProgram - Total Grant $65,500).

Three research in high-performance VLSIsystem design are being addressed:1. how to relate the system performance function,

characterized by electrical parameters, to thegeometrical parameters of the VLSI physicaldesign;

2. how to model performance driven VLSI physicaldesigns based on given technology andcomputational capability; and

3. how to characterize the fundamental computationalaspects of modeled problems and develop effectivealgorithms for solving them.A distributed RLC circuit model for

interconnects is being designed. It considers: non-monotone circuit response, coupling effects amongthe signal lines, and low energy consumption. Efficient computation methods that solve time-varying Maxwell equations using the adaptivewavelet collocation method are being devised. Thealgorithms and methods are being included in a CADsystem.

University of Washington; Susan Eggers; SimultaneousMultithreading; (MIP- 9632977); $3318,305; 24 months;(Support from: Experimental Systems Program,Prototyping Tools and Methodology - Total Grant$519,164).

This is a project to develop and extend supportfor multithreaded computation on superscalarprocessors. The intention is to provide highprocessor utilization despite increasing memorylatency. In simultaneous multithreading, multiple independent threads will issue instructions to asuperscalar processor's functional units in a singlecycle. The objective of this project is to fully definethe low-level architecture for simultaneousmultithreading, including scheduling, registerarchitecture, pipeline design, and speculativeexecution. The project is developing compiler andoperating systems support for multithreadedexecution on the new processor architecture. Aprimary goal is to maximize multiple threadperformance without increasing single thread latency.Most measurements are from detailed simulations,using simulators and compilers provided byindustrial partners.

MEMS, SFF, MCM

University of California - Berkeley; Carlo H Sequin, PaulK Wright: Rapid Prototyping Interface for 3D Solid Parts;(MIP-9632345); $301,123; 24 months.

It is proposed to develop a simple and clearlanguage for use as a digital interface in SolidFree-Form Fabrication. This language is called"SIF" for "Solid Interchange Format" inspired byCIF, the Caltech Intermediate Form for LSI layout

description. The role of SIF would be to describethe ideal solid part desired, in a fabrication-process-independent way. It is further proposed to create afoundation for some of the key tools needed withsuch an exchange language, in particular, a robustslicing tool to create 2.5D layers needed for processplanning, as well as checker programs that will verifythat the shape specified in the SIF file is indeed aclosed solid, has the required topological and

Prototyping Tools and Methodology 71

geometric properties, and specifies only realizablefeatures containing certain minimum feature sizesand separations.

Finally, it is proposed to develop test structuresof various kinds that will test the robustness ofanalysis and conversion tools working from SIF inputfor different SFF fabrication processes and tomonitor the quality of individual production runs.

University of California - Los Angeles; K J Pister:CAREER: MEMS for the Masses; (MIP-9624124);$135,000; 48 months; (Support from: Prototyping Toolsand Methodology Program, MicroelectromechanicalResearch - Total Grant $200,000).

A method is proposed for the decoupling ofdesign and manufacturing of micro-electromechanical systems (MEMS) and devices. Adesign infrastructure is to be developed that willallow non-experts to quickly design and simulateMEMS devices and systems. The philosophyfollows the VLSI paradigm, where there is a clearseparation between the wafer fabrication and thedesign effort that creates the pattern which is to beimplemented.

MEMS software tools, device models, andeducational materials will be made available on theInternet. These tools will include schematic editing,layout synthesis, parameter extraction and simulation.

The proposal also contains a strong educationplan extending the PI's successes in recruitingundergraduates, including women andunder-represented minorities, to become researchstudents.

University of Central Florida; Aravinda Kar, AmarMukherjee: Design Methodology for Laser-Aided DirectRapid Prototyping (LADRP); (MIP-9625752); $269,187; 24months.

The proposed study is concerned with a one-stepdirect process to fabricate three-dimensional partsusing a laser beam. This process is referred to as theLaser-Aided Direct Rapid Prototyping (LADRP). Laser light can melt and/or vaporize virtually anymaterial and laser tooling leads to the unification ofvarious conventional tools because a laser beam canbe used to carry out many different machiningoperations such as cutting, drilling, welding andmilling. Such process integration is very importantfor the rapid production of three- dimensional partsdirectly in near net shape.

The success of the proposed rapid prototypingprocess depends on the development of systematic

design methodologies and developing suitable digitalinterfaces between design and manufacturing. Theproposed research will carry out experimental studiesand develop mathematical models for the LADRPprocess, and will develop design rule characterizationof the LADRP process so that lower- level CADtools for process planning simulation and verificationmay be implemented. A layered descriptionlanguage will be developed that can generate theslices of 2.5-D layers for the part from an input filespecified in some higher level description languagesuch as the STL or ACIS format.

Carnegie-Mellon University; Gary K Fedder:CAREER:Schematic Design for Microelectromechanical Systems;(MIP-9625471); $200,000; 48 months.

The proposed research deals with developingtools for the design of suspended micromechanicalsystems. A Schematic design methodology is to bedevised which complements and builds upon existingdesign tools, chiefly commercial CAD packages thathandle 3D visualization, finite-element analysis,macromodeling and simulation. The work includes:general design methodology; schematic design,including validation; identifying reusablecomponents; generalized component interface;creating a set of lumped-parameter componentmodels and design, fabrication and test of prototypecomponents.

University of Pennsylvania; Ruzena K Bajcsy, DimitriMetaxas, Vijay Kumar, Daniel K Bogen: RapidPrototyping of Rehabilitation Aids for the PhysicallyDisabled; (MIP-9420397 A002, A003); $92,180; 12months; (Support from: Prototyping Tools andMethodology Program, CISE Institutional Infrastructure- Total Grant $342,180).

The methods of rapid prototyping are ideallysuited to rehabilitation devices. Because eachperson requires unique performance and function in arehabilitation device, devices specific to each personmust be rapidly designed and produced. This projectis investigating a completely integrated approach tothe design and prototyping of passive mechanicalrehabilitation devices. The approach involves: thequantitative assessment of the form and performanceof human limbs; the design of the assistive device;evaluation of the device using virtual prototyping;feedback from the consumer and therapist; actualprototyping of the device; evaluation of the functionand performance of the device; and redesign basedon performance. The contributions of the product

72 Prototyping Tools and Methodology

include: the development of new computer-basedtools for the assessment of human performance; amanufacturing technique for a new class ofhyperelastic materials; the integration of tools into arapid prototyping system for rehabilitation devices;and development of mechanisms for systematicevaluation of the final product.

West Virginia University; Lawrence A Hornak: NYI:Cointegrated Polymer Waveguide Optical Interconnectionsfor Wafer-Level MCM Systems; (MIP-9257101 A004);$62,500; 12 months.

Motivated by the need for robust polymersoptically superior to polyamides yet suitable forcointegration of optical interconnection waveguides

directly with the active CMOS interconnection substrate ofadvanced multi-chip modules (MCMs), the research seeks tofabricate the first optical waveguides withpolyphenylsilsesquioxane (PPSQ), a spin castable, lowtemperature processed silicon ladder polymer used as a thinand thick film dielectric for microelectronics. This materialpotentially offers the low loss obtainable with less stableoptical polymers while offering thermal stability and processlatitude (patterning, wet, dry etching) exceeding that ofpolyamide. This research assesses the suitability of PPSQtogether with planarizing and superstrate polymer layers forproviding a multilayer system supporting fabrication of highdensity waveguide arrays directly over the Si devices ofemerging active MCM substrate.

Education

California Institute of Technology; Erik K Antonsson: AWorkshop on Structured Design Methods for MEMS;November 12-15, 1995, Pasadena, California;(MIP-9529977); $48,464; 12 months.

This is a proposal to hold a workshop involvingabout forty leading researchers from academia andindustry to discuss:1. the importance and value of Structured Design

Methods for MEMS;2. the research opportunities in this area, and,3. the likely increase in effectiveness of MEMS

design utilizing these methods.

Earmark Inc; Elisabeth Perez-Luna: Intersections: Art,Science and Technology -- A Radio Project; (ESI-9634183);$8,000; 12 months; (Support from: Informal ScienceEducation, Prototyping Tools and Methodology Program,Signal Processing Systems Program - Total Grant$25,000).

This project will examine the implications of theintersection of art, science, and technology asrevealed by the events occurring around thecelebration of the fiftieth anniversary of the firstgeneral electronic computer, ENIAC-50. Thefinished product will be radio programming andaudio material that presents the coming together ofscientists, artists, and other participants inPhiladelphia. It will build on the previous researchand explorations in both of these fields towardfinding commonalties and ways in which each hasinfluenced the other. The finished product will bebroadcast for the general public and also can be madeavailable to scientists and educators in the field asresource material for courses, seminars, and lecturesas they explore the intersections of science and artand implications this has for research and education.

Prototyping Tools and Methodology 73

Infrastructure

Advanced Research Projects Agency; Robert F. Lucas;NSF/ARPA Agreement for Use of ARPA VLSIImplementations; (MIP-9419682 A001); $350,000; 12months; (Joint support with the MicroelectromechanicalResearch Program, the Manufacturing Machines andEquipment Program, and the DUE Course andCurriculum Program - Total Grant $800,000).

A 1994 Memorandum of Understanding (MOU)between the National Science Foundation (NSF) andthe Advanced Research Projects Agency (ARPA)extended a three-year joint program supporting VLSI(Very Large Scale Integration Fabrication) byMOSIS (Metal Oxide Semiconductor ImplementationService) for qualifying educational institutions. The

continuation of the MOU expands the original program toaccelerate critical capabilities for Microsystems Design andPrototyping in U.S. educational institutions. This includesexpanding the original services and technologies available toschools authorized to use MOSIS as they become generallyavailable and cost-effective (e.g., semi-custom and galliumarsenide chip fabrication), stressing VLSI education,especially undergraduate education needed for designingfuture electronic system; exploring new fabrication servicesdesigned specifically for the research and educationcommunity's desire for cost effective experimentation of state-of-the-art technologies (e.g., design of advanced sensor andmicro-mechanical devices); and rapid prototypingmethodologies, tools, and services needed for completesystems.

Index 75

Index of PYI, NYI, CAREER, and PFF Investigators

CAREER Faculty Early Career DevelopmentNYI NSF Young InvestigatorPYI Presidential Young InvestigatorPFF Presidential Faculty Fellow

BBaraniuk, Richard G . . . . . . . . . . NYI . . . . . . . . . . . . . . . 36Bresler, Yoram . . . . . . . . . . . . . . . PYI . . . . . . . . . . . . . . . 37Brockman, Jay B. . . . . . . . . . . . . CAREER . . . . . . . . . . . 68Buckley, Kevin M . . . . . . . . . . . . PYI . . . . . . . . . . . . . . . 43Burns, Steven M. . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . . 9

CChapman, Richard O . . . . . . . . . . CAREER . . . . . . . . . . . . 3Chen, Peter M. . . . . . . . . . . . . . . CAREER . . . . . . . . . . . 27Cong, Jason. . . . . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . . 3Conte, Thomas M . . . . . . . . . . . . . CAREER . . . . . . . . . . . 21Cosman, Pamela C. . . . . . . . . . . . CAREER . . . . . . . . . . . 36

DDevadas, Srinivas . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . . 7

EEtienne-Cummings, Ralph. . . . . . CAREER . . . . . . . . . . . 67

FFang, Jiayuan . . . . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . 69Farrens, Matthew. . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . 19Fedder, Gary K . . . . . . . . . . . . . . . CAREER . . . . . . . . . . . 71Ferguson, Frankie J. . . . . . . . . . . PYI . . . . . . . . . . . . . . . 13Fiez, Terri S. . . . . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . 34Franzon, Paul D. . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . 70

GGreen, Michael M . . . . . . . . . . . . NYI . . . . . . . . . . . .11, 49

H

Hornak, Lawrence A. . . . . . . . . . NYI . . . . . . . . . . . . . . . 72

JJacome, Margarida . . . . . . . . . . . . CAREER . . . . . . . . . . . . 8

KKahng, Andrew B . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . . 4

LLarrabee, Tracy . . . . . . . . . . . . . . PYI . . . . . . . . . . . . . . . 13Law, Mark E . . . . . . . . . . . . . . . . PFF . . . . . . . . . . . . . . . 67Li, Jian . . . . . . . . . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . 42Liu, K.J. Ray . . . . . . . . . . . . . . . . NYI . . . . . . . . . . . .47, 68Loughlin, Patrick . . . . . . . . . . . . . CAREER . . . . . . . . . . . 35

MMalik, Sharad. . . . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . 11Myers, Chris J . . . . . . . . . . . . . . . CAREER . . . . . . . . . . . . 8

NNagle, David F . . . . . . . . . . . . . . . CAREER . . . . . . . . . . . 22Najm, Farid N . . . . . . . . . . . . . . . CAREER . . . . . . . . . . . 68

OOrchard, Michael T. . . . . . . . . . . NYI . . . . . . . . . . . . . . . 37

PParhi, Keshab K . . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . 48Pedram, Massoud . . . . . . . . . . . . . NYI . . . . . . . . . . . . . 4, 20Peir, Jih-Kwon . . . . . . . . . . . . . . . CAREER . . . . . . . . . . . 24Pister, K J . . . . . . . . . . . . . . . . . . . CAREER . . . . . . . . . . . 71Pomeranz, Irith . . . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . 13Prince, Jerry L . . . . . . . . . . . . . . . PFF . . . . . . . . . . . . . . . 38

RRiskin, Eve A . . . . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . 41Robins, Gabriel . . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . . 9

SSapatnekar, Sachin . . . . . . . . . . . . CAREER . . . . . . . . . . . 20Schultz, Richard R. . . . . . . . . . . . CAREER . . . . . . . . . . . 40Shanbhag, Naresh. . . . . . . . . . . . CAREER . . . . . . . . . . . 10Shetler, Joy S. . . . . . . . . . . . . . . . CAREER . . . . . . . . . . . 19Siu, Kai-Yeung . . . . . . . . . . . . . . . NYI . . . . . . . . . . . .23, 48Stonick, Virginia L . . . . . . . . . . . . PYI . . . . . . . . . . . . . . . 35

TTorrellas, Josep. . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . 54

VVarma, Anujan . . . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . 19

XXu, Guanghan . . . . . . . . . . . . . . . CAREER . . . . . . . . . . 44

YYang, Woodward. . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . 33Yang, Andrew T. . . . . . . . . . . . . . NYI . . . . . . . . . . . . . . . 12Yun, Kenneth Y. . . . . . . . . . . . . . CAREER . . . . . . . . . . . . 4

ZZhou, Dian. . . . . . . . . . . . . . . . . . NYI . . . . . . . . . . . . . 7, 70

Index 77

Index of Principal Investigators

AAbarbanel, Henry D. I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Allstot, David J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Anderson, Charles W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Antonsson, Erik K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 72Arce, Gonzalo R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

BBailey, Michael J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Bajcsy, Ruzena K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Banerjee, Prithviraj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Baraniuk, Richard G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Barnwell, Thomas P. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Berwick, Robert. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Bhuyan, Laxminarayan N. . . . . . . . . . . . . . . . . . . . . . . . . . . 28Bogen, Daniel K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Borriello, Gaetano. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Bresler, Yoram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Brewer, Forrest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Brockman, Jay B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Brockwell, Peter J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Brown, Geoffrey M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Brunvand, Erik L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8, 12Bryant, Kelvin S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Buckley, Kevin M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Bunch, James R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Burns, Steven M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CCao, Pei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Carley, L. Richard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Carter, Harold W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Casinovi, Giorgio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Chapman, Richard O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Chen, Tom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Chen, Peter M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Cheng, Chung-Kuan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4, 19Choi, Hyeong-Ah. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Christie, Phillip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 24Chrzanowska-Jeske, Malgorzata. . . . . . . . . . . . . . . . . . . . . . 7Clark, Douglas W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29, 55Clarke, Edmund M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Clarkson, Peter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Clements, Mark A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Coleman, Jeffrey O . . . . . . . . . . . . . . . . . . . . . . . . . . . .11, 48Cong, Jason. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Conte, Thomas M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Cook, Dianne H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Cosman, Pamela C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Culler, David E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Cypher, Robert. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DDas, Chita R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Davidson, Edward S. . . . . . . . . . . . . . . . . . . . . . . . . . . .11, 20Davis, Alan L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Davis, Richard A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46De Micheli, Giovanni. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 54Devadas, Srinivas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Doksum, Kjell A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Donoho, David L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Dougherty, Edward R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Dubois, Michel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Dugan, Joanne . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

EEbeling, Carl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Eggers, Susan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55, 70Ercegovac, Milos D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Etienne-Cummings, Ralph. . . . . . . . . . . . . . . . . . . . . . . . . . 67Etter, Delores M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

FFahlman, Scott E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Fang, Jiayuan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Farrens, Matthew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Fedder, Gary K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Felten, Edward W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Ferguson, Frankie J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Fickas, Stephen F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Fiez, Terri S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Finger, Susan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Flynn, Michael J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Fortes, Jose A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Franzon, Paul D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70French, Judson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Fuchs, Henry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

GGallagher, Neal C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Goel, Ashok K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Gopalakrishnan, Ganesh. . . . . . . . . . . . . . . . . . . . . . . . . 8, 12Gray, Paul R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Gray, Robert M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Green, Michael M . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11, 49Greenberg, Richard J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Gupta, Rajesh K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

HHa, Dong . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Hachtel, Gary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Hill, Mark D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Hollis, Ralph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Hornak, Lawrence A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Hu, Xiaobo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Hughey, Richard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Hurson, Ali R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

78 Index

IIrwin, Mary J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Itoga, Stephen Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

JJacome, Margarida . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Jain, Ramesh C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Jha, Niraj K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Johnson, Don H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Johnson, Barry W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Johnstone, Iain M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

KKahng, Andrew B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Kar, Aravinda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Karplus, Kevin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Karpovsky, Mark G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Kassam, Saleem A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Kaufman, Arie E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Kavi, Krishna M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Kedem, Zvi M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Kim, Eun Sok . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Kime, Charles R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Koren, Israel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Koren, Yoram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Kryder, Mark H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Kumar, Vijay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Kunz, Wolfgang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Kwong, Dim-Lee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

LLagally, Max G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Larrabee, Tracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Larus, James R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Law, Mark E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Lentz, Karen P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Li, Kai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Li, Jian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Lightner, Michael . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Lin, Rong . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Lipton, Richard J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Liu, Wentai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Liu, C. L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Liu, K.J. Ray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47, 68Loughlin, Patrick . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Lucas, Robert F.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

MMakki, Rafic Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Malik, Sharad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Marek-Sadowska, Malgorzata. . . . . . . . . . . . . . . . . . . . . 9, 67Martonosi, Margaret R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Masaki, Ichiro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Maurer, Peter M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6McClellan, James H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37McCluskey, Edward J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12McGrath, S. J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37McIlrath, Lisa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Melhem, Rami . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Menon, Premachandran. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Messina, Paul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Metaxas, Dimitri . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Meyer, Robert G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Miller, Eric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Milor, Linda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Mohapatra, Prasant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Mudge, Trevor N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11, 20Mukherjee, Amar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Mullis, Clifford T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Murdocca, Miles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Myers, Chris J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

NNagle, David F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Najm, Farid N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Nejhad, Mehrdad G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

OOlshen, Richard A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Orchard, Michael T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Orsak, Geoffrey C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Ososanya, Esther T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Owens, Robert M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

PParhi, Keshab K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Pearlman, William A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Pease, R Fabian W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Pedram, Massoud . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4, 20Peir, Jih-Kwon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Perez-Luna, Elisabeth. . . . . . . . . . . . . . . . . . . . . . . . . .49, 72Petropulu, Athina P. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Pinkham, Roger S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Pister, K J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Pomeranz, Irith . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Poulton, John W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Pradhan, Dhiraj K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Prince, Jerry L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

QQiao, Chunming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

RRamachandran, Umakishore. . . . . . . . . . . . . . . . . . . . . . . . 25Ramanathan, Parameswaran . . . . . . . . . . . . . . . . . . . . . . . . . 24Reddy, A.L. Narasimha . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Riskin, Eve A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Robins, Gabriel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 15Rosenblatt, Murray. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Roy, Kaushik . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Roysam, Badrinath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Russell, Susan J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Rutenbar, Rob A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Index 79

SSaab, Daniel G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Sakallah, Karem A. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11, 20Samarov, Alexander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Sapatnekar, Sachin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Sarrafzadeh, Majid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Satyanarayanan, Mahadev . . . . . . . . . . . . . . . . . . . . . . . . . . 61Sauer, Ken D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Schafer, Ronald W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Scharf, Louis L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Schultz, Richard R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Segall, Zary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Sejnowski, Terrence J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Sequin, Carlo H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Sha, Edwin H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Shanbhag, Naresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Shetler, Joy S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Shin, Kang G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Shirazi, Behrooz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Siewiorek, Daniel P. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Silverman, Harvey F . . . . . . . . . . . . . . . . . . . . . . . . . . .49, 62Simoncelli, Eero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Siu, Kai-Yeung . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23, 48Smith, James E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Snyder, Lawrence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55, 63Sohi, Gurindar S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Somani, Arun K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Somenzi, Fabio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Stewart, Alan L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Stonick, Virginia L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Strom, Robert G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Stroud, Charles E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Swindlehurst, A. L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

TTaylor, D. Lansing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Taylor, Ronald D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Thomas, Donald E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Thornton, Mitchell A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Torrellas, Josep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

UUlsoy, A. Galip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

VVaidya, Nitin H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Varma, Anujan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Vemuri, Ranganadha R . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Voelcker, Herbert B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59VonMayrhauser, Anneliese. . . . . . . . . . . . . . . . . . . . . . . . . . 5

WWah, Benjamin W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Walker, Duncan M H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Weiss, Lee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Wild, John J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Willson, A. N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Witkin, Andrew P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Wong, S. Simon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Wood, David A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Woods, John W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Wooley, Bruce A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Wright, Paul K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Wyatt, John L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

XXu, Guanghan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43, 44

YYang, Qing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Yang, Woodward. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Yang, Andrew T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Yuh, Junku. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Yun, Kenneth Y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

ZZhou, Dian. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 70Zoltowski, Michael D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Zwaenepoel, Willy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Index 81

Index of Institutions

Advanced Research Projects Agency. . . . . . . . . . . . . . . . . . 73Auburn University . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Boston University . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Brigham Young University. . . . . . . . . . . . . . . . . . . . . . . . . 45Brown University. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49, 62

California Institute of Technology. . . . . . . . . . . . . . . 3, 53, 72California Polytechnic State University. . . . . . . . . . . . . . . . 19Carnegie-Mellon University . . . . . . . . . . . 7, 22, 35, 61, 62, 71Case Western Reserve University . . . . . . . . . . . . . . . . . . . . 14Colorado State University. . . . . . . . . . . . . . . . . . . . . . . . 5, 46Cornell University . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59, 69

Drexel University . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Earmark Inc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49, 72

George Mason University . . . . . . . . . . . . . . . . . . . . . . . . . . 45George Washington University . . . . . . . . . . . . . . . . . . . . . . 20Georgia Institute of Technology. . . . . . . . . . . . . . .10, 25, 37

Harvard University . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Iowa State University. . . . . . . . . . . . . . . . . . . . . . . .20, 26, 47

Johns Hopkins University. . . . . . . . . . . . . . . . . . . . . . .26, 38

Massachusetts Institute of Technology. . . . . 7, 23, 47, 48, 59Medico-Technological Research Institute. . . . . . . . . . . . . . 39Michigan Technological University. . . . . . . . . . . . .11, 48, 69National Institute of Standards and Technology. . . . . . . . . 63National Academy of Sciences. . . . . . . . . . . . . . . . . . . . . . 58New York University . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55North Carolina A & T State University. . . . . . . . . . . . . . . . 53North Carolina State University - Raleigh. . . . . . . . . . .21, 70Northeastern University . . . . . . . . . . . . . . . . . . . . . . . . .33, 38Northwestern University . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ohio State University. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Pennsylvania State University. . . . . . . . . . . . . . . . .27, 28, 62Portland State University. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Princeton University . . . . . . . . . . . . . . . . . . . . . .11, 13, 29, 55Purdue University . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 25, 43

Rensselaer Polytechnic Institute. . . . . . . . . . . . . . . . . .39, 40Rochester Institute of Tech. . . . . . . . . . . . . . . . . . . . . . . . . 40Rutgers, The State University. . . . . . . . . . . . . . . . . . . . . . . 20

Salk Institute for Biological Studies. . . . . . . . . . . . . . . . . . 63Southern Illinois University - Carbondale. . . . . . . . . . . . . . 67Stanford University. . . . . . . . . . . . . . . . . . . . 3, 12, 36, 42, 54State University of New York - Binghamton. . . . . . . . . . . . 69State University of New York - Buffalo. . . . . . . . . . . . . . . 21State University of New York - Geneseo. . . . . . . . . . . . . . . 27

State University of New York - Stony Brook. . . . .11, 49, 60Stevens Institute of Technology. . . . . . . . . . . . . . . . . . . . . . 39

TERC Inc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Texas A & M University . . . . . . . . . . . . . . . . . . . 8, 24, 28, 53Tufts University . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

University of Arizona . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45University of Arkansas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3University of California - Berkeley. . . . . . . . . .33, 46, 54, 70University of California - Davis. . . . . . . . . . . . . . . . . . . . . . 19University of California - Los Angeles. . . . . . 3, 4, 24, 46, 71University of California - San Diego. . . . 4, 19, 34, 36, 57, 67University of California - Santa Barbara. . . . . . . . . . . . . 9, 67University of California - Santa Cruz. . . . . . . . . . .13, 19, 58University of Central Florida . . . . . . . . . . . . . . . . . . . . . . . . 71University of Cincinnati . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14University of Colorado - Boulder. . . . . . . . . . . . . . . 5, 42, 47University of Delaware. . . . . . . . . . . . . . . . . . . . . . . 5, 24, 34University of Florida . . . . . . . . . . . . . . . . . . . . . . . .24, 42, 67University of Hawaii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58University of Illinois - Urbana-Champaign . . . . . 6, 10, 22, 37 . . . . . . . . . 54, 68University of Iowa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13University of Kentucky . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68University of Maryland - College Park. . . . . . . . . . . . .47, 68University of Massachusetts - Amherst. . . . . . . . . . . . .10, 13University of Michigan - Ann Arbor. . . . . . . . .11, 20, 27, 59University of Minnesota . . . . . . . . . . . . . . . . . . . . . . . . .43, 48University of North Carolina - Chapel Hill . . . . . . . . . . . . . 60University of North Carolina - Charlotte . . . . . . . . . . 7, 13, 70University of North Dakota . . . . . . . . . . . . . . . . . . . . . . . . . 40University of Notre Dame . . . . . . . . . . . . . . . . . . . . . 7, 38, 68University of Oregon - Eugene . . . . . . . . . . . . . . . . . . . . . . 60University of Pennsylvania . . . . . . . . . . . . . . . . . . .41, 43, 71University of Pittsburgh. . . . . . . . . . . . . . . . . . . . . . . . .22, 35University of Rhode Island. . . . . . . . . . . . . . . . . . . . . . . . . 23University of South Florida . . . . . . . . . . . . . . . . . . . . . . . . . . 6University of Southern California. . . . . . . . . . . . . . . 4, 20, 53University of Texas - Arlington . . . . . . . . . . . . . . . . . . . . . . 28University of Texas - Austin . . . . . . . . . . . . . . . . . . . 8, 43, 44University of Utah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8, 12University of Virginia - Charlottesville. . . . . . . . . . . 9, 12, 15University of Washington . . . . . . 9, 12, 15, 29, 41, 55, 63, 70University of Wisconsin - Madison . . . . . . .14, 24, 41, 56, 57

Virginia Polytechnic Institute and State University. . . . . . . 15

Washington State University. . . . . . . . . . . . . . . . . . . . . . . . 34West Virginia University . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Western Michigan University . . . . . . . . . . . . . . . . . . . . . . . 23William Marsh Rice University. . . . . . . . . . . . . . . .36, 44, 53

82 Index

SPINE PRINTING

MIPS - SUMMARY OF AWARDS - FISCAL YEAR 1996 NSF 97-144