Programmable Logic Devices (Pld)

7/29/2019 Programmable Logic Devices (Pld)

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PROGRAMMABLE LOGIC

DEVICES (PLD)


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PLD

Problems by Using Basic Gates

Many components on PCB:

As no. of components rise, nodesinterconnection complexity grow exponentially

Growth in interconnection will cause increase

in interference, PCB size, PCB design cost, and

manufacturing time


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PLD

The purpose of a PLD device is to permit elaborate digital logicdesigns to be implemented by the user in a single device.

Can be erased electrically and reprogrammed with a new design,making them very well suited for academic and prototyping

Types of Programmable Logic DevicesSPLDs (Simple Programmable Logic Devices) ROM (Read-Only Memory)

PLA (Programmable Logic Array)

PAL (Programmable Array Logic)

GAL (Generic Array Logic)

CPLD (Complex Programmable Logic Device)FPGA (Field-Programmable Gate Array)


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PLD

The first three varieties are quite similar to eachother:

They all have an input connection matrix, which

connects the inputs of the device to an array of AND-gates.

They all have an output connection matrix, whichconnect the outputs of the AND-gates to the inputs ofOR-gates which drive the outputs of the device.

The gate array is significantly different and will bedescribed later.


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PLD

The differences between the first three categories

are these:

1. In a ROM, the input connection matrix is hardwired.

The user can modify the output connection matrix. In a PAL/GAL the output connection matrix is

hardwired. The user can modify the input connection

matrix.

In a PLA the user can modify both the input connectionmatrix and the output connection matrix.


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General structure of PLDs.


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(a) Symbol. (b) Logic equivalent.

Buffer/inverter


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(a) Before programming. (b) After programming.

Programming by blowing fuses.


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OR - PLD Notation


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AND - PLD Notation


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PLD notation.

(a) Unprogrammed and-gate.(b) Unprogrammed or-gate.

(c) Programmed and-gate realizing the termac.

(d) Programmed or-gate realizing the terma +b.

(e) Special notation for an and-gate having all itsinput fuses intact.

(f) Special notation for an or-gate having all itsinput fuses intact.

(g) And-gate with non-fusible inputs.(h) Or-gate with non-fusible inputs.


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PROM Notation


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A 2n m PROM

(a) Logic diagram.

(b) Representation in PLD

notation.


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Using a PROM for logic design

(a) Truth table. (b) PROM realization.


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A simple four-input, three-output PAL device.


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An example of using a PAL device to realize two

Boolean functions. (a) Karnaugh maps. (b) Realization.


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Logic diagram of an n p m PLA


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(a) Maps showing the multiple-output prime implicants. (b) Partial covering of thef1 andf2

maps. (c) Maps for the multiple-output minimal sum. (d) Realization using a 3 4 2 PLA.

Example of combinational logic design

using a PLA.


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(a) Circuit diagram. (b) Symbolic representation.

Exclusive-or-gate with a programmable

fuse


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General structure of a PLA having true and

complemented output capability


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Karnaugh maps for the functionsf1(x,y,z) = m(1,2,3,7) and

f2(x,y,z) = m(0,1,2,6)


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Two realizations off1(x,y,z) = m(1,2,3,7) andf2(x,y,z) = m(0,1,2,6).

(a) Realization based onf1 and 2 (b) Realization based on 1 and 2ff f


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Introduction to FPGA & CPLD


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FPGA AND CPLD

1. FPGA - Field-Programmable Gate Array.

2. CPLD - Complex Programmable Logic

Device

3. FPGA and CPLD is an advance PLD.

4. Support thousands of gate where as PLD

only support hundreds of gates.


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What is an FPGA?

Before the advent of programmable logic, custom logic circuits werebuilt at the board level using standard components, or at the gate levelin expensive application-specific (custom) integrated circuits.

FPGA is an integrated circuit that contains many (64 to over 10,000)identical logic cells that can be viewed as standard components. Each

logic cell can independently take on any one of a limited set ofpersonalities.

Individual cells are interconnected by a matrix of wires andprogrammable switches. A user's design is implemented by specifyingthe simple logic function for each cell and selectively closing theswitches in the interconnect matrix.

Array of logic cells and interconnect form a fabric of basic buildingblocks for logic circuits. Complex designs are created by combiningthese basic blocks to create the desired circuit


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FPGA architecture


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What does a logic cell do?

The logic cell architecture varies between different device families.

Each logic cell combines a few binary inputs (typically between 3 and10) to one or two outputs according to a Boolean logic functionspecified in the user program .

In most families, the user also has the option of registering the

combinatorial output of the cell, so that clocked logic can be easilyimplemented.

Cell's combinatorial logic may be physically implemented as a smalllook-up table memory (LUT) or as a set of multiplexers and gates.

LUT devices tend to be a bit more flexible and provide more inputs percell than multiplexer cells at the expense of propagation delay.


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what does 'Field Programmable'mean?

Field Programmable means that the FPGA's function is definedby a user's program rather than by the manufacturer of thedevice.

A typical integrated circuit performs a particular functiondefined at the time of manufacture. In contrast, the FPGA's

function is defined by a program written by someone other thanthe device manufacturer.

Depending on the particular device, the program iseither 'burned' in permanently or semi-permanently as part of aboard assembly process, or is loaded from an external memoryeach time the device is powered up.

This user programmability gives the user access to complexintegrated designs without the high engineering costs associatedwith application specific integrated circuits.


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How are FPGA programs created?

Individually defining the many switch connections and celllogic functions would be a daunting task.

This task is handled by special software. The softwaretranslates a user's schematic diagrams or textual hardware

description language code then places and routes thetranslated design.

Most of the software packages have hooks to allow theuser to influence implementation, placement and routing toobtain better performance and utilization of the device.

Libraries of more complex function macros (eg. adders)further simplify the design process by providing commoncircuits that are already optimized for speed or area.


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FPGA

FPGA applications:-i. DSP

ii. Software-defined radio

iii. Aerospace

iv. Defense systemv. ASIC Prototyping

vi. Medical Imaging

vii. Computer vision

viii. Speech Recognitionix. Cryptography

x. Bioinformatic

xi. And others.


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CPLD

1. Complexity of CPLD is between FPGA and

PLD.

2. CPLD featured in common PLD:-

i. Non-volatile configuration memorydoes not

need an external configuration PROM.

ii. Routing constraints. Not for large and deeply

layered logic.


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CPLD

3. CPLD featured in common FPGA:-

i. Large number of gates available.

ii. Can include complicated feedback path.

4. CPLD application:-

i. Address coding

ii. High performance control logiciii. Complex finite state machines


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CPLD

5. CPLD architecture:-

LAB Logic Array Block / uses PALs

PIA Programmable Interconnect Array

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Programmable Logic Devices (Pld)