Prospects for High-Aspect-Ratio FinFETs in Low-Power Logic

Mark Rodwell, Doron Elias University of California, Santa Barbara

3rd Berkeley Symposium on Energy Efficient Electronic Systems, October 28-29, 2013

High Aspect Ratio Fins for Low-Power LogicInGaAs finFET:8 nm thick fin200 nm high

InGaAs NFET

height>> pitch

InGaAs PFET

Enables ~4 nm fin bodies→ 8 nm gate length10:1 more current per unit die area

→ smaller IC die area complements lithographic scalingEnables high speed, ultra low-power logic,

Vdd~300 mV

Fin thickness defined by Atomic layer epitaxy → nm thickness control Fin height defined by sidewall growth → 200 nm high fins

D. Elias, DRC 2013, June, Notre Dame

-0.4 -0.2 0.0 0.2 0.4 0.610-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

SS ~ 80 mV V

DS = 0.1 V

SS ~ 120 mV V

DS = 0.5 V

VDS

= 0.1 to 0.7 V

0.2 V increment

Curr

ent D

ensi

ty (m

A/

m)

Gate Bias (V)

Background: III-V MOS

V. Chobpattana et al (Stemmer group), APPLIED PHYSICS LETTERS 102, 022907 (2013)

Lg = 60 nm

-0.4 -0.2 0.0 0.2 0.4 0.60.0

0.4

0.8

1.2

1.6

Gm

(mS

/m)

Curr

ent D

ensi

ty (m

A/

m)

Gate Bias (V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2V

DS = 0.1 to 0.7 V

0.2 V increment

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0

0.4

0.8

1.2

1.6

2.0

Curr

ent D

ensi

ty (m

A/

m)

Drain Bias (V)

Ron

= 268 Ohm-m

at VGS

= 1.0 V

VGS

= -0.4 V to 1.0 V

0.2 V increment

FinFETs by Atomic Layer Epitaxy: Why ?

26 / bodybody TT

Electrostatics: body must be thinner than ~Lg /2→ less than 4 nm thick body for 8 nm Lg

Problem: threshold becomes sensitive to body thickness

3bodybodyth TTV

Problem:low mobility unless surfaces are very smooth

Implication: At sub-8-nm gate length, need :atomically-smooth interfaces atomically-precise control of channel thickness

side benefit: high drive current→ low-voltage, low-power logic

ALE-Defined finFET: Process Flow

Fin template: formed by {110}-facet-selective etch→ atomically smoothChannel thickness set by ALE growth→ atomically preciseNot shown: gate dielectric, gate metal, S/D metal

Images

HfO2

TiN

fin, ~8nm

100

nm fi

n pi

tch

draindrain

50 n

m fi

n pi

tch

sourcesource

channelchannel

10 n

m th

ick

fins,

100

nm

tal

l

Goal: Tall Fins for High Drive Current

Goal: fin height >> fin pitch (spacing)→ more current per fin→ less fins needed → higher integration density

pitch fin

height finJ

width transistor

currentsurface

7Higher density→ shorter wires→ smaller CwireVdd/I, CwireVdd2/2

Is the IC Area Reduction Significant ?Clock/interconnect drivers need large drive currents. Area reduction for these is likely substantial.

FETs in Cache Memory & Registers are drawn at minimum width No area reduction for these.

Most, but not all, Logic Gates will be drawn at minimum width.

Benefit must be evaluated by VLSI architect, not by device physicist.

300 mV Logic: Can We Address The CV2/2 Limit ?

The CV2/2 dissipation limit

0 0.1 0.2 0.3 0.4 0.50.1

1

10

100

1000

Vgs

I d, A

/m

60mV/decade

Subthreshold logic Tunnel FETs

Threshold set for acceptable off-state dissipation IoffVdd.

Vdd set for target Ion, hence acceptable CVdd/Ion.

Vdd

Cwire

With minimum Cwire,a minimum switching energy CwireVdd

2/2 is set

Bandgap of P+ source truncates thermal distribution.

Potential for low Ioff at low Vdd.

Obtaining high Ion /Vdd is the challenge.0 0.1 0.2 0.3 0.4 0.50.1

1

10

100

1000

Vgs

I d, A

/m

60mV/decade

Vdd is simply reduced.Decreases energy CVdd

2/2.Increases delay CVdd/Ion.

Goal: Tall Fins for Low-Power, Low-Voltage Logic

Supply reduced from 500mV to 268 mV while maintaining high speed.

0 0.1 0.2 0.3 0.4 0.50

200

400

600

800

1000

Vgs

I d, A

mp

s p

er

me

ter

of

FE

T w

idth nominal 1mA/micron

@500mV Vdd

(a)

0 0.1 0.2 0.3 0.4 0.50.1

1

10

100

1000

Vgs

60mV/decade

0.1mA/micron @ V

gs=0mV

(b)

-0.1 0 0.1 0.2 0.3 0.4 0.50

2000

4000

6000

8000

10000

Vgs

I d,

Am

ps

pe

r m

ete

r o

f F

ET

fo

otp

rint

wid

th

60 mVdec.

1000 A/m @ Vgs=268mV

(c)

finFET:10:1 height/pitch

-0.1 0 0.1 0.2 0.3 0.4 0.510-1

100

101

102

103

104

Vgs

0.1 A/m @ Vgs=0mV

(d)

finFET:10:1 height/pitch

3.5:1 power savings ? Must consider FET capacitances.

channel-gate3

fringingmfF/ 3.015

ctinterconnemfF/ 2.0

injectionon DDg

g

wiretotal

VvLI

W

LC

energy2/

delay2/2

DDtotalsw

onDDtotalgate

VCE

IVC

Assumes (Hodges & Jackson, 2003): (1) Charge-control analysis (2) Ion,PFET / Wg=0.5*Ion,NFET / Wg (3) FO=FI=1

Power and Delay Comparison

11

Planar FET, Vdd=500 mV

tall finFET, Vdd=268 mV

-0.1 0 0.1 0.2 0.3 0.4 0.50

2000

4000

6000

8000

10000

Vgs

I d,

Am

ps

pe

r m

ete

r o

f F

ET

fo

otp

rin

t w

idth

60 mVdec.

1000 A/m @ Vgs=268mV

finFET:10:1 height/pitch

0 0.1 0.2 0.3 0.4 0.50

200

400

600

800

1000

Vgs

I d, A

mp

s p

er

me

ter

of

FE

T w

idth nominal 1mA/micron

@500mV VddIon=20 mA, Ioff=2nA

Ion=20 mA, Ioff=2nA

Cg-ch=IonLg /vinjVdd=1.3 aF

Cg-ch=IonLg /vinjVdd=3.7 aF

Cgd-f = Cgs-f = 6 aF

Cgd-f = Cgs-f = 60 aF

Cwire= 2 fF (10 mm length)

Cwire= 2 fF (10 mm length)

Ctotal = 2.1 fF (various multipliers)delay= 52 psCtotal VDD

2= 0.26 fJ

Ctotal = 2.9 fF (various multipliers)delay= 39 psCtotal VDD

2= 0.11 fJ

Why tall finFETs ? Why Not Just Subthreshold Logic ?

Planar FET, Vdd=268 mV

tall finFET, Vdd=268 mV

-0.1 0 0.1 0.2 0.3 0.4 0.50

2000

4000

6000

8000

10000

Vgs

I d,

Am

ps

pe

r m

ete

r o

f F

ET

fo

otp

rin

t w

idth

60 mVdec.

1000 A/m @ Vgs=268mV

finFET:10:1 height/pitch

Ion=2.0 mA

Ion=20 mA

Low Ion→ large CVDD/Ion delay,subthreshold logic is slow.

-0.1 0 0.1 0.2 0.3 0.4 0.50

2000

4000

6000

8000

10000

VgsI d

, A

mp

s p

er

me

ter

of

FE

T c

ha

nn

el

wid

th

60 mVdec.

1000 A/m @ Vgs=268mV

finFET:10:1 height/pitch

12

Why tall finFETs ? Why Not Just Subthreshold Logic ?

Planar FET, Vdd=268 mV

tall finFET, Vdd=268 mV

-0.1 0 0.1 0.2 0.3 0.4 0.50

2000

4000

6000

8000

10000

Vgs

I d,

Am

ps

pe

r m

ete

r o

f F

ET

fo

otp

rin

t w

idth

60 mVdec.

1000 A/m @ Vgs=268mV

finFET:10:1 height/pitch

Ion=20 mA

Ion=20 mA

Die size increased 10:1

-0.1 0 0.1 0.2 0.3 0.4 0.50

2000

4000

6000

8000

10000

VgsI d

, A

mp

s p

er

me

ter

of

FE

T c

ha

nn

el

wid

th

60 mVdec.

1000 A/m @ Vgs=268mV

finFET:10:1 height/pitch

(also: longer interconnects, etc)

13

Tunnel FETs & High-Aspect-Ratio Fins

Quick performance estimate:Assume, for a moment, that P/N tunneling probability is 10%*.Typical of the best reported ohmic contacts .*

*Contact to N-InGaAs @ 6E19/cm3 doping: m*=0.1m0, 0.2 eV, 0.5 nm barrier Baraskar, et al: Journal of Applied Physics, 114, 154516 (2013)

Then on-currents for tunnel FETs are ~10:1 smaller than that of normal FETs.

Unless Ion/Wg is high, tunnel FETs will suffer from eitherlarge CwireV/I gate delays or (increasing FET widths) large die areas.

Using high-aspect ratio fin structures, tunnel FET drive currents can be increased.Parasitic fringing capacitance will then also contribute to CV/I & CV2.

finFETs Defined by Atomic Layer EpitaxyInGaAs finFET:8 nm thick fin200 nm high

InGaAs NFET

height>> pitch

InGaAs PFET

Benefits:Enables ~4 nm fin bodies→ 8 nm gate length10:1 more current per unit die area

→ smaller IC die areaEnables high speed, ultra low-power logic,

Vdd~300 mV

Fin thickness defined by Atomic layer epitaxy → nm thickness control Fin height defined by sidewall growth → 200 nm high fins

D. Elias, DRC 2013, June, Notre Dame

(end)

Backups

Lithographic Scaling vs. 3-D for High-Density Logic

18

Past VLSI Scaling: more FETs per IC because of(1) shorter gate & contact lengths(2) increased mA/micron→ less gate width Wg.

Today, Ion / Wg (mA/micron) is not increasing soon, once S/D tunneling dominates, Ion/Wg will start to decrease

Sub-16nm lithography is also difficult. Further reductions in feature size are expensive.

Can 3-D transistors increase integration density ?

Clear: increased Ion for a given FET footprint size.

Less clear: decreased sizeof minimum-geometry FET.

Clear: can suppress S/D tunneling:tunneling distance >> lithographic distance.

Scaling in the S/D tunneling limitAt 4-8 nm Gate Lengths, high leakage from source/drain tunneling

/)2(exp 2/1* / gthtunnelDS LqVmJ

increases exponentially as gate length is reduced.

Reducing tunneling through increased mass can be counterproductiveincreasing m* → less tunneling, but lower FET on-current→ need more die area

Instead: Ultra-tall fins to increase the integration density

example: 3-input NOR gate.other cases: clock & interconnect drivers

19

2/3*

,

2/1*

1

2/3

1)/()/(1

where, V 1m

mA84

oequivodos

othgs

mmgcc

mmgK

VVKJ

Minimum gate length: source-drain tunneling (2)

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.01 0.1 1

no

rma

lized

driv

e c

urr

en

t K

1

m*/mo

g=2

EET=1.0 nmEET= (dielectric thickness*

SiO2 /

oxide )+

(mean wavefunction depth*SiO2

/semiconductor

)

0.6 nm

0.4 nm

g=1

InAs (2 nm well) 100 Silicon(2 nm well)

0.3 nm

increased m* → decreased Ion /Wg → decreases packing density

analysis: Rodwell et al, 2010 DRC

/EETε

)/c/c(c oxequiv

2SiO

1depthinversion_

11

20

Geometric Solutions to S/D Tunneling

Transport (& tunneling) distance larger than lithographic gate length.Feature used NOW in our current planar FETs.Can be incorporated in high-aspect-ratio finFETs

UID InGaAsvertical spacer

21

Why Not Release Fins Before S/D Regrowth ?

Images of released ~10 nm fins:

S/D regrowth provides mechanical support

D. Elias, DRC 2013, June, Notre Dame

Wire Lengths & Wire Capacitances in VLSI

23

FET logic gate

gate die area

Integrated Circuit Layout

areafootprint r transisto

area gate logic area IC

interconnect 1/2area)footprint r (transisto lenght mean wire

mfF/ 0.2 ecapacitanc wiring

1/2area)footprint r (transisto

ecapacitanc gmean wirin

more current per fin→ less fins needed → higher integration density

more current per fin→ shorter wires→ smaller CwireVdd/I, CwireVdd2/2

FET Capacitances, Interconnect Capacitances

24

gfgsfgd WCC mfF/ 3.0

ecapacitanc fringing

,,

DDgchg VvLIC injectionon

ecapacitanc channel-gate

wirewire LC mfF/ 2.0

ecapacitancct interconne

Similar capacitancesin finFET

Gate Capacitance, Energy, and Delay

25

gfgsfgd WCC mfF/ 3.0

ecapacitanc fringing

,,

DDgchg VvLIC injectionon

ecapacitanc channel-gate

wirewire LC mfF/ 2.0

ecapacitancct interconne

channel-gate3

fringingmfF/ 3.015

ctinterconnemfF/ 2.0

injectionon DDg

g

wiretotal

VvLI

W

LC

energy2/

delay2/2

DDtotalsw

onDDtotal

VCE

IVC

Assumes: (1) Charge-control analysis* (2) Ion,PFET / Wg=0.5*Ion,NFET / Wg

(3) FO=FI=1

*Hodges & Jackson, 2003