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Copyright © Siemens Austral Andina 2009. All rights reserved.
SIEMENS
FUNDAMENTOS DE LOS SISTEMAS DE PROTECCION NUMERICOS
Protección Diferencial de Barras Distribuida
Page 1Copyright © Siemens Austral Andina 2009. All rights reserved.
ED SE PTI
Versions
7SS50 Centralised versionSummation transformer
7SS51 Centralised versionPhase segregated
7SS52 Distributed versionPhase segregated
B U S BA R P R O T E C T IO N 7S S 52 11- 5 CA 0 0
SIPROTEC
B US B A R P R O T E C TI ON 7S S5 21 1-5 C A00
SIPROTEC
B U S B A R P R O TE C TIO N 7S S 52 1 1-5 CA 00
SIPROTEC
B U S B A R P R O T E CT I O N 7S S5 2 11 -5C A 0 0
S IP R O T E C
1 2 48
B U S B A R P R OTE C TIO N 7 SS 52 1 1-5 C A 0 0
SIPROTEC
3
Page 2Copyright © Siemens Austral Andina 2009. All rights reserved.
ED SE PTI
q Further development of the centralised busbar and breaker failureprotection 7SS50/51
q Employing the prooven low impedance principle which is already used by Siemens in conventional, analogue and numerical protection schemes
q Firmware based on experienced software 7SS50/51( about 200 systems worldwide in service )
q Tripping time 15ms ( heavy duty tripping contact )
q Current transformer saturation after 3ms tolerable
q Integrated two-stage circuit-breaker failure protection
Page 3Copyright © Siemens Austral Andina 2009. All rights reserved.
ED SE PTI
q Phase segregated measurement for each bus section
q Additional, isolator independant 'checkzone'
q Transfer bus treated as separate bus section
q Fault detection within the 'dead zone' between CB and CT of buscouplers
q Bay specific O/C-interlocking of trip command
q Bay-out-of-service function for maintenance
Page 4Copyright © Siemens Austral Andina 2009. All rights reserved.
ED SE PTI
Substation configurations
q Single, double or triple busbar with transfer bus
q 48 bays
q 12 busbar sections
q 4 couplers, 24 sectionalisers
Page 5Copyright © Siemens Austral Andina 2009. All rights reserved.
ED SE PTI
central unit
bay units
B USB AR PROT ECTIO N 7SS5211-5CA00
SIPR OTEC
BUSBAR PROT ECTION 7SS 5211-5CA00
S IPR OTEC
BUS BA R PROT ECTION 7S S5211-5 CA00
S IPR OTEC
B U S B A R P R O T E C T I O N 7 S S 5 2 1 1 - 5 C A 0 0
S I P R O T E C
1 2 48
BUSB AR PROTECTION 7S S5211 -5CA 00
SIPR OTE C
3
central unit
bay units
Page 6Copyright © Siemens Austral Andina 2009. All rights reserved.
ED SE PTI
TRIP L1/1
intertrip
device failure
trip release
TRIP L1/2TRIP L2/1TRIP L2/2TRIP L3/1TRIP L3/2
TRIP /1
BF release
==
TRIP /2
IL1
I
I
I
L2
L3
0
BFBF L1
L2BF L3
CB OFF
V+
Q1 ONQ1 OFF
bay out of
CB in service
Q2 ONQ2 OFF
CB ON
Q3 ONQ3 OFF
Q4/7 ONQ4/7 OFF
Q9 ONQ9 OFF
BF trig. puls/CB test
V-
OF
RS232
TTLcentral unit(OF, 1,2 MBit/s)
operating/diagnosis
OF
TTL
TTL
(RS232, 19,2kBd)
18 LEDs
LC-Display
membrane keyboard
bay unit
service
Page 7Copyright © Siemens Austral Andina 2009. All rights reserved.
ED SE PTI
Features of the bay unit
q Sampling, processing, testing and display of measured values
q Special handling of measured values for use in couplers
q Isolator position monitoring and indication
q Data acquisition for breaker failure protection
q Serial port for communication with the central unit
q Cyclic testing, self monitoring
Page 8Copyright © Siemens Austral Andina 2009. All rights reserved.
ED SE PTI
==
reset of LEDs
bay unit 1(OF, 1,2 MBit/s)
operating/diagnosis(RS232, 19,2kBd)
central unit
OF
RS232
TTL
OF
TTL
TTL
release differential
time synchronisation
control master unit(OF)
OF
TTL
bay unit 48(OF, 1,2 MBit/s)
annunciation 1
annunciation 16 (32)
34 LEDs
LC-Display
membrane keyboard
current supervision
release disturbancerecord buffer
freeze disturbancerecord buffer
V+V-
device failure
Page 9Copyright © Siemens Austral Andina 2009. All rights reserved.
ED SE PTI
Features of the central unit
q Phase- and sectionsegregated measurement
q Circuit-breaker failure protection
q Communication and synchronisation with bay units
q Cyclic checks of the entire system
q Administration of configuration data and parameters
q Interface to local PC ( DIGSI )
q Fault reporting and status indication
q Fault recording
Page 10Copyright © Siemens Austral Andina 2009. All rights reserved.
ED SE PTI
Serial link central unit - bay unit
q Synchronous data transmission
q Full duplex communication via 2 optical fibres (62,5/125µm, 820nm, 1,5km, FSMA)
q Protocol in accordance to HDLC with additional monitoring of length of telegram (High Level Data Link Control Procedures for Data Communication)
q 1,2 MBaud
q Cycle time 1ms (50Hz), 0.83ms (60Hz)
q Hamming-distance d = 4
Page 11Copyright © Siemens Austral Andina 2009. All rights reserved.
ED SE PTI
Circuit-breaker failure protection
q Two-stage for faults outside the busbar l Stage 1: repetition of tripsignal for faulty bay l Stage 2: tripping of every bay connected to the same bus sectionl Phase segregated unbalancing (reversal of current) l Limit of differential current related to nominal bay currentl Bay-specific minimum current releasel Bay-specific intertrip l Unbalancing on receive signal from the opposite protection
q Busbar faultsl Bay-specific intertrip
q Bus section specific, O/C-controlled distribution of trip commands in combination with external circuit-breaker failure protection devices
Functionality configurable independently for each bay
Page 12Copyright © Siemens Austral Andina 2009. All rights reserved.
ED SE PTI
q Modular system
q Few types ofcomponents
q easy to extend
q easy to assemble
central unitZPS
(BSZ1)
DPR
ZPS(BSZ2)
DPR
ZPS(BSZ3)
DPR
ZPS(SBK)
DPR
ZPS(SK1)
DPR
ZPS(SK2)
DPR
ZPS(SK3)
DPR
ZPS(SK4)
DPR
ZPS(SK5)
DPR
ZPS(SK6)
EAZ1 EAZ2 SV
1 2 8 48
bay 1 bay 2 bay 48
ZPS: processing unitSBK: system management
BSZ: protection algorithmSK: Serial link
EAZ: I/O unitSV: power supply
bay unitA/D µC
bay unitA/D µC
bay unitA/D µC
Page 13Copyright © Siemens Austral Andina 2009. All rights reserved.
ED SE PTI
central unitZPS
(BSZ1)
DPR
ZPS(BSZ2)
DPR
ZPS(BSZ3)
DPR
ZPS(SBK)
DPR
ZPS(SK1)
DPR
ZPS(SK6)
1 2 8 48
Abzweig 1 Abzweig 48
ZPS: processing unitSBK: system management
BSZ: protection algorithmSK: Serial link
EAZ: I/O unitSV: power supply
bay unitA/D µC
bay unitA/D µC
Calculationeven
samples
Interface to upto 8 bay units
Date acquisition ofbay informations,
indication, tripcommands
Calculation
checkzone
MasterSystemcontrol
Calculationodd
samples
Page 14Copyright © Siemens Austral Andina 2009. All rights reserved.
ED SE PTI
Security against malfunction: 3-out-of-3 decision per bay
(BSZ 2)DPR
ZPS(BSZ 3)
DPR
ZPS
L+L -
(BSZ 1)DPR
ZPS
Short circuit in the checkzone, calculated fromall samples
Short circuit in disciminative zone x,calculated fromeven samples
Short circuit in disciminative zone x,calculated fromodd samples
Trip- relay(per bay)
3 pole tripping control per bay
