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PS VFE & PS/SPD FE Electronics Status and Plans 21 November 2007 LPC Clermont

PS VFE & PS/SPD FE Electronics Status and Plans 21 November 2007 LPC Clermont

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Page 1: PS VFE & PS/SPD FE Electronics Status and Plans 21 November 2007 LPC Clermont

PS VFE & PS/SPD FE Electronics Status and Plans

21 November 2007

LPC Clermont

Page 2: PS VFE & PS/SPD FE Electronics Status and Plans 21 November 2007 LPC Clermont

2

PS/SPD FEB Production Status

Production & Tests finished:

112 PS/SPD FEB produced (including 2 prototypes)

100 installed

8 boards shipped back to Hitachi for reparations / returned to LPC / in testing

Hard bug spotted on FE current limiters thresholds ( DL1 & DL2 ):

currents in FEPGA increases by 0.2-0.3 A when connecting VFE to FE / whatever VFE/FE activity current limit underestimated

current limit hard controlled by a resistor value / increased to max value of 2 A ( nominal 1.6 A expected )

Page 3: PS VFE & PS/SPD FE Electronics Status and Plans 21 November 2007 LPC Clermont

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FEB Installation Status

All 100 FE boards patched for 2 A, ‘on flight’ in pit 8.

1+ week work for de-cabling / soldering / re-cabling

C side fully tested:

- New 2 A limit: All FE/VFE couples checked OK

- RJ45 cabling (VFE/FE ): 2 pathologic channels ( SM3 & SM4 Top) / RJ45 cable or VFE side connection problem

A side testing ongoing …

- 25 % done ( PRS6 + ½ PRS5 )

- 1 dead VFE/FE contact / FE connector suspected PRS5-FE02

- Last board FE 106 installed last week / Tests required

Page 4: PS VFE & PS/SPD FE Electronics Status and Plans 21 November 2007 LPC Clermont

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VFE Sagita Issues

Sagita on back of VFE boards lost of connection for CLOCK signal / Due to ?

- Stresses through VFE RJ45 cables / in detector movements

- ‘Natural’ relaxation of the VFE board / in time

Statistics:

- C side: 7 / 50 VFE lost from may to July

2 / 50 VFE lost from July to September

2 / 50 VFE lost from September to November

- A side: 2 / 50 VFE lost from may to September

No loss from September to November

VFE electronics

VFE connectorsRJ45

RJ45RJ45 RJ45 RJ45

CLOCK

Signal Signalpower

Schematics of VFE ( 2 boards + connectors): sagitta caused by ?

Page 5: PS VFE & PS/SPD FE Electronics Status and Plans 21 November 2007 LPC Clermont

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Marathon PSU Issues

Marathon power supply unit (PSU) PRS7 dead

- shortcut suspected @ 380 V connector @ Marathon side (platform) / To be confirmed

- PSU returned for repair / Bldg 4. / No spare ? / How long ?

Pathologic channel 0 on Marathon VFE PSU / Both sides! / Pending issue

- C side: SPD is concerned

- A side: PS is concerned

Page 6: PS VFE & PS/SPD FE Electronics Status and Plans 21 November 2007 LPC Clermont

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VFE Temperature Monitoring & Cooling

Monitoring of VFE temperatures functional (ELMBs / PVSS)

Cooling installed !

- Water leakage alert on Sunday 11 November / But … the cooling was turned off on Friday 9 ???

- To be commissioned

SM4-VFE05 / No cooling VFE ON

Neighbour VFE ONAll OFF

( degrees C / hours )

Page 7: PS VFE & PS/SPD FE Electronics Status and Plans 21 November 2007 LPC Clermont

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Prospects

Commissioning:

- Get to work with CROC V4 & final specs setup / DAQ tests

- VFE cooling stress tests

- Flash A side channels with LEDs

Calibration:

- Set internal Phasers FE/VFE for DAQ

Monitoring:

- FE/VFE connectivity / Periodic survey

Foreseen strategy: 1st Validate remote operation with CROC V4 in PRS0 / commission cooling This will allow automatisation of calibration & monitoring tasks