qb mp 8086, microprocessor lab manual viva questions

8/10/2019 qb mp 8086, microprocessor lab manual viva questions

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QUESTION-BANK

Q1. Differentiate between microprocessor and microcontroer!

Ans. 1. Microprocessor is a general purpose devise

2. Microcontroller is indented for a specific purpose

3. Memory ,I/O devices etc need to be interfaced with microprocessor . Microcontroller is having its own memory , I/O etc integrated with it

!. "e can say that microprocessor is a cpu on a chip

#. Microcontroller is a system on a chip

Q". #$at is an instr%ction &%e%e! E'pain!

Ans. $his is introduced in %&%# processor.$his 'ueue is in the (I) and is used forstoring the predecoded instructions.$his will overlap the fetching and e*ecution cycle.

$he + ) will tae the instructions from the 'ueue for decoding and e*ecution.

Q(. #$at is )E* prefi'! +ow it f%nctions for strin, instr%ctions!

Ans. $his -+ prefi* is used for repeating. $he instruction with -+ prefi* will e*ecuterepeatedly till the count in the c* register will be ero. $his can be used in with some of

the string handling instructions.

Q. E'pain t$e instr%ctions i/ 0DS ii/ *US+ iii/ TEST i2/ 30D

Ans.

i0 4 load pointer to

Move a 32 bit content from the memory given as source to 1#

bit destination register specified and to register.

ii0 )56 4 push the flag

7fter the e*ecution the content of the flag register will bepushed to the stac.$he higher byte to sp81 and lower tosp82

iii0 $+$ 4 logical comparison $his will compare the source and the destination specified.

$he result will be reflected only in the flag registers.

iv0 9 4 this will clear the direction flag.

Q4. #$at is stac5! E'pain t$e %se and operation of stac5 and stac5 pointer!

Ans. 7 stac is a portion of the memory used for the temporary storage. 7 stac is a last In first Out memory. 7 stac grows in the decreasing order. 7 stac will hold the

temporary information:s push and pop are the instructions used for storing and

accessing data from the stac. 9ontents can be moved as 1# bit only using push and pop instructions.


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Q6. #$at are t$e fa,s in 7876!

Ans. In %&%# 9arry flag, arity flag, 7u*iliary carry flag, ;ero flag, Overflow flag, $rap flag, Interrupt flag, irection flag, and ign flag.

Q9. #$at are t$e 2ario%s interr%pts in 7876! E'pain.Ans. Masable interrupts,


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Q11. T$e "s compement si,ned data contents of A0 e&%a -1 and t$e contents of 30

are

-". #$at res%t is prod%ced in A> b: e'ec%tin, t$e foowin, instr%ctions

i/


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Acc%m%atorregister consists of 2 %8bit registers 7 and 75, which can be combined

together and used as a 1#8bit register 7@. 7 in this case contains the low8order byte of

the word, and 75 contains the high8order byte. 7ccumulator can be used for I/Ooperations and string manipulation.

Baseregister consists of 2 %8bit registers ( and (5, which can be combined together

and used as a 1#8bit register (@. ( in this case contains the low8order byte of the word,and (5 contains the high8order byte. (@ register usually contains a data pointer used for

based, based inde*ed or register indirect addressing.

3o%ntregister consists of 2 %8bit registers 9 and 95, which can be combined together

and used as a 1#8bit register 9@. "hen combined, 9 register contains the low8order

byte of the word, and 95 contains the high8order byte. 9ount register can be used as a

counter in string manipulation and shift/rotate instructions.

Dataregister consists of 2 %8bit registers and 5, which can be combined together

and used as a 1#8bit register @. "hen combined, register contains the low8orderbyte of the word, and 5 contains the high8order byte. ata register can be used as a port

number in I/O operations. In integer 328bit multiply and divide instruction the @register contains high8order word of the initial or resulting number.

$he following registers are both general and inde* registers4

Stac5 *ointer=0 is a 1#8bit register pointing to program stac.

Base *ointer=(0 is a 1#8bit register pointing to data in stac segment. ( register is

usually used for based, based inde*ed or register indirect addressing.

So%rce Inde'=I0 is a 1#8bit register. I is used for inde*ed, based inde*ed and registerindirect addressing, as well as a source data address in string manipulation instructions.

Destination Inde'=I0 is a 1#8bit register. I is used for inde*ed, based inde*ed and

register indirect addressing, as well as a destination data address in string manipulationinstructions.

Introd%ction to Ad2anced processors


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Q1. E'pain t$e 78176 microprocessor e2o%tion.

Ans.$he %&1%# microprocessor was developed by Intel in 1E%2. It is an improved %&%#

with several common support functions built in4 cloc generator, system controller,interrupt controller, M7 controller, and timer/counter. It also added % new instructions

and e*ecutes instructions faster than the %&%#. 7s with the %&%#, it has a 1#8bit e*ternal

bus and is also available as the %&1%%, with an %8bit e*ternal data bus. $he initial clocrate of the %&1%# and %&1%% was # M5. In 1E%F Intel announced the second generation

of the %&1%# family4 the %&91%#/91%%. $he %&1%# was redesigned as a static, stand8alone

module nown as the %&91%# Modular 9ore and is pin compatible with the %&1%# family,while adding an enhanced feature set. $he high8performance 95MO III process allowed

the %&91%# to run at twice the cloc rate of the


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rogrammable Interrupt 9ontroller

$imers

rogrammable M7 )nit

rogrammable 9hip election )nit

ower ave/ower own 6eature

-efresh 9ontrol )nit

Q. Draw t$e timin, dia,ram of 78176.

Ans.


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Q6. #$at are t$e feat%res of 78"76!

Ans.%&2%# have following features41. independent units =%&%# has only two units0

2. 28bit 7ddress busin

3. (us )nit generates all data, address and I/O signals.

refetcher flushes the prefetched data, if I) finds a branch instruction.. 7ddress )nit =7)0 off8loads address generation, translation and checing from

().units =

!. Instruction )nit off8loads +) by performing the instruction decoding.

Q9. Draw t$e interfacin, dia,ram of 78"76.

Ans.


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ly two units0

Q7. E'pain t$e e2o%tion of 78"76.

Ans.$he %&2%# was introduced by Intel on 6ebruary 1, 1E%2. 7s the %&1%#/%&1%% 9)s

were not really significant to personal computing, the %&2%# was IntelHs ne*t step

processor for micro computers.Intel added four more address lines to the %&%#/%&1%# design. $he %&%#, %&%%, %&1%#,

and %&1%% all contained 2& address lines, giving these processors one megabyte of

addressibility =22& ? 1M(0. $he %&2%#, with its 2 address lines, gives 1# megabytes ofaddressibility =22 ? 1# M(0.

$he most substantial difference between the %&2%# and the %&%#/%&%% is the addition of a

protected mode. In protected mode, segment registers became pointers into a table of

memory descriptors rather than being a direct part of the address. 7mong other things,protected mode allows safe e*ecution of multiple programs at once by protecting each

program in memory. O normally operates in real mode, in which segment registers act

Dust as they do in the %&%#/%&%%. rotected mode is used by Microsoft "indows, I(MHsO/2 and )


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industry. 7M, I(M, and 5arris were nown to produce %&2%# chips as O+M productsK

while iemens, 6uDitsu, and Cruger either cloned it or was also second8sources. (etween

these various manufacturers, the %&2%# was offered in speeds ranging from # M5 to 2!M54

Intel4#812.!M5

iemens4%81#M57M4%82&M5

5arris41&82!M5

$he %&2%# was typically made in 3 pacage versions, each with #% contacts4 a G78,9998and a 998pacage.

Q;. Is t$ere an: instr%ction added to 78"76 instr%ction set! If :es? mention.

Ans.Les, in %&2%# few instruction is added with %&1%# instruction set.$hey are written below4 7- 8 7dDust - 6ield of egment elector

9$ 8 9lear $as8witched 6lag in 9-O

7- 8 oad 7ccess -ights (yte G$/I$ 8 oad Global/Interrupt escriptor $able

-egister $ 8 oad ocal escriptor $able -egister

M" 8 oad Machine tatus "ord

O77 8 oad 7ll -egisters

8 oad egment imit

$- 8 oad $as -egister

G$ 8 tore Global escriptor $able -egister

I$ 8 tore Interrupt escriptor $able -egister

$ 8 tore ocal escriptor $able -egister

M" 8 tore Machine tatus "ord

$- 8 tore $as -egister

+--/+-" 8 erify a egment for -eading or "riting

Q18. #$at are t$e feat%res of 78(76!

Ans.6eatures of %&3%# are given below4 2F!,&&& transistors

Intel:s first practical 328bit microprocessor

328bit data bus and memory address

G( of memory

Memory management unit

Multitasing
http://www.cpu-collection.de/?l0=package#PGAhttp://www.cpu-collection.de/?l0=package#LCChttp://www.cpu-collection.de/?l0=package#PLCChttp://www.cpu-collection.de/?l0=package#PGAhttp://www.cpu-collection.de/?l0=package#LCChttp://www.cpu-collection.de/?l0=package#PLCC


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Q11. #$at are t$e feat%res of *enti%m!

Ans.6eatures of entium4

! architecture / %&!%#

Introductory version4 #&M5 and ##M5, 11&MI / 1&&M5, 1!&MI

1#C( of cache sie =%C( I9, %C( 90

G( of memory system, #8bit data bus +*ecutes up to two instructions at a time =If they don:t conflictN0

Q1". #rite down t$e addressin, modes of 78(76 wit$ e'ampes.

Ans.7ddressing modes of %&3%#4

-egister addressing4 MO +9@, +@

Immediate addressing4 MO +(@, 123!#F%5

irect addressing4 MO 9@, I$

-egister indirect addressing4 MO 7, +9@P

(ase8plus8inde* addressing4 MO +7@>+(@P, 9

-egister relative addressing4 MO 7@, +9@>P (ase relative8plus8inde* addressing4 MO +7@, 7--7L +(@>+9@P

caled8inde* addressing4 MO +@, +7@>B+(@P

Q1(. Draw t$e interna arc$itect%re of 78(76.

Ans.


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Q1. #$at are t$e comparisons between 7876? 78"76? 78(76? *enti%m!

7ns.

7876 78"76 78(76 *enti%m

Introd%ced F% %2 %! E!3oc5 Speed !Q1& M5 #812M5 1#833M5 1!&82&& M5

B%s widt$ 1# bits 1# bits 32 bits # bits

No.of transistor 2E&&& 13&&& 2F!&&& !.! million

Addressabe


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qb mp 8086, microprocessor lab manual viva questions