QSPI XIP Demo - Intel€¦ · Select the file ‘Altera-SoCFPGA-HardwareLib-XIP-CV-GNU.zip’ and click ‘Open’ 7. Click ‘Finish’ to import the project. 8. Go to Project->Build

10/15/2015

Advanced Information QSPI XIP Demo rev1

Date:2015/09/15

Revision: 1.0

QSPI XIP Demo

10/15/2015


QSPI XIP Demo

Contents

1 Introduction .................................................................................................................................... 3

2 Pre-requisites ................................................................................................................................. 4

3 Demo Deliverables.......................................................................................................................... 5

4 Running the demo........................................................................................................................... 6

4.1 Configure the Board to boot from QSPI Flash ............................................................................... 6

4.2 Flash the Preloader Image ......................................................................................................... 6

4.3 Flash the Bare-metal application image ....................................................................................... 6

4.4 Boot the Board ........................................................................................................................ 6

5 Re-compiling the demo .................................................................................................................... 8

5.1 Preloader................................................................................................................................ 8

5.2 Bare-metal Application ............................................................................................................. 8

6 Debugging the demo ....................................................................................................................... 9

7 Demo Architecture ........................................................................................................................ 10

7.1 Preloader.............................................................................................................................. 10

7.2 Boot Sequence ...................................................................................................................... 10

7.3 Memory Usage ...................................................................................................................... 10

7.4 QSPI Memory Usage ............................................................................................................... 11

7.5 Cache Settings ....................................................................................................................... 12

7.6 MMU Translation Tables ......................................................................................................... 12

7.7 Lock the data to L2 cache ........................................................................................................ 12

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1 Introduction

This document presents a demo that shows a bare-metal application running from QSPI Flash, on a Cyclone V

Soc Development Kit, without using SDRAM.

Some more details about the demo:

QSPI Flash (1MB window) is used for program and read only data HPOS OCRAM (64KB) is used for regular data storage

OCRAM is cleared at the beginning of the bare-metal application Caches are demonstrated. Interrupts are demonstrated.

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2 Pre-requisites

This section presents the prerequisites necessary for running and compiling the demo.

For running the demo:

Cyclone V Development Kit, rev D preferable SoC EDS 15.0 (for Quartus Flash Programmer) Serial terminal running on PC (TeraTerm for example)

For compiling the Preloader:

SoC EDS 15.0

For compiling and debugging the bare-metal application:

SoC EDS 15.0, including ARM DS-5

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3 Demo Deliverables

This demo is delivered as a three different files:

xip_demo.docx -current document

14.0_preloader_xip.patch -preloader patch

Altera-SoCFPGA-HardwareLib-XIP-CV-GNU.zip -sample application archive and

precompiled Preloader

The sample application archive Altera-SoCFPGA-HardwareLib-XIP-CV-GNU.zip contains the following:

Altera-SoCFPGA-HardwareLib-XIP-CV-GNU

debug-unhosted.ds -debugger script

Makefile -makefile

io.c -printf support code

mmu_tables.c -mmu tables code

xip_demo.c -main demo code

test_function_1.c -function to test execution time

test_function_2.c -function to test execution time

mmu_tables.h -mmu tables header

custom_reset.s -zero ocram code

check_mmu_tables.pl -check mmu placement script

generate_mmu_tables.pl -generate mmu tables script

xip_demo-mkimage.bin -application image

xip_demo.axf -application executable

preloader_xip

preloader-mkpimage.bin -preloader image

uboot-socfpga

spl

u-boot-spl -preloader executable

The binary image files are highlighted in red.

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4 Running the demo

In order to run the demo, the following steps need to be performed:

1. Configure board to boot from QSPI Flash 2. Flash the Preloader image 3. Flash the Bare-metal application image 4. Boot the board

4.1 Configure the Board to boot from QSPI Flash

Se the BSEL jumpers like this:

BSEL BSEL 0 BSEL 1 BSEL 2 Description

7 Left Left Left 3.3 V SPI or quad SPI

4.2 Flash the Preloader Image

1. Configure board to boot from QSPI Flash. 2. Start an Embedded Command Shell 3. Run the following commands to flash Preloader Image

quartus_hps -c 1 -o PV Altera-SoCFPGA-HardwareLib-XIP-CV-GNU/preloader_xip/preloader-mkpimage.bin

Note: if the flashing fails from the first try, please try it again. It may be related to the HPS booting while the

Flash Programmer tries to access the QSPI.

4.3 Flash the Bare-metal application image

1. Configure board to boot from QSPI Flash. 2. Start an Embedded Command Shell 3. Run the following commands to flash Preloader Image

quartus_hps -c 1 -o P -a 0x100000 Altera-SoCFPGA-HardwareLib-XIP-CV-GNU/xip_demo-mkimage.bin

Note: if the flashing fails from the first try, please try it again. It may be related to the HPS booting while the

Flash Programmer tries to access the QSPI.

4.4 Boot the Board

After the images were flashed, connect with a serial terminal to the board, using 115,200-8-N-1 settings and

power-cycle or reset the HPS. The following will be displayed on the console:

U-Boot SPL 2013.01.01 (Oct 20 2014 - 10:37:07) BOARD : Altera SOCFPGA Cyclone V Board

CLOCK: EOSC1 clock 25000 KHz


CLOCK: F2S_SDR_REF clock 0 KHz

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CLOCK: F2S_PER_REF clock 0 KHz CLOCK: MPU clock 925 MHz

CLOCK: DDR clock 400 MHz

CLOCK: UART clock 100000 KHz

CLOCK: MMC clock 50000 KHz

CLOCK: QSPI clock 370000 KHz

SDRAM: ECC Enabled SF: Read data capture delay calibrated to 3 (0 - 7)

SF: Detected N25Q512 with page size 65536, total: 67108864

Both SPI and serial NOR flash in XIP mode

Hello XIP World!

Execution duration without cache enable : 2625723 ticks.

alt_mmu_init alt_mmu_va_space_enable

alt_cache_system_enable

lock by line.

Execution duration Lock data to cache line: 2625712 ticks.

unlock by line.

Execution duration with cache line lock : 18060 ticks. Execution duration load larger data : 5242826 ticks.

Execution duration run the code again : 18071 ticks.

Global Timer Interrupt: 1 of 5



Global Timer Interrupt: 4 of 5 Global Timer Interrupt: 5 of 5

Done.

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5 Re-compiling the demo

This section describes how to re-compile the demo if any changes are necessary.

5.1 Preloader

The following steps are required in order to generate and compile the Preloader

1. Start Embedded Command Shell 2. Use bsp-editor to generate a Preloader based on the Cyclone V GHRD from SoC EDS 15.0 3. In bsp-editor, perform the following changes to the default configuration parameters

a. Uncheck BOOT_FROM_SDMMC b. Check BOOT_FROM_QSPI c. Check SKIP_SDRAM d. Uncheck WATCHDOG_ENABLE ( sample application does not pet it) e. Uncheck SDRAM_SCRUBBING f. Uncheck SDRAM_SCRUB_REMAIN_REGION g. Uncheck HARDWARE_DIAGNOSTIC

4. Change current folder to the Generated Preloader 5. Compile the Preloader using ‘make’ – this will bring in all source code 6. Clean the Preloader using ‘make clean’ 7. Patch the Preloader source using the following command:

patch -p1 < 14.0.1_preloader_xip.patch

8. Recompile the Preloader using ‘make’

Note that the Patch contains the following changes:

File /uboot-socfpga/include/configs/socfpga_common.h o Enabled XIP by defining CONFIG_SPL_SPI_XIP o Enabled QSPI remap by defining CONFIG_SPL_SPI_XIP_REMAPADDR

File uboot-socfpga/drivers/spi/cadence_qspi_apb.c o Used new macro CONFIG_SPL_SPI_XIP_REMAPADDR to remap QSPI address just before

jumping to QSPI.

5.2 Bare-metal Application

The following steps are required in order to rebuild the sample application:

1. Start an Embedded Command Shell 2. Start ARM DS-5 AE by running the command ‘eclipse &’ 3. Select a new workspace (or reuse an existing one) 4. Go to File -> Import -> General -> Existing Projects into Workspace and click ‘Next’ 5. Choose ‘Select archive file’ option and click the associate ‘Browse’ button 6. Select the file ‘Altera-SoCFPGA-HardwareLib-XIP-CV-GNU.zip’ and click ‘Open’ 7. Click ‘Finish’ to import the project. 8. Go to Project->Build project. This will compile the project.

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6 Debugging the demo

This section presents how to debug the demo using ARM DS-5 Altera Edition.

The following steps are necessary:

1. Import and compile the sample bare-metal application as described in section 5.2 - Bare-metal Application.

2. Flash the bare-metal application to the QSPI flash, using the instructions from section 4.3. - Flash the Bare-metal application image. This is required because DS-5 is not able to load the image directly into QSPI flash.

3. Go to Run -> Debug Configurations - > DS-5 Debugger and select the ‘Altera-SoCFPGA-HardwareLib-XIP-CV-GNU-Debug’ debug configuration

4. On the ‘Connection’ tab, click the Connection ‘Browse’ button and select the USB Blaster instance associated with the board to be debugged.

5. Click the ‘Debug’ button 6. The debugger will then do the following:

Reset the board

Download and run the Preloader executable Load the bare-metal application image symbols

Run the bare-metal application up to the ‘main’ function 7. The debugger is now stopped at entry to the ‘main’ function, and regular debugging can be used.

Note that all the breakpoints used will be hardware breakpoints, since the debugger cannot write to QSPI Flash.

This is transparently done by the debugger, based on the following line in the debugger script:

# Disable SW Breakpoints for Flash Code Stepping

memory 0xFFA00000 +0x100000 nobp ro noverify

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7 Demo Architecture

This section presents a little bit more details about the demo architecture.

7.1 Preloader

The Preloader included in the 15.0 SoC EDS release natively supports the XIP mode. However, it required a small

change to allow the whole 1MB of QSPI Flash Window to be used (by default the first 256KB are used by the four

Preloader images).

In order to do that, the Cadence QSPI controller was programmed to use the remap feature, to point the XIP

window to the 2nd MB of QSPI Flash. The modification is minor (4 lines of code) and will be included as a

standard feature in the future. The Preloader patch file was included, to enable Preloader demo recompilation.

7.2 Boot Sequence

The standard boot sequence is used, with the BootROM loading the Preloader, then the Preloader loading the

bare-metal application.

7.3 Memory Usage

The following table presents the linker sections that the bare-metal application uses. This setup was used for the

following reasons:

QSPI image needs to start with the actual entrypoint (Preloader requirement) MMU L1 table needs to be aligned to 16KB (ARM requirement) MMU L2 table needs to be aligned to 1KB (ARM requirement) MMU L1 table needs to refer to MMU L2 table address as a constant value (MMU tables in QSPI read

only memory constraint – address needs to be known at compile time)

Section Start Size Description

ram 0xFFFF0000 64K-4K

Onchip RAM. Minus 4KB for the

PLL workaround.

qspi_rom_startup 0xFFA00000 16K – 64

QSPI: Startup code, needs to

be at the beginning of the

image. Minus 64bytes for

Mkimage header

qspi_rom_mmu_ttb1 0xFFA04000 16K QSPI: L1 Translation Table

Boot ROM

Preloader Application Reset

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Section Start Size Description

qspi_rom_mmu_ttb2 0xFFA08000 1K QSPI: L2 Translation Table

qspi_rom 0xFFA08400 1M - 33K

QSPI: Rest of it – code and

constant data

7.4 QSPI Memory Usage

The demo uses only 2MB of the QSPI Flash:

1st MB: Preloader Images 2nd MB: Bare-metal Application Image

Bare-metal Application Image

(1MB – 64B)

0x0010_0000

0x0004_0000

Unused(768KB)

4 x Preloader Images(256KB)

0x0020_0000

0x0000_0000

mkimage header (64B)

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The rest of the QSPI can be used for other purposes, such as storing FPGA configuration images that can be used

by the Preloader to configure the FPGA.

7.5 Cache Settings

The following table presents the cache settings that were used.

Area L1 Cacheable L2 Cacheable

1MB QSPI Flash Yes Yes

64KB OCRAM Yes No

Rest of Memory No No

Note that making OCRAM also L2 cacheable did not improve the speed of the system. That is because OCRAM

has a similar speed with the L2 cache. However, making OCRAM L1 cacheable did make a significant

improvement in execution speed.

7.6 MMU Translation Tables

The MMU tables are used to describe the cache settings for different memory areas. For this demo, the

following Tables were used:

L1 Translation Table – describes memory like this: o 1MB cacheable section for QSPI window o 1MB L2 described page table for last MB of address space o 1MB non-cacheable sections for the rest of address space

L2 Translation Table for last MB of address space: o Large page – 64KB OCRAM as L1 cacheable o Large pages – for the rest of the 1MB area

Note that the MMU tables were generated using the included script – ‘generate_mmu_tables.pl’. The tables are

human readable and editable, so the script is not really required. It was included for completeness.

Also note that the absolute placement of the MMU tables is checked by the script ‘check_mmu_tables.pl’ that is

called by the Makefile.

7.7 Lock the data to L2 cache

The application preloads the desired piece of date to the L2 cache and locks it to improve the execution

efficiency.

Lockdown by line

When lockdown by line feature is enabled during a period of time, all newly allocated cache lines get marked as

locked. The controller then considers them as locked and does not naturally evict them. Lockdown by line

feature can be enabled by setting bit [0] of the Lockdown by Line Enable Register.

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Function desicription

To see if locking works or not, the demo uses below function to test this:

void test_function_1(void) {

__asm("nop");// copy 256*1024/4 times

}

The function will have 256K nops, measure and compare the time that the function takes to see if cache line

locking works.

Run the code without cache enabled. It takes 2625723 ticks.

Run the code with cache enabled. Lock the code and desired data in L2 cache.

Enable caches. Enable cache line locking.

Call function test_function_1. The desired data will be locked to L2 cache. The execution time of function is 2625712 ticks.

Disable cache line locking.

Run the again to see if cache is locked. The execution time of the function is 18060 ticks, this can prove that the desired data is locked in L2 cache.

Read a huge amount of data (512KB) that would evict the data from cache if it was not locked

Run the code again to see that it takes the same amount as in step 3. The execution time of the function is 18071 ticks, which is the same as step 3, and this can confirm that the desired data is locked in L2 cache.

Function test result

U-Boot SPL 2013.01.01 (Sep 23 2015 - 17:42:01)

BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 25000 KHz


CLOCK: F2S_SDR_REF clock 0 KHz

CLOCK: F2S_PER_REF clock 0 KHz

CLOCK: MPU clock 925 MHz

CLOCK: DDR clock 400 MHz CLOCK: UART clock 100000 KHz

CLOCK: MMC clock 50000 KHz

CLOCK: QSPI clock 370000 KHz

INFO : Watchdog enabled

SF: Read data capture delay calibrated to 3 (0 - 7)

SF: Detected N25Q00 with page size 65536, total: 134217728

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Both SPI and serial NOR flash in XIP mode Hello XIP World!

Execution duration without cache enable : 2625723 ticks.

alt_mmu_init

alt_mmu_va_space_enable

alt_cache_system_enable

lock by line. Execution duration Lock data to cache line: 2625712 ticks.

unlock by line.

Execution duration with cache line lock : 18060 ticks.

Execution duration load larger data : 5242826 ticks.

Execution duration run the code again : 18071 ticks.

Global Timer Interrupt: 1 of 5 Global Timer Interrupt: 2 of 5




Done.

Documents

QSPI XIP Demo - Intel€¦ · Select the file ‘Altera-SoCFPGA-HardwareLib-XIP-CV-GNU.zip’ and click ‘Open’ 7. Click ‘Finish’ to import the project. 8. Go to Project->Build