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1 PRESENTED BY SHAHBAZ SARIK B.Tech 5 th Sem ECE MD ASHRAF ADIL MD ASHRAF ADIL B.Tech 5 th Sem ECE

Quiz the World Using Fpga

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Page 1: Quiz the World Using Fpga

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PRESENTED BY

SHAHBAZ SARIK B.Tech 5th Sem ECEMD ASHRAF ADILMD ASHRAF ADIL B.Tech 5th Sem ECE

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Specially designed for quizzing.Contains quiz buzzer and marking

scheme.Completely wireless.Sucessfully implemented and tested.

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INTRODUCTION

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System requirementsSystem requirements

Software toolsFPGA boardLaserLdr

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PICTURES

SPARTAN 3 LASER

LDR

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System descriptionSystem description

It has three different parts:

1.Control segment. 2.Teams 3.Receiver and displayer.

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DISPLAY

R S

D

D

D

U

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UD S S

S S

S S

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S S

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System diagram

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LDR

SOURCE

WORKING OF THE SENSOR

CORESSPONDING CIRCUIT

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--Library declaration library IEEE; use IEEE.std_logic_1164.all; --Entity declaration entity quizbuzzer is

port (reset: in STD_LOGIC;team: in STD_LOGIC_VECTOR (4 downto 0);buz: out STD_LOGIC_VECTOR (4 downto 0)

); end quizbuzzer; --Architecture architecture quizbuzzer of quizbuzzer is begin

process(reset,team)variable active:std_logic;begin

if(reset='1')thenbuz<="00000"; active:='1';

Buzzer code

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elsif(active='1' and team="00001")thenactive:='0';buz<="00001";

elsif(active='1' and team="00010")then active:='0';buz<="00010";

elsif(active='1' and team="00100")then active:='0';buz<="00100";

elsif(active='1' and team="01000")then active:='0';buz<="01000";

elsif(active='1' and team="10000")then active:='0';buz<="10000";

end if;end if;

end process; end quizbuzzer;

Code ends

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library IEEE;use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all;--Entity declarationentity \quiz marking scheme\ is port( clk: in std_logic;

reset : in STD_LOGIC; t1 : in STD_LOGIC_VECTOR(1 downto 0);

t2 : in STD_LOGIC_VECTOR(1 downto 0); t3 : in STD_LOGIC_VECTOR(1 downto 0); t4 : in STD_LOGIC_VECTOR(1 downto 0); t5 : in STD_LOGIC_VECTOR(1 downto 0); m1 : inout STD_LOGIC_VECTOR(4 downto 0); m2 : inout STD_LOGIC_VECTOR(4 downto 0); m3 : inout STD_LOGIC_VECTOR(4 downto 0); m4 : inout STD_LOGIC_VECTOR(4 downto 0); m5 : inout STD_LOGIC_VECTOR(4 downto 0)

);end \quiz marking scheme\;

Code for marking scheme--Library declaration

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architecture \quiz marking scheme\ of \quiz marking scheme\ is begin process(reset,clk,t1,t2,t3,t4,t5,m1,m2,m3,m4,m5)begin

if(reset='1')thenm1<="00000"; m2<="00000";m3<="00000";m4<="00000";m5<="00000";

--Incrementingelsif(clk'event and clk='1' and t1(1)='1')then

m1<=m1+"00001";elsif(clk'event and clk='1' and t2(1)='1')then

m2<=m2+"00001";elsif(clk'event and clk='1' and t3(1)='1')then

m3<=m3+"00001";elsif(clk'event and clk='1' and t4(1)='1')then

m4<=m4+"00001";elsif(clk'event and clk='1' and t5(1)='1')then

m5<=m5+"00001";

--Archtecture declaration

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elsif(clk'event and clk='1' and t1(0)='1' and m1>"00000")thenm1<=m1-"00001";

elsif(clk'event and clk='1' and t2(0)='1' and m2>"00000")thenm2<=m2-"00001";

elsif(clk'event and clk='1' and t3(0)='1' and m3>"00000")thenm3<=m3-"00001";

elsif(clk'event and clk='1' and t4(0)='1' and m4>"00000")thenm4<=m4-"00001";

elsif(clk'event and clk='1' and t5(0)='1' and m5>"00000")thenm5<=m5-"00001";

end if;end process;

end \quiz marking scheme\;

--Decrementing`

Code ends04/11/23 12

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Schematic diagram

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Technology schematic

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Simulation result

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ADVANTAGESADVANTAGES 

Completely wireless

Fully portable  Reprogrammable as per user requirement  Cost efficient  High accuracy.   

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QUERIES??