R11 Statistical Analysis of Random Telegraph Noise in ... Workshops/2017 Workshop/2017 Papers/… · Statistical Analysis of Random Telegraph Noise in Source Follower Transistors

Statistical Analysis of Random Telegraph Noise in Source Follower Transistors with Various Shapes

Shinya Ichinoa, Takezo Mawakia, Shunichi Wakashimaa, Akinobu Teramotob, Rihito Kurodaa,

Phillipe Gaubertb, Tetsuya Gotob, Tomoyuki Suwab and Shigetoshi Sugawaa,b aGraduate School of Engineering, Tohoku University,

bNew Industry Creation Hatchery Center, Tohoku University 6-6-11, Aza-Aoba, Aramaki, Aoba-ku, Sendai, Miyagi, Japan 980-8579

TEL: +81-22-795-4833, FAX: +81-22-795-4834, Email address: [email protected]

ABSTRACT In this paper, a statistical analysis of random telegraph

noise (RTN) in source follower (SF) transistors with various shapes using an array test circuit is discussed. It is shown that a transistor without shallow trench isolation (STI) edge is effective for reducing RTN and the influence of traps at the source side on RTN is significant, from the evaluation of transistors with asymmetric gate width of source and drain.

INTRODUCTION RTN is one of the most crucial problems in high-

sensitivity CMOS image sensors. RTN occurs at in-pixel source follower amplifier of CMOS image sensors, and it causes deterioration of image quality, especially in low light scenes[1]. RTN in MOSFETs is caused by capture/emission of the carriers by/from traps in the gate insulator film[2]. RTN is a stochastic event and the influence of RTN becomes larger as the scale-down of CMOS circuits continues. It is difficult to reduce the effect of RTN by circuit technology only, therefore, it is necessary to introduce device and process technologies in a transistor level to reduce RTN. As methods to reduce RTN, for instance, introductions of buried channel transistor[3], atomically flat gate insulator film[4] and transistors with ring shaped gate[5-6] have been reported to be effective.

In this paper, a statistical analysis of RTN in SF transistors with various shapes (rectangle, trapezoid and octagon) using an array test circuit is discussed.

ARRAY TEST CIRCUIT STRUCTURE AND EVALUATION SYSTEM

Fig. 1 shows the block diagram of the array test circuit and Fig. 2 shows layout diagrams of the measured SF transistors with various gate sizes and gate shapes. The details of design specifications summarized in Table 1. In this research, besides general rectangular transistors, trapezoidal and octagonal transistors were also fabricated. Here, trapezoidal transistors are effective for the evaluation of influence of the trap location along source-drain direction[7]. Octagonal transistors are effective for the evaluation of the influence of the STI edge on carriers in the channel[5-6]. There are three rectangular transistors in Table 1. Here, Pix. 1 is a reference rectangular transistor. Pix. 2 and Pix. 3 are the

rectangular transistors of the same area as trapezoidal and octagonal transistors, respectively. Each type of transistor was fabricated with a common gate length of 0.52 μm. These are all buried channel transistors[3]. There are 4608 pixels for each transistor type and these pixels are arranged in an array as a CMOS image sensor. In the column circuits, there are two readout paths used for different measurement modes. One path is connected to analog memories similar to conventional CMOS image sensor. The other path is directly connected to chip output buffer, it is used for high speed continuous signal sampling for selected pixels. Fig. 3 and Table 2 show the chip micrograph and the design specifications, respectively. There are 384H × 299V pixels in this chip, including other SF transistors with different specifications in terms of gate insulator film thickness and carrier type in addition to the gate size and the gate shape. In this paper, we focus on the analysis of the gate sizes and the gate shapes. Fig. 4 shows a measurement board used to evaluate the RTN. In this measurement board, a low floor noise of 60 μVRMS is obtained.

Fig. 1. Block diagram of the array test circuit.

Fig. 2. Layout diagrams of the SF transistors.

Horizontal Shift Register

Verti

cal S

hift

Reg

iste

r

CX2 CX1

VCLR

VVCLR

SEL

NS

SS CAM1

CAM2

OutputBuffer

Pixel Array

T

XPD

R1 R2

VR1 VR2

CFD

Unit pixel

SF

WSSource

WDWAve

L

Gate

DrainWS

(WD)

L

WAve Drain(Source)

Source(Drain)

Gate

WD (WS)

STI edge

W

DrainSource

Gate

STI edge

L

Trapezoidal SF Octagonal SFRectangular SF

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between the two well defined discrete states may also be captured during the measurement. The unsettled data points are highlighted as the red area in Fig. 3.

Accordingly, in Fig. 3, we define a “settling ratio” for the 3-peak histogram as the ratio of the number of the settled points (the blue area) vs. the total sample size (the sum of the blue and the red area). Intuitively, we expect that the settling ratio depends on the time constants of both the circuits and the RTN traps.

The settling ratios are plotted against the RTN time constants for the 1,000 noisiest pixels in Fig. 11, under the 1X and 8X gains. The settling ratios ap-proach 100% for pixels with longer time constants, but decrease sharply for pixels with shorter time constants. For the same pixel with a fixed time con-stant, the settling ratio is higher at 1X gain than that at 8X gain. Because the column amplifier bandwidth, determined by the ratio of the feedback capacitance C2 and the sampling capacitance C1, is higher at 1X gain than that at 8X gain.

To understand the data, we developed a RTN behavior model in MATLAB to simulate the settling ratio dependence on the time constant. First, we generate an ideal random telegraphic waveform for a single-trap RTN using random numbers for a given pair of emission and capture time constants with a large number of emission-capture transitions. Second, the time-domain waveform is transformed into the frequency domain using the FFT, multiplied by a low-pass filter corresponding to the circuit time con-stant, and transformed back to the time domain using the inverse FFT. Then, the periodically sampled RTN histogram and the settling ratio can be calculated from the resulting telegraphic waveform. Fig. 12 shows that the data in Fig. 11 can be reasonably re-produced by the RTN behavior model, where the circuit time constants at 1X and 8X gains are

approximately 0.24s and 0.64s, respectively, from circuit simulation.

Conclusions

In summary, a new on-chip RTN time constant extraction method was developed, based on the re-laxation from the correlated to the uncorrelated dou-ble sampling. The pixels of an 8.3MP array are sorted into four different groups according to the number of observable RTN traps. The effects of circuit band-width on RTN settling ratio and time constant ex-traction were studied and accounted for in MATLAB behavior simulation.

Reference [1] J. Janesick et al., Proc. SPIE, vol. 7742, 2006. [2] X. Wang et al., IEDM, 2006, pp. 115-118. [3] K. Abe et al., IISW, 2007, pp. 62-65. [4] T. Obara et al., JJAP, Vo1.53, 2014, pp. 04ECI9.1-7. [5] R. Kuroda, ICMTS, 2016, pp. 46-51 (and references therein) [6] C. Chao et al., J-EDS, vol. 5, no. 1, 2017, pp. 79-89. [7] M.F. Snoeij et al., Workshop on CCD & AIS, 2005. [8] C. Walck, “Handbook on statistical distributions for exper-

imentalists,” Stockholm, Sweden, 2007, Ch. 15, pp. 57-60.

Figure 10. The distributions of the extracted time constants at 1X gain in (a) and (b); 8X gain in (c) and (d), for 1-peak and 3-peak pixels, respectively.

Figure 11. The RTN settling ratios of all 3-peak pixels vs. the time constants measured at 1X and 8X gain, respectively.

Figure 12. The MATLAB simulated RTN settling ratio vs. the characteristic time constant 𝜏𝜏𝑠𝑠 under various circuit settling time constants.

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Table 1 The measured SF transistor structures in pixel arrays.

Fig. 3. Array test chip micrograph.

Table 2

Array test chip design specifications.

Technology 1P5M 0.18μm CMOS with

Pinned Photodiode Die Size 4800μm

H × 4800μm

V Pixel Size 10μm

H × 10μm

V Number of Pixels 384H × 299V Pixels

Fig. 4. Picture of measurement board.

RESULTS AND DISCUSSIONS

Fig. 5 shows the measured IDS-VGS characteristics of SF transistors used for Pix. 1~6. Here, typical transistors prepared on the wafer were measured. These are buried channel transistors, which is effective for reducing RTN[3]. In this graph, it is clear that the transistors with special shapes draw IDS-VGS curves differently from the normal (rectangular) transistors. The threshold voltages are negative due to the buried channel structure[3]. Table 3 shows the subthreshold swing factors (SS) and the SF gains of these transistors. For the trapezoidal transistors, there is a clear difference of the SS between the transistors with larger or smaller gate width at the source side. SS is the smallest in Pix. 6.

Fig. 6 shows the cumulative probability of VRMS in the Gumbel plot. In this graph, the cumulative probability is calculated by 4608 pixels in the array test circuit and VRMS is defined as the root mean square when output signals of each pixel are sampled for 100000 points at 1μs period. The output voltages were 1.9 V for each type of transistor. In Fig. 6(a), the measured results of transistors with different gate widths under constant drain current (1.0 μA) are shown. Under the constant drain current, the distribution of VRMS is smaller for larger gate width. In Fig. 6(b), a comparison between the rectangular and octagonal transistors with nearly equal gate area under the drain current at 0.1 μA and 1.0 μA is shown. From the results, the appearance probability of RTN in octagonal transistors is less than the rectangular transistors with almost the same gate area under each drain current. Fig. 6(c) shows a comparison between the two trapezoidal transistors under the constant drain

current density. The result shows that the trapezoidal transistors with the larger gate width at the source side tend to exhibit larger VRMS values than the transistors with the smaller gate width at the source side.

Pixel Array

(384Hx299V)

Column ReadoutCircuits

Vert

ical

Shi

ft R

egis

ter


ADC Amp.

Buffer

to FPGA from FPGA

GND

Chip

Voltage Generation

CircuitExternal Power

Source Connector

BoardPower Source

Pixel No. SF Type SF Shape L

[μm] W [μm] W/L Area

[μm2] Number of

Transistors Targets Pix. 1

3.3V nMOS (Buried Channel)

Rectangle 0.52 0.34 0.65 0.177 18048 Reference

Pix. 2 0.52 3.27 6.29 1.700 4608 Almost the same W/L as Pix. 6 Pix. 3 0.52 0.66 1.27 0.343 4608 Same W/L as Pix. 4 and Pix. 5 Pix. 4

Trapezoid 0.52 WAve:0.66

WS/WD:0.98/0.34 1.27 0.343 4608 Low current density at source side. Pix. 5 0.52 WAve:0.66

WS/WD:0.34/0.98 1.27 0.343 4608 High current density at source side. Pix. 6 Octagon 0.52 WAve:3.78

WS/WD:5.51/2.06 7.27 1.968 4608 Without STI

-1.0 -0.5 0.0 0.5 1.0 1.5 2.010-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Pix1_W034 Pix2_W327 Pix3_W066 Pix4_WSL Pix5_WSS Pix6_Octagon

ID (A

)

VGS (V)

Sample Names SS(mV/decade) SF gain

Pix. 1 Rectangular SF (W=0.34) 118 0.84Pix. 2 Rectangular SF (W=3.27) 112 0.84Pix. 3 Rectangular SF (W=0.66) 111 0.84Pix. 4 Trapezoidal SF (WS>WD) 141 0.83Pix. 5 Trapezoidal SF (WS<WD) 118 0.80Pix. 6 Octagonal SF 100 0.84

-1.0 -0.5 0.0 0.5 1.0 1.5 2.010-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Pix.1 Rectangular SF (W=0.34) Pix.2 Rectangular SF (W=3.27) Pix.3 Rectangular SF (W=0.66) Pix.4 Trapezoidal SF (WS>WD) Pix.5 Trapezoidal SF (WS<WD) Pix.6 Octagonal SF

IDS

[A]

VGS [V]

11uA

VDS=1.3V VBS=0.0V

1uA

0.1uA

Fig. 5. IDS-VGS characteristics of SF transistors.

Table 3 Subthreshold swing factors and SF gains of transistors in Fig. 5.

Subthreshold swing factors were extracted at a drain current range from 10-9 A to 10-7 A.

SF gains were extracted at VDS=1.3 V and IDS=15 μA.

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Table 2




H × 4800μm

V Pixel Size 10μm

H × 10μm







Pixel Array

(384Hx299V)


Vert

ical

Shi

ft R

egis

ter


ADC Amp.

Buffer

to FPGA from FPGA

GND

Chip

Voltage Generation


Source Connector

BoardPower Source



[μm2] Number of








WS/WD:5.51/2.06 7.27 1.968 4608 Without STI

-1.0 -0.5 0.0 0.5 1.0 1.5 2.010-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3


ID (A

)

VGS (V)



-1.0 -0.5 0.0 0.5 1.0 1.5 2.010-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3


IDS

[A]

VGS [V]

11uA

VDS=1.3V VBS=0.0V

1uA

0.1uA







Table 2




H × 4800μm

V Pixel Size 10μm

H × 10μm







Pixel Array

(384Hx299V)


Vert

ical

Shi

ft R

egis

ter


ADC Amp.

Buffer

to FPGA from FPGA

GND

Chip

Voltage Generation


Source Connector

BoardPower Source



[μm2] Number of








WS/WD:5.51/2.06 7.27 1.968 4608 Without STI

-1.0 -0.5 0.0 0.5 1.0 1.5 2.010-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3


ID (A

)

VGS (V)



-1.0 -0.5 0.0 0.5 1.0 1.5 2.010-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3


IDS

[A]

VGS [V]

11uA

VDS=1.3V VBS=0.0V

1uA

0.1uA





Fig. 7 shows VRMS values of rectangular and octagonal transistors at the cumulative probability of 99.9% as a function of drain current. When the drain current is large, both VRMSs are nearly equal. On the other hand, as the drain current becomes smaller, the VRMS becomes larger in the rectangular transistors. Fig. 8 shows 4608 IDS-VGS curves of rectangular and octagonal transistors, respectively. The output voltages were at 1.9 V for each type of transistors. It is clear that for the octagonal transistors, the variation of VGS at low drain current is smaller and the slopes of IDS-VGS curves in sub-threshold region is higher than those of the

rectangular transistors. Furthermore, comparing Fig. 8(a) with (b) and from the IDS-VGS curves of Fig. 2, the drain current is larger in the rectangular transistors than the octagonal transistors at low VGS. This is because, as shown in Fig. 9, when the VGS is low in the rectangular transistors, the effect of the parasitic transistor due to the sub-channel formed by electric field concentration around the STI edge are greater. Fig. 10 shows the standard deviation of VGS in the rectangular and the octagonal transistors as a function of the drain current. When the drain current becomes smaller, the σVGS becomes larger in rectangular transistors, whereas it

SiSiO2Main Channel Sub

Channel

Electric FieldTrap

Gate Electrode

10-7 10-6 10-57

8

9

10

11

12

13 Rectangular SF (Pix. 2) Octagonal SF (Pix. 6)

σVG

S [m

V]

IDS [A]

4608 nMOSFETs(Buried Channel)

VBS= -1.9V

10-7

10-6

10-5

0.1 0.2 0.3 0.4 0.5VGS [V]

IDS

[A]

10-7

10-6

10-5

0.1 0.2 0.3 0.4 0.5VGS [V]

IDS

[A]

Rectangular SF(Pix. 2)


VBS= -1.9V VBS= -1.9V

Octagonal SF(Pix. 6)


10-7 10-6 10-5

100

120

140

160

180

200

220 Rectangular SF (Pix. 2) Octagonal SF (Pix. 6)

VRM

S at

99.

9% [

V]

IDS [A]


VBS=-1.9V

Fig. 10. Standard deviation of VGS as a function of drain current (Pix. 2 and Pix. 6).

Fig. 8. IDS-VGS characteristics of all evaluated transistors (4608 pixels). (a) Rectangular transistors (Pix. 2), (b) Octagonal transistors (Pix. 6). The output voltages were at 1.9 V for each type of transistor.

Fig. 7. VRMS values at cumulative probability of 99.9% as a function of drain current (Pix. 2 and Pix. 6).

Fig. 6. Cumulative probability of the VRMS. (a) Comparison of different gate width under constant drain current (IDS = 1.0 μA), (b) Comparison between rectangular transistors and octagonal transistor with nearly equal gate area (IDS = 1.0 μA, 0.1 μA), (c) Comparison between trapezoidal transistors under constant drain current (IDS = 1.0 μA). The output voltages were at 1.9 V for each type of transistors.

Fig. 9. The effect of parasitic transistor due to the sub-channel formed by electric field concentration around STI edge.

0 100 200 300 400 500 600 700-2

0

2

4

6

8

10

Cum

ulat

ive

Prob

abilit

y [%

]

Line2_L052W034_1uA_Vbs1.9 Line6_L052W066_1uA_Vbs1.9 Line5_L052W327_1uA_Vbs1.9

99.99

90

110

50

99.9

99

VRMS [V]

-ln(-ln(P))

0 100 200 300 400 500 600 700-2

0

2

4

6

8

10

Cum

ulat

ive

Prob

abilit

y [%

]

Line9_Octagon_0.1uA_Vbs1.9 Line9_Octagon_1uA_Vbs1.9 Line5_L052W327_0.1uA_Vbs1.9 Line5_L052W327_1uA_Vbs1.9

99.99

90

110

50

99.9

99

VRMS [V]

-ln(-ln(P))0 100 200 300 400 500 600 700

-2

0

2

4

6

8

10

-ln(-ln(P))

Line7_Trapezoid_WS_large_1uA_Vbs1.9 Line8_Trapezoid_WS_small_1uA_Vbs1.9

Cum

ulat

ive

Prob

abilit

y [%

]

99.99

90

110

50

99.9

99

VRMS [V]

3.27/0.52(Pix.2)

0.66/0.52(Pix.3) 0.34/0.52

(Pix.1)

(W/L)

WS<WD(Pix.5)

WS>WD(Pix.4)


VD=3.3V, VBS=-1.9V IDS=1.0μA

Sampling rate=1μsec100000 sampling


VD=3.3V, VBS=-1.9V IDS=0.1μA, 1.0μA



VD=3.3V, VBS=-1.9V IDS=1.0μA


1.0μA(Pix.6)

0.1μA(Pix.6)

1.0μA(Pix.2)

0.1μA(Pix.2)

(Pix.6)

(Pix.2)

(a) (b) (c)

(a) (b)

− 41−

does not change very much in octagonal transistors. Therefore, the transistor structure which does not have the influence of STI edge in the channel carriers is effective for reducing the threshold voltage variation. Fig. 11 shows the correlation between VRMS and SS for the rectangular and the octagonal transistors, respectively. SS was extracted at current range of 10-7 A to 10-6 A. Here, the SS of transistors with VRMS higher 90 μV showing RTN signals were plotted. It is clear that pixels where RTN is observed are often found in an area larger than the average SS value indicated by dotted lines in this figure. The obtained result shows that transistors with large SS lead to large VRMS

[8] in rectangular and octagonal transistors. Fig. 12 shows the appearance probability of transistors with RTN, defined by VRMS of more than 90 μV as a function of the segmented SS regions for rectangular and octagonal transistors. Here, the bin size of SS was taken at 2 mV/decade. It is clear that when SS becomes larger, the appearance probability of transistors with large VRMS becomes higher[8]. Comparing these two types of transistors, there are large SS values in rectangular transistors. It shows that the percolation of channel occurs due to the STI edge. Furthermore, the result suggests that the trap density at the STI edge is higher than that at the gate insulator film on main channel because the appearance probability of octagonal transistors is smaller than that of rectangular transistors at the same range of SS. Fig. 13 shows the cross sectional views of the trapezoidal transistors. Comparing (a) with (b), the transistors with narrow gate width at source side induce

higher carrier density at source side than transistors with narrow gate width at drain side under constant drain current operation. For this reason and from the distribution in Fig. 6(c), it is considered that the increase of current density at source side is effective for reducing RTN because the traps near source side are more influential to the RTN appearance probability[7], and higher drain current density operation reduces the effect of the parasitic transistor due to the sub-channel formed by electric field concentration around the STI edge.

CONCLUSION

In this paper, by evaluating the array test circuit with various shapes of SF transistors in pixels of a CMOS image sensor, it was demonstrated that transistor without STI edge is effective for reducing RTN because of the suppression of generating percolated channel around STI edge where the trap density is likely to be high. It was also shown that increasing carrier density at source side of the channel is effective to reduce RTN. These findings are important to the design of in-pixel SF transistors with small RTN for low noise CMOS image sensors.

REFERENCES [1] C. Leyris et al., Proc. ESSCIRC, p. 376, 2006. [2] M. J. Kirton, et al., Adv. Phys. 38, p. 367, 1989. [3] A. Yonezawa, et al., Proc. Int. Rel. Phys. Symp., p. 3B.5.1, 2012. [4] T. Goto, et al., JJAP 54, p.04DA04-1, 2015. [5] D. Pates, et al., ISSCC, Tech. Dig. Papers, p.418, 2011. [6] M.W. Seo, et al., IEEE Trans. ED, 61, 6, p. 2093, 2014. [7] K. Abe, et al., Proc. Int. Rel. Phys. Symp, p.996, 2009. [8] R. Kuroda, et al., IEEE Trans. ED, 60, 10, pp. 3555, 2013.

Drain

Source

STI

Gateinsulator

filmTrap

Si

－－－－－－－－

Drain

Source

STI

Si

－－－－－－－－

Gateinsulator

film

90 100 110 120 13010-1

100

101

102

Rectangular SF (Pix. 2)Octagonal SF (Pix. 6)

Appe

ranc

e pr

obab

ility

of T

r.w

ith R

TN [%

]

Subthreshold Swing Factor [mV/dec]

90

140

190

240

290

340

90 100 110 120 130 140

Subthreshold Swing Factor [mV/dec]

VRM

S [

V]

90

140

190

240

290

340

90 100 110 120 130 140

VRM

S [

V]Subthreshold Swing Factor [mV/dec]

Average:109 mV/dec

Rectangular SF(Pix. 2)

VBS= -1.9VIDS=0.1μA

Average:101 mV/dec

Octagonal SF(Pix. 6)



bin size= 2mV/dec

Fig. 11. Correlation between VRMS and SS for (a) rectangular transistors (Pix. 2), (b) octagonal transistors (Pix. 6).

Fig. 12. Appearance probability of transistors with RTN as a function of SS.

Fig. 13. Cross sectional views of trapezoidal transistors. (a) Trapezoidal transistor with shorter gate width at source side, (b) Trapezoidal transistor with longer gate width at source side.

(a) (b)

(a) (b)

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Documents

R11 Statistical Analysis of Random Telegraph Noise in ... Workshops/2017 Workshop/2017 Papers/… · Statistical Analysis of Random Telegraph Noise in Source Follower Transistors