Radia%on(Hardened(Very(Low(Power((ASICs

Micro-RDCMicroelectronics Research Development CorporationMicro-RDCMicroelectronics Research Development Corporation

29th Annual AIAA/USU Conference on Small Satellites

Radia%on Hardened Very Low Power ASICs for Satellite Command Control and Data Handling (C&DH) and Sensor Integra%on


Sasan Ardalan, Donald Elkins Micro-RDC

2100 Airpark Rd. SE, Suite 120; Albuquerque, NM 87106 [email protected]

2 Micro-RDCMicroelectronics Research Development CorporationMicro-RDCMicroelectronics Research Development Corporation


Outline •  Structured ASIC 90nm IBM 9LP Process Overview •  Radia=on Hardened by Design •  System on a Chip ASIC Overview •  Support Chip Parallel EEPROM to SPI Slave Conversion •  Post Silicon Verifica=on with Robo=c ARM Demonstra=on •  Reference Rad Hard Cubesat design with 32bit OpenRISC SoC ASIC as C&DH •  Conclusions •  Ques=ons



Funding Support

•  The development of the ASICs has been funded by the Air Force Research Laboratory (AFRL).



Structured ASIC 90nm CMOS IBM 9LP Hardness Es=mate:

•  TID > 1Mrad(Si) •  SEU < 1e-‐8 Errors/day •  SEL > 100 MeV-‐cm2/mg (LET)



RHBD Circuit Approach (SEU and SET)

Ref: Mavis, Eaton 2002

Ref: Mavis, MRQW 2007



BGA Packaging with 0.8mm Pitch for the 7x7mm and 3x3mm ASIC Die



8051XC SoC ASIC 7x7mm Die



Power Consump%on of the 8051XC SoC ASIC Silicon



Rad Hard Real Time Clock

•  From Evatronics Design Guide on Real Time Clock for 8051XC

–  The Real Time Clock realizes a real =me count with a resolu=on of 1/256th second. It allows the user to read seconds, minutes, hours, day of the week and the date. The date is represented by a 16-‐bit number, which value is interpreted by the user socware. The RTC enables a count of 179 years. The RTC features an alarm func=on which may be used to generate interrupts at a given =me during a day or periodically. These interrupts may be used to resume opera=on from the IDLE/DEEP SLEEP mode at a given =me.



Cores and Peripherals for the 32 bit OpenRISC SoC and Super Mini-‐PnP SoC ASICs

32bit OpenRISC SoC 7x7mm Die Super Mini-PnP SoC 5x5mm Die

Mini-PnP 8 Bit RISC 8Kx14 Instruction



32 BIT OPEN RISC SOC ASIC



Bondout of the 32 bit OpenCores SoC ASIC to an LGA-‐484 package (22x22) 7x7 mm Die



32 bit OpenRISC SoC ASIC Core Current Consump%on versus Clock Frequency



PARALLEL NVM TO SPI CONVERSION SUPPORT CHIP ASIC

3x3 mm Die Support Chip ASIC Bonded Out to LGA-484 Package for Post Silicon Verification



Support Chip ASIC used to Convert a Parallel EEPROM (NVM) to a SPI interface to Support Firmware Bootup

to the SoC ASICs



Silicon Verifica=on of Support Chip EEPROM Interface

Rad Hard Support Chip ASIC designed so that System on a Chip (SoC) ASICs can Bootup from Rad Hard Parallel EEPROMS or Read Data from Parallel EEPROM and Program the EEPROM.

• The chip provides a Slave SPI Interface to Parallel EEPROMs. • We have verified that we can program a parallel EEPROM via the SPI Slave interface of the Support Chip. • Support for 16 MBytes or 128 MBits of Storage. • We have demonstrated that the Rad Hard Parallel EEPROMs in space can be reprogrammed using the Support Chip via a SPI interface.



Test Setup for The Support Chip to Provide SPI Slave Interface to ATMEL Parallel EEPROM for Reading and Wri%ng



Close Up View of Daughter Card for ATMEL EEPROM interface through 100 MHz Hirose FX-‐2 Connector to Support Chip ASIC



32bit OpenRISC SoC and Support Chip Integra%on (Robo%c ARM Control )



Robo%c ARM Control using the 32 bit OpenRISC SoC ASIC



Robo%c ARM Setup for Control Using the 32bit OpenRISC SoC ASIC



Robo%c ARM Setup Board Close Up



Robot ARM Demonstra%on Showing I2C LCD Displaying Bar Charts for Robot ARM Posi%ons. Also LED Matrix Shows Posi%on



Reference Rad Hard Cubesat design with 32bit OpenRISC SoC ASIC as C&DH



References Ardalan, S, et.al., Radiation Hardened by Design 90nm CMOS ASIM Chip for Space-borne Sensor

Applications, Respace/MAPLD August 24 , 2011 Ardalan, S, et.al., Radiation Hardened by Design 8 bit RISC with Dual I2C Bus Support and SPI for

External NVM Support, Small Sat Conference, August 8 , 2011 Ardalan, Sasan, et. al., On-demand On-line Scrubbing of the RHBD Structured ASIC Appliqué

Sensor Interface Module, RESPACE/MAPLD November 1-4, 2010. Ardalan, S, Don Elkins, et. al, High Density Interconnect Technology (HDI) for Chip Scale and Land

Grid Array Packaging for Space Qualifiable Radiation Hardened Systems on a Chip Solutions, GOMACTech 2013

Mavis, D.G. and Eaton, P.H., Soft Error Rate Mitigation Techniques for Modern Microcircuits,

Proceedings of the 2002 International Reliability Physics Symposium (IRPS), pp. 216-225. Mavis, D.G. and Eaton, P.H., Temporally Redundant Latch for Preventing Single Event Disruptions

in Sequential Integrated Circuits, United States Patent Number 6,127,864, October 2000. Mavis, D.G., Radiation Hardened by Design Structured ASIC and Reliable Digital Components,

MRQW 2007. Baxter, Julius, Open Source Hardware Development and the OpenRISC Project: A Review of the

OpenRISC Architecture and Implementations, Master’s Thesis at IMIT, 2011

Documents

Radia%on(Hardened(Very(Low(Power((ASICs