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Static Random Access Memory
삼성전자 (주)
변 현 근
1. Introduction of SRAM
2. SRAM Cell and Basic Core Operation
3. SRAM Chip Architecture
4. High Speed SRAM Circuit Technique
CONTENTS
1-1. Basic Architecture and AC/DC Characteristics
1. Introduction of Static Random Access Memory
I/O Circuit
Clk Gen. Pre-Charge Circuit
Row
Dec
oder
WriteDriver
ClkGen.
An+1 An+2 . . . . An+m
MEMORY ARRAY 2 Rows 2 Columns
n
m
Column Decoder
A1A2A3.. ...
An
I/O1..
I/Oi
/WE
/OE
/CS
VddVss
1-1-1. Functional Block Diagram of Standard SRAM
Address
/CS
/OE
Data Out Data ValidHigh-Z
tCO
tOH
tRC
tAA
tOLZ
t LZ
tOHZ
t HZ
tOE
1-1-2. Typical Read Cycle Timing
Parameter Symbol
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Output Enable to Low-Z Output
Chip Enable to Low-Z Output
Output Disable to High-Z Output
Chip Disable to High-Z Output
Output Hold from Address Change
tRC
tAA
tCO
tOE
tOLZ
tLZ
tOHZ
tHZ
tOH
UnitMin Max
KM68V1002-12
12
-
-
-
0
3
0
0
3
-
12
12
6
-
-
6
6
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min Max
15
-
-
-
0
3
0
0
3
-
15
15
7
-
-
7
7
-
Min Max
20
-
-
-
0
3
0
0
3
-
20
20
8
-
-
8
8
-
KM68V1002-15 KM68V1002-20
Example of 1Mb SRAM
(From SAMSUNG SRAM Databook 1996)
1-1-3. Typical Write Cycle Timing
Address
/CS
/WE
Data InHigh-Z
tCW
tDH
tWC
tAW
t WP
t WR
tOWHigh-Z
tWHZ
tAS
tDW
/OE
Data Out
Data Valid
Example of 1Mb SRAM
Parameter Symbol
Read Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
UnitMin Max
KM68V1002-12
12
8
0
8
12
0
0
6
0
3
-
-
-
-
-
-
6
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min Max
15
10
0
10
15
0
0
7
0
3
-
-
-
-
-
-
7
-
-
-
Min Max
20
12
0
12
20
0
0
8
0
3
-
-
-
-
-
-
9
-
-
-
KM68V1002-15 KM68V1002-20
(From SAMSUNG SRAM Databook 1996)
1-1-4. DC and Operating Characteristics
Parameter Symbol Test Conditions Min Max Unit
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current
Output Low Voltage
Output High Voltage
VIN=Vss to Vcc
/CS=VIH or /OE=VIH or /WE=VIL
VOUT=VSS to Vcc
Min. Cycle, 100% Duty
/CS=VIL, VIN=VIH or VIL,
IOUT=0mA
Min. Cycle, /CS=VIH
f=0MHz, /CS -0.2V,
VIN -0.2V or VIN
IOL=8mA
IOH = - 4mA
ILI
ILO
ICC
ISB
ISB1
VOL
VOH
-2
-2
-
-
-
-
-
-
-
-
2.4
2
2
200
20
10
0.1
0.4
-
uA
uA
mA
mA
mA
V
V
≥ Vcc ≤ 0.2V
≥ Vcc Normal
L-ver.
(TA= 0 to 70 C, Vcc=3.3V 0.3V)±0
Example of 1Mb SRAM DC Power
(From SAMSUNG SRAM Databook 1996)
1-2. SRAM Features
1-2-1. Low Power SRAM
= Low Power Supply Voltage : 5V -> 3V -> 1.8V -> sub 1.0V
-> Low Power Dissipation for Handheld Application
= Low Standby Power Dissipation : 100uA -> 10uA -> 1uA
-> support for Data Retention Application
= Small Size Package : sTSOP, CSP(uBGA, FPBGA), MCP
-> reduce the package area for Handheld Application
set-upData Retention Mode
Recovery
/CS Vdd-0.2V
Vdd
3.0V
2.2V
VDR
/CSGND
≥
Data Retention Mode
Transition Timing to Battery
Battery Back-Up System
Main PowerSupply Voltage
Battery Back-UpVoltage
C L
to SRAM Power Supply Voltage
1-2-2. FAST SRAM
= Power Supply Voltage : 5V, 3.3V
-> JEDEC standard power supply voltage
= Low Operating Power Dissipation
-> Application for large amount of SRAM usage
= FAST Speed requirements : 8ns-20ns
1-2-3. Synchronous SRAM
= Low Power Supply Voltage : 3.3V -> 2.5V -> 1.8V
-> Small geometry Transistor technology to improve speed
= Various Sync. SRAM Features : LW(Late Write), DLW(Deep Late Write),
DDR(Double Data Rate)
-> Late Write operation to enhance the bus efficiency
= High Bandwidth Interface : LVTTL -> LVCMOS -> HSTL
= FAST Speed Requirements : 150MHz-over 500MHz(1Gbps)
= High Performance Package Solution : TQFP, BGA, FCBGA
Various Sync. SRAM Features
Standard Write (Register-Register/Pipe Line)
RA1
Q1
tCYC
ADDRESS
DQx
CLK
WA2 A3
D2
Read Write
Q3
RA1
Q1
tCYC
ADDRESS
DQx
CLK
WA2 A3
D2
Read Write
Q3
Standard Write (Register-Latch/Flow Through)
RA1
Q1
tCYC
tCD
ADDRESS
DQx
CLK
WA2
D2 Q3
RA3 WA4
Read Write Read
Late Write (Register-Register/Pipe Line)
Late Write (Register-Latch/Flow Through)
RA1
Q1
tCYC
tCD
ADDRESS
DQx
CLK
WA2
D2 Q3
RA3 WA4
Read Write Read
D4
Write
Deep Late Write (Register-Register/Pipe Line)
A1
Q1
tCYC
tCD=5ns
ADDRESS
DQx
CLK
A2
D2
A3 A4
Q3 D4
ReadWrite Write
Read
1X CLK2X Data Rate
DQ (Burst)
ADDR. RD1
D21 D22 D23 D24 Q31 Q32
WR2 RD3
Q11 Q12 Q13 Q14 Q33 Q34
Read ReadWrite
Double Data Rate (Register-Register/Pipe Line)
High Bandwidth Interface
Min. 1.2VSwing
Min. 1.4VSwing
TTL LVTTL HSTL(VREF=0.75~1.0V)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Min. 1.0VSwing
LVCMOS
0.8V
2.2V
0.8V
2.0V
0.7V
1.7V
Voltage
0.65~0.9V
0.85~1.1V
1.5V Interface
2.5V Interface
Min. 0.2V Swing
5V Interface
3.3V Interface
1-3. SRAM cell Technology
= Low cost, High Density Commodity SRAM for Small Microprocessor controlled system
. Change from NMOS Cell to Mix-MOS Cell
= Low Standby power for Battery Back-Up and Battery Operated System
. Change from Mix-MOS Cell to TFT(Thin Film Transistor) or Full CMOS Cell
= FAST speed for Cache SRAM
. Change from NMOS Cell to Mix-MOS or Full CMOS Cell
PMOS Enhancement Load Cell
1-3-1. History of SRAM memory cells
- Substituting Bipolar SRAM Cell . High device yield and low cost. Low standby power dissipation as compared with the bipolar SRAM cell
- Use diffusion process to make MOS transistor in mid of 1960s. Limitation of the low power supply voltage due to increase Vtp
X YXY
-Vdd
DataLine
DataLine
. 64 bit Array
. SiO2 120nm
. Vdd = -18V
. 150 - 200ns
( From Joseph H. Friedrich [1], Fairchild 1968 )
- Substituting PMOS Load SRAM Cell . Meet sub 100ns speed
- Use high doping substrate or substrate bias in end of 1960s. High stand-by power dissipation. Limitation of small cell size
X
Vdd
BitLineBit
Line
X
. 144 bit Array
. Vdd = 12V
. 40ns write cycle
( From Yasuo Tarui. et al., [2] NEC 1969)
NMOS Enhancement Load Cell
- Substituting NMOS Enhancement Load SRAM Cell . Fully static with no dynamic or bootstrapped node. Low voltage operation (5V supply voltage) due to the low threshold voltage
- Use ion implantation process. High stand-by power dissipation. Limitation of small cell size
X
BitLineBit
Line
X
. 1K bit Array
. SiO2 120nm
. Vdd = 5V
. 150ns
( From R.M.Jecmen. et al., [3] Intel 1974)
NMOS Depletion Load Cell
- Substituting NMOS Load SRAM Cell . Cost effective chip size. Low stand-by dissipation
- Negative Temperature Coefficient Resistance: Isb = I0 exp (-Ea/KT). Compensate the temperature dependence of the junction leakage current
and the subthreshold current- Have been used 16Kb SARM to 1Mb SRAM since end of 1970s
. Limitation of low stand-by power dissipation for high density SRAM
. Limitation of low power supply voltage (less 2.5V) operation- High density limitation [4]
. SLOW : 4Mb (with 1uA stand-by current)
. FAST : 4Gb (minimum 4mA stand-by current)
X
BitLineBit
Line
X
High-Resistivity Poly Load Cell (Mix-MOS)
Arsenic Implanted region
Length
PolysilicionResistor
CVD SIO2
SIO2
- Compatible cell size as compared with poly load cell- Low stand-by power dissipation with retaining data retention voltage- Improved SER (Soft Error Rate)- Using high density SRAM (4Mb SRAM) since end of 1980s
. Complicated process. Limitation of low power supply voltage (less 3.0V) operation
X
BitLine
BitLine
X
P-WELL
N+ N+
Gate
TFTChannel
TFT Gate
Bottom Gate TFT
P-WELL
N+ N+
Gate
TFTChannel
TFT Gate
Top Gate TFT
P+ P+ P+ P+
TFT (Thin Film Transistor) Load Cell
- Ultra low stand-by power dissipation with good data retention characteristics- Good stability for wide noise margin
. Less 2.0V low power supply voltage operation- Good SER (Soft Error Rate) Characteristics- Future SRAM Technology for Low Vdd/Ultra High speed product- Limitation of small cell size
. Mainly used internal cache of MPU
X
BitLineBit
Line
X
Full CMOS Cell
1-3-2. Comparison of layout of load devices in SRAM memory cells
NMOS and Mix-MOS SRAM cell
Depletion mode Load Single polysilicon Cell Double polysilicon Cell
- Cell size reduction. scaling from 3um CMOS to 2um CMOS. adding the second level of polysilicon for the stacked load resistor [5]
Full CMOS SRAM cell
Single aluminum interconnect Double aluminum interconnect
- Cell size reduction. adding the second level of metal for the local interconnection [6]
1-4. SRAM Technology for Peripheral Circuits
= MOS SRAMs are the fastest MOS memories.
= Bipolar SRAMs are the fastest of all memories.
1-4-1. Bipolar
- Application for ultra high speed SRAM . Cache and Main Memory in high performance mainframe computers. ECL interface
- High cost and High power dissipation
- Lower cost than Bipolar
- Limitation of high density and high performance due to complicated circuit design . need dynamic circuit and bootstrapped circuit technique
- Limitation of low power dissipation and high speed
1-4-2. NMOS
1-4-3. CMOS
1-4-4. BiCMOS
- High speed . application for small volume/high performance
- Complicated process [7][8]
. use triple diffused BiCMOS process
- Limitation of low power supply voltage [9]
. improve the MOS Transistor (Lower Vth)
. use BiNMOS or NBiCMOS
. Base boost technique
- Low cost and low power dissipation- Easy to make high density SRAM
- Limitation of high speed
. improve the MOS Transistor
. use Dynamic Gate Logic
Propagation Delay with Process Technology
0
100
200
300
400
500
600
700
800
0 1 2 3
CMOS
AMOS
BiCMOS
CMOS
3D-BiCMOS
BiCMOS
tPD (ps/stage)
Laod capacitance CL(pF)
Vdd=3.3V
Temp=25℃
150
200
250
300
350
400
450
500
1.5 2 2.5 3 3.5 4 4.5 5 5.5
CMOS
AMOS
BiCMOS
tPD (ps/stage)
CMOS
3D-BiCMOS
BiCMOS
Power Supply Voltage Vdd(V)
CL=1pFTemp=25℃
(From H.G. Byun et al. [10], Samsung 1995)
0
1
2
3
4
5
1.5 2.5 3.5 4.5 5.5
CMOS
BiCMOS
BiNMOS
NBiCMOS
tPD (ps/stage)
Power Supply Voltage Vdd(V)
CL=1pFTemp=25℃
2
CMOS BiCMOS BiNMOS NBiCMOS
Propagation Delay with Inverter Logic (From H.G. Byun et al. [10], Samsung 1995)
2-1. SRAM Cell Operation
2-1-1 Chip Power-Down Mode (Stand-By)
2. SRAM Cell and Basic Core Operation
X
BitLineBit
Line
X
L
Off
Off
X
BitLineBit
Line
X R R
H L
ON
Vdd
Isb
H
- One inverter is always ON for the Poly Laod or NMOS Load cellswhen in the standby mode.. Current(Isb) is drawn from Vdd
- In the Full-CMOS cell, one transistor in each of the coupled inverters is OFF.. Only junction leakage current is drawn from Vdd
2-1-2. Data Retention
X
BitLine
BitLine
X R R
Isp
Ion
Isd
Ij
Vdd
Vnh VnlVbl
- Data Retention Voltage (Vdr). Min. power supply voltage to retain high node data in the standby mode.
- a prerequisite of Data RetentionIon [= (Vdd - Vnh) / R] > Isp + Isd + Ij
Where Ion = Charge CurrentIsp = Sbthreshold current of Pass Transistor @ VDS=Vnh-Vbl, Vgs=0VIsd = Sbthreshold current of Pull-down Transistor @ VDS=Vnh, Vgs=VnlIj = Junction leakage for high node @ Vnh
1 105 1010
No
of C
ells
Charge Current / Leakage Current
1 105 1010
No
of C
ells
Charge Current / Leakage Current
High Resistive Poly Load Cell
BitLineBit
Line
BitLineBit
Line
? ?
ON
10-13A
10-15A
OffOff
Off
Off
10-15A
10-8A
10-13A
ON
10-13A
? ?
ON
Off
Off
Off
TFT (Thin Film Transistor) Load Cell
Marginal Large Margin
(From T.Y.OOTAMI. et al. [11], Toshiba 1990)
Data Retention Margin
2-2. Read/Write Operation
Word Line
R
BL
R
FULL CMOS CELLPOLY LOAD CELL
/BL BL /BL
DATA BUS
/DATA BUS
ColumnSelect
ColumnSelect
To Sense Amplifier and Data Input Buffer
Read/Write Margin Analysis
/BL
BL
/BLWL
TripPoint
RM (Read Margin)
WM (Write Margin)
WL
L L
A A
B B Iread
D D
E
Iwrite
WL
R
A A
B B Iread
D D
E
Iwrite
R
TP
D : A
A : B
D : E
Read Operating Region
Write Operating Region
2-2-1. Poly Load Cell Read/Write Operation
TP: MEMORY CELL TRIP VOLTAGE
BIT
LIN
E V
OL
TA
GE
WL
A A
B B Iread
D D
E
Iwrite
C C
TP
D : A
C : A : B
(D // C+A) : E
Read Operating Region
Write Operating Region
2-2-2. Full CMOS Cell Read/Write Operation
BIT
LIN
E V
OL
TA
GE
TP: MEMORY CELL TRIP VOLTAGE
2-3. SRAM Cell Stability
2-3-1 Static-Noise Margin (SNM)
What is the Static-Noise margin (SNM)?
+ -
+ -
Vn
Vn
Vn : Static Noise Source
SNM : Maximum Value of Vn
WL
/BLBL
Static-Noise margin (SNM) for Poly Load Cell
Assumption
- Q1, Q2, Q3 : Saturation Region
- Q4 : Linear Region
MOS Models
- Id = 1/2 (Vgs - Vth) 2 Saturation Region
- Id = Vds (Vgs - Vth - 1/2 Vds) Linear Region
where = W/L . eff Cox
β
β
β μ
Analytic Expressions
- Kirchhoff Current Equation
Id1 = Id3 , Id2 = Id4
- Kirchhoff Voltage Equation
Vgs3 = Vn + Vds4
Vgs1 = Vdd - Vn - Vgs4
Vgs2 = Vdd - Vds4
R
Q3
R
Q4
dβ
Vn+ -
? ?+ -
Vn
dβID3 ID4
ID1 ID2
aβ aβQ1 Q2
Vdd
Results
SNM (Vn(MAX)) = γ√ - 1 γ√ + 1
Vth + γ+ 1 - √2 3/2 + + 1 γ γ
γ γ√ + 1 ( )(Vdd - Vth)
where (Cell Ratio) = / γ aβdβ
(From E. Seevink. et al. [12], 1987)
Saturated Enhancement Load Inverter
R
Vout
ID3
ID1
Vdd
Vin
Vout
Vin
Vdd
Voh
Vol
Vth Vdd
1 Subthreshold Region :sharply Drop to Vdd - Vth (with Body Effect)
2 Driver Saturated
3 Driver Nonsaturated
SNM with Supply voltage
0
100
200
300
400
500
600
0 1 2 3 4 5 6
Theory Equation
Simulation (Simple Model)
Simulation (Extended Model)
stat
ic n
oise
mar
gin
SN
M [
mV
]
Supply Voltage [V]
(Source : IEEE Journal of Solid -State Circuits 1987)
Ratio = 3.5γ
DC Transfer Characteristics
SNM of Poly Load Cell
SNM with Cell ratio
0
100
200
300
400
500
600
700
0 1 2 3 4 5 6
Theory Equation
Simulation (Simple Model)
Simulation (Extended Model)
Vdd = 5Vst
atic
noi
se m
argi
n S
NM
[m
V]
Ratio
(Source : IEEE Journal of Solid -State Circuits 1987)
(From E. Seevink. et al. [12], 1987)
(From E. Seevink. et al. [12], 1987)
- Good correlation between theory equation and simple model- Slope difference for the extended model simulation
--> caused by omitted short channel effect from the simple model
Static-Noise margin (SNM) for Full CMOS Cell
Assumption
- Q2, Q3 : Saturation Region
- Q4, Q5 : Linear Region
MOS Models
- Id = 1/2 (Vgs - Vth) 2 Saturation Region
- Id = Vds (Vgs - Vth - 1/2 Vds) Linear Region
where = W/L . eff Cox
β
β
β μ
Analytic Expressions
- Kirchhoff Current Equation
Id3 = Id5 , Id2 = Id4
- Kirchhoff Voltage Equation
Vgs3 = Vn + Vds4
Vgs5 = Vdd - Vn - Vds4
Vds5 = Vdd - Vn - Vgs4
Vgs2 = Vdd - Vds4
Q3 Q4
dβ
Vn+ -
? ?+ -
Vn
dβID3 ID4
ID5
ID2
aβ aβQ1 Q2
Vdd
pβ
Results SNM (Vn(MAX))
= Vth -(k + 1)
1 [
γ+ 1Vdd -
γ2 + 1Vth
1 + γ
γ+ 1k ( )
√- ]
Vdd - 2Vth
+1 + kγ
qγ
q (1 + 2k + k2 )γ
q
where (Cell Ratio) = / γ aβdβ q = / aβpβ
k = γ
γ+ 1 √γ+ 1 - Vs2 / Vr2( γ+ 1 - 1) k = Vs -
γγ+ 1
Vth
Vs = Vdd - Vth
(From E. Seevink. et al. [12], 1987)
Vout
ID3
ID1
Vdd
Vin
Vout
Vin
Vdd
Voh
Vol
Vth Vdd
1 NMOS SaturatedPMOS Nonsaturated
2 NMOS NonsaturatedPMOS Saturated
Saturated Enhancement Load Inverter
SNM of Full CMOS Cell
DC Transfer Characteristics
0
100
200
300
400
500
600
700
0 1 2 3 4 5 6
Theory Equation
Simulation (Simple Model)
Simulation (Extended Model)
stat
ic n
oise
mar
gin
SN
M [
mV
]
Supply Voltage [V]
Ratio = 2γ
Ratio = 1γ
(Source : IEEE Journal of Solid -State Circuits 1987)
300
400
500
600
700
800
900
0 1 2 3 4 5 6
Theory Equation
Simulation (Simple Model)
Simulation (Extended Model)
Ratio
stat
ic n
oise
mar
gin
SN
M [
mV
]
Vdd = 5V
Vdd = 3V
(Source : IEEE Journal of Solid -State Circuits 1987)
- Good correlation between theory equation and simulation--> Short channel effect is compensated by the PMOS transistor.
- Optimum SNM can be obtained through proper choice of ratio (r and q) for Vdd.
SNM with Supply voltage(From E. Seevink. et al. [12], 1987)
SNM with Cell ratio (From E. Seevink. et al. [12], 1987)
Static-Noise Source (Vn)
- DC Disturbance. Layout Pattern Offset . Process mismatches
: Non-uniformity of ion-implantation or Gate oxide thickness etc.
- Dynamic Disturbance. Alpha( ) Particles. Crosstalk. Voltage supply ripple. Thermal noise
α
Memory cell Asymetry
L L
A+ A-
B- B+
x y
SNM
Half Cell transfer curvesVy
Vx
2-3-2. Dynamic-Noise Margin (DNM)
Assumptions
- Q2, Q3 : Weaker Device. High Threshold Voltage. Longer channel Length. Narrow channel width
- BL and /BL are precharged to Vdd
(From Barbara Chappel. et al. [13], 1985)
WL
/BLBL
L L
? ?Q1 Q2
Q3 Q4
- 1 . 5
- 1
- 0 . 5
0
0 . 5
1
1 . 5
0 1 2 3 4 5
Cha
nge
in V
olta
ge
Initial Stored High Voltage
Region 1
No change instored high
Region 4 Region 3 Region 2
Some discharging ofstored high
Some refresh ofstored high
Cell swtchesstate
(1) Region 1- The device on the high node of the cell (Q3) did not conduct during the read.
(2) Region 2- Current through Q3 caused some discharging of the stored high during the read- the voltage on the low node ??having increased enough to turn Q3 momentarily
while the large precharged bitline capacitance was being discharged.(3) Region 3
- The current through Q3 more than compensated the discharge current through Q1.(4) Region 4
- The cell switches to the opposite state because the devices have been mismatched.
2-4. SRAM Cell Speed and Power
dt = [ Ctot / Iread ] dV
Where dt is read speed for core(bit line and data bus line) operation.
Ctot is capacitance load fixed by SRAM density.
Iread is cell current fixed by pass gate size (A)
dV is voltage swing fixed by ratio (D : A)
WL 1
L L
A A
B B
D D
WL 2
L L
A A
B B
E E
CBL CBL
CDB CDB
Iread
LH
2-5. Memory Cell Alpha Particle Sensitivity
- Decreasing Q alpha [14]
. Polyimid coating (blocks alphas)
. Adopting a p-well structure is useful in reducing the collection efficiency
. The area ratio of n+ storage region(A and B) to the other n+ region(Vdd and Ground., etc)has to be small to reduce the collection efficiency
. The two individual storage nodes(A and B) are placed closely.
- Decreasing Charging Time of the High Storage Node [15]
. use DWL(Divided Word Line) architecture to increase average interval time ( ti )
. use TFT(Thin Film Transistor) Load or Full CMOS cell to decrease Charging time ( tch )
- Balance the Load characteristics to improve the stability
- Increasing cell capacitance and cell stability (Cell size issue)
delta V = Qalpha / Ccell
To improve SER immunity
BL /BL
WL
Load
Vdd Vdd
IL(on)
Qalpha
Ccell
A B
Ground Ground
3. SRAM Chip Architecture
3-1. High Density SRAM Array
3-1-1. Problems
Example of 64K SRAM Architecture
Where Iread = 100uA/ColumnPoly1(for Word Line) Resistance 5 Ohm/ㅁ
Line Width 1umcapacitance 2fF/gate
Bit Line Capacitance (CBL) 3.9 fF/cell
Power Dissipation for Read operation: 256 Column @ 100uA/Column
= 25.6mA
Word Line Speed: Resistance (R) 256 x10um/1um x 5 Ohm/ㅁ
= 12.8 Kohm: Capacitance (C) 2 x 256 Gates @ 2fF
= 1.024 pFRC Delay = 13.1ns
Bit Line Speed: Capacitance (C) 256 cells x 3.9fF/cell
= 1 pF: Bit Line Slew Rate (dV/dt=Iread/CBL) = 100mV/ns2ns for 200mV swing
256 x 256Memory
Array
memory cell10um x 10umBit Line Precharge
Row
Decoder
Column Decoder
Sense Amplifier
I/OCircuitry
Address
3-1-2. Divided Word Line & Bit Line Architecture
Example of 64K SRAM Architecture
Where Iread = 100uA/ColumnPoly1(for Word Line) Resistance 5 Ohm/ㅁ
Line Width 1umcapacitance 2fF/gate
Bit Line Capacitance (CBL) 3.9 fF/cell
Power Dissipation for Read operation: 64 Column @ 100uA/Column
= 6.4mA
Word Line Speed: Resistance (R) 64 x10um/1um x 5 Ohm/ㅁ
= 3.2 Kohm: Capacitance (C) 2 x 64 Gates @ 2fF
= 0.256 pFRC Delay = 0.8ns
Bit Line Speed: Capacitance (C) 128 cells x 3.9fF/cell
= 0.5 pF: Bit Line Slew Rate (dV/dt=Iread/CBL) = 200mV/ns1ns for 200mV swing
I/OCircuitry
Column Decoder
64 x
128
BL PreR
ow D
ecod
er
64 x
128
Row
Dec
oder
64 x
128
64 x
128
BL Pre BL Pre BL Pre
Sense Amplifier
Column Decoder
64 x
128
Row
Dec
oder
64 x
256
Row
Dec
oder
64 x
128
64 x
128
BL PreBL Pre BL Pre BL Pre
Address
3-2. Chip Architecture for High Density SRAM
3-2-1. Divided word line (DWL) structure[16]
Simplified schematic concept of DWL Performance enhancement on 64K RAM
3-2-2 Shared word-line and hierarchical word-line structure[17]
Shared word-line structure for a 72K SRAM
3-2-3 Divided bit-line structure[18]
Block diagrams of shorten the bit-lines
3-2-4. Variable Impedance Bitline Loads[19]
CELL
SAT
SAT
/BLBL
DB
/DB
/SAS
Word Line
P2(WE)
P2(/WE)
Ai
/WE
Bit Line
Word Line
4. High Speed SRAM Circuit Technique
4-1. Address transition detection (ATD) for improved speed[20]
ATD - Address transition Detection
SPi
SPj
DelayAiD
AjDDelay
SAT
Ai
Aj
Ai
AiD
SPi
Aj
AjD
SPj
SAT
ATD - How it is used
CELL
SAT
SAT
SAT
/BLBL
DB
/DB
SAS
/SAS
Bit Line Shorter
Data Line Shorter
Sense Amp. Shorter
WORDLINE
SAT
BIT LINE
DATA BUS
SENSE AMP
4-2. Fast sense amplifier
Data Sensing Scheme
V0+Vi-Vi+
Vref Constant Current (Biased Saturation)
Current Mirror(High Gain)
CURRENT MIRRIORSINGLE ENDED
V0+Vi- Vi+
VrefConstant Current (Biased Saturation)
Biased Linear(Resistive)
V0-Vref
CLASICAL FULL DIFFERENTIAL
(W/L)n1
(W/L)p1
(W/L)n2
(W/L)p2
- Determine the sense amplifier scheme[21]
. Current mirror amplifier with high CMRR(Common -mode rejection ratio)
. Current multiplier with high driving capability - Determine the number of stage
Current Mirrior: (W/L)n2
(W/L)n1
(W/L)p2
(W/L)p1= = 1
Current Multiplier: (W/L)n2
(W/L)n1
(W/L)p2
(W/L)p1= = N > 1
Speed vs. Gain - How many stages?
CASE 1: 1 Stage - A = 16
2.4V
150mV
8ns
SLEW RATE = 150mV/ns
INPUT
OUTPUT SLEW RATE = 150mV/ns
CASE 2: 4 Stage - A = 2
2.4V
150mV
4ns
SLEW RATE = 150mV/ns
SLEW RATE = 1.2V/ns
SLEW RATE = 150mV/ns
OUTPUT
INPUT
SLEW RATE = 600mV/ns
SLEW RATE = 300mV/ns
1ns
1ns
1ns
1ns
4-3. Dynamic circuitry[22]
IN
Precharge
N
Out
Dynamic State
Dynamic State
IN
weak keeper
Qf
Qf Precharge
C
Out
QrQs
Qs
QfN
- Separate pull-up and pull-down operation during transition time.
- Lower the loading on output driver.
- Decrease the switching logic threshold.
Basic Dynamic gate
IN
1
2
Out
Qs: Slow Keeper TransistorQf: Fast Transistor for Enable PathQr: Reset Transistor for Self-Resetting
Reset Timing Chain
IN OUT
1
2
Qs Qr
Qf
Qf
Qs QrQf
Qs Qr
Qf
IN OUT
(From T. Chappell et al. [23], 1991)
4-4. Fast datapath
Address Decoder
o
- Reduce the address decoder delay using PMOS load decoders and Divided wordline Architecture
- Short bit-line & Data Bus using 90 rotated architecture
PMOS load decoder CMOS load decoder trade-off in current and cycle time
(From Sasaki, K. et al. [24], 1988)
Short bit-lines Architecture
traditional orientation of word-lins andbit-lines
layout at 90 to traditional orientation intended to shorten the bit-lines
o
(From Kohno, Y et al. [25], 1988) (From Sasaki, K. et al. [24], 1988)
4-5. Interface Circuit Technique
- Reduce the impedance variation with temperature and voltage
Impedance Controlled Output Driver Scheme
ZQCOUNTER
ZQ COMPARATOR
ZQ DRIVER
DOUTBUFFER
DLAT
DLATB
VDDQ
DQ
DOUx
DODx
UP/DOWN
ZQ DETECTORNMOS
ARRAY
VDDQ
ZQPAD
VZQ
EXT. RZQ
REFUP MOS
ARRAY
Off Chip Driver
(*From Cell Array)
NMOSARRAY
VDDQ
R1
R1
(From Pilo, H. et al. [26], 1996)
References
[1] J.H. Friedrich , “A coincident-select MOS storage Array” , IEEE Journal of Solid-State Circuits, Sep 1968, PP280-285
[2] Y. Tarui. et al., “A 40ns 144bit n-channel MOS LSI Memory” , IEEE Journal of Solid-State Circuits, Oct 1969, PP271-279
[3] R.M. Jecmen. et al., “HMOS II Static RAMs overtake bipolar competition” , Electronics, Vol. 52, Sep 1979, PP124-128
[4] H. Kato. et al., “Consideration of poly-si loaded cell Capacity Limits for Low Power and High-Speed SRAMs” ,IEEE Journal of Solid-State Circuits, Apr 1992, PP683-685
[5] T. Ohzone, et al., “ Ion-Implanted Ti Poly Crystalline-Silicon High Value Resistor for High density Poly Load Static RAM Application” , IEEE Trans. Electron Devices, ED-32, 1985, PP1749
[6] T. Watanabe, et al., “A Bettery Backup 64K CMOS SRAM with Double-Level Aluminum Technology” , IEEE Journal of
Solid-State Circuits, Oct 1983
[7] K. Miyata, “BiCMOS Technology overview” , 1987 IEDM Short Course on BiCMOS Technology, Oct 1987
[8] Young. I. et al., “A High Performance 256K TTL SRAM Using 0.8um Triple Diffused BiCMOS with 3V Circuit Techniques”Symposium on VLSI Circuits, Digest of Technical Papers, May 1991, PP17-18
[9] H. Momose. et al., “A Supply Voltage Design for half Micron BiCMOS gates”, Symposium on VLSI Technology , Digest of Technical Papers, May 1989, PP55-56
[10] H.G. Byun. et al., “고속 SRAM 개발 동향”, 전자공학회지 제22권 제2호, 95년 2월, PP90-97[11] T.Y. Ootani. et al., “A 4Mb CMOS SRAM with a PMOS Thin-Film Transistor Load cell”, IEEE Journal of Solid-State Circuits,
Oct 1990, PP1082-1091[12] Evert Seevinck. et al., “Static Noise Margin Analysis of MOS SRAM cells”, IEEE Journal of Solid-State Circuits,
Oct 1987, PP748-754[11] B. Chappel. et al., 밪tability and SER Analysis of Static RAM cells ?, IEEE Journal of Solid-State Circuits, Feb 1985, PP383-399
[13] B. Chappel. et al., “Stability and SER Analysis of Static RAM cells”, IEEE Journal of Solid-State Circuits, Feb 1985, PP383-399
[14] K. Anami. et al., “A 35ns 16K NMOS Static RAM”, IEEE Journal of Solid-State Circuits, Oct 1982, PP815-820
[15] M. Yoshimoto. et al., “A Divided Word-Line Structure in the Static RAM and its Application to a 64K Full CMOS RAM”,IEEE Journal of Solid-State Circuits, Oct 1983, PP479-484
[16] M. Yoshimoto. et al., “A Divided Word-Line Structure in the Static RAM and its Application to a 64K Full CMOS RAM”,IEEE Journal of Solid-State Circuits, Oct 1983, PP479-484
[17] M. Segawa, et al, “A 18ns 8KW x9b NMOS SRAM”, ISSCC Proceedings, Feb. 1986, PP202
[18] S.T. Flannagan. et al., “ Two 13ns 64K CMOS SRAMs with very low Active Power and Improved Asynchronous Circuit Technique”, IEEE Journal of Solid-State Circuits, Oct 1986, PP692-702
[19] Yamamoto, S. et al., “A 256K CMOS SRAM with Variable Impedance Data-Line Loads”, IEEE Journal of Solid States Circuits,Vol. SC-20, No.5, Oct. 1985, PP924
[20] L. C. Sood, et al., “A 35ns 2Kx8 HMOS Static RAM”, IEEE Journal of Solid-State Circuits, Oct 1983, PP498[21] K. Ochii, et al., “A 17ns 64K CMOS SRAM with a Schmitt Trigger Sense amplifier” , ISSCC Proceedings, Feb. 1985, PP64[22] Proceedings of VLSI Circuit Workshop , 1996 Symposium on VLSI Circuits[23] T. Chappell et al., “A 2ns Cycle, 4ns Access 512Kb CMOS ECL SRAM”, ISSCC Digest of Technical Papers, Feb 1991, PP50-51 [24] Sasaki, K. et al., “A 15ns 1-Mbit CMOS SRAM”, IEEE Journal of Solid State Circuits, Vol. 23, No.5, Oct 1998, PP1067[25] Kohno, Y. et al., “A 14ns 1Mb CMOS SRAM with Variable Bit Organization, IEEE Journal of Solid State Circuits, Vol. 23, No.5,
Oct. 1988, PP1060[26] Pilo, H. et al., “A 300MHz, 3.3V 1Mb SRAM Fabricated in a 0.5um CMOS Process”, ISSCC Digest of Technical Papers,
Feb. 1996, PP148-149