Reading: Chapter 6.1-6

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Combinational Circuits

Courtesy of Dr. Brown, Dr. Vranesic, Dr. Harris, Dr. Zhou and Dr. Hadimioglu

Reading: Chapter 6.1-6.6

❑Combinational logic

●Output at any time is determined completely by the current input.▪ We will later consider circuits where the output is determined by the input

and the current state (memory) of the system.

● In this chapter we will consider some useful building blocks that can be pieced together and used in larger designs.

●This will include:▪ Multiplexers (selectors) and demultiplexers (distributors)

▪ Encoders, priority encoders, decoders

▪ Adders (full and half, refer to last chapter)

▪ Parity generators and parity checkers

▪ Shifters and rotators

▪ Comparators

11/1/2021 2CSCE2114: Digital Design

Introduction

❑Standard decoder is an N-to-M decoder, where M ≤ 2N

●Can be written as N:M or NxM decoder

●All outputs Dm are inactive except for the one corresponding to the binary value of the input An…A1A0.

●Example: 3-to-8-line decoder


Basic Decoder (DEC)

3-t

o-8

D

ecod

er

20

21

22

0

1

1

0 0

1 0

2 0

3 0

4 0

5 0

6 1

7 0

Example:

Input of 110

3-t

o-8

D

ecoder

20

21

22

A0

A1

A2

D0

D1

D2

D3

D4

D5

D6

D7

0

1

2

3

4

5

6

7

❑Enable signal

●Often, combinational logic building blocks will also have an enable line that turns on outputs or leaves them off.

❑3-to-8 Decoder with Enable


Decoders With Enable

3-t

o-8

D

ecoder

A0

A1

A2

Module Enable

20

21

22

E

D0

D1

D2

D3

D4

D5

D6

D7

0

1

2

3

4

5

6

7

❑ Truth table for a 3-to-8-line decoder:


3-to-8 Decoders

OutputsInputs

A2 A1 A0 E D7 D6 D5 D4 D3 D2 D1 D0

X X X 0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0 0 0 1

0 0 1 1 0 0 0 0 0 0 1 0

0 1 0 1 0 0 0 0 0 1 0 0

0 1 1 1 0 0 0 0 1 0 0 0

1 0 0 1 0 0 0 1 0 0 0 0

1 0 1 1 0 0 1 0 0 0 0 0

1 1 0 1 0 1 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0 0

❑Any Boolean function can be implemented

●Using a decoder and OR gates

●OR together the function’s minterms.


Logic Synthesis with Decoders

OutputsInputs

A2 A1 A0 F1 F2

0 0 0 0 0

0 0 1 1 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 1

1 1 0 0 0

1 1 1 1 0

3-t

o-8

D

ecoder

0

1

2

3

4

5

6

7

20

21

22

F2

F1A0

A1

A2

❑We can also use multiple decoders to form a larger decoder.

●3-to-8 Decoder Implemented with two 2-to-4 Decoders


Expand Decoders

A2 used with enable input to control which decoder will output the 1.

A1 and A0 used to select

which output on specific

decoder will output 1.

2-t

o-4

D

ecoder 0

1

2

3

D0

D1

D2

D3

20

21

E

2-t

o-4

D

ecoder D4

D5

D6

D7

A0

A1

A2

20

21

E

0

1

2

3

❑Standard binary encoder is an m-to-n encoder, where m ≤ 2n

●Only one input should be active

●Example: 8-to-3-line encoder


Basic Encoder (ENC)

8-t

o-3

E

ncoder

20

21

22

0

0

1

0 0

0 1

0 2

0 3

1 4

0 5

0 6

0 7

Example:Input of 00010000

8-t

o-3

E

ncoder

20

21

22

A0

A1

A2

D0

D1

D

0

1

2 2

D3 3

D4 4

D5 5

D6 6

D7 7

E

Module Enable

❑ Truth table for an 8-to-3-line encoder:

●Assumed that only one input is 1.


Encoder Truth Table

OutputsInputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

❑Encoder assumes only a single input is active:

●Encoders are useful when the occurrence of one of several disjoint events needs to be represented by an integer identifying the event.

●Example: Wind direction encoder


Designing With Encoders

8-t

o-3

E

ncod

er

0

1

2

3

4

5

6

7

20

21

22

1

0

0

E

1

NNE

E

SES

SW

NW

W

❑A priority encoder

● takes the active input with the highest index and translates that index

●A valid bit indicates if the inputs are active


Priority Encoders (P-ENC)

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 V

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 0 1 X 0 0 1 1

0 0 0 0 0 1 X X 0 1 0 1

0 0 0 0 1 X X X 0 1 1 1

0 0 0 1 X X X X 1 0 0 1

0 0 1 X X X X X 1 0 1 1

0 1 X X X X X X 1 1 0 1

1 X X X X X X X 1 1 1 1

0 0 0 0 0 0 0 0 X X X 0

Inputs Outputs

❑Priority encoders are useful when inputs have a known priority

●Example: Resolving interrupt requests


Design With P-ENC

❑Selects one of many inputs to be directed to an output


Basic Multiplexer (MUX)

OutputInputs

X Y A3 A2 A1 A0 F

0 0 X X X 0 A0=0

0 1 X X 0 X A1=0

1 0 X 0 X X A2=0

1 1 0 X X X A3=0

0 0 X X X 1 A0=1

0 1 X X 1 X A1=1

1 0 X 1 X X A2=1

1 1 1 X X X A3=1

4x1

Multip

lexer

0

1

2

F

S1 S0

X Y

A0

A1

A2

A3 3

E

Module Enable


Design a 2:1 MUX

(a) Graphical symbol

f

s

w0

w1

0

1

(b) Truth table

0

1

f

fs

w0

w1

(c) Sum-of-products circuit

s

w0

w1

(d) Circuit with transmission gates

w 0

w 1 f

s

❑Logic function


Design a 4:1 MUX

F= S1 S0 A0 + S1 S0 A1 + S1 S0 A2 + S1 S0 A3

S1

A0

A1

S0

A3

A2

F

❑ The 4x1 MUX can be implemented with pass gates:

●Only one of An gets passed to output depending on the value of X and Y


Design a 4:1 MUX

F

A0

A1

A2

A3

Y X

❑You can form basic gate functions from MUX


MUX As A Logic Element

A B AND

0 0 0

0 1 0

1 0 0

1 1 1

A B XOR

0 0 0

0 1 1

1 0 1

1 1 0

4:1 MUX

S1 S0

F = AB

0

1

2

31

A B

0

0

0

4:1 MUX

S1 S0

F = A + B

0

1

2

30

A B

0

1

1

❑Any Boolean function can be implemented

●Set the inputs corresponding to the truth table

●Set selectors as the variables.


Logic Synthesis with MUX

8x1

Mu

ltip

lexe

r

F

E

Module Enable

0

X Y Z

7S2 S1S

0 0

1 1

0 2

1 3

0 4

0 5

1 6

0

Example:X Y Z F

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 0

❑We can reduce the size of mux if other gates are allowed

● If INV is allowed, reduce the selector by 1

● If two input gates are also allowed, reduce the selector by 2


Logic Synthesis with MUX

Example:

4x1MUX

F

E

Module Enable

X Y

S1 S0

Z 0

Z 1

0 2

Z 3

2x1MUX F

E

Module Enable

X

S0

Z 0

YZ 1

X Y Z F

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 0

❑Larger MUX can be designed with smaller MUX

●Example: Design a 4-to-1 MUX with 2-to1 MUX

●Note the order of the selectors


Expand MUX

Y

A0

A1

0

1

fY

A2

A3

0

1

X

0

1

❑ Takes one input and selects one output to copy the input.


Basic DeMultiplexer (DEMUX)

X Y F3 F2 F1 F0

0 0 0 0 0 D

0 1 0 0 D 0

1 0 0 D 0 0

1 1 D 0 0 0

1x4

D

em

ultip

lexe

r 0

1D

F0

F1

2 F2

3 F3

E

Module Enable

S1 S0

X Y

Inputs Outputs

❑DeMUX1x4


Design a 1:4 DEMUX

S1

F0

F1

S0

F3

F2

D

F3 = S1 S0 D

F2 = S1 S0 D

F1 = S1 S0 D

F0 = S1 S0 D

❑A demux is useful for routing an input to a desired location.

●Example:


Design With DEMUX

1x4

D

em

ultip

lexe

r 0

1

2

3

E

S1 S0

X Y

Processing Unit 0

Processing Unit 1

Processing Unit 2

Processing Unit 3

Selects which PU to send the input data.

Input Data

1

❑Larger DEMUX can be design with smaller DEMUX

●Example Design a 1:8 DEMUX


Expand DEMUX

1:4

DEMUX

F0

F3

F2

F1

S1 S0

3

2

1

0

1:2

DEMUX

D

S2

1

0

1:4

DEMUX

F4

F7

F6

F5

S1 S0

3

2

1

0

❑Given two n-bit magnitudes, a comparator indicates whether:

●A = B, A > B, or A < B


Comparators

G Greater (A > B)

E Equal (A = B)

L Less (A < B)

cinG

cE

in

cL

in

Greater

Equal

Less

Cascaded input values from other

comparators

n-bit input magnitudes

A B

n nResults of

comparisons

4-Bit Comparator

Documents

Reading: Chapter 6.1-6