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REASON (IST-2000-30193) Third Annual Report Workpackage 3. Raimund Ubar Tallinn Technical University r aiub@pld . ttu.ee. Tasks and Goals. WP3 is devoted to training in design for testability of SoC , and develop ing research skills and creativity by development of - PowerPoint PPT Presentation
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3rd Annual Review MeetingSinaia, Romania, February 21-22, 2005
REASON (IST-2000-30193)Third Annual Report
Workpackage 3
Raimund UbarTallinn Technical University
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Tasks and Goals
WP3 is devoted to – training in design for testability of SoC, and – developing research skills and creativity
by– development of
• courses (Task 3.1), • tools (Task 3,2), • research scenarios (Task 3.3), and
– dissemination of new methods and tools in tutorials, seminars and workshops (Task 3.4)
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
WP3 Timeline
Month 0 6 12 18 24 30 36
Task 3.1 Courses Task 3.2 Tools Task 3.3 Scenarios Task 3.4 Delivery Deliverables D3.1 D3.2 D3.3 D3.4 Milestones M1 M2 M3 M4
The development activities in T3.1, T3.2, and T3.3 were mainly related to new initiatives and AGBOT
Environment
AGBOT
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
New Activities in T3.2 & T3.3
• Task 3.2. Teaching, training and research environment• Task 3.3. Research scenarios
• Internet based “living pictures” for training (WP8)– development of research scenarios
• Tool development for SW based lab research (WP3)– interfaces for joint use of tools
• Educhip for HW based lab research (WP9)– software development for EduChip– Research scenarios for EduChip
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Contribution to WP3 in 2004
TeachingMaterials
T3.1
ToolsT3.2
TrainingActions
T3.4
ResearchScenarios
T3.3
TULC, TTU, WUT
TTU, IISAS, TULC,
FEISTU
TULC, VSTU, IISAS, FEISTUBSU,TTU,WUT
TTU,TUI,TULCIISAS, FEISTU,
VSTU, LPU,WUT,BSU,TUS
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Cooperation in 2004
IISAS
FEISTU
TUSPUB
WUT
TTU
TULC
TUI
Tools & Research Scenarios AGBOT
Training Actions VSTU
BSUTULKTU
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Cooperation between other WPs
Task 3.2Tools
SW/HW Environment
WP8Applets
WP9Educhip
Task 3.3. Research training scenarios
Development of the research environmentin cooperation with WP8 and WP9
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Cooperation between other WPs
WP10Conferences
MIXDESDDECSEWDTW
BEC
WP2 Smolenice
WP7Sinaia
WP3 Task 3.1. Course development
Joint tutorials:
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Task 3.2. Tool integration
VHDL/Verilog/
System C Logic synthesisSynopsys/Cadence
Gate-Level EDIF
EDIF-SSBDD
EDIF-ISCASISCASNetlist
ISCASBenchmarks
UniversitySoftware
SSBDD
VHDL-DD
DD
HierarchicalATPG
DefGen/DelayIISAS
DefectLibrary
Defect/FaultAnalysis
WUT
Turbo-TesterTTU
High-Level ATPGKTU
Cooperation: IISAS, KTU, TTU, WUT, TULC
Optimization of Scan-Based DfT
TULC
Test Set
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Tools for test generation and fault simulation
Lab Research Env. - 1 Task 3.2
Design ErrorDiagnosis
TestGeneration
BISTEmulation
Design TestSet
Levels:GateMacroRTL
FaultTable
Test SetOptimization
Methods:BILBOCSTPHybrid
FaultSimulation
FaultyArea
Circuits:CombinationalSequential
LogicSimulation
Formats:EDIFAGM
Defect Library
HazardAnalysis
Data
Specifi-cation
Algorithms:DeterministicRandomGenetic Multivalued
Simulation
Fault models:Stuck-at faultsPhysical defects
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Lab Research Env. - 2
DefSimChip
Task 3.2
Educhip based
Manual patterns
Random patterns
Deterministic SAF patterns
Deterministic defect-patterns
DefSim software (firmware, drivers)DefSim software (firmware, drivers)
DefGen, Turbo Tester, etc.DefGen, Turbo Tester, etc.
DefSim User Interface
Cooperation: IISAS, TTU, WUT
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
.
ROM. . .
SoC
Core
Co
ntro
ller
• Combining – on-line generated pseudo-
random patterns – with pre-generated and stored
test patterns
• Problems :– To find the best characteristics
for test generator (PRPG)
– To find the best level of mixing pseudo-random test and stored test as the tradeoff between memory cost and testing time
Hybrid BIST:
CORE UNDER TEST
Response Analyzer
Test Generator
Task 3.3. Scenario: Hybrid BIST
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Optimization of Hybrid BIST
Cost curves for BIST:
Total Cost
C TOTAL
C
Cost of
pseudorandom test
patterns C GEN
Number of remaining
faults after applying k
pseudorandom test
patterns r NOT (k)
Cost of stored
test C MEM
L
LOPT
k rDET(k) rNOT(k) FC(k) t(k)
1 155 839 15.6% 1042 76 763 23.2% 1043 65 698 29.8% 1004 90 608 38.8% 1015 44 564 43.3% 99
10 104 421 57.6% 9520 44 311 68.7% 8750 51 218 78.1% 74
100 16 145 85.4% 52200 18 114 88.5% 41411 31 70 93.0% 26954 18 28 97.2% 12
1560 8 16 98.4% 72153 11 5 99.5% 33449 2 3 99.7% 24519 2 1 99.9% 14520 1 0 100.0% 0
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
T 3.3. Sc: Hybrid Functional BIST
Register block
ALU
Signature analyser
Data
K
M Automatic
Test Pattern Generator
MUX
Register block
ALU
Signature analyser
Deterministictest set
K
M Automatic
Test Pattern Generator
MUXFunctional test
Deterministic test
Random resistant faults
Test patterns are stored in the memory
Publications: MIXDES’2004, ETS’2005
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
To be compared:To be compared:• genetically optimized vs. genetically optimized vs.
manually obtained LFSRmanually obtained LFSR• original vs. “BISTed” device original vs. “BISTed” device
complexitycomplexity
LFSRConfig.
BISTEmulator
Circuit Model (VHDL)
Fault Table
Circuit Model
TestSet
GeneticOptimizer
WP8: BISTApplet
DfT Structure (VHDL)
Synthesis Tools
Estimated Growth of
Complexity
Task 3.3. Scenario: BIST design
TTUIISASOther
Polynomial,Initial state
Cooperation: IISAS, TTU
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Events in 2004
No Event code Event name and organiser Type Date Place Lang. No. of part. -------------- No. of lect.
Eval.
1
TTU_JONK
System Verification and Test UJ, TTU
training course with lab works international, open,
19.01-10.03. 2004
Jonkoping, Sweden
English 24 -------- 2
N/A
2
TTU_TGFS
Test Generation and Fault Simulation in Digital Systems TTU
Course, national, open
6-8.04. 2004
Kharkov, Ukraine
English 130 -------- 1
N/A
3 TTU_DFTDDECS
Defect Oriented Test Generation IISAS, TTU
tutorial, international, open
18.04. 2004
Stara Lesna, Slovakia
English 45 --------- 4
N/A
4
TTU_HTDDECS
Additional Hardware for IC Testability Improvement IISAS, TTU
tutorial, international, open
18.04. 2004
Stara Lesna,
Slovakia
English 45 --------- 4
N/A
5
TUS_TSTSOF
Advanced methods of testing electronic systems TUS
tutorial, international, open
29.05. 2004
Sofia, Bulgaria
English 43 --------- 4
A: 37 B: 6 C: 0 D: 0 E: 0
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Events in 2004
No Event code Event name and organiser Type Date Place Lang. No. of part. -------------- No. of lect.
Eval.
6
TTU_TESTMIX
Advanced Methods of Testing Electronics Systems TTU, TUL
tutorial, international, open
25.06. 2004
Szczecin,
Poland English 8
-------- 3
N/A
7
TULC_FICT
FPGA circuits - overview, design tools and applications TULC
workshop, national, open
01.07. 2004
Prague,
Czech Rep.
Czech 16 -------- 3
N/A
8
TUS_DFTSOF
Design for Testability TUS
workshop, international, open
22-23.07. 2004
Sofia,
Bulgaria English 37
-------- N/A
A: 23 B: 8 C: 2 D: 0 E: 0
9 VSTU_TTU_TestTourVladimir
Advanced methods of digital and analog test VSTU/TTU
tutorial, international, open
03.09. 2004
Vladimir,
Russian Fed.
English 39 --------- 4
A: 21 B: 18 C: 0 D: 0 E: 0
10 VSTU_TTU_TestTourTomsk
Advanced methods of digital and analog test VSTU/TTU
tutorial, international, open
06.09. 2004
Tomsk,
Russian Fed.
English 30 --------- 7
A: 12 B: 10 C: 8 D: 0 E: 0
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Events in 2004
No Event code Event name and organiser Type Date Place Lang. No. of part. -------------- No. of lect.
Eval.
11
TULC_SIMT
Tools for IC simulation TULC
seminar, national, open
08.09. 2004
Liberec, Czech Rep.
Czech 12 --------- N/A
A: 7 B: 1 C: 0 D: 0 E: 0
12 VSTU_TTU_TestTourIrkutsk
Advanced methods of digital and analog test VSTU/TTU
tutorial, international, open
11.09. 2004
Irkutsk, Russian Fed.
English 39 --------- N/A
A: 12 B: 17 C: 10 D: 0 E: 0
13 VSTU_TTU_TestTourVladivostok
Advanced methods of digital and analog test VSTU/TTU
tutorial, international, open
13.09. 2004
Vladivostok, Russian Fed.
English 26 --------- N/A
A: 19 B: 6 C: 1 D: 0 E: 0
14 TTU_VIERHAUS
Test Technology Course TTU
course, international, open
20-21. 09. 2004
Tallinn, Estonia
English 28 --------- 1
N/A
15
TTU_BECTERM
Advanced topics of thermal testing of digital circuits TTU
tutorial, international, open
04.10. 2004
Tallinn, Estonia
English 22 --------- 2
A: 6 B: 5 C: 0 D: 0 E: 0
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Events in 2004
No Event code Event name and organiser Type Date Place Lang. No. of part. -------------- No. of lect.
Eval.
16
TTU_BECSOC
Advanced topics of SOC design and test
TTU
tutorial, international, open
05.10. 2004
Tallinn,
Estonia
English 31 --------- 2
A: 7 B: 3 C: 0 D: 0 E: 0
17
TTU_BECDAT
Advanced topics of digital and analog test TTU
tutorial, international, open
06.10. 2004
Tallinn,
Estonia
English 23 --------- 5
A: 7 B: 6 C: 0 D: 0 E: 0
18
TTU_HIER
Hierarchical test approaches for digital systems PUB, TTU
course, international, closed
09.10. 2004
Sinaia,
Romania
English 16 --------- N/A
A: 14 B: 2 C: 0 D: 0
19 TTU_DADFT04
Design for testability TTU, TUD
summer school, international, open
11.10.- 15.10. 2004
Darmstadt,
Germany
English 9 --------- 2
A: 2 B: 5 C: 2 D: 0
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Events in 2004
No Event code Event name and organiser Type Date Place Lang. No. of part. -------------- No. of lect.
Eval.
20
TUS_TDC
Testing of Digital Circuits TUS
workshop, international, open
28.10. 2004
Sofia, Bulgaria
English 21 --------- N/A
A: 12 B: 8 C: 1 D: 0
21
BSU_TUT_TDTIC
Testing and testability design of IC and systems BSU
tutorial, international, open
12.11. 2004
Minsk, Byelorussia
English 56 --------- 2
A: 35 B: 18 C: 13 D: 0 E: 0
In total: 18 international events out of 21
11 different countries
15 joint events
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Geography of Events
4
2
12
3
1
1
1
4
1
1
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Geography of Lecturers
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Participants
0
50
100
150
200
250
300
350
400
450
W P 3
New EU countries
Other CEE/NIScountriesEU-15 countries
Other countries
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Evaluation results
0
50
100
150
200
250
No. of ratings
A
B
C
D
E
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Other activities in 2004• AGBOT – Handbook of Testing (397 pages)
1. Introduction2. Defects, faults and fault models 3. Test generation techniques and algorithms 4. Design for testability5. Built-in self-test6. On-line testing7. IDDQ testing.8. Analog test and diagnostics9. Appendix 1: Tools, that can be used for practical exercises10.Appendix 2: Philosophy of Mentor test tools
The reviewing process is running and simultaneously the reviewed chapters are being formatted for printing.
3rd Annual Review MeetingSinaia, Romania, February 21-22, 2005
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Other activities in 2004• IEEE EWDTW - joint East-West event in D&T
– Bringing expert skills from West to East• Y. Zorian (USA) Virage Logic and TTTC - Embedded Test for SoC• Ch. Landrault (France) LIRMM - Memory testing• B. Magnhagen (Sweden) DixiCAD - Optical testing
– Knowledge transfer from East to West• Many experts from leading scientific centers of Russia, Ukraine,
Byelorussia shared their knowledge with conference participants
• Russian Test Tour• REASON: 7 lecturers from FEISTU, TTU, TUI, VSTU, WUT• RUSSIA: Vladimir, Tomsk, Irkutsk, Vladivostok (134 participants)
• Meetings - Lviv, Liberec, Lodz, Prague, Bratislava, Sofia
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Main achievements: Cooperation• To increase the synergy of the project, tight links created to
• WP8 (distance learning) and • WP9 (hardware based experimental research teaching)• WP10 (linking tutorials to conferences: MIXDES, BEC, DDECS, EWDTW• New links (in 2004): WP2, WP7 (joint tutorials)
• Continuous extension of the Task 3.2• 2003: from tool development to creation of research training environment • 2004: web based access to the environment
• AGBOT – a great book on testing• partners: FEISTU, IISAS, TTU, TULC, VSTU (14 authors)• a special AGBOT server set up by TULC in order to simplify collaborationNew:• broader scope, compared to existing books• tools for laboratory research • theoretical support for Educhips, new lab conception• a book for teachers• 2-3 times cheaper than IEEE/Kluwer books
• Intensive joint research - 12 joint publications (8 – 2002, 5 - 2003)
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Main achievements: Training• 21 tutorials and training actions on Digital and Analog SoC Testing were
organized in 11 countries
• 15 joint tutorials, given by the partners from FEISTU, IISAS, TTU, TULC, VSTU, and WUT
• 2 WP3 tutorials included into the TTTC TTEP database
• Expert skills from IEEE and western industry were drawn (in 3 events): – the world leaders in test Y.Zorian (USA), Ch. Landrault (France) were invited to support
REASON events at EWDTW in Ukraine– many other western VIPs outside REASON (A.Jerraya, W.Hartenstein, T.Vierhaus,
M.Renovell, B.Magnhagen, M.Glesner, H.Tenhunen, S.Kumar) consortium were invited to tutorials in Slovakia and Estonia
– a Teaching Tour to Russia was organized in Sept with more than 15 lectures in 4 events all over Russia from Vladimir to Vladivostok
• Knowledge transfer from East to West– Parts of the REASON WP3 tutorials were invited to be presented in Sweden and Germany
(summer school) – MSc and PhD students from West to East
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Responses to the 2nd review
• While the development of 14 tools has been useful to the project, the long terms use will require long-term support. The developments w.r.t. intellectual property should be safeguarded. Commercial alternatives are more suitable for long-term use
– The “home made” tools are the results of research which is ongoing, in this way the tool environment is kept alive and continuously updated
– good possibility to involve students in research and in updating and improving the tools
– because of the web based user access to tools, the support is easier– switching from “home made” to commercial can always be made if
possible
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Responses to the 2nd review
• Links and interfaces between the 14 software tools to be improved and clearly documented. Users must have a clear view of the global testing path– The interfaces between partner tools have now been created – also the interfaces and converters to commercial tools are available
(EDIF, VHDL, Verilog, System C)• Benefits for industry to be clarified and/or improved
– Competence Centre of Mission Critical Embedded Systems (ELIKO) has been created (with contracts between 7 private companies, 2 res. institutions under leadership of TTU)
– in this centre currently 2 test oriented joint projects with industry covering REASON WP3 topics are running
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
Main goals for 2005• AGBOT: Completing the Handbook on Testing
• Completing the development of research environment (incl. Educhip)– Development and update of a series of research scenarios– Special target: Hands-on lab courses for partners with partner tools– Testing the research scenarios
• A series of tutorials and courses planned: – Lecture course in Sweden, Febr-March– Tutorial at DDECS, April 18, Sopron– 2 tutorials at European Test Symposion, May 21-25, Tallinn– 1-day tutorial on VHDL, June, Liberec– Special session on Educhips at MIXDES– Other hands-on training sessions
• WP3 Workshop, May 20, Tallinn
3rd Annual Review Meeting, Sinaia, Romania, February 21-22, 2005
• Intensive cooperation has been the target, local actions were less important– Joint courses, tutorials and tool environments– Joint research scenarios– Joint work on the textbook: AGBOT– Joint research – 12 joint publications (side effect)
• Visibility of the WP3 team at the European level is increased
Conclusions