Reducing Test Application Time Through Test Data Mutation Encoding

Reducing Test Application Time Through Test Data Mutation Encoding

Reducing Test Application Time Through Test Data Mutation Encoding

Sherief Reda and Alex OrailogluSherief Reda and Alex Orailoglu

Computer Science Engineering Dept.Computer Science Engineering Dept.

University of California, San DiegoUniversity of California, San Diego

OutlineOutline

Introduction

Test Data Mutation Encoding

Time Reduction Analysis

Experimental Results

Conclusions

Motivation

Scheme overviewOverlap explorationComputational aspects

Hardware challengesDon’t care handling

IntroductionIntroduction

Advancements in VLSI device fabrication Unprecedented integration levels

Increased test application time hinders volume manufacturing in today’s demanding market.

High integration manufacturing Increased test application time

Testing multiple cores on System-on-a-Chip (SoC) Increased test application time

MotivationMotivation0

1

X

1

XX

X

X

1

1

0

X

X

1

X

1

TDI

LFSR

TDO

X

0

X

1

X0

1

X

X

0

X

X

1

X

0

X

Scan chain length

Test time increase

Flip

Flip

Mutation reduces test time by specifying only the bits to be flipped

Problem: Test responses destroy the scan cells’ content!

Test Vector I Test Vector II

Mutate

Decompose scan chain

0

X

X

1

1

X

1

1

1

X

X

X

1

0

X

X

Large test vectors are transformed into small horizontal test slices


1

X

1

XX

X

X

1

1

0

X

X

1

X

1

TDI

LFSR

TDO

0 1 1 1

X X X 0

X 1 X X

1 1 X X

Scan chain length Bits to specify inversion

Small test slice Small number of bits to specify an inversion


1

X

1

XX

X

X

1

1

0

X

X

1

X

1

TDI

LFSR

TDO

Decompose scan chain

0

0

0

1

1

1

1

1

1

1

1

1

1

0

0

0

Large test vectors are transformed into small horizontal test slicesScan chain length Bits to specify inversion

Small test slice Small number of bits to specify an inversion

Test Data Mutation EncodingTest Data Mutation Encoding

TDO

2x4 Decoder

TDIDSR

Flip

DORENABLE

MISR

CLK0 0 0 0

0 00

1

0

1

00

1

1

1

1

0

1

1

1

0

1

TDI: Test Data Input

DSR: Decoder Shift Register

DOR: Decoder Output Register

TDO: Test Data Output

0(00)1(01)2(10)3(11)

1 1 0 0Mutated

Test Slice

Bits 2 & 3 need to be flipped

10, 11 to be injected = 4 bits

Overlap can reduce this to just 11 = 2 bits

0011011


2x4 Decoder

TDIDSR

Flip

DORENABLE

MISR TDO

CLK0 1 0 0

1 00

1

0

1

00

1

1

1

1

0

1

1

1

0

1

1 1 0 0Mutated

Test Slice








0(00)1(01)2(10)3(11)

001101


TDO

2x4 Decoder

TDIDSR

Flip

DORENABLE

MISR

CLK1 1

0

0

1 1

1 1 0

0

0

1

0

1

00

1

1

1

1

0

1

1

1

0

1

1 1 0 0Mutated

Test Slice








0(00)1(01)2(10)3(11)

00110


2x4 Decoder

TDIDSR

Flip

DORENABLE

MISR TDO

CLK1 1

1

0

0 1

1 1 0

1

1 1 0 0

0

1

0

1

00

1

1

1

1

0

1

1

1

0

1

1 1 1 0Mutated

Test Slice





0(00)1(01)2(10)3(11)

0011


2x4 Decoder

TDIDSR

Flip

DORENABLE

MISR TDO

CLK1 1

1

0

1 0

1 1 0

1

1 1 0 0

0

1

0

1

00

1

1

1

1

0

1

1

1

0

1

0 1 1 0Mutated

Test Slice





0(00)1(01)2(10)3(11)

001


2x4 Decoder

TDIDSR

Flip

DORENABLE

MISR TDO

CLK0 1

1

0

1 1

1 1 0

1

1 1 0 0

00 11

0

1

0

1

00

1

1

1

1

0

1

1

1

0

1

0 1 1 0Mutated

Test Slice





0(00)1(01)2(10)3(11)

00


2x4 Decoder

TDIDSR

Flip

DORENABLE

MISR TDO

CLK0 1

1

0

0 1

1 1 0

1

1 1 0 0

00 11

0

1

0

1

00

1

1

1

1

0

1

1

1

0

1

0 1 1 1Mutated

Test Slice





0(00)1(01)2(10)3(11)

0


2x4 Decoder

TDIDSR

Flip

DORENABLE

MISR TDO

CLK0 1

1

1

0 0

1 1 0

1

1 1 0 0

00

111 11

0

0

1

0

1

00

1

1

1

1

0

1

1

1

0

1

0 1 1 1Mutated

Test Slice

7 clock cycles are needed to inject 21 bits through 3 parallel streams to mutate the test vector.

57% reduction in test application time





0(00)1(01)2(10)3(11)

Fundamental ChallengesFundamental Challenges

Input test data indicates flips needed to mutate test slices.

Optimal ordering of the indices maximal overlap minimal test application time.

Problem: What is the flipping order that attains the minimal number of clock cycles?

Input test data encodes the indices of flip locations.

Overlap ExplorationOverlap Exploration

000

100

1

0

0 0 0

3x8 Decoder

MISR TDO

TDI

000

100

110

0100

1

0

1

1 0 0

3x8 Decoder

MISR TDO

TDI


000

100

110

111

011

101

010

001

State Transition Diagram of DSR (DeBruijn Diagram)

0

0

0 0

0

0

1

0

1 1

1 1

1

1

1

0

0 1 1

3x8 Decoder

MISR TDO

TDI

4 1

2

5

6

7

3

0


000

100

110

111

011

101

010

001


0

0

0 0

0

0

1

0

1 1

1 1

1

1

1

0

0 1 2 3 4 5 6 7

0

1

2

3

4

5

6

7

Distance Matrix

0 3 2 3 1 3 2 3

1 0 2 3 1 3 2 3

2 1 0 3 2 1 2 3

2 1 2 0 2 1 2 3

3 2 1 2 0 2 1 2

3 2 3 2 3 0 1 2

3 2 3 1 3 2 0 1

3 2 3 1 3 2 3 0

Objective: Mutating an 8 bit test slice through flipping bits 2 & 6

4 1

2

5

6

7

3

0


000

100

110

111

011

101

010

001


0

0

0 0

0

0

1

0

1 1

1 1

1

1

1

0


0 1 2 3 4 5 6 7

0

1

2

3

4

5

6

7

Distance Matrix

0 3 2 3 1 3 2 3

1 0 2 3 1 3 2 3

2 1 0 3 2 1 2 3

2 1 2 0 2 1 2 3

3 2 1 2 0 2 1 2

3 2 3 2 3 0 1 2

3 2 3 1 3 2 0 1

3 2 3 1 3 2 3 0

First option: 4-2-6 yields 3 clock cycles

4 1

2

5

6

7

3

0


000

100

110

111

011

101

010

001


0

0

0 0

0

0

1

0

1 1

1 1

1

1

1

0


0 1 2 3 4 5 6 7

0

1

2

3

4

5

6

7

Distance Matrix

0 3 2 3 1 3 2 3

1 0 2 3 1 3 2 3

2 1 0 3 2 1 2 3

2 1 2 0 2 1 2 3

3 2 1 2 0 2 1 2

3 2 3 2 3 0 1 2

3 2 3 1 3 2 0 1

3 2 3 1 3 2 3 0

Second option: 4-6-2 yields 4 clock cycles

4 1

2

5

6

7

3

0


Computational AspectsComputational Aspects

Optimal number of test bits Enumerating all the possible trips to pick the one that achieves the minimal total distance

If there are n bits to flip, then there are n! trips to consider in order to calculate the optimal trip

Large number of flips Enumeration of all trips is computationally infeasible A greedy strategy is utilized

000

100

110

111

011

101

010

001

Greedy strategy is applied to visit the three states

0

0

0 0

0

0

1

0

1 1

1 1

1

1

1

0

Greedy strategy

- Repeat until the test slice is mutated:

Move from the current state to the closest next state corresponding to the bit index to be flipped

- Move from the initial state to the closest state.

Objective: Mutating an 8 bit test slice through flipping bits 5, 6 & 7

4 1

2

5

6

7

3

0


000

100

110

111

011

101

010

001


0

0

0 0

0

0

1

0

1 1

1 1

1

1

1

0

Greedy strategy





4 1

2

5

6

7

3

0


000

100

110

111

011

101

010

001


0

0

0 0

0

0

1

0

1 1

1 1

1

1

1

0

Greedy strategy





4 1

2

5

6

7

3

0


000

100

110

111

011

101

010

001


0

0

0 0

0

0

1

0

1 1

1 1

1

1

1

0

Greedy strategy





4 1

2

5

6

7

3

0


Don’t Care HandlingDon’t Care Handling

Test Slice A

Test Slice B

Test Slice C

Test Slice D

11100110x0xxx0xxxxxxxxxx

76543210

xxxxxxxx1x0xx0xxTest Slice E


Test Slice A

Test Slice B

Test Slice C

Test Slice D

Test Slice E

11100110x0xxx0xxxxxxxxxx

76543210

xxxxxxxx1x0xx0xx

There are 2 cases: A run of don’t cares in between two identical specified bits

A run of don’t cares in between two distinctly specified bits


Test Slice A

Test Slice B

Test Slice C

Test Slice D

Test Slice E

1110011010xxx0xx1xxxxxxx

76543210

1xxxxxxx1x0xx0xx

There are 2 cases: A run of don’t cares in between two identical specified bits

A run of don’t cares in between two distinctly specified bits


Assume we have the 3 test slices.

11100110x0xxx0xx0x0xxxxx

11100110Test Slice A

Test Slice B

Test Slice C

7654321076543210

x0xxx0xx0x0xxxxx

6 clock cycle

1010001000000010

000

100

110

111

011

101

010

001

0

0

0 0

0

0

1

0

1 1

1 1

1

1

0

A B3 Clock Cycles

4 1

2

5

6

7

3

0


Assume we have the 3 test slices.

1110011076543210

6 clock cycle

1010001000000010

000

100

110

111

011

101

010

001

0

0

0 0

0

0

1

0

1 1

1 1

1

1

0

B C3 Clock Cycles


Test Slice A

Test Slice B

Test Slice C

765432104 1

2

5

6

7

3

0

1110011010000010000000104 clock cycles

76543210

While mutating test slice A to test slice B we can flip bit 5 in anticipation for test slice C. This saves 2 bits in mutating test slice B to C.


000

100

110

111

011

101

010

001

0

0

0 0

0

0

1

0

1 1

1 1

1

1

1

0

4 1

2

5

6

7

3

0 Assume we have the 3 test slices.


Test Slice A

Test Slice B

Test Slice C

76543210

A B3 Clock Cycles

1110011010000010000000104 clock cycles

76543210

While mutating test slice A to test slice B we can flip bit 5 in anticipation for test slice C. This saves 2 bits in mutating test slice B to C.


000

100

110

111

011

101

010

001

0

0

0 0

0

0

1

0

1 1

1 1

1

1

1

0

4 1

2

5

6

7

3

0 Assume we have the 3 test slices.


Test Slice A

Test Slice B

Test Slice C

76543210

B C1 Clock Cycle

Reducing I/O Pin RequirementsReducing I/O Pin Requirements

TD

O/E

nabl

e

To alleviate the requirement of adding an extra ENABLE pin, one of the I/O pins can be multiplexed or the TDO can be multiplexed.

TDI

MIS

R

v

Control v

Enable

TDO

CLK

2x4 decoder

How many scan chains should the original scan chain be decomposed into? What is the decoder size to be used?

What is the attainable time reduction for various scan chain configurations?

What is the relation between the number of flips to be performed in mutating test slices and the achievable time reduction?

Fundamental IssuesFundamental Issues

OutlineOutline

Introduction

Test Data Mutation Encoding

Time Reduction Analysis

Experimental Results

Conclusions

Motivation

Scheme overviewOverlap explorationComputational aspects

Hardware requirementsDon’t care handling

Time Reduction AnalysisTime Reduction Analysis

000

100

110

111

011

101

010

001

0

0

0 0

0

0

1

0

11

1 1

1

1

1

0

Initial State

0 0 0

ShiftsNew Reachable

StatesNext State

0 10 0 0

1 X 0 0 1

2 X X 0 2

3 X X X 4

If we only need to flip one bit to mutate the current test slice to the next test slice, how many shift clock cycles are needed?

0 0 0

3x8 Decoder

MISR TDO

TDI

Hardware Organization State transition diagram of the decoder shift

register

0 0 1 0 0 10 1

X 0 01 2

X X 02 2

X X X3 3

Weighted average shifts for state 000: 2.125 cyclesWeighted average shifts for state 001: 1.875 cycles

The average number of clock cycles needed to reach a combination of states is not only function of the initial state but also of the particular combination of states to be visited.


0

0.5

1

1.5

2

2.5

0 1 2 3 4 5 6 7

Initial State

Average ClockCycles

Given an initial state, what is the average number of clock cycles needed to reach a different state? 1.84 clock cycles.

0246810121416

0 1 2 3 4 5 6 7 8

Bits to flip

Average number of clock cycles

4

8

16

32

Test Slice Size


In general, what is the average number of clock cycles needed to mutate the test slices of various sizes?

05101520253035

0 1 2 3

Bits to Flip

Time Reduction Ratio

4

8

16

32

Test Slice Size

0246810121416

0 1 2 3 4 5 6 7 8

Bits to flip

Average number of shift clock cycles

4

8

16

32


Test Slice Size

Time Reduction Ratio =Test Slice Size

Average number of shift clock cycles

0

0.5

1

1.5

2

2.5

3

3.5

4

1 2

Normalized Time Reduction Ratio

4

8

16

32

Test Slice Size

In this experiment, we assume that the number of bits to be flipped to mutate a 32 bit test slice is 8 times the number of bits to be flipped to mutate a 4 bit slice.


Bits to Flip x Test slice size/4

Experimental ResultsExperimental Results

0

50000

100000

150000

200000

s38584 s38417 s35932 s15850 s13207

ISCAS'89 Circuits

Clock Cycles

Compressing MinTest vectors results in an average time reduction ratio of 2.4 for the 5 benchmark circuits

MinTest: Hamzaoglu & Patel, ITC, 1998

Virtual Scan Chains: Jas & Touba, VTS, 2000

Golomb Coding: Chandra & Chakrabarty, VTS, 2000

Test Data Mutation using MinTest fully specified vectors

MinTest fully specified vectors are compressed using test data mutation


020000

400006000080000100000

120000140000160000

180000

s38584 s38417 s35932 s15850 s13207

ISCAS'89 Circuits

Clock Cycles

Compressing the incompletely specified test vectors, using last flip heuristic, results in an average time reduction ratio of 6.7 in comparison with MinTest for the 5 benchmark circuits

MinTest: Hamzaoglu & Patel, ITC, 1998MinTest: Hamzaoglu & Patel, ITC, 1998

Test Data Mutation using MinTest fully specified vectors

Test Data Mutation using incompletely specified vectors

Test Data Mutation is applied to incompletely specified test vectors obtained from Atalanta


0

1000020000

3000040000

5000060000

7000080000

90000

s38584 s38417 s35932 s15850 s13207

ISCAS'89 Circuits

Clock Cycles

Augmenting Scan Chain Concealment results in an increased test time reduction by a factor of 1.8

Scan Chain Concealment: Bayraktaroglu, Orailoglu, DAC, 2001

Test Data Mutation using scan chain concealment fully specified vectors

ConclusionsConclusions

A new methodology to reduce test application time through test data mutation is presented

Thorough analysis of the proposed method identifies configurations and conditions for optimal test time reduction

Reduced hardware overhead

Experimental results on ISCAS’89 benchmarks confirm drastic test time application reductions

Effective overlapping of test data yields huge reductions in test application time

Documents

Reducing Test Application Time Through Test Data Mutation Encoding