Registers and Counters Sequential Circuits · PDF file · 2007-01-15state counter • Ripple Counter ... T and JK FFs for Counting • 1. Use a circuit of T-type flip-flop ... 59:51

Chapter 8

Sequential Circuits for Registers and Counters

Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2

Lesson 3

COUNTERS COUNTERS


•• CountersCounters•• TT--FF FF ——Basic Counting element Basic Counting element •• State Diagram of State Diagram of --ve Pulse ve Pulse

triggered 16triggered 16--state counterstate counter•• Ripple CounterRipple Counter

Outline


Counting

• Often there is a need to count the number of pulses or triggering at an input.

• Counting is an essential circuit in computers.


Various Features in counters

• Delays at FFs — Synchronous and Ripple • Output bits at FFs — 4, 8 or 16 bit• FFs used — D-FF, JK, RS• Family — TTL, LSTTL, CMOS, HCMOS • Outputs — Synchronous, Asynchronous


Modulo-6 Counter

• If a counter returns to original state after QB= ‘1’, QC = ‘0’ and QD = ‘1’, and QA is always = ‘0’we say it is modulo-6 counter

• Counter returns to original state of Qs after 6 counts


State Diagram of Modulo 7S01

S11

S31

S51

S41


Modulo-7 Counter

• If a counter returns to original state after QB= ‘1’, QC = ‘1’ and QD = ‘0’, and QA is always = ‘0’, we say it is modulo-7 counter




S11

S31

S61


Modulo-10 Counter

• If a counter returns to original state after QA= ‘1’, QB = ‘0’ QC = ‘0’ and QD = ‘1’, we say it is modulo-10 counter




S11

S31

S71

S91


Various types of counters

• Ripple Counter— 4, 8 or 16 bit• Binary Counter — 4, 8 or 16 bit• Ring Counter — 4, 8 or 16 bit• Decade Counter - Modulo 10 • Modulo n counter — 5, 10 or 6 bit


•• CountersCounters•• TT--FF FF ——Basic Counting elementBasic Counting element•• State Diagram of State Diagram of --ve Pulse ve Pulse

triggered 16triggered 16--state counterstate counter•• Ripple CounterRipple Counter

Outline


Divide by 2 as Counting Element

• A divide-by-2 circuit produces one output pulse for every two pulses applied to its input.

• A divide-by-two circuit is made from a T-FF


T and JK FFs for Counting

• 1. Use a circuit of T-type flip-flop• 2. Use a single JK flip-flop with its J and K

inputs made ‘1’. The T-flip-flop (FF) is designed from JK or any other method to act as a divide-by-two circuit and JK input is now the T-input.


TD and SR FFs for Counting

• 3.Use a D flip-flop (not D-latch) with its Q output feedback to the D input

• 4. Alternatively Use a S-R flip-flop with a NOT in-between S and R to get a D-FF and then convert a D-FF into T


T-FF

• D input = T XOR Q n and Q n+1 = Q n

• JK FF functions as T-FF if J = 1 and K =1


T- from D- Flip-Flop + ve edge triggered

• Output Q and Q

Q

QD

Q

QD Divide by 2FF

T

T

+ve Edge triggered circuit

↑


T from JK Flip-Flop – ve edge triggered

• Output Q and Q

Q

Q

K=1

J = 1

Q

Q1

1

Divideby 2FFClock

T

-ve Edge triggered circuit

↓

R

SPreset

clear

PR CLR


• Counters• T-FF — Basic Counting element •• State Diagram of State Diagram of --ve Pulse ve Pulse

triggered 16triggered 16--state counterstate counter• Ripple Counter

Outline


State DiagramS151

S01

S31

S71

S111


• Counters• T-FF Basic Counting element • State Diagram of -ve Pulse

triggered 16-state counter•• Ripple CounterRipple Counter

Outline


Cascading T-FFs

• T FF acts as a divide-by-2 circuit, if Q output of the FF connects to the T input of the second FF, and the Q output from the second FF connects to T-input of the third flip-flop and so on, the FFs are said to be in a cascade


4-bit Ripple Counter (Binary Asynchronous Counter)

Divideby 2FF

QDivideby 2FFQ

Q

Divideby 2FF

Divideby 2FF

Asynchronous Counter as each flip flop has output delay tp of s and final output delays by

4 times the tp of one FF

Q Q Q

CLR

Count input A After tp

After 4×tp

input B


Additional feature in ripple counter in IC 7493 to enable its conversion to modulo-6

counterR (1)

R(2) To CLR


-ve edge triggered T- FFCLR = 1, J = K = 1

Inputs CLR = 1, J = K = 1 Outputs

CLK Count= Qn+1(A) Qn+1(B) Qn+1(C) Qn+1(D)

Qn+1 means next state after nth clock input and after a delay of tp at successive FFs. At each transition, Delay = 4×tp at Qn+1(D)

↓ 1 0 0 0 1

↓ 2 0 0 1 0↓ 3 0 0 1 1


-ve edge triggered T- FFCLR = 1, J = K = 1

Inputs CLR = 1, J = K = 1 Outputs

CLK Count = Qn+1(A) Qn+1(B) Qn+1(C) Qn+1(D)

Qn+1 means next state after nth clock input and after a delay of tp at successive FFs. Delay = 4×tp at Qn+1(D) on each transition

↓ 4 0 1 0 0

↓ 5 0 1 0 1↓ 6 0 1 1 0↓ 7 0 1 1 1


Timing Diagram when -ve edge asynchronous counter QD delays transition by 4 tp from clock edge

CLK(shift)

QA

QB

t

QC

QD


Summary


Counters• T-FF functions as counter, because it

toggles at every negative edge• T-FF is made from J-K, D-FF when D

= Q and from RS-FF, when S = R and S connects Q

• Ripple counter has cascaded T-FFs, the output of each FF connects to T-input of the next


Counters

• Counting delay = n times tp for a n-bit ripple counter

• 16-bit can be converted to modulo-6, 7 and 10 counters by resetting the counter at next transition when Qs show count = 5, 6 and 9


End of Lesson 3

COUNTERSCOUNTERS


THANK YOUTHANK YOU

Documents

Registers and Counters Sequential Circuits · PDF file · 2007-01-15state counter • Ripple Counter ... T and JK FFs for Counting • 1. Use a circuit of T-type flip-flop ... 59:51