Universidade de CoimbraFaculdade de Ciências e Tecnologia

Departamento de Engenharia Electrotécnica e de Computadores

Projeto de Sistemas Digitais – 2014/2015

ReportProject: SD Card Interfacing (w/ Qsys)

Pedro Miguel Oliveira Girão2011168175

Pedro Miguel Parola Duarte2011154219

July 13, 2015

Index1 Introduction 1

1.1 Video Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 List of Abbreviations 1

3 Previous Work 2

4 Qsys 24.1 Qsys Core Functionalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2 Architecture and Design of Qsys . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34.3 Qsys Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34.4 Qsys Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34.5 Avalon Switch Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.6 Automated System Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 Nios II System 5

6 Qsys IP Cores 66.1 Instantiating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7 Project Implementation 67.1 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77.2 SD Card Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77.3 Qsys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77.4 Eclipse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

8 Results and Discussion 10

9 Future Work 12

10 References 13

List of Figures1 SD Card Avalon Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Qsys Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Nios II System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Project Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Qsys System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Digital Frame Software - Sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Eclipse Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Bitmap Image Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 DE2 FPGA board used for the project . . . . . . . . . . . . . . . . . . . . . . . . . 1010 Empty RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011 Empty SD card notice on the Nios II console . . . . . . . . . . . . . . . . . . . . . 1112 Connected SD card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113 Image being displayed on the VGA screen . . . . . . . . . . . . . . . . . . . . . . . 1114 Writing the file name on the VGA screen . . . . . . . . . . . . . . . . . . . . . . . 1215 Seventh picture (in binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

16 Displaying the seventh image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Projeto de Sistemas Digitais 2014/15 SD Card Interfacing

AbstractThis project mostly deals with the Nios II system, which we used to be able to interact with a

SD card. The Altera DE2 Board (FPGA technology) supports communication with the SD card viathe SD card controller present on the board. The implemented features were made possible by usingAltera’s System integration Tool (Qsys), in the Altera Quartus 13.0sp1 environment. Therefore, thegoal of this project is to explore some of the SD card communication applications with the AlteraDE2 Board.

Key-words: FPGA, SD, Nios, embedded processor, communication.

1. IntroductionAlthough we keep hearing about the advantages and breakthroughs of cloud-based computing

and storage, physical memory still plays a major part in today’s world; in fact, “the global marketfor Secure Digital (SD) Memory Cards is forecast to reach $21.3 billion by the year 2018, driven byurgent requirement for scalabilty, higher speed and storage capacity, portability and ease-of-use.” [1].The portability of data is of high interest, used in projects ranging from low to very high complexity.

Our project consists on the creation of a digital photo frame. In order to do so, it is requiredthat we detect an SD card on the SD card port and, with the help of the Nios II processor, accessthe correct information (specifically, images only) sequentially, writing these images onto memoryon the board. The information present on the memory will then be sent on through to the VGAscreen, effectively displaying the original image.

Also, and taking into the account that none of the project developers had previously workedwith or had any experience with using the Nios II processor (or the Qsys tool, for that matter),this project was one that had many obstacles during it’s development. Albeit this was true, it wasboth a challenging and rewarding experience to keep going forth and finish this project.

Our main objective with this project is to leave a complete Qsys system that has out-of-the-boxcapability of interaction with the SD card, sparing following designers hours of work, by establishinga platform on which they can build upon; this will make designers avoid the same problems we’vefaced, even at a level of learning how to overcome basic SD card interaction issues, and let themconcentrate on simply developing their application on top of this previously built and reviewedplatform.

Our example of an electronic/digital frame is one of many that can be built in the designedhardware system. Future works on this topic should come easy should anyone want to try.

1.1 Video Link

A video with the project demonstration can be found at https://www.youtube.com/watch?v=VN04H7oGTp0.

2. List of Abbreviations· BCD - Binary Coded Decimal · IRQ - Interruption Request· FAT - File Allocation Table · LED - Light-Emitting Diode· FPGA - Field Programmable Gate Array · PLL - Phase Lock(ed) Loop· FSM - Finite State Machine · SD - Secure Digital· HAL - Hardware Abstraction Layer · USB - Universal Serial Bus· HDL - Hardware Descriptive Language · VGA - Video Graphics Array· IP - Intellectual Property

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3. Previous WorkBefore going with the hands-on approach, we’ve passed many hours going through online

research trying to find the best materials and papers which applied to our situation. As such, withthis same research we were able to find some interesting tutorials, in which we based most of ourwork. Whereas most the the information contained in these documents were of high importance,most of these documents act merely as tutorials on how to successfully build a basic Nios II system,with low complexity, such as Introduction to the Altera Qsys System Integration Tool [7]. Thisdocument made us understand how we could create a basic Nios II system, explaining most of the“under the hood” behaviour. In this example, we designed a system which, when integrated intoa Quartus II project and implemented and ran on a DE2 board, creates a direct control over thegreen LEDs (LEDG7-0 ) with the rightmost slider switches (SW7-0 ). The control is done by havingthe Nios II processor execute a program stored in the on-chip memory (continuous operation wasrequired so that as the switches were toggled the lights changed accordingly).

We must also mention that we took use of the fact that HAL was already implemented. NiosII HAL is a well defined software layer that forms a clear distinction between application anddevice-level software; it also provides services such as file descriptors, I/O control and bufferingwhich are required by the ANSI C library functions (which we used in our project) so that ourHAL driver doesn’t have to provide these same functions.

Analysing other documents such as Video IP Cores for Altera DE-Series Boards [17], we under-stood how to make use of the Character Buffer for VGA display, which renders ASCII characterinto actual graphical representation for display. We used this information to print the displayedimage file name in white (as it is not possible to change the color).

In addition, with the help of other documents, such as Greedy Snake Video Game Based On NiosII System [15], we studied the behaviour of the VGA itself, to ensure we understood the differencesbetween the X-Y and Consecutive modes and how to correctly install it in a Qsys system.

4. QsysQsys is a system integration tool present in the Quartus II software, which captures system-level

hardware designs at a high level of abstraction, automating the task of defining and integratingcustom HDL design blocks (from here on out called components or IP cores). Qsys is implementedfor the purpose of generating a complete system-on-a-programmable-chip consuming less time thanother integration methods more commonly used.

Altera has the Qsys (or, in previous software editions, SOPC Builder) functionality alreadyavailable in Quartus II. This allows us to directly connect the soft and hardware components inorder to build a complete system which can be re-programmed or run in any of the FPGA boardsof the same family. One of the main advantages of using this tool is that it already includes a biglibrary, which has built-in components such as the Nios II processor, some memories, in/outputaddressing, among others. We can combine these components on a single chip in order to tackle aspecific problem.

To create the system with Qsys, a user can access and interconnect the components in aGUI-based (Graphical User Interface) approach.

4.1 Qsys Core Functionalities• Describes the hardware of the system;• Performs the system generation;• Performs memory mapping for initiating the software development;• Produces test benches to simulate the design.

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4.2 Architecture and Design of Qsys

Created designs develop a top level HDL file via connection of the various modules, which areconsidered the building blocks for the Qsys system. To connect multiple components in the system,the modules use Avalon interfaces like memory-mapping, streaming and IRQs.

4.3 Qsys Components

The aforementioned components are referred as hardware blocks of the system. In thesecomponents, HDL descriptions of the components used to create the system are available, alsoindicating the parameters (if any) that determine the operating mode of the components.

These Qsys components are connected to the system interconnect fabric using the AvalonMemory-Mapped1 or streaming interface.

Altera_UP_SD_Card_Avalon_Interfacei_avalon_chip_select

i_avalon_address[7..0]

i_avalon_writedata[31..0]

o_avalon_readdata[31..0]

i_avalon_read

i_avalon_write

i_avalon_byteenable[3..0]

o_avalon_waitrequest

i_clock

i_reset

i_reset_n

AvalonInterface

FSM

SDCard

Interface

b_SD_cmd

b_SD_dat

b_SD_dat3

o_SD_clock

Figure 1: SD Card Avalon Interface

4.4 Qsys Design Flow

The Qsys design flow, i.e., the order of instructions which one must follow in order to createthe system is the following:

• Add a component to the system via the Component Library;

• Add/edit necessary memory addresses and IRQs;

• Connect added components with other system components and clock sinks;

• Start the system generation (and, if desired, system level simulation).

• After this is done, we must integrate the created system in Quartus II in the main blockdiagram file, making a connection with other Quartus-level components or connecting allneeded in/outputs to their pin assignments;

• Download .sof file onto the DE2 Board (or, more generally, an Altera FPGA);

• Perform system testing.1Avalon Memory-Mapped (or Avalon-MM) is an address-based read/write interface typical of master-slave con-

nections.

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Figure 2: Qsys Design Flow

4.5 Avalon Switch Interconnect

The Avalon switch interconnect fabric is a sort of combination of interconnect and logic resources.It is used for stocking the Avalon Memory-Mapped master and slaves on the components, and isreferred to as a component that has information about all of the connections made between themaster and slaves in the whole system, by also assuring that these connections are routed precisely.In it’s turn, the interconnect fabric allows that a virtual infinite number of master-slave componentconnections is possible. Hence, the system interconnect fabric is mainly used to be a bedrock,i.e., supporting interfaces for on-chip components and off-chip devices of the system. The systemimplementation fabric acts as a partial crossbar interconnects structure (a matrix with multiplein/outputs) which arranges simultaneous paths between the master and the slave components.

4.6 Automated System Generation

The Qsys tool will automatically go through configuring the processor to be used in the QuartusII project. Therefore, and after generating the system in Qsys, one can integrate the created systemblock file in the main Quartus project, and as aforementioned download the project onto the boardvia the Programmer tool.

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5. Nios II SystemThe Nios II processor (and other components) is used as a part of the entire system we developed,

which can be integrated into an Altera DE2 board, as follows:

Figure 3: Nios II System

The communication between the computer and the board is ensured by the use of the JTAG-UART interface, since it provides a USB link between the board and the host computer connectedto the board. This link is commonly named USB-Blaster.

Figure 4: Project Design Overview

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6. Qsys IP CoresDE2 boards offer an SD card port, to which we can connect an SD card, allowing access to

larger amounts of data. The SD Card IP Core is an actual hardware circuit on the DE2 boardthat facilitates the use of an SD card; when included in a design and connected to the SD cardport, it detects an SD card when a card is plugged into the port. The circuit can afterwards accessany data stored onto the card in an easy and efficient way. This core acts therefore as an interfaceconnecting the system and the SD card. The Avalon interconnect receives both read and writerequests from the Avalon Interface FSM and interprets them as commands or data requests. Theraw data stored on the SD card is accessed therefore by these data requests: when a request isissued, the SD card interface module is activated, which communicates with the SD card to processthe request, and the result is returned by the Avalon Interface FSM through its interconnect.

6.1 Instantiating the Core

To be able to add the SD Card IP Core in a Qsys design, we must have previously installedthe University Program IP Cores. After doing so, we create an instance (a copy) of the core in thedesign, connecting the card’s ports to the correct pins on the FPGA through the Pin Assigner:

Table 1: Pin Assignments for SD Card Port

Pin Name DE2b_SD_cmd PIN_Y21b_SD_dat PIN_AD24b_SD_dat3 PIN_AC23b_SD_clock PIN_AD25

In addition, the clock input is set to 50 MHz by default. If desired, it can be connect to anexternal clock source.

7. Project ImplementationFor our project, and as an extra to the required functionalities, we use certain elements like

LEDs and switches to create a hardware project built ready to be utilized with the possibilityof obtaining some form of feedback from the system (like LEDs) or performing input operations(through the switches). An example of application of these features would be to keep one an LEDon as long as there was data being accessed on the card (having different LEDs turn on for reador write operations, possibly different colours). We also proceeded to implement JTAG-UARTcomponents on the system so that we could use C-language functions such as printf(), to makedebugging easier through the application console, or even to write the image name on the screen.

This project deals with a Nios II system that reads *.bmp image files from the SD card (inreal time) and presents it in a VGA screen connected to the board. Some user interaction is madepossible through the inclusion of the switches in the project, where one can select the image2 tobe displayed next. For simplicity the images use a name template of the form bmpi.bmp where i isthe image number.

2The switches are read as a BCD (binary coded decimal) and indicate the image’s index.

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7.1 Requirements

To be able to make this project, it is fully necessary to have:

• Altera DE2 Cyclone II FPGA board;

• Quartus II Web Edition v13.0sp1 (includes Nios II EDS);

• Cyclone II device support;

• Quartus II Programmer and SignalTap II ;

• SD card with less than 2GB formatted as FAT16 (or FAT under Windows 7);

• USB-Blaster Driver correctly installed;

• VGA screen connected to the board;

7.2 SD Card Controller

Altera’s DE2 boards come with one SD card port, where the SD card is plugged. It is absolutelynecessary for the SD card to be formatted in FAT 16 (or, as appears on Windows 7, simply FAT)format. Data is stored in several clusters inside the card, that are identified by an ID that rangesfrom 2 through to 65520. If files are saved in FAT16 format they occupy several clusters dependingon the size of the actual file. The SD Card IP Core we used in our project works only with FAT16,and as such the SD card must have no more than 2GB of capacity. This system partitions thewhole memory into blocks of data, having each block occupy 512 bytes with the smallest possibledata information be 16 bit long.

To successfully format an SD card, the write protection lock on the side of the card must be inthe “unlock” position. The unlock position is shown in the below image.

7.3 Qsys

All of the used components in the project where instantiated and connected using the Qsystool. A sample view of the system can be observed in Figure 5; a more detailed view is present inthe detailed tutorial that we produced and should accompany this report. The detailed tutorialalso offers an exhaustive listing of all the components used, their connections, memory addresses,among others, as well as some advices and/or instructions in order to create a fully working systemand correct possible errors if need be.

Looking at Figure 5 we can easily identify most of the components. First we have the Nios IIprocessor, followed by the clock and a PLL (up_clocks_0 ); then we have the video components thatallow us to work with the VGA (these components have names of the form video_component_name)and the memories (both SRAM, which we use as a pixel buffer, and SDRAM which we’ll use tostore the program’s instructions in). A few PIO (Parallel In/Outputs) are also available and areused to access the boards’ LEDs and switches. Most importantly we have the SD Card interface(which was the central point of this project).

This system features all the necessary components to easily work with the SD Card and theVGA. Color data read from the SD Card can be placed for each pixel in a 16bit-RGB format inthe SRAM since this component is used as a pixel buffer and will then be displayed on the screen.

Having created this system one must only generate the Quartus II files in order to compile theproject and program the FPGA board.

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Figure 5: Qsys System

7.4 Eclipse

After the FPGA hardware programming we turn to software in order to develop the digitalframe project. Figure 6 shows a sample of the code developed3.

Figure 6: Digital Frame Software - Sample3The full code is attached to this report as ’source.c’ and is also present in the detailed tutorial.

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The simplified software flowchart is as follows:

Figure 7: Eclipse Design Flow

After initial variable (for instance pointers for the LED and switches memory space) anddevice (for instance the character buffer and the SD Card) initialization the software checks forthe presence and validity of the SD Card and enters a loop until the SD Card is removed.

For each iteration of the loop the value from the switches is read and compared against zero.A value of zero means that the software should be in automatic mode (going sequentially throughthe images and returning to the first after the last one). A value different from zero chooses theimage file as explained above.

Knowing the image name the SD Card access is pretty straight forward, one must call thealt_up_sd_card_fopen() function to open the file and then sequentially read the file byte by byte.

A few concerns when writing the code were to be aware of the BMP file format as shownin Figure 8. For instance in 24-bit depth images (as the ones we’re using) the header is always54bytes and a conversion must be made in order to draw the image on the screen using 16bit-RGBcolor format as we set in the hardware system. Furthermore one should be careful with the pixelmapping as the first pixel data in a BMP file corresponds to the lower left pixel and the last pixelcorresponds to the top right pixel.

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Figure 8: Bitmap Image Structure

8. Results and DiscussionThis project correctly reads images from an SD card and displays it on a VGA while providing

user interaction in the form of specific image selection. The SD card is primarily used as the sourceof the image files in this project, acting as external memory. The reading speeds from the SD cardare somewhat slow, which is why the display rate is inevitably slow as well.

In the next figure, we can see the FPGA used to develop the project:

Figure 9: DE2 FPGA board used for the project

After the board is programmed, but before the program is ran, the information present in theVGA is only noise (there is no actual information stored in the RAM memory):

Figure 10: Empty RAM

Also, if the program runs with an empty SD card, it will clear the screen in a white color, and

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the system will notify the user that it is trying to open the files (with the specified name template)but is unable to do so, since the card has no information.

Figure 11: Empty SD card notice on the Nios II console

We can then pass some *.bmp image files from a computer or other device onto the SD card,and afterwards connect this card to the board.

Figure 12: Connected SD card

After re-running the program, or resetting the board with the rightmost push button, the screenwill display the images present on the card cyclically, beginning with the Altera image, with awhite background, and continuing with the following images.

Figure 13: Image being displayed on the VGA screen

We also display the currently displayed image name as it is on the SD card (again, obeying thename template specified for this project). The name must mandatorily be written in white color,since the function that writes characters to the VGA screen is only able to write them in white. Assuch, on pictures with white backgrounds such as the first image, the name is not visible, althoughit is being written.

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Figure 14: Writing the file name on the VGA screen

As we have mentioned before, we also allow the user to manually select (with the switches)which image should be displayed after the current image finishes loading to the screen. In addition,if the switches are kept on after the select image finishes loading, the program will go through theimage loading process again, effectively writing the same image again. As such, if the user selectsanother image, the transition is not instant, as the program must finish loading the current imageto the screen.

On the example shown below, we select that the seventh image be displayed. Since the switcheswere kept on, the image is kept static in the screen to the user (but in practice the program keepsredrawing the picture in the background).

Figure 15: Seventh picture (in binary) Figure 16: Displaying the seventh image

9. Future WorkWith the system we created, we hope that future students and designers can use it as bedrock

of new and innovative projects, making use of this extra storage space that the system allows tocreate new and interesting applications (software-wise), for example, the possibility to explore more“intensive” data processing (up to 2GB of data).

Had we had more time, we would also like to have analysed the possibility of implementinganother type of file system (taking into account that the compatibility with the number of bitsshould not be a problem since SD card access is serial-based). Thus, we would like to investigatewhether there is something stopping the creation of a library similar to HAL to communicate witha SD card formatted in another file system, such as FAT32, EXT3, and others.

If this investigation revealed that it would in fact be possible to achieve such a goal, then severalparallel projects would naturally arise (one per file system). The individual analysis of differentfile systems would be particularly interesting to enable access to more than 16 bit addresses, thusaddressing a much larger memory zone.

We would also be interested in displaying other image types than *.bmp (or, for that matter,.*bmp files with less than 24 bit color depth), to increase the usability of our electronic frame.

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10. References[1] Global Industry Analysts Inc., Market for SD Cards to Reach $21.3 Billion by

2018, http://www.storagenewsletter.com/rubriques/market-reportsresearch/global-industry-analysts-sd-cards/, 13th July 2012, [Last checked: 13th of July,2015].

[2] Altera, Quartus II Help, http://quartushelp.altera.com/13.1/mergedProjects/reference/glossary/def_qsys.htm, [Last checked: 13th of July, 2015].

[3] Altera, DE2 Development and Education Board - User Manual, http://www.ece.tufts.edu/~hchang/ee129-f06/project/project2/DE2_UserManual.pdf, [Last checked: 13th of July,2015].

[4] Altera, My First Nios II Software Tutorial, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/tt/tt_my_first_nios_sw.pdf, [Last checked:13th of July, 2015].

[5] Terasic (A. Houng), My First Nios II Tutorial (1), https://www.youtube.com/watch?v=DBkza5-SlqQ, [Last checked: 13th of July, 2015].

[6] Altera (A. Agrawal), Design of Qsys system showcasing Nios II processor - SD card interface,https://www.youtube.com/watch?v=NmMX80iOAW4, [Last checked: 13th of July, 2015].

[7] Altera, Introduction to the Altera Qsys System Integration Tool, ftp://ftp.altera.com/up/pub/Altera_Material/12.1/Tutorials/Introduction_to_the_Altera_Qsys_Tool.pdf,[Last checked: 13th of July, 2015].

[8] Altera, Altera Monitor Program Tutorial, ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Tutorials/Altera_Monitor_Program_NiosII.pdf, [Last checked: 13th of July, 2015].

[9] R. Karam, Simple SC Card Interfacing, http://robkaram.com/simple-sd-card-interfacing/, [Last checked: 13th of July, 2015].

[10] Altera, Altera University Program Secure Data Card IP Core, ftp://ftp.altera.com/up/pub/Altera_Material/11.0/University_Program_IP_Cores/Memory/SD_Card_Interface_for_SoPC_Builder.pdf,Alternative link: ftp://ftp.altera.com/up/pub/Altera_Material/11.0/University_Program_IP_Cores/Memory/SD_Card_Interface_for_SoPC_Builder.pdf, [Last checked:13th of July, 2015].

[11] S. Moslehpour, K. Jenab, and E. H. Siliveri , Design and Implementation of NIOS II Systemfor Audio Application, http://www.ijetch.org/papers/631-T927.pdf, [Last checked: 13th

of July, 2015].

[12] Altera, Overview of the Hardware Abstraction Layer, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/n2sw_nii52003.pdf, [Lastchecked: 13th of July, 2015].

[13] Altera Forum, Read from sd card an image on DE2-115, http://www.alteraforum.com/forum/showthread.php?t=42633, [Last checked: 13th of July, 2015].

[14] R. Wong and V. Santhanagopalan, ECE 5760 Final Project - Music Playerhttp://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/f2010/vs327_rw363/WAV_player/ECE%205760.htm, [Last checked: 13th of July, 2015].

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[15] J. Li, Greedy Snake Video Game Based On Nios II System, https://www.theseus.fi/bitstream/handle/10024/72469/Li_Jinpeng.pdf?sequence=1, [Last checked: 13th of July,2015].

[16] Altera, University Program IP Cores, https://www.altera.com/support/training/university/materials-ip-cores.tablet.html, [Last checked: 13th of July, 2015].

[17] Altera, Video IP Cores for Altera DE-Series Boards, ftp://ftp.altera.com/up/pub/Altera_Material/13.1/University_Program_IP_Cores/Audio_Video/Video.pdf, [Lastchecked: 13th of July, 2015].

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