Report on the IT ASIC Front-End evaluation · RD53A Analog Front-end 2 Single amplification stage with Krummenacher feedback for linear ToT charge encoding and detector leakage current

Report on the IT ASIC Front-End evaluation

Duccio Abbaneo, Jorgen Christiansen, Natale Demaria, Karl Ecklund, Natalia Emriskova, Luigi Gaioni, Dominik Koukola, Flavio Loddo, Michael McGinnis, Stefano Mersi, Ernesto Migliore, Ennio Monteil, Stella Orfanelli2019-06-05Tracker Plenary during Tracker Week

2RD53A Analog Front-end

●Single amplification stage with Krummenacher feedback for linear ToT charge encoding and detector leakage current compensation●Asynchronous current comparator●4 bit local DAC for threshold tuning

Linear FE

● Continuous reset integrator first stage with DC-coupled pre-comparator stage● Two-stage open loop, fully differential input comparator● Leakage current compensation circuit (can be enabled/disabled)● 4+1 bit local DAC for threshold tuning

Differential FE

Guidelines: https://twiki.cern.ch/twiki/pub/RD53/RD53ATesting/SYNC_FE_TESTING_SPECIFICATIONS.pdfhttps://twiki.cern.ch/twiki/pub/RD53/RD53ATesting/LIN_AFE_guidelines.pdfhttps://twiki.cern.ch/twiki/pub/RD53/RD53ATesting/Diff_userguide.pdf

●Telescopic-cascoded CSA with Krummenacher feedback for linear ToT charge encoding and detector leakage current compensation●Synchronous hit discriminator with track-and-latch comparator●Threshold trimming using the auto-zeroing technique (no local trim DAC → no SEU) , to be performed during Abort Gap (every ~ 80 us)●ToT counting using 40 MHz clock or fast counting using latch as local oscillator (30-400 MHz)

Synchronous FE

3Analog Front-End reviewDecember ‘18 – January ‘19: RD53 Review of RD53A Analog Front-ends. Committee made of ASIC design experts independent from the two experiments & detector experts from ATLAS and CMS● Assess the functionality of the designs● Identify potential issues & suggest corrective actions● Propose a list of specific tests to be carried out, test conditions and the most

suitable metrics to be used in comparing the front-ends● Compile a complete report of the findings → January 31, 2019

Each of the two experiments could use the results of this review process, together with other investigations and considerations as appropriate, to define the preferred design choice

4Result of January reviewFirst review conclusions:

● We have presented measurement results showing that the three front-ends have shown strong points but also imperfections. Unfortunately and due to [schedule constraints], the cause of some of the imperfections are to this date not understood. Based on the technical facts exposed in this document, the review committee believes that the Linear Front End is the design that presents a lower risk in its integration into a full scale chip. The reviewers recommend the designers to follow the recommendations that have been exposed in this document and to study the performance of the comparator for its optimization (with minor modifications).

● The reviewers would like to encourage the other teams to continue investigating the limitations on their front-ends– perform more measurements (and on more samples)– improve interaction between the measurement and the design teams– reproduce effects in [chip] simulation to better understand the observed effects

5Recommendations → new Task ForceATLAS: choice done at the end of February, constrained by ATLAS chip submission in September 2019: Differential FECMS: choice before July, to allow CMS prototype chip submission in April 2020. This allowed to address the Front-End selection with a structured approach: a Task Force was formed (with a mix of chip designers, DAQ and simulation experts) to collect material for a final decision within May. Following the recommendations of the review, the aim was to:

● Follow-up possible design improvements● Characterize issues (via the interactions of measurements and simulations)● Define a set of parameters impacting detector performance and evaluate the

different designs against these

Outline of the talk



Outline of the talk



8Design improvementsSYNCHRONOUS LINEAR DIFFERENTIAL

Advantages• No trimming needed• No overdrive

• Well understood architecture • Very low noise occupancy• Small threshold dispersion

Limitations• Large noise occupancy with

sensors• Large overdrive• TDAC saturation at cold

• Large timing dispersion• Tuning issues with leakage

current

Here some brief summary of design improvements (and standing limitations).Too much work to be reported here – more details available in yesterday’s IT ASICs session:● Synchronous:

https://indico.cern.ch/event/818375/contributions/3429701/attachments/1844782/3026266/Sync_FE_presentation_15052019.pdf● Linear:

https://indico.cern.ch/event/818375/contributions/3429702/attachments/1844810/3026316/LIN_AFE_summary.pdf● Differential:

https://indico.cern.ch/event/818375/contributions/3429700/attachments/1844754/3026224/Loddo_IT_ASIC_15May2019_V2.pdf

https://indico.cern.ch/event/818375/

https://indico.cern.ch/event/818375/contributions/3429701/attachments/1844782/3026266/Sync_FE_presentation_15052019.pdf

https://indico.cern.ch/event/818375/contributions/3429702/attachments/1844810/3026316/LIN_AFE_summary.pdf

https://indico.cern.ch/event/818375/contributions/3429700/attachments/1844754/3026224/Loddo_IT_ASIC_15May2019_V2.pdf

9Synchronous front-endMain developments after January Review:● Studies on AZ-related spikes on power rails:

fix available: new AZ distribution schemesee yesterday’s talk for details

● Fake hits measurements & threshold shift:see next slides

● Noise simulations and matching with measurements:ENC noise better reproduced now in simulation – see yesterday’s talk for details

● Improvements to the faster return to baseline (Krum. circuit)design improvement available: more phase margin – see next slides

Also the results obtained with non-uniform irradiation has been studied and understood

Power spikesFixed design

Ennio Monteil

10Sync: fake hits & threshold drift

Small threshold decrease (~20 e¯ / AZ cycle)This effect visible also in simulation But: current can be different among pixels (mismatches)

Small number of pathological pixels show a much larger drift~ 0.2% of the pixels show this behaviour

Effect is understood and a mitigation strategy is proposed(dedicated voltage line to decrease the mean shift → reduce extreme ones)

Threshold vs. time: average Threshold vs. time: noisy pixel

Ennio Monteil

11Sync: feedback improvementFront-end stability with fast return to baseline was demonstrated to be important (see later)

Design change proposed & evaluated: modification of Krummenacher W/L = 1.2÷1 → 0.3÷4

Simulation for different PA bias & feedback capacitance: noise performance improves, stability of the first stage improves – same front-end tuning

Input signal1 ke¯Speed1 TOT₈₀/2500 e¯Ileak20 nA (worst case)

0 fF

25 fF

50 fF

400 ns 400 ns

100 mV

Current Improved

Ennio Monteil

12Linear front-endThe RD53A version of the LIN front-end has been extensively tested

RD53A main issues:● Larger time-walk: improved version of the

comparator (improved time-walk)Prototype chip including new TDAC has been characterized (also after irradiation) showing good results

● Channel trimming saturation effect (TDAC): new 5-bit TDAC (saturation effect fixed)

Post-layout simulations (different corners) do not point out particular issues for the new version of the Linear FE: (noise and thr. dispersion, timewalk, ToT linearity, TDAC range, threshold tuning, voltage drop, fast return-to-baseline)

overdrive

Natalia Emriskova

13Lin: improved time-walk RD53A RD53B

Significant improvement in time-walk shown in simulation at the cost of a marginal increase in static current consumption

Luigi Gaioni

14Lin: improved threshold trimming

RD53A RD53B

Saturation effect @ cold (large ILDAC)

Trimming DAC [4b]0x0 0xF

Trim

min

g cu

rren

t [µA

]

0

0xF

0.8Room T

Cold

Room T

Cold

TDAC saturation effect fixed in RD53B

Trimming DAC [5b]0x0 0x1F Luigi Gaioni

Trim

min

g cu

rren

t [µA

]0

1.6

15Lin: improved trimming in siliconNew version of the TDAC was integrated in a small prototype chipPrototype TDAC chip irradiated: fully functional at 460Mrad (& steps @ 1, 85 Mrad)

RD53B(X-rays, 3 Mrad/h, room T)

Luigi Gaioni

16Differential front-endDIFF FE is designed by: Amanda Krieger, Dario Gnani, Abder Mekkaoui, Aikaterini Papadopoulou (LBNL)

PreAmplifierStraight regulated cascode (single bias)Gain selectionDischarge with simple MOSFET in parallel (no Krummenacher) Global bias DAC setting of discharge current (VFF → ToT)

Leakage Current Compensation Circuit (LCC)Low-pass filter with bias DAC adjustable gain/cutoff frequencyPlaced in parallel with Cfeed and discharge MOSFET to drain sensor DC leakage

PreComparatorUses the PREAMP input node as a pseudo-differential reference to generate a differential thresholding circuitAdditional gain (2×)Differential Trim DAC

ComparatorContinuous time single-to-diff OpAmpPositive feedback in OTA to enhance gain

17Diff: strong pointsVery low noise

excellent minimum threshold⇒Fast rise time

low time walk⇒

Natalia Emriskova

18Diff: limitations● Bug between comparator output and the first digital gate

Simple solution implemented in design (see yesterday’s slides)Patch applied for tests: 8×8 pixel matrix masked

● Slow comparator output stageThe output stage discharges at ≈20ns/V σ⇒ TIME = (dt/dV) σTHR = 1.8 ns (10 ns pk-pk)Solution: inverting the comp polarity (faster) ⇒ σTIME = (dt/dV) σTHR = 1.2 ns (6 ns pk-pk)

● Trimming DAC affects ToT valuesSolution: no changes – accept as deterministic

● Problematic threshold tuning after irradiation at coldMitigation found (see next slides)

● Not well understood behaviour with irradiated sensors/leakage current at coldSolution not yet found (see next slides)

● Limited return-to-baseline tuning rangePerformance at the limit of CMS requirements (see further slides)

Timing Mask

19Diff: threshold tuning irrad/coldProblematic threshold tuning after irradiation at cold: due to the combined effect of PMOS threshold increase for both cold T and irradiation, the PRECOMP doesn’t work properlyProblematic threshold tuning after irradiation at cold: due to the combined effect of PMOS threshold increase for both cold T and irradiation, the PRECOMP doesn’t work properly

Mitigation: decrease LLOAD from 4 µm to 0.6 µm → Vmargin ≥ 0 at -30 °C and 500 Mrad

Our hottest module:1250 Mrad in 3000 fb¯¹(Fluka with no addedmargin)

20Diff: irrad sensor/leakage currentNot well understood behaviour with irradiated sensors/leakage current at cold T:

● Tests with bias current from few irradiated sensor and un-irradiated modules with IR LEDs● Threshold tuning was difficult and not always successful● Proper usage and biasing of LCC was not understood before RD53A testing● For irradiated sensor, also problem with PRECOMP described before contributes to the issue

No improvement suggested(no modifications foreseen so far)

Example test withHV = 260VIleak = 0.75 mA ≈ 10nA/pixel

Outline of the talk



22Detector performance estimation

Relevant detector performance-related parameters were identified and are summarised above.Corresponding measurable quantities were identified to be:

● TOT for a defined charge: Q/TOT₄₀— 3000 e¯/TOT40 correspond to ~1% inefficiency in L1● Noise — 10¯⁶ occupancy correspond to 1% of L4 hits

– occupancy (excluding pixels with >10¯⁴ rate)– fraction of noisy pixels (only pixels with >10¯⁴ rate)

● Out-of-time hit rate (with the complex method described above)● Absolute threshold● Track resolution

feature impacts on affected detector performance

fast rise time & comparator hits correct BX assignment bandwidth + fake rate + hit resolution

fast return to baseline dead time efficiency (esp L1)

slow return to baseline TOT accuracy hit resolution

low noise hit rate fake hits bandwidth + fake rate (esp L4)

low detection threshold low-charge hit detection hit resolution + efficiency

low channel noise TOT accuracy hit resolution

The relation between these parameterswas studied in detail (see next slides)

23TOT accuracy

CMSSW simulations allowed to understand the impact of charge resolution in the TOT.This is determined by TOT quantization and its calibration spread, which depend on:

● Setting of the return-to-baseline current● Spread of the TOT value for a given charge injection

(due to both channel-to-channel variation and threshold spread)● Possible use of fast-TOT counter

feature impacts on affected detector performance







24Impact of Q resolution on track σOne of the relevant parameters to investigate was the impact of the resolution in the conversion between charge and TOT

A number of studies were performed using the full CMSSW simulation to extract the impact of Q/TOT on σxy and σz for– Threshold: 1200 e¯ or 2400 e¯– Q/TOT₈₀: 300 e¯, 1500 e¯, 3000 e¯– Pixel: 50×50 µm², 25×100 µm²

Other simulation parameters:Single µ, with pT=10 GeV/c

Planar 150 µm-thick sensorsNo noisy pixels

Simple in-time threshold: 1200 e¯

25

0 1500 300010

15

20

Charge resolution [e¯/TOT ]₈₀

Tra

ck x

y r

eso

lutio

n [µ

m]

₀

2400e¯

1200e¯

2400e¯1200e¯

50×50

25×100

Threshold

0 1500 30000

40

80

120

160

Charge resolution [e¯/TOT ]₈₀T

rack

z r

eso

lutio

n [µ

m]

₀

2400e¯

1200e¯

2400e¯1200e¯

Threshold

50×50

25×100

50×50

Impact of Q resolution on track σThe track resolution on xy₀ plane and on z₀ is sensitive to the pixel geometry and on the threshold. Results show that it is quite insensitive to Q/TOT₈₀ instead (x axis in the plots). This is due to the fact that the single-hit resolution rms is dominated by cluster losing hits

Very little impact of TOT accuracy Ernesto Migliore

26Noise and thresholdfeature impacts on affected detector performance







27Noise comparison

● Assemblies noisier that bare chips● Noise: SYNC > LIN> DIFF

Natalia Emriskova

SYNC

SYNC

LIN

DIFF

Noise rms Noise tails

SYNC

● Occupancy from noise tails clearly depends on selected threshold

28Noise occupancy

Output: • Noise hit distribution

sort pixels by number of hits

• TOT40 distribution

check if TOT40 of noise hits is low

• Average noise occupancy

2 pixels with

8 noise hits

Noise occupancy=𝑁h𝑖𝑡𝑠

𝑁 𝑝𝑖𝑥𝑒𝑙𝑠×𝑁 𝑒𝑣𝑒𝑛𝑡𝑠

Method: • No injection, no particles• Send 106 triggers• Count hits

Natalia Emriskova

29Noise occupancy

SYNC LIN

Noise hit distribution:• SYNC slow decrease + long tail• LIN quick decrease + some outliers• DIFFvery robust to noise, not a single noise hit over 106 triggers

Natalia Emriskova

30Pixel masking (“noisy” pixels)

o Required average noise occupancy of 10-6 corresponds to 1% of noise hits in layer 4

o Pixels > 100 hits / 106 triggers, i.e. with noise occupancy > 10-4

⟶ Declared noisy and masked to lower the overall noise occupancy of the FE

Masking

Natalia Emriskova

31Noise occupancy

Natalia Emriskova

● Noise occupancy: SYNC > LIN DIFF≫● Layer 1 scenario: threshold 1000 e- & fast discharge critical for SYNC FE (RD53A)⟶

32Noise occupancy vs PreAmp current

o The noise occupancy can be lowered by increasing the PA bias current in all 3 FEs

o But in has an impact on the power consumption

Reminder: Preamplifier bias• FE parameter (current)• Influence the speed of rise of the signal• Influence on the noise• Main contribution to the power

consumption

Decreasing global threshold

PA bias

Natalia Emriskova

33Noise and threshold: resultsfeature impacts on affected detector performance







● Moving the detection threshold to 1000 e¯ increases the noise occupancy in a measurable way for both the Linear and the Synchronous front-end

● Noise occupancy can be mitigated by increasing the PreAmp current● Noise occupancy:

● SYNC > LIN DIFF≫● SYNC FE has long tail in the noise distribution

34Fast return-to-baselinefeature impacts on affected detector performance







A return-to-baseline giving Q/TOT40=3000 e¯ (i.e. Q/TOT80=1500 e¯) corresponds to an expected dead time of 1% in L1. This is considered the target for CMS.

35

Preamplifier feedback current

influences:

• discharge speed

⇒ return to baseline

• time over threshold

⇒ dead time

• PA speed

⇒ higher noise occupancy

Increasing feedback current

Threshold

Increasing feedback current

o Important to reduce dead time in the detector (in particular in the innermost layers)o How fast can the preamplifier be discharged conserving good detection performance?

Preamplifier return-to-baseline

Natalia Emriskova

36Return-to-baseline comparison

o Target discharge speed 3000 e¯/TOT₄₀

reached by all FEso LIN and SYNC can discharge also fastero DIFF saturates

SYNC LIN

DIFF

Natalia Emriskova

37Return-to-baseline and noise

Noise: SYNC > LIN > DIFF (consistent with previous measurements)

• DIFF very low noise even at fast discharge

• LIN below 10-6 masking about 1% of pixels

• SYNC above 10-6 masking more than 2% Natalia Emriskova

38Fast return-to-baseline: resultsfeature impacts on affected detector performance







● target Q/TOT₈₀ =1500 e¯ can be reached by all FEs (but Diff is at the limit)● going to a faster return-to-baseline reduces the phase margin of the front-end amplifier and

increases the noise hit rates.● influence on the threshold dispersion is negligible (see yesterday’s slides)

A return-to-baseline giving Q/TOT₄₀=3000 e¯ (i.e. Q/TOT₈₀=1500 e¯) corresponds to an expected dead time of 1% in L1. This is considered the target for CMS.

39Late hits evaluationfeature impacts on affected detector performance







A slow front-end would result in a (large?) number of pixel hits being assigned to the wrong BX. This will negatively affect both bandwidth and resolutionA dedicated analysis combining measurements and CMSSW simulations was set-up to study this effect (see next slides)

40

1. FE timing measurements 2. Hit timing/amplitude:

CMSSW simulationDepending on the location

Late hits evaluation

Ernesto Migliore

41Time/ampl. measurements: “tornado”

Analog front ends: Synchronous Linear Differential

Thresholds: 1000 e-

1200 e-

PA discharge speed: Slow (TOT = 5.3 / 6ke-) Fast (TOT = 2.0 / 6ke-)

Test conditionsChip #279 + #281

Sensor 100×25 μm2

(150μm PT)

HV - 120 V

Temp. - 10 °C

Measurement combinations

Dominik Koukola

42

42

Time/ampl. measurements: “tornado”

LinearSynchronous DifferentialDominik Koukola

43Tornado time alignment

4.6

ns

Ernesto Migliore, Dominik Koukola


4.6

ns


4.6 ns margin(=3 plot bins)reasonable marginto include● clock jitter● clock distribution

skew in chip● pix-to-pix variations● other effects


4.6

ns

: fraction of hits with correct BX assignedα


46Tornado time alignment : fraction of hits with wrong BXβ


47Tornado time alignment=1- - : fraction of hits lostγ α β


48Comparison of RD53A front-ends

● Existing Linear FE (RD53A) shows significantly more late hits than SYNC and DIFF● Improvement with new design? We need to trust chip simulations!

Dominik Koukola

49Chip simulation validated

Measurement and simulation in good agreement: we can trust simulationDominik Koukola

50Comparison of front-ends

Fraction of mis-assigned pixel hits in the same ballparkDominik Koukola

51Out-of-time hit occupancy

β×estimated hit occupancy with occupancy information from TDR

Our noiserequirement

Dominik Koukola

52Fast rise time & comparator: resultsfeature impacts on affected detector performance







The PreAmp+Comparator speed determines the late hit rate, that will especially impact bandwidthThe background of late hits is almost uniform in the tracker, with a rate 10¯⁴~10¯⁵/BXThe current design of the Linear has a larger fraction of late hits, but the designed improvement shows a much reduced late hit rate (similar to the other Front-Ends)Systematic errors in this estimation were also evaluated (see yesterday’s slides by Dominik)

53ConclusionsA considerable additional effort was was put by the designers into understanding and improving the existing designs. Also a large effort was put by the whole Task Force to characterize the designs and expected detector performance. The results show that these circuits could work with the foreseen improvements for our detector upgrade. The lowest risk option was selected, by identifying each design’s limitations in view of the detector performance:

– the differential front-end showed limitations in cold operation after irradiation, for which a mitigation has been devised, and in the operation with irradiated sensors in cold; our L1 working point of Q/TOT₈₀ = 1500 e¯ is at the end of the range in which the FE can be tuned; the FE has also other issues that are well understood and fixable, together with the best noise performance (orders of magnitude below the requirements). The Task Force deemed this option to be marginal w.r.t. our requirements of radiation tolerance and hit rates, notably for L1

– the synchronous front-end showed some better understood features (drift of the threshold) and some other that were not reproduced in the simulation (noise occupancy – although still below or similar to the irreducible late hit background of 10¯⁵) together with the best timing performance

– the linear front-end was identified by the original Front-End review (of Dec18-Jan19) as the lowest-risk option. The two drawbacks were addressed: the main drawback for this option was evidenced to be the slow timing response, with its corresponding impact on out-of-time hits (which is predicted by simulations to be solved in the next design iteration)

● Since all other arguments in favour of one or another front-end are not compelling, the task force has chosen the linear front-end for the integration in the next RD53 design for CMS (C-ROC)

54CROC

Documents

Report on the IT ASIC Front-End evaluation · RD53A Analog Front-end 2 Single amplification stage with Krummenacher feedback for linear ToT charge encoding and detector leakage current