Research Article A Formal Approach for RT-DVS …downloads.hindawi.com/journals/mpe/2015/815230.pdfMathematicalProblems in Engineering to the analytical models proposed in existing

Research ArticleA Formal Approach for RT-DVS Algorithms EvaluationBased on Statistical Model Checking

Shengxin Dai Mei Hong Bing Guo Yang He Qiongyu Zhang Lin Sun and Yi Du

College of Computer Science Sichuan University Chengdu 610065 China

Correspondence should be addressed to Mei Hong hongmeiscueducn

Received 1 June 2015 Accepted 12 July 2015

Academic Editor Xiaoyu Song

Copyright copy 2015 Shengxin Dai et al This is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

Energy saving is a crucial concern in embedded real time systems Many RT-DVS algorithms have been proposed to save energywhile preserving deadline guarantees This paper presents a novel approach to evaluate RT-DVS algorithms using statistical modelchecking A scalable framework is proposed for RT-DVS algorithms evaluation in which the relevant components are modeledas stochastic timed automata and the evaluation metrics including utilization bound energy efficiency battery awareness andtemperature awareness are expressed as statistical queries Evaluation of these metrics is performed by verifying the correspondingqueries using UPPAAL-SMC and analyzing the statistical information provided by the tool We demonstrate the applicability ofour framework via a case study of five classical RT-DVS algorithms

1 Introduction

Energy saving has become a crucial concern for embeddedreal time systems especially for the battery-powered systemsHigh energy consumption not only shortens the lifespanof computing system but also leads to high processor tem-perature that degrades system performance robustness andreliability Therefore system level power management hasgained significant attention in recent years

Dynamic voltage scaling (DVS) is a way to save energyin processor which adjusts the supply voltage and operat-ing frequency dynamically The energy consumption scalesquadratically to the supply voltage (119864 prop 119881

2) and the oper-ating frequency almost linearly depends on the supply volt-age DVS permits trading system performance for energysaving through frequency and voltage scaling [1] Howeverchanging the operating frequency will affect the executiontime of the tasks and may violate the timing constraints Realtime DVS (RT-DVS) [1] is proposed to achieve energy savingwhile ensuring temporal correctness

A number of RT-DVS algorithms [1ndash4] have been devel-oped in the last two decades Many of these algorithms focuson periodic tasks assuming that the tasks timing attributesincluding period worst-case execution time (WCET at

the maximum available processor frequency) and deadlineare known in advance These algorithms have been experi-mentally studied using simulation based approaches both onsoftware simulators [5 6] and on hardware platforms [7 8]However simulation based evaluation is time consuming andoften not completely reliable Hence we propose evaluatingDVS algorithms with statistical model checking approachwhich is based on mathematical models and logics

In this paper we illustrate the applicability of statisti-cal model checking [9] an automatic formal verificationtechnique to the area of RT-DVS algorithms evaluationThe relevant components involved in RT-DVS algorithmsevaluation aremodeled as stochastic timed automata [10] andimplemented in statistical model checker UPPAAL-SMC[10] Subsequently the evaluation metrics including uti-lization bound energy efficiency battery awareness andtemperature awareness are expressed as statistical queriesand written in metric interval temporal logic (MITL) [10]Finally the system model is verified with respect to sta-tistical queries using UPPAAL-SMC The model checkerestimates the probability of the system to satisfy the queriesWhat is more the tool provides statistical information forexample probability densities and means which is used forfurther evaluation We propose a scalable framework for

Hindawi Publishing CorporationMathematical Problems in EngineeringVolume 2015 Article ID 815230 12 pageshttpdxdoiorg1011552015815230

2 Mathematical Problems in Engineering

RT-DVS algorithms evaluation In the sequel a case studyis conducted in order to demonstrate the applicability of ourframework

To the best of our knowledge this is the first researcheffort that proposes evaluating RT-DVS algorithms using sta-tistical model checking Our conclusions are partly observedby the simulation based approaches However we obtainthese conclusions in a more automatic and reliable mannerWhat is more we consider the impact of temperature onthe energy efficiency of RT-DVS algorithms In addition itshould be emphasized that our approach is not limited tothe algorithms described in this paper but all the dynamicvoltage scaling algorithms can be modeled and then evalu-ated with our framework Furthermore although multicoresystems are increasingly used single core systems are stillof interest since the approaches can be applied to multicoresystems with some modification

The rest of the paper is structured as follows Section 2introduces the fundamental theories of RT-DVS algo-rithms Section 3 introduces statistical model checking basedapproach for RT-DVS algorithms evaluation Section 4describes the system model in detail Section 5 describes thestatistical queries for evaluation Section 6 presents a casestudy to evaluate five classical RT-DVS algorithms Section 7gives an overview of the related work Finally Section 8concludes the paper

2 Power Consumption andRT-DVS Algorithms

This section introduces some fundamental theories of RT-DVS algorithms which are the foundation of the modelspresented later

21 Processor Power Distribution The power consumptionof the processor can be divided into three componentsdynamic static and short circuit power [4] Short circuitpower is comparatively insignificant to dynamic and staticpower thus it is negligible [4] so we do not discuss it in thispaper

A DVS enabled processor has a discrete set of oper-ating frequencies 119865 = 119891

1 1198912 119891

119899 and each clock

frequency is associated with a supply voltage level in set119881 = V

1 V2 V

119899 Meanwhile processor has two modes

of operation (1) idle mode when it does not have any jobin the system and thus dissipates only static power and (2)

active mode when the processor executes some jobs in thesystem and dissipates both dynamic power and static power[11] For many years dynamic power dissipation was thedominant factor in total power consumption which can beapproximated with the following formula

119875dyn = 119862119897sdot 119873sw sdot 119881

2119889119889

sdot 119891 (1)

where 119862119897is the load capacitance 119873sw is the average number

of circuit switches per clock 119881119889119889

is the supply voltage and 119891

is the operating frequency The operating frequency almostlinearly depends on the supply voltage [4]

119891 = 119896 sdot(119881119889119889

minus 119881119905)2

119881119889119889

(2)

where 119896 is a constant and 119881119905is the threshold voltage By

substituting (2) in (1) the dynamic power at supply voltageV119896will be formulated as [12]

119875dyn (V119896) = 1198620 sdot V3119896 (3)

where 1198620 is a processor specific constants and V119896isin 119881 is 119896th

voltage levelStatic power or leakage power increases its dominance

of total power consumption in recent years which can beformulated as [11]

119875sta = 119873gate sdot 119868leak sdot 119881119889119889 (4)

where119873gate represents the number of gates 119868leak is the leakagecurrent and 119868leak has a nonlinear exponential relationshipwith both temperature and supply voltage Fortunately it hasbeen shown in [13] that the static power can be approxima-tively calculated with

119875sta (V119896) = (1198621 (119896) +1198622 (119896) sdot 119879) sdot V119896 (5)

where 1198621(119896) and 1198622(119896) are some processor specific voltagesensitive constants and 119879 is the processor temperature Asreported in [13] using (5) can accurately estimate the staticpower with relative error less than 13

In general the total power of the processor at activemodelis formulated as

Pow (V119896) = 1198620 sdot V

3119896+ (1198621 (119896) +1198622 (119896) sdot 119879) sdot V

119896 (6)

Lastly we discuss the processor temperature in detail Weadopt the well-known lumped RC model [12] to describe thetransient behavior of the processor temperature as

120597119879 (119905)

120597119905= 120588 sdotPow (119905) minus 120573 sdot 119879 (119905) (7)

where 120588 and 120573 are processor specific thermal coefficientsand Pow(119905) and 119879(119905) are the instantaneous power and tem-perature respectively Without loss of generality we havescaled the temperature such that the ambient temperatureis considered zero Otherwise an offset equals the ambienttemperature which is substituted in (7)

22 RT-DVS Algorithms RT-DVS algorithms exploit twotypes of slack time [3] (1) static slack when the totalutilization is less than 1 there exists time interval that canbe used for voltage scaling and (2) dynamic slack when theactual execution time of the task is smaller than itsWCET atime interval is generated to further reduce the supply voltageRT-DVS algorithms differ in the way they estimate and utilize

Mathematical Problems in Engineering 3

RT-DVSalgorithms

models

Tasksetsgenerator

model

Platformmodel

UPPAAL-SMC

Statisticalqueries

Probabilityinterval

Statisticalinformation

ccRM laEDF Utilizationbound

Batteryawareness

InformationtableFill in

middot middot middot middot middot middot

Figure 1 Illustration of our approach

the static and dynamic slacks accordingly they can be furtherdivided into three types as follows

(1) We have static voltage scaling [1] for example staticEarliest Deadline First (staEDF) and static RateMonotonic (staRM) which only exploits the staticslacks by setting the operating frequency to the lowestpossible one that guarantees the taskset feasibilityNote that the frequency is set at the starting and neverchanged during execution

(2) We have cycle conserving scaling [1] for examplecycle conserving EDF (ccEDF) and cycle conservingRM (ccRM) which exploits the dynamic slacks byupdating the utilization whenever a task is releasedor terminated thus when a task is terminated earlythe remaining time can be used to scale the frequencydown

(3) We have look-ahead scaling [1] for example look-ahead EDF (laEDF) which exploits both static anddynamic slacks by pushing tasks as close as possibleto their deadlines and sets the operating frequency tothe slowest possible one that ensures that all futuredeadlines are met

3 RT-DVS Algorithms Evaluation Based onStatistical Model Checking

31 Statistical Model Checking and UPPAAL-SMC Statisticalmodel checking [9] is one of the quantitative verification [14]approaches which efficiently addresses verification problemby combining the Monte Carlo method with temporal logicmodel checking [15] It automatically samples the traces(or simulations) of the system model checks whether thesamples satisfy or violate the quantitative property and finallyapplies a statistical estimation technique to compute anapproximate value for the probability that the property issatisfied [15]The estimation is correct up to some confidencelevel that can be parameterized by user

UPPAAL-SMC [10] is a stochastic and statistical modelchecking extension of UPPAAL toolbox for verification

of stochastic hybrid systems The modeling formalism ofUPPAAL is an extension of classical timed automata withadditional features such as integer variables data structuresuser-defined functions and synchronization And the mod-eling formalism of UPPAAL-SMC is based on a stochasticinterpretation and extension of the timed automata used inUPPAAL it has been extended to handle stochastic and non-linear dynamic behaviors discrete probabilities a stochasticinterpretation for timed delays and even dynamic processcreation [10] In UPPAAL-SMC a system is represented asa network of interacting stochastic timed automata (STAs)which communicate via broadcast channels and shared vari-ables [10] Three types of queries are supported by UPPAAL-SMC that is probability estimation hypothesis testing andprobability comparison The probability confidence intervalcan be estimated by the query 119875119903[119887119900119906119899119889](120593) the hypothesistesting is achieved by the query 119875119903[119887119900119906119899119889](120593) gt= 119901 (where119901 is a specified threshold) and probability comparison isachieved by the query 119875119903[119887119900119906119899119889

1](1205931) gt= 119875119903[119887119900119906119899119889

2](1205932)

where 119887119900119906119899119889 defines how to bound the runs There are threeways to bound the runs they are by time (specifying lt=

119873 where 119873 is positive integer) by cost (specifying 119909 lt=

119873 where 119909 is a specific clock) and by number of steps(specifying lt= 119873) [10] In addition to the three classicalqueries UPPAAL-SMC supports the evaluation of expectedvalues ofmin ormax of an expression that evaluates to a clockor an integer value the queries are 119864[119887119900119906119899119889 119862](119898119894119899 119890119909119901119903)

or 119864[119887119900119906119899119889 119862](119898119886119909 119890119909119901119903) respectively where 119887119900119906119899119889 isas previously explained 119862 accounts for the number of runsexplicitly and 119890119909119901119903 is the expression to be evaluated

32 Statistical Model Checking Based Approach for RT-DVSAlgorithms Our approach is illustrated in Figure 1 EachRT-DVS algorithm is modeled as timed automata Tasksetsgenerator model consists of tasksets attributes generatormodel and task template It is used to generate the tasksetsto which the algorithms can be applied Platform modelconsists of processor model and battery model in whichthe variation of energy consumption processor temperatureand the electronic charges in battery is modeled according


to the analytical models proposed in existing papers suchas [3 12 13 16] UPPAAL-SMC automatically compositesthe models in advance then the entire system model forevaluation can be obtained

There are four evaluation metrics in our approach andthey are expressed as statistical queries and written in MITLas follows

(1) The utilization bound 119880119887of an algorithm 119860 is the

maximum utilization that any tasksets whose utiliza-tion is smaller than 119880

119887are schedulable according to

119860 [17] Bigger utilization bound indicates that thecorresponding algorithm has better scalability fortasksets scheduling

(2) Energy efficiency of an algorithm is represented by thetotal energy consumption of the system in a boundedtime Less energy consumption indicates that thecorresponding algorithm is more energy efficient

(3) Battery awareness is represented by battery utilizationwhich is the ratio of the energy dissipated untilthe battery is empty to the total capacity of thebattery Higher battery utilization indicates that thecorresponding algorithm is more battery aware thatis more charges have been used before the batterycannot provide energy for the first time

(4) Temperature awareness is represented by the expectedvalue of themaximumprocessor temperature Higherexpected temperature indicates that the correspond-ing algorithm is less temperature aware that is it ismore likely to cause a hotspot

UPPAAL-SMC is employed to verify the system modelwith respect to the statistical queries We alter the parame-ters in tasksets attributes and observe how each parameterimpacts the RT-DVS algorithms Tasksets generator modelis involved in every evaluation in order to generate thetasksets with respect to specified taskset characteristicsThusall the algorithms are applied to the tasksets with the sameattributes instead of prior generated tasksets We record thestatistical information provided by the model checker in theinformation tables and each item of the tables is obtainedby an individual verification process Finally we visualize theinformation tables in the form of line chart so that intuitiveresults can be obtained

4 System Modeling with UPPAAL-SMC

In this section we describe the framework for RT-DVSalgorithms evaluation in detail Eachmodel of the frameworkis discussed separately all the models are composited viachannels and shared variables so as to obtain the entiremodelfor evaluation

We consider that a system consists of a taskset composedof 119899 independent periodic tasks that is 119879 = 120591

1 1205912 120591

119899

and it is executing upon a single DVS enabled processor Eachtask is characterized by a period 119875 a worst-case executiontime WCET and a relative deadline 119863 that equals the taskperiod Each task generates infinite jobs with the first jobarriving at time zero and subsequent arrives every 119875 timeunits We assume that the voltage scaling and the task

preemption overheads are negligible in both the time and theenergy consumed

41 Global Data Structures In order to store the attributesof the system some data structures are defined and theUPPAAL-SMC declaration of global data structures is shownas follows

const int119873 = sdot sdot sdot typedef int [0119873 minus 1] 119905 119894119889double period [119873]double wcec [119873]const double 119861119862119864119865 = sdot sdot sdot

const int 119865119877119864119878 = sdot sdot sdot

typedef int [0 119865119877119864119878 minus 1] 119901 119894119889const double fres [119865119877119864119878] = sdot sdot sdot const double voltages [119865119877119864119878] = sdot sdot sdot const double 1198880 = sdot sdot sdot const double 1198881 [119865119877119864119878] = sdot sdot sdot const double 1198882 [119865119877119864119878] = sdot sdot sdot const double 119901 = sdot sdot sdot const double 119887 = sdot sdot sdot

where the number of tasks is encoded with constant 119873

and 119905 119894119889 type declaration indicates that task identifiers areintegers ranging from 0 to119873 minus 1 The task period and worst-case execution cycles (119882119862119864119862 ie the value obtained bymultiplying 119882119862119864119879 by the maximum frequency) are storedin two arrays named 119901119890119903119894119900119889[119873] and 119908119888119890119888[119873] respectivelyand task identifiers are used to index these two arrays Theconstant 119861119862119864119865 defines the best case execution cycles fractionof 119882119862119864119862 hence the actual execution cycles will be in rangeof [119861119862119864119865 lowast 119882119862119864119862119882119862119864119862] The number of scaling levelsrepresents how many discrete operating frequencies that theprocessor supports is encoded with constant FRES and 119891 119894119889

type declares frequency identifiers All the discrete operatingfrequencies are normalized with respect to the maximumfrequency which are stored in 119891119903119890119904[119865119877119864119878] array and thecorresponding supply voltages are stored in voltages[FRES]both of the two arrays are indexed by frequency identifiersThe identifier of the current frequency is encoded with 119865119903119890which is initially set to 1 And the remaining variables are theprocessor specific parameters which have been described informulas (6) and (7)

42 Tasksets Generator Modeling421 Tasksets Attributes Generator Modeling To evaluate theRT-DVS algorithms requires a method of generating tasksetsto which the algorithms can be applied Two importanttaskset parameters for tasksets generation are the tasksetcardinality 119899 and the taskset utilization 119906 The tasksets gener-ation algorithm sets the utilization of each task meanwhileit guarantees the total utilization sum

119899

119894=1 119880119894 = 119906 where 119880119894=

119882119862119864119879119894119879119894is the utilization of 120591

119894 Once task period has been


Initial

C

time[tid]=0release[tid]

time[tid]gt=period[tid]error=true

error=true

Error

time[tid]gtperiod[tid]

exec998400==0ampampReady

time[tid]lt=period[tid]run[tid]

preempt[tid]

execlt=acecampampexec998400==fres[Fre]

exec==acecampamptime[tid]lt=period[tid]

Run

finish[tid]

Finish

time[tid]lt=period[tid]ampampexec998400==0

time[tid]==period[tid]release[tid]

time[tid]=0exec=0

exec998400==0ampamptime[tid]998400==0

acec=(random(10)lowast(1minusBCEF)+BCEF)lowastwcec[tid]


Figure 2 Task template

chosen its119882119862119864119879 and119882119862119864119862 can be calculated in the sequelUUniFast [18] algorithm is an efficient algorithm for taskutilization generation which generates unbiased utilizationvalues and supports parameter independence

The tasksets attributes generator is modeled as timedautomata in form of UPPAAL template which has twolocations that linked with one transition in which UUniFastalgorithm is implemented and the initial location is acommitted location This model takes three parameters thetaskset cardinality 119899 the taskset utilization 119906 and the taskcardinality period 119901 The first two parameters have beendescribed in advance and the task cardinality period119901 is usedto bound the tasks period in range of [5 lowast 119901 10 lowast 119901] Taskattributes can be obtained with combining all the parameterswith UUniFast algorithm

422 Real Time Task Modeling The task attributes areassociated with a timed automata template that captures thestates of tasksThe task template is depicted in Figure 2 whichtakes a single parameter namely the task identifier 119905119894119889 whichis used to index the task attributes arrays as well Each task isrepresented by an instance of the task template parameterizedwith the task attributes And all the jobs (instances of the task)of one task share the same task identifier

Whenever a job is released it signals the scheduler thatit is ready for execution using 119903119890119897119890119886119904119890[119905119894119889] Meanwhile twoclock variables called 119905119894119898119890[119905119894119889] and 119890119909119890119888 are initializedwhere 119905119894119898119890[119905119894119889] represents the time since the beginning of

the current period and 119890119909119890119888 is a stopwatch used for countingthe execution cycles in current period respectively More-over the actual execution cycles 119886119888119890119888 of this job is calculatedwith formula 119886119888119890119888 = (119903119886119899119889119900119898(10) lowast (1 minus 119861119862119864119865) +

119861119862119864119865) lowast 119908119888119890119888[119905119894119889] that is it is a value in range of [119861119862119864119865 lowast

119882119862119864119862119882119862119864119862]The invariant on location 119877119890119886119889119910 indicates that 119890119909119890119888 does

not progress (119890119909119890119888 == 0) that is the job is not running and119905119894119898119890[119905119894119889] cannot be larger than the task period The location119877119906119899 corresponds to busy executing in which the growth rateof 119890119909119890119888 is fres[Fre] that is the current normalized frequencyWhen 119890119909119890119888 is equal to 119886119888119890119888 the template moves to 119865119894119899119894119904ℎ

location and stays in this location until the next period startsWhen the job is running it may be preempted by a higherpriority job this behaviour is implemented by 119901119903119890119890119898119901119905[119905119894119889]Whenever the job misses its deadline that is 119905119894119898119890[119905119894119889] gt

119901119890119903119894119900119889[119905119894119889] the template moves to 119864119903119903119900119903 location and setsthe value of global variable 119890119903119903119900119903 to TRUE

43 RT-DVS Algorithms Scheduler Modeling In order todispatch the tasks and implement the RT-DVS algorithms thescheduler template is introduced Each RT-DVS algorithm isimplemented with an individual template however all thetemplates are similar Besides some extra data structuresshould be appended in order to provide the informationas required for example last 119886119888119890119888 of the task for ccEDFAlthough it is not a trivial work to implement the templateswe will not describe all the templates but detailedly explainone template insteadWe use ccEDF algorithm template as anexample it is shown in Figure 3

The scheduler template is equipped with a task iden-tifier array named 119902119906119890119906119890 and all the elements in 119902119906119890119906119890

are initialized to minus1 with function 119868119899119894119905119894119886119897() It stays inIdle location unless a job is released or finished executionWhen 119903119890119897119890119886119904119890[119905] arrives the scheduler inserts the task iden-tifier into 119902119906119890119906119890 based on EDF policy using the function119904119888ℎ119864119863119865(119905) and then adjusts the operating frequency using thefunction 119888119888119864119863119865119877(119905) in which the corresponding function119905119886119904119896 119903119890119897119890119886119904119890() [1] is implemented After that the scheduleralters the state of the relevant jobs if the incoming job hashigher priority than the running job the scheduler preemptsthe running job and dispatches the incoming job to run elseif queue is empty the incoming job is dispatched to executeotherwise no operation is performed

Upon receiving 119891119894119899119894119904ℎ[119905] the scheduler pops the firsttask identifier out of 119902119906119890119906119890 and then adjusts the operatingfrequency using the function 119888119888119864119863119865119865(119905) in which the cor-responding function 119905119886119904119896 119888119900119898119901119897119890119905119894119900119899() [1] is implementedFinally the scheduler selects the next highest priority job in119902119906119890119906119890 (if it is not empty) to execute Committed location(encircled with C) is employed to achieve atomic transitionthus 119868119889119897119890 is the only location where the time can elapse

44 Platform Modeling

441 Processor Modeling The template of processor alter-nates between 119868119889119897119890 and 119860119888119905119894V119890 locations which represent thetwomodes of processor operation as shown in Figure 4 Twovariables named 119879119900119905119886119897119864119899119890119903119892119910 and 119879 are defined in order


runid=minus1run[runid]reset()

reset()runid==minus1

tt_idfinish[t]

tt_idrelease[t]

Idle

Init

C

C

Initial()

tid=tschEDF(t)ccEDFR(t)

run[runid]reset()

reset()oldid=minus1ampamprunid==oldid

Inserted

oldid==minus1

preempt[oldid]oldid=minus1ampamprunid==tid

C

Cpop()runid=queue[0]

ccEDFF(t)

Figure 3 ccEDF template

empty()

empty()

IdleBIGEXP

ampamp

BIGEXPRun

TotalEnergy998400==(c1[Fre]+c2[Fre]lowastT)lowastvoltages[Fre]

T998400==plowast(c1[Fre]+c2[Fre]lowastT)lowastvoltages[Fre]minusblowastT

voltages[Fre]lowastvoltages[Fre]

voltages[Fre]lowastvoltages[Fre]+(c1[Fre]+c2[Fre]lowastT)lowastvoltages[Fre])minusblowastT

+(c1[Fre]+c2[Fre voltages[Fre]ampamp]lowastlowastT)lowastT998400==plowast(c0lowastvoltages[Fre]lowast

TotalEnergy998400==c0lowastvoltages[Fre]lowast

Figure 4 Processor template

to capture the energy consumption and the instantaneousprocessor temperature respectivelyThe invariants of the twolocations describe the variation of the two variables based onformulas (6) and (7)

442 Battery Modeling The kinetic battery model (KiBaM)[16] has proven to be the best suited model for performancemodeling and cooperate with possible workload model Themodel partitions the battery charge into two wells availablecharge well 119886V119886(119905) and bound charge well 119887119900119906(119905) The totalcapacity 119862 is partitioned into the two wells with a factor of 119888hence initially the charges in the two wells are 119886V119886(0) = 119888lowast119862

and 119887119900119906(0) = (1 minus 119888) lowast 119862 The available charge well providesenergy to the current load 119897(119905) and the bound charge wellprovides electrons to the available charge well The chargeflows from the bound charge well to the available chargewell at a rate proportional to a conduction parameter 119896 andthe height difference between the two wells The battery isconsidered empty when there is no charge left in the availablecharge well that is 119886V119886(119905) = 0 The variation of the chargein both wells is described as a system of ordinary differentialequations

120597119886V119886 (119905)

120597119905= minus 119897 (119905) + 119896 sdot (

119887119900119906 (119905)

1 minus 119888minus

119886V119886 (119905)

119888)

120597119887119900119906 (119905)

120597119905= minus 119896 sdot (

119887119900119906 (119905)

1 minus 119888minus

119886V119886 (119905)

119888)

(8)

On

Off

avalt=0

ava998400==0ampampbou998400==0

ava998400==minus(empty()lowastc0lowast

voltages[Fre]lowastvoltages[Fre]lowastvoltages[Fre]

+klowast(bou(1minusc)minusavcc)ampampbou998400

==minusk (bou(1minusc)minusavac)ampampavagt=0lowast

+(c1[Fre]+c2[Fre]lowastT)lowastvoltages[Fre])

Figure 5 Battery template

The template of the battery mainly consists of twolocations 119874119899 and 119874119891119891 which indicate that the battery isavailable and empty as shown in Figure 5 The invarianton location 119874119899 represents the variation of the charge inboth wells based on formula (8) When there is no chargeleft in the available charge well the template moves to 119874119891119891

location


5 Statistical Queries for Evaluation

In this section we list out the statistical queries of thecorresponding evaluation metric

Seeking the utilization bound of an algorithm 119860 isregarded as a hypothesis problem For a given taskset utiliza-tion 119906 is the probability of the tasksets are not schedulable issmaller than or equal to a threshold 119902 And the verification islimited up to119861 time unitsWe increase 119906 until the query is notsatisfied for the first time and the value of 119906 is the utilizationbound of 119860 The corresponding query for model checking is

119875119903 [lt= 119861] (119890119903119903119900119903) lt= 119902 (9)

If UPPAAL-SMC reports that the query is satisfied thetasksets are deemed schedulable

The key for energy efficiency evaluation is to estimatethe energy consumption under each algorithm within a timebound 119861 The corresponding query is

119875119903 [119879119900119905119886119897119864119899119890119903119892119910 lt= 119872119860119883] (119892119879119894119898119890 gt= 119861ampamp119890119903119903119900119903) (10)

where 119879119900119905119886119897119864119899119890119903119892119910 records the energy consumption 119872119860119883

is a constant larger than the reachable range of the energyconsumption of all runs and 119892119879119894119898119890 is a clock that indicatesthe time since the beginning Thus this query computes theprobability of reaching time beyond 119861 and the system isnot error within a large energy bound One thing shouldbe emphasized here is that 119890119903119903119900119903 is necessary in order toeliminate the impact of unschedulable samples UPPAAL-SMC discards the unschedulable samples and generates moretraces to meet the defined confidence level

Battery awareness is represented by the battery utiliza-tion With a known battery capability the total energydissipated until the battery is empty is required to calculatethe utilization The corresponding query is

119875119903 [119879119900119905119900119886119897119864119899119890119903119892119910 lt= 119872119860119883] (119892119879119894119898119890 gt 0ampamp119886V119886 lt= 0ampamp119890119903119903119900119903) (11)

in which 119886V119886 indicates the charge left in available well and119892119879119894119898119890 gt 0 is used to eliminate the impact of the initial state

The expected value of the maximum processor temper-ature is required for temperature awareness evaluation Thecorresponding query is

119864 [lt= 10000 500] (119898119886119909 119879) (12)

in which 119879 indicates the processor temperature which hasbeen scaled down to the ambient temperature Thus thisquery performs 500 runs and returns the expected value ofthe maximum processor temperature

6 Case Study

In this section in order to illustrate the applicability of ourframework for RT-DVS algorithms evaluation we perform acase study using our framework to evaluate five classical RT-DVS algorithms

Table 1 Parameters for the linearized leakage power

119891119896

V119896

1198621 1198622

10 15 14038 0064108 12 07439 0030806 09 0390 0007704 06 0204 00081

61 Experimental Setting We choose RT-DVS algorithmsproposed in [1] because these algorithms are the most citedones in the literature and they cover all the three types of RT-DVS algorithms as introduced in the previous section

In our experiments tasksets are generated with tasksetsgenerator model and taskset utilization is varied with astep size of 005 within the range of [05 1] The cardinalitynumber and period are 4 and 100 respectively The defaultprocessor characteristics are obtained from [12] whose nor-malized frequencies are varied with a step size of 02 withinthe range of [04 1] the processor specified consent1198620 = 668and parameters for the linearized leakage power are listed inTable 1 and the thermal coefficients 120588 = 00071∘CW and120573 = 00041

The parameters in statistical queries are set as followsthe time bound 119861 = 10000 and the threshold 119902 = 0001The statistical parameters for verification are set as followsthe probability of false negatives 120572 = 0001 the probabilityuncertainty 120576 = 001 and both lower and upper bound ofindifference region 120575 = 0005

62 Utilization Bound Evaluation In these experiments weseek the utilization bound of the RT-DVS algorithms It isshown that all tasksets are schedulable according to EDFbased algorithms if the taskset utilization is not greater than1 And according to both RM based algorithms tasksetsare schedulable if the taskset utilization is 075 but notschedulable if the taskset utilization is 08 In order toget more precise bound we change the step size to 001Finally we observed that according to 119904119905119886119877119872 tasksetsare schedulable if the taskset utilization is 079 but notschedulable if the taskset utilization is 08 and accordingto 119888119888119877119872 tasksets are schedulable if the taskset utilization is078 but not schedulable if the taskset utilization is 079Thusthe utilization bound of 119904119905119886119877119872 and 119888119888119877119872 is 079 and 078respectively

63 Energy Efficiency Evaluation In these experiments weinvestigate the energy efficiency of all RT-DVS algorithmsThe original EDF algorithm is included as a baseline case inevaluation similar to [1] The energy consumption of eachRT-DVS algorithm is normalized with respect to the energyconsumption of the original EDF algorithm

631 Taskset Utilization To investigate the impact of thetaskset utilization on the energy efficiency of RT-DVS algo-rithms experiments with various utilization were performedAnd 119861119862119864119865 is set to 1 so that the tasks do consume their119882119862119864119862 thus staEDF and ccEDF have the same behavior


05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

Figure 6 Utilization impact

02 04 06 08 10

01

02

03

04

05

06

07

BCEF

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(a) Utilization = 05

02 04 06 08 10

02

04

06

08

10

BCEF

Task

set u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDF

(b) Utilization = 07

Figure 7 BCEF impact

As shown in Figure 6 the energy efficiency of all algo-rithms decreases dramatically as the utilization increasesAnd EDF based algorithms are more efficient than RM basedalgorithms One interesting observation is that the curve ofstaEDF is in the likeness of stairs which have salient pointswhen the task utilization is equal to the discrete frequenciesthat is 119906 = 06 and 119906 = 08 This is because of thefact that staEDF uses the taskset utilization to scale theoperating frequency What is more interesting is that at thesalient points staEDF is more efficient than the aggressivealgorithm laEDF This is because laEDF defers works inorder to take advantage of early termination However inthese experiments we assume that all tasks do consume their119882119862119864119862 this requires operating at high frequencies later inorder to meet all the deadlines that may dissipate moreenergy

632 BCEF In this set of experiments we investigate howeach RT-DVS algorithm takes advantage of slack times Wevary the 119861119862119864119865 in range of [01 1] with a step size of 01 andthe taskset utilization is equal to 05 and 07 respectively

As shown in Figure 7 the energy efficiency of staticRT-DVS algorithms is not highly affected by 119861119862119864119865 andfor other algorithms their efficiency decreases as 119861119862119864119865

increases This conforms to the results in [1] that the staticalgorithms do not take advantage of early termination andcycle conserving algorithms and look-ahead algorithmmakeuse of these slacks We must emphasize that the curvesof the algorithms do not indicate the actual energy con-sumption but its ration to the energy consumed by EDFalgorithmTherefore the flat curves do not denote the actualenergy consumption being equal at every point but indicatesthat the actual energy consumption is linearly increased


Cardinality number4 6 8 10 12

02

04

06

08

10

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

Figure 8 Cardinality impact

Table 2 Parameters for the linearized leakage power of processor 2

119891119896

V119896

1198621 1198622

10 110 18497 0214909027 105 14998 0204308797 100 12315 0194208553 095 10238 0184608291 090 86126 0175408010 085 73249 01666

with 119861119862119864119865 and the increase rate is almost equal to EDFalgorithm

633 Cardinality Number In these experiments we inves-tigate the impact of the number of tasks on the energyconsumption Experiments with various numbers of tasksin range of [4 12] with step size of 2 were performedmeanwhile they keep the taskset utilization 119880 = 07 and119861119862119864119865 = 01

As shown in Figure 8 we observed that as the cardinalitynumber increases the normalized energy consumption of allthe algorithms is not highly affected

634 Processor Characteristics In these experiments weinvestigate the impact of varying the processor characteris-tics We obtained other processor characteristics from [13](we named the default processor as processor 1 and thisprocessor as processor 2) where the processor specifiedconsent 1198620 = 15 and parameters for the linearized leakagepower are listed in Table 2 and the thermal coefficients 120588 =

0002941∘CW and 120573 = 0003676 In addition we investigatethe algorithms upon processors with cooling systems coolfan for processor 1 (thus 120573 = 00071) [12] water sprayfor processor 2 (thus 120573 = 0043898) [13] Other systemparameters are set as follows taskset utilization 119880 = 07cardinality number 119899 = 4 and 119861119862119864119865 = 01

As shown in Figure 9 both RM based algorithms havea better performance upon processor 2 this is because theleakage power accounts for a larger proportion of the totalpower This conforms to the results in [1] that RM basedalgorithms have better performance as the idle level energyconsumption increases For EDF based algorithms whenthe taskset utilization is smaller than the lowest frequencyavailable in processor 2 that is 119891 = 0801 there is nodifference among these algorithms and they have worseperformance upon processor 2 it is clear that this is becauseof the lowest available frequency limitation However whenthe taskset utilization is bigger than the lowest frequencyall algorithms have better performance upon processor 2thus the curves grow much gently This is because morefrequencies are available so that the algorithms can selectthe most suitable operating frequency that results in betterenergy efficiency

In addition it is shown that although cooling systemshighly decrease actual energy consumption the normalizedenergy is not highly affectedThis is because all the algorithmsin our case study focus on dynamic power reducing they donot take any advantage of the static power reducing derivedfrom cooling systems

64 Battery Awareness Evaluation In these experiments weinvestigate how each RT-DVS algorithm takes advantage ofthe capacity of battery The parameters of the battery are asfollows the total capacity 119862 = 60000 the factor 119888 = 106and the conduction parameter 119896 = 2324 times 10minus4119904minus1 similarto the ones used in [19] All the results are normalized withrespect to the total capacity of the battery so that the batteryutilization can be obtained

As shown in Figure 10 the utilization of battery decreasesas the taskset utilization increases This is because as thetaskset utilization increases less time is left for the battery torecover charges from bound well this is also the reason whyvarious RT-DVS algorithms utilize different percent of thetotal battery capacity It can be observed that the utilizationof the battery under look-ahead RT-DVS algorithm (93of the total energy) is over twice as that under originalEDF algorithm (42 of the total energy) when the tasksetutilization is low

65 Temperature Awareness Evaluation In these experi-ments we investigate the expected value of the maximumprocessor temperature at every taskset utilization level undereach RT-DVS algorithm

As shown in Figure 11 the maximum processor tempera-ture grows rapidly as the utilization increases and the growthrate is almost proportional to the energy efficiency of thecorresponding algorithm

66 Summary We have evaluated how each parameter forexample the taskset attributes and the processor characteris-tics impacts the energy efficiency of the RT-DVS algorithmsIn the sequel evaluation of other metrics is also performedOur experiments have shown that the most impact param-eters on the energy efficiency of RT-DVS algorithms are


05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(a) Processor 1 120573 = 041

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(b) Processor 2 120573 = 0003676

05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(c) Processor 1 120573 = 071

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(d) Processor 2 120573 = 0043898Figure 9 Processor impact

05 06 07 08 09 10

04

05

03

06

07

08

09

10

Taskset utilization

Batte

ry u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDFEDF

Figure 10 Battery awareness

05 06 07 08 09 10

10

20

30

40

50

Taskset utilization

Tem

pera

ture

staEDFstaRMccEDF

ccRMlaEDFEDF

Figure 11 Temperature awareness


the taskset utilization and processor characteristics espe-cially the lowest available frequency and the density of thefrequencies Moreover we observed that the battery aware-ness and temperature awareness are almost proportional tothe energy efficiency

The conclusions obtained in these experiments have beenpartly observed by simulation based approaches Thus theseexperiments demonstrated the correctness of our approachFurthermore we obtained correct results while consideringthe impact of processor temperature

7 Related Work

Shin et al [6] have proposed a simulator for performancecompression of DVS algorithms called SimDVS In additionthey have performed three case studies to demonstrate theeffectiveness of the simulator including performance evalu-ation of InterDVS IntraDVS and HybridDVS algorithms aswell as overhead measurement of InterDVS algorithms thatis the more efficient DVS algorithmsmay suffer more systemoverhead

Kim et al [5] have compared several DVS algorithmsfor hard real time periodic tasks Their experiments wereperformed using a simulator environment called SimDVS[6] They have evaluated the impact of several parametersfor example number of tasks utilization scaling levels andspeed bound on the energy efficiency of the DVS algorithmsThey conclude that the existing EDF based DVS algorithmsare close to optimal bound andmore research should be donefor better RM based DVS algorithms

Saha and Ravindran [20] have implemented fourteenDVS algorithms in the ChronOS real time Linux kernel andevaluated their energy efficiency on two hardware platformsincluding an Intel i5 processor and anAMDZacate processorWorkload is generated with a synthetic application andmeasures the energy consumption by accounting for energyconsumption in the active and idle states and the systemenergy using a multimeter They concluded that energyefficiency ofDVS algorithms highly depends on the processorcharacteristics that is the relative power of the active and theidle states and the number of frequency steps available

Lin et al [8] have designed a framework includinghardware settings and software implementation to evaluatepower aware scheduling algorithms on Intel PXA255 XScaleprocessor namely real energy In addition this frameworkwas also used for testing the implementation of DVS algo-rithmsThey have evaluated several classical DVS algorithmsand concluded that these algorithms are effective for reduc-ing the processors energy consumption however they alsoconcluded that these algorithms do not effectively reduce thesystems energy consumption

Grosu et al [21] have explored the usability of statisticalmodel checking for measuring quantitative properties ofsystems A specification formalism for measurement compu-tation is proposed in which a set of measurement variablesare associated with each state in the state space In the sequelthey developed a Monte Carlo technique for generatinga suitable set of samples in order to satisfy the desiredconfidence bound Finally they illustrated their method

for measuring the aggregate behavior of flock of bird-likeagents

Zhang et al [22] have presented a formal frameworkfor symbolic analysis of programmable logic controllers(PLC) systems The framework provides automatic analysisof reliability calculations and performance measurementsThey translate the embedded control program into a logicexpression and embedded the hardware uncertainty intothe expression so that the reliability of the system can beobtained The PLC system is abstracted as Hidden MarkovModel and it is combined with the reliability of system toform a regular Markov Model Finally the performancemeasurement is obtained with probabilistic model checkingtools

David et al [23] have presented a process that combinescontrol synthesis model checking and statistical modelchecking in order to examine the consequences of adoptingthe control strategy Strategy is synthesized for a timed gameand a given control objective with control synthesis tech-niques Then model checking is employed to verify correct-ness properties of the timed game under the synthesizedstrategy Lastly statistical model checking is applied to evalu-ate the performance aspects of the synthesized strategy

David et al [24] have presented a study of statisticalmodel checking for analyzing performance properties ofenergy aware building A framework for modeling and an-alysing energy aware building is presented which allowsevaluating the performance of the control strategies Comforttime and energy consumption are obtained under variousenvironmental settings The framework has been applied tothe Hybrid Systems Verification Benchmark

8 Conclusion

We have shown that statistical model checking supportsautomatic evaluation of RT-DVS algorithms In contrast tosimulation based evaluation the approach proposed in thispaper inherit the advantages of the statisticalmodel checkingIt performs a reliable result with respect to a user-definedconfidence level Moreover it automatically generates thetasksets and eliminates the impact of the unschedulable sam-ples In addition the framework proposed in this paper canbe used for verification of the algorithms We are presentlyextending this work by adding more RT-DVS algorithmsbattery aware algorithms and temperature aware algorithmsinto this framework meanwhile capturing more processorconfigurations

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

Acknowledgments

This work was supported in part by the State Key Program ofNational Natural Science Foundation of China under Grantno 61332001 the National Natural Science Foundation ofChina under Grant no 61272104 and the Basic Research forApplication Foundation of Sichuan Province no 2014JY0112


References

[1] P Pillai and K G Shin ldquoReal-time dynamic voltage scalingfor low-power embedded operating systemsrdquo ACM SIGOPSOperating Systems Review vol 35 no 5 pp 89ndash102 2001

[2] H Aydin R Melhem D Mosse and P Mejia-Alvarez ldquoPower-aware scheduling for periodic real-time tasksrdquo IEEE Transac-tions on Computers vol 53 no 5 pp 584ndash600 2004

[3] N Bansal T Kimbrel and K Pruhs ldquoSpeed scaling to manageenergy and temperaturerdquo Journal of the ACM vol 54 no 1Article ID 1206038 p 39 2007

[4] S Zhuravlev J C Saez S Blagodurov A Fedorova and MPrieto ldquoSurvey of energy-cognizant scheduling techniquesrdquoIEEE Transactions on Parallel and Distributed Systems vol 24no 7 pp 1447ndash1464 2013

[5] W Kim D Shin H-S Yun J Kim and S LMin ldquoPerformancecomparison of dynamic voltage scaling algorithms for hard real-time systemsrdquo in Proceedings of the 8th IEEE Real-Time andEmbedded Technology and Applications Symposium (RTAS rsquo02)pp 219ndash228 IEEE September 2002

[6] D K Shin W Kim J Jeon J Kim and S L Min ldquoSimDVS anintegrated simulation environment for performance evaluationof dynamic voltage scaling algorithmsrdquo in Power-Aware Com-puter Systems vol 2325 of Lecture Notes in Computer Sciencepp 141ndash156 Springer Berlin Germany 2003

[7] J Lin W Song and A K Cheng ldquoReal-energy a new frame-work and a case study to evaluate power-aware real-timescheduling algorithmsrdquo in Proceedings of the ACMIEEE Inter-national Symposium on Low-Power Electronics and Design(ISLPED rsquo10) pp 153ndash158 IEEE Austin Tex USA August 2010

[8] J D Lin A M K Cheng andW Song ldquoA practical frameworkto study low-power scheduling algorithms on real-time andembedded systemsrdquo Journal of Low Power Electronics andApplications vol 4 no 2 pp 90ndash109 2014

[9] A Legay B Delahaye and S Bensalem ldquoStatistical modelchecking an overviewrdquo in Runtime Verification H Barringer YFalcone B Finkbeiner et al Eds Lecture Notes in ComputerScience pp 122ndash135 Springer 2010

[10] A David K G Larsen A Legay M Mikucionis and D BPoulsen ldquoUppaal SMC tutorialrdquo International Journal on Soft-ware Tools for Technology Transfer vol 17 no 4 pp 397ndash4152015

[11] W P Liao L He and K M Lepak ldquoTemperature and supplyvoltage aware performance and power modeling at microarchi-tecture levelrdquo IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems vol 24 no 7 pp 1042ndash10532005

[12] M Mohaqeqi M Kargahi and A Movaghar ldquoAnalyticalleakage-aware thermal modeling of a real-time systemrdquo IEEETransactions on Computers vol 63 no 6 pp 1377ndash1391 2014

[13] G Quan and V Chaturvedi ldquoFeasibility analysis for temper-ature-constraint hard real-time periodic tasksrdquo IEEE Transac-tions on Industrial Informatics vol 6 no 3 pp 329ndash339 2010

[14] M Kwiatkowska ldquoFrom software verification to everywareverificationrdquo Computer SciencemdashResearch and Developmentvol 28 no 4 pp 295ndash310 2013

[15] E Clarke and P Zuliani ldquoStatistical model checking for cyber-physical systemsrdquo in Automated Technology for Verification andAnalysis T Bultan and P-A Hsiung Eds vol 6996 of LectureNotes in Computer Science pp 1ndash12 Springer Berlin Germany2011

[16] M R Jongerden and B R Haverkort ldquoWhich battery model touserdquo IET Software vol 3 no 6 pp 445ndash457 2009

[17] R I Davis and A Burns ldquoA survey of hard real-time schedulingfor multiprocessor systemsrdquo ACM Computing Surveys vol 43no 4 article 35 2011

[18] E Bini and G C Buttazzo ldquoMeasuring the performance ofschedulability testsrdquo Real-Time Systems vol 30 no 1-2 pp 129ndash154 2005

[19] E R Wognsen R R Hansen and K G Larsen ldquoBattery-aware scheduling of mixed criticality systemsrdquo in LeveragingApplications of Formal Methods Verification and ValidationSpecialized Techniques and Applications T Margaria and BSteffen Eds vol 8803 of Lecture Notes in Computer Science pp208ndash222 Springer Berlin Germany 2014

[20] S Saha and B Ravindran ldquoAn experimental evaluation of real-time DVFS scheduling algorithmsrdquo in Proceedings of the 5thAnnual International Systems and Storage Conference (SYSTORrsquo12) pp 1ndash12 ACM Haifa Israel June 2012

[21] R Grosu D Peled C R Ramakrishnan S Smolka S Stollerand J Yang ldquoUsing statistical model checking for measuringsystemsrdquo in Leveraging Applications of Formal Methods Verifi-cation and Validation Specialized Techniques and ApplicationsT Margaria and B Steffen Eds vol 8803 of Lecture Notesin Computer Science pp 223ndash238 Springer Berlin Germany2014

[22] H H Zhang Y Jiang W N Hung X Song M Gu and J SunldquoSymbolic analysis of programmable logic controllersrdquo IEEETransactions on Computers vol 63 no 10 pp 2563ndash2575 2014

[23] ADavidH Fang KG Larsen andZ Zhang ldquoVerification andperformance evaluation of timed game strategiesrdquo in FormalModeling and Analysis of Timed Systems Proceedings of the 12thInternational Conference (FORMATS rsquo14) vol 8711 of LectureNotes in Computer Science pp 100ndash114 Springer 2014

[24] A David D Du K G Larsen M Mikucionis and A SkouldquoAn evaluation framework for energy aware buildings usingstatistical model checkingrdquo Science China Information Sciencesvol 55 no 12 pp 2694ndash2707 2012

Submit your manuscripts athttpwwwhindawicom

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MathematicsJournal of


Mathematical Problems in Engineering

Hindawi Publishing Corporationhttpwwwhindawicom

Differential EquationsInternational Journal of

Volume 2014

Applied MathematicsJournal of


Probability and StatisticsHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

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OptimizationJournal of


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International Journal of


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Function Spaces

Abstract and Applied AnalysisHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of Mathematics and Mathematical Sciences


The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014


Algebra

Discrete Dynamics in Nature and Society



Decision SciencesAdvances in

Discrete MathematicsJournal of


Volume 2014 Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Stochastic AnalysisInternational Journal of


RT-DVS algorithms evaluation In the sequel a case studyis conducted in order to demonstrate the applicability of ourframework

To the best of our knowledge this is the first researcheffort that proposes evaluating RT-DVS algorithms using sta-tistical model checking Our conclusions are partly observedby the simulation based approaches However we obtainthese conclusions in a more automatic and reliable mannerWhat is more we consider the impact of temperature onthe energy efficiency of RT-DVS algorithms In addition itshould be emphasized that our approach is not limited tothe algorithms described in this paper but all the dynamicvoltage scaling algorithms can be modeled and then evalu-ated with our framework Furthermore although multicoresystems are increasingly used single core systems are stillof interest since the approaches can be applied to multicoresystems with some modification

The rest of the paper is structured as follows Section 2introduces the fundamental theories of RT-DVS algo-rithms Section 3 introduces statistical model checking basedapproach for RT-DVS algorithms evaluation Section 4describes the system model in detail Section 5 describes thestatistical queries for evaluation Section 6 presents a casestudy to evaluate five classical RT-DVS algorithms Section 7gives an overview of the related work Finally Section 8concludes the paper

2 Power Consumption andRT-DVS Algorithms

This section introduces some fundamental theories of RT-DVS algorithms which are the foundation of the modelspresented later

21 Processor Power Distribution The power consumptionof the processor can be divided into three componentsdynamic static and short circuit power [4] Short circuitpower is comparatively insignificant to dynamic and staticpower thus it is negligible [4] so we do not discuss it in thispaper

A DVS enabled processor has a discrete set of oper-ating frequencies 119865 = 119891

1 1198912 119891

119899 and each clock

frequency is associated with a supply voltage level in set119881 = V

1 V2 V

119899 Meanwhile processor has two modes

of operation (1) idle mode when it does not have any jobin the system and thus dissipates only static power and (2)

active mode when the processor executes some jobs in thesystem and dissipates both dynamic power and static power[11] For many years dynamic power dissipation was thedominant factor in total power consumption which can beapproximated with the following formula

119875dyn = 119862119897sdot 119873sw sdot 119881

2119889119889

sdot 119891 (1)

where 119862119897is the load capacitance 119873sw is the average number

of circuit switches per clock 119881119889119889

is the supply voltage and 119891

is the operating frequency The operating frequency almostlinearly depends on the supply voltage [4]

119891 = 119896 sdot(119881119889119889

minus 119881119905)2

119881119889119889

(2)

where 119896 is a constant and 119881119905is the threshold voltage By

substituting (2) in (1) the dynamic power at supply voltageV119896will be formulated as [12]

119875dyn (V119896) = 1198620 sdot V3119896 (3)

where 1198620 is a processor specific constants and V119896isin 119881 is 119896th

voltage levelStatic power or leakage power increases its dominance

of total power consumption in recent years which can beformulated as [11]

119875sta = 119873gate sdot 119868leak sdot 119881119889119889 (4)

where119873gate represents the number of gates 119868leak is the leakagecurrent and 119868leak has a nonlinear exponential relationshipwith both temperature and supply voltage Fortunately it hasbeen shown in [13] that the static power can be approxima-tively calculated with

119875sta (V119896) = (1198621 (119896) +1198622 (119896) sdot 119879) sdot V119896 (5)

where 1198621(119896) and 1198622(119896) are some processor specific voltagesensitive constants and 119879 is the processor temperature Asreported in [13] using (5) can accurately estimate the staticpower with relative error less than 13

In general the total power of the processor at activemodelis formulated as

Pow (V119896) = 1198620 sdot V

3119896+ (1198621 (119896) +1198622 (119896) sdot 119879) sdot V

119896 (6)

Lastly we discuss the processor temperature in detail Weadopt the well-known lumped RC model [12] to describe thetransient behavior of the processor temperature as

120597119879 (119905)

120597119905= 120588 sdotPow (119905) minus 120573 sdot 119879 (119905) (7)

where 120588 and 120573 are processor specific thermal coefficientsand Pow(119905) and 119879(119905) are the instantaneous power and tem-perature respectively Without loss of generality we havescaled the temperature such that the ambient temperatureis considered zero Otherwise an offset equals the ambienttemperature which is substituted in (7)

22 RT-DVS Algorithms RT-DVS algorithms exploit twotypes of slack time [3] (1) static slack when the totalutilization is less than 1 there exists time interval that canbe used for voltage scaling and (2) dynamic slack when theactual execution time of the task is smaller than itsWCET atime interval is generated to further reduce the supply voltageRT-DVS algorithms differ in the way they estimate and utilize


RT-DVSalgorithms

models

Tasksetsgenerator

model

Platformmodel

UPPAAL-SMC

Statisticalqueries

Probabilityinterval



Batteryawareness












1](1205931) gt= 119875119903[119887119900119906119899119889

2](1205932)




















1 1205912 120591

119899











119899

119894=1 119880119894 = 119906 where 119880119894=




Initial

C



error=true

Error




preempt[tid]



Run

finish[tid]

Finish



time[tid]=0exec=0
























tt_idfinish[t]

tt_idrelease[t]

Idle

Init

C

C

Initial()


run[runid]reset()


Inserted

oldid==minus1


C


ccEDFF(t)


empty()

empty()

IdleBIGEXP

ampamp

BIGEXPRun











120597119886V119886 (119905)

120597119905= minus 119897 (119905) + 119896 sdot (

119887119900119906 (119905)

1 minus 119888minus

119886V119886 (119905)

119888)

120597119887119900119906 (119905)

120597119905= minus 119896 sdot (

119887119900119906 (119905)

1 minus 119888minus

119886V119886 (119905)

119888)

(8)

On

Off

avalt=0









location





119875119903 [lt= 119861] (119890119903119903119900119903) lt= 119902 (9)



119875119903 [119879119900119905119886119897119864119899119890119903119892119910 lt= 119872119860119883] (119892119879119894119898119890 gt= 119861ampamp119890119903119903119900119903) (10)







119864 [lt= 10000 500] (119898119886119909 119879) (12)


6 Case Study



119891119896

V119896

1198621 1198622

10 15 14038 0064108 12 07439 0030806 09 0390 0007704 06 0204 00081








05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


02 04 06 08 10

01

02

03

04

05

06

07

BCEF

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


02 04 06 08 10

02

04

06

08

10

BCEF

Task

set u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDF









02

04

06

08

10

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF



119891119896

V119896

1198621 1198622

10 110 18497 0214909027 105 14998 0204308797 100 12315 0194208553 095 10238 0184608291 090 86126 0175408010 085 73249 01666














05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(a) Processor 1 120573 = 041

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(b) Processor 2 120573 = 0003676

05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(c) Processor 1 120573 = 071

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


05 06 07 08 09 10

04

05

03

06

07

08

09

10

Taskset utilization

Batte

ry u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDFEDF


05 06 07 08 09 10

10

20

30

40

50

Taskset utilization

Tem

pera

ture

staEDFstaRMccEDF

ccRMlaEDFEDF





7 Related Work










8 Conclusion




Acknowledgments



References
































Volume 2014




Journal of











Journal of


Function Spaces






Algebra










RT-DVSalgorithms

models

Tasksetsgenerator

model

Platformmodel

UPPAAL-SMC

Statisticalqueries

Probabilityinterval



Batteryawareness












1](1205931) gt= 119875119903[119887119900119906119899119889

2](1205932)




















1 1205912 120591

119899











119899

119894=1 119880119894 = 119906 where 119880119894=




Initial

C



error=true

Error




preempt[tid]



Run

finish[tid]

Finish



time[tid]=0exec=0
























tt_idfinish[t]

tt_idrelease[t]

Idle

Init

C

C

Initial()


run[runid]reset()


Inserted

oldid==minus1


C


ccEDFF(t)


empty()

empty()

IdleBIGEXP

ampamp

BIGEXPRun











120597119886V119886 (119905)

120597119905= minus 119897 (119905) + 119896 sdot (

119887119900119906 (119905)

1 minus 119888minus

119886V119886 (119905)

119888)

120597119887119900119906 (119905)

120597119905= minus 119896 sdot (

119887119900119906 (119905)

1 minus 119888minus

119886V119886 (119905)

119888)

(8)

On

Off

avalt=0









location





119875119903 [lt= 119861] (119890119903119903119900119903) lt= 119902 (9)



119875119903 [119879119900119905119886119897119864119899119890119903119892119910 lt= 119872119860119883] (119892119879119894119898119890 gt= 119861ampamp119890119903119903119900119903) (10)







119864 [lt= 10000 500] (119898119886119909 119879) (12)


6 Case Study



119891119896

V119896

1198621 1198622

10 15 14038 0064108 12 07439 0030806 09 0390 0007704 06 0204 00081








05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


02 04 06 08 10

01

02

03

04

05

06

07

BCEF

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


02 04 06 08 10

02

04

06

08

10

BCEF

Task

set u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDF









02

04

06

08

10

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF



119891119896

V119896

1198621 1198622

10 110 18497 0214909027 105 14998 0204308797 100 12315 0194208553 095 10238 0184608291 090 86126 0175408010 085 73249 01666














05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(a) Processor 1 120573 = 041

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(b) Processor 2 120573 = 0003676

05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(c) Processor 1 120573 = 071

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


05 06 07 08 09 10

04

05

03

06

07

08

09

10

Taskset utilization

Batte

ry u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDFEDF


05 06 07 08 09 10

10

20

30

40

50

Taskset utilization

Tem

pera

ture

staEDFstaRMccEDF

ccRMlaEDFEDF





7 Related Work










8 Conclusion




Acknowledgments



References
































Volume 2014




Journal of











Journal of


Function Spaces






Algebra























1 1205912 120591

119899











119899

119894=1 119880119894 = 119906 where 119880119894=




Initial

C



error=true

Error




preempt[tid]



Run

finish[tid]

Finish



time[tid]=0exec=0
























tt_idfinish[t]

tt_idrelease[t]

Idle

Init

C

C

Initial()


run[runid]reset()


Inserted

oldid==minus1


C


ccEDFF(t)


empty()

empty()

IdleBIGEXP

ampamp

BIGEXPRun











120597119886V119886 (119905)

120597119905= minus 119897 (119905) + 119896 sdot (

119887119900119906 (119905)

1 minus 119888minus

119886V119886 (119905)

119888)

120597119887119900119906 (119905)

120597119905= minus 119896 sdot (

119887119900119906 (119905)

1 minus 119888minus

119886V119886 (119905)

119888)

(8)

On

Off

avalt=0









location





119875119903 [lt= 119861] (119890119903119903119900119903) lt= 119902 (9)



119875119903 [119879119900119905119886119897119864119899119890119903119892119910 lt= 119872119860119883] (119892119879119894119898119890 gt= 119861ampamp119890119903119903119900119903) (10)







119864 [lt= 10000 500] (119898119886119909 119879) (12)


6 Case Study



119891119896

V119896

1198621 1198622

10 15 14038 0064108 12 07439 0030806 09 0390 0007704 06 0204 00081








05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


02 04 06 08 10

01

02

03

04

05

06

07

BCEF

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


02 04 06 08 10

02

04

06

08

10

BCEF

Task

set u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDF









02

04

06

08

10

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF



119891119896

V119896

1198621 1198622

10 110 18497 0214909027 105 14998 0204308797 100 12315 0194208553 095 10238 0184608291 090 86126 0175408010 085 73249 01666














05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(a) Processor 1 120573 = 041

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(b) Processor 2 120573 = 0003676

05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(c) Processor 1 120573 = 071

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


05 06 07 08 09 10

04

05

03

06

07

08

09

10

Taskset utilization

Batte

ry u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDFEDF


05 06 07 08 09 10

10

20

30

40

50

Taskset utilization

Tem

pera

ture

staEDFstaRMccEDF

ccRMlaEDFEDF





7 Related Work










8 Conclusion




Acknowledgments



References
































Volume 2014




Journal of











Journal of


Function Spaces






Algebra










Initial

C



error=true

Error




preempt[tid]



Run

finish[tid]

Finish



time[tid]=0exec=0
























tt_idfinish[t]

tt_idrelease[t]

Idle

Init

C

C

Initial()


run[runid]reset()


Inserted

oldid==minus1


C


ccEDFF(t)


empty()

empty()

IdleBIGEXP

ampamp

BIGEXPRun











120597119886V119886 (119905)

120597119905= minus 119897 (119905) + 119896 sdot (

119887119900119906 (119905)

1 minus 119888minus

119886V119886 (119905)

119888)

120597119887119900119906 (119905)

120597119905= minus 119896 sdot (

119887119900119906 (119905)

1 minus 119888minus

119886V119886 (119905)

119888)

(8)

On

Off

avalt=0









location





119875119903 [lt= 119861] (119890119903119903119900119903) lt= 119902 (9)



119875119903 [119879119900119905119886119897119864119899119890119903119892119910 lt= 119872119860119883] (119892119879119894119898119890 gt= 119861ampamp119890119903119903119900119903) (10)







119864 [lt= 10000 500] (119898119886119909 119879) (12)


6 Case Study



119891119896

V119896

1198621 1198622

10 15 14038 0064108 12 07439 0030806 09 0390 0007704 06 0204 00081








05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


02 04 06 08 10

01

02

03

04

05

06

07

BCEF

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


02 04 06 08 10

02

04

06

08

10

BCEF

Task

set u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDF









02

04

06

08

10

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF



119891119896

V119896

1198621 1198622

10 110 18497 0214909027 105 14998 0204308797 100 12315 0194208553 095 10238 0184608291 090 86126 0175408010 085 73249 01666














05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(a) Processor 1 120573 = 041

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(b) Processor 2 120573 = 0003676

05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(c) Processor 1 120573 = 071

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


05 06 07 08 09 10

04

05

03

06

07

08

09

10

Taskset utilization

Batte

ry u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDFEDF


05 06 07 08 09 10

10

20

30

40

50

Taskset utilization

Tem

pera

ture

staEDFstaRMccEDF

ccRMlaEDFEDF





7 Related Work










8 Conclusion




Acknowledgments



References
































Volume 2014




Journal of











Journal of


Function Spaces






Algebra












tt_idfinish[t]

tt_idrelease[t]

Idle

Init

C

C

Initial()


run[runid]reset()


Inserted

oldid==minus1


C


ccEDFF(t)


empty()

empty()

IdleBIGEXP

ampamp

BIGEXPRun











120597119886V119886 (119905)

120597119905= minus 119897 (119905) + 119896 sdot (

119887119900119906 (119905)

1 minus 119888minus

119886V119886 (119905)

119888)

120597119887119900119906 (119905)

120597119905= minus 119896 sdot (

119887119900119906 (119905)

1 minus 119888minus

119886V119886 (119905)

119888)

(8)

On

Off

avalt=0









location





119875119903 [lt= 119861] (119890119903119903119900119903) lt= 119902 (9)



119875119903 [119879119900119905119886119897119864119899119890119903119892119910 lt= 119872119860119883] (119892119879119894119898119890 gt= 119861ampamp119890119903119903119900119903) (10)







119864 [lt= 10000 500] (119898119886119909 119879) (12)


6 Case Study



119891119896

V119896

1198621 1198622

10 15 14038 0064108 12 07439 0030806 09 0390 0007704 06 0204 00081








05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


02 04 06 08 10

01

02

03

04

05

06

07

BCEF

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


02 04 06 08 10

02

04

06

08

10

BCEF

Task

set u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDF









02

04

06

08

10

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF



119891119896

V119896

1198621 1198622

10 110 18497 0214909027 105 14998 0204308797 100 12315 0194208553 095 10238 0184608291 090 86126 0175408010 085 73249 01666














05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(a) Processor 1 120573 = 041

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(b) Processor 2 120573 = 0003676

05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(c) Processor 1 120573 = 071

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


05 06 07 08 09 10

04

05

03

06

07

08

09

10

Taskset utilization

Batte

ry u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDFEDF


05 06 07 08 09 10

10

20

30

40

50

Taskset utilization

Tem

pera

ture

staEDFstaRMccEDF

ccRMlaEDFEDF





7 Related Work










8 Conclusion




Acknowledgments



References
































Volume 2014




Journal of











Journal of


Function Spaces






Algebra













119875119903 [lt= 119861] (119890119903119903119900119903) lt= 119902 (9)



119875119903 [119879119900119905119886119897119864119899119890119903119892119910 lt= 119872119860119883] (119892119879119894119898119890 gt= 119861ampamp119890119903119903119900119903) (10)







119864 [lt= 10000 500] (119898119886119909 119879) (12)


6 Case Study



119891119896

V119896

1198621 1198622

10 15 14038 0064108 12 07439 0030806 09 0390 0007704 06 0204 00081








05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


02 04 06 08 10

01

02

03

04

05

06

07

BCEF

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


02 04 06 08 10

02

04

06

08

10

BCEF

Task

set u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDF









02

04

06

08

10

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF



119891119896

V119896

1198621 1198622

10 110 18497 0214909027 105 14998 0204308797 100 12315 0194208553 095 10238 0184608291 090 86126 0175408010 085 73249 01666














05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(a) Processor 1 120573 = 041

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(b) Processor 2 120573 = 0003676

05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(c) Processor 1 120573 = 071

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


05 06 07 08 09 10

04

05

03

06

07

08

09

10

Taskset utilization

Batte

ry u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDFEDF


05 06 07 08 09 10

10

20

30

40

50

Taskset utilization

Tem

pera

ture

staEDFstaRMccEDF

ccRMlaEDFEDF





7 Related Work










8 Conclusion




Acknowledgments



References
































Volume 2014




Journal of











Journal of


Function Spaces






Algebra










05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


02 04 06 08 10

01

02

03

04

05

06

07

BCEF

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


02 04 06 08 10

02

04

06

08

10

BCEF

Task

set u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDF









02

04

06

08

10

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF



119891119896

V119896

1198621 1198622

10 110 18497 0214909027 105 14998 0204308797 100 12315 0194208553 095 10238 0184608291 090 86126 0175408010 085 73249 01666














05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(a) Processor 1 120573 = 041

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(b) Processor 2 120573 = 0003676

05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(c) Processor 1 120573 = 071

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


05 06 07 08 09 10

04

05

03

06

07

08

09

10

Taskset utilization

Batte

ry u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDFEDF


05 06 07 08 09 10

10

20

30

40

50

Taskset utilization

Tem

pera

ture

staEDFstaRMccEDF

ccRMlaEDFEDF





7 Related Work










8 Conclusion




Acknowledgments



References
































Volume 2014




Journal of











Journal of


Function Spaces






Algebra











02

04

06

08

10

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF



119891119896

V119896

1198621 1198622

10 110 18497 0214909027 105 14998 0204308797 100 12315 0194208553 095 10238 0184608291 090 86126 0175408010 085 73249 01666














05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(a) Processor 1 120573 = 041

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(b) Processor 2 120573 = 0003676

05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(c) Processor 1 120573 = 071

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


05 06 07 08 09 10

04

05

03

06

07

08

09

10

Taskset utilization

Batte

ry u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDFEDF


05 06 07 08 09 10

10

20

30

40

50

Taskset utilization

Tem

pera

ture

staEDFstaRMccEDF

ccRMlaEDFEDF





7 Related Work










8 Conclusion




Acknowledgments



References
































Volume 2014




Journal of











Journal of


Function Spaces






Algebra










05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(a) Processor 1 120573 = 041

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(b) Processor 2 120573 = 0003676

05 06 07 08 09 10

02

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF

(c) Processor 1 120573 = 071

05 06 07 08 09 10

04

06

08

10

Taskset utilization

Nor

mal

ized

ener

gy

staEDFstaRMccEDF

ccRMlaEDF


05 06 07 08 09 10

04

05

03

06

07

08

09

10

Taskset utilization

Batte

ry u

tiliz

atio

n

staEDFstaRMccEDF

ccRMlaEDFEDF


05 06 07 08 09 10

10

20

30

40

50

Taskset utilization

Tem

pera

ture

staEDFstaRMccEDF

ccRMlaEDFEDF





7 Related Work










8 Conclusion




Acknowledgments



References
































Volume 2014




Journal of











Journal of


Function Spaces






Algebra












7 Related Work










8 Conclusion




Acknowledgments



References
































Volume 2014




Journal of











Journal of


Function Spaces






Algebra










References
































Volume 2014




Journal of











Journal of


Function Spaces






Algebra
















Volume 2014




Journal of











Journal of


Function Spaces






Algebra









Documents

Research Article A Formal Approach for RT-DVS …downloads.hindawi.com/journals/mpe/2015/815230.pdfMathematicalProblems in Engineering to the analytical models proposed in existing