16
Research Article FPGA-Based Implementation of All-Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator Kaiyu Wang, Zhiming Song, Xianwei Qi, Qingxin Yan, and Zhenan Tang Dalian Institute of Semiconductor Technology and School of Electronic Science and Technology, Dalian University of Technology, Dalian 116023, China Correspondence should be addressed to Zhenan Tang; [email protected] Received 27 June 2014; Revised 3 August 2014; Accepted 6 August 2014; Published 31 August 2014 Academic Editor: Nadia Nedjah Copyright © 2014 Kaiyu Wang et al. is is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. is paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shiſt keying (QPSK). e ADCRL combines classic closed-loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum likelihood frequency estimator (MLFE) so as to make the best use of the advantages of the two types of carrier recovery loops and obtain a more robust performance in the procedure of carrier recovery. Besides, considering that, for MLFE, the accurate estimation of frequency offset is associated with the linear characteristic of its frequency discriminator (FD), the Coordinate Rotation Digital Computer (CORDIC) algorithm is introduced into the FD based on MLFE to unwrap linearly phase difference. e frequency offset contained within the phase difference unwrapped is estimated by the MLFE implemented just using some shiſter and multiply- accumulate units to assist the ADCOL to lock quickly and precisely. e joint simulation results of ModelSim and MATLAB show that the performances of the proposed ADCRL in locked-in time and range are superior to those of the ADCOL. On the other hand, a systematic design procedure based on FPGA for the proposed ADCRL is also presented. 1. Introduction Along with the continuous development of the technologies of field programmable logic gate array (FPGA) and digital signal processing, the FPGAs in possession of large capacity and low power dissipation make it possible to realize a true soſtware defined radio and integrate a whole digital commu- nication system into the chips in order to reconfigure flex- ibly the continuously evolving communication protocols and minimize the volume of spacecraſt. A typical example applying the soſtware defined radio (SDR) based on FPGA to deep space communication is the National Aeronautic and Space Administration (NASA) Electra radio, in which the baseband processing is entirely implemented in a FPGA. Virtually any channel code, modulation, and data rate may be accommodated via suitable reprogramming of this SDR [1]. In communication system, the style of modulation and demodulation plays an important role and directly influences the performance of the system. However, in deep space com- munication, both power efficiency and bandwidth efficiency of a communication system should be simultaneously consid- ered. erefore, the modulation and demodulation method of QPSK have been widely used into deep space communica- tion. With respect to QPSK demodulator, there are two differ- ent solutions to demodulate. ey are noncoherent demod- ulation and coherent demodulation, respectively. Compared with noncoherent demodulation, coherent demodulation can be implemented in a simpler structure so as to save the logic resources of FPGA. Hence, this paper takes the QPSK coherent demodulator as the object of our study. In QPSK coherent demodulator, a special phase-locked loop (PLL), namely, Costas loop, is used to synchronize the locally generated carrier with the carrier contained in the received input buried by external noise. It is well known that the PLL has an outstanding ability to restrain noise as a result of its narrow-band characteristic. erefore, it can precisely realize carrier tracking. Nonetheless, in the design procedure of the PLL, the pair of contradictions between lock-in frequency range and tracking precision is always difficult to reconcile. In particular, in deep space Hindawi Publishing Corporation International Journal of Reconfigurable Computing Volume 2014, Article ID 502942, 15 pages http://dx.doi.org/10.1155/2014/502942

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Research ArticleFPGA-Based Implementation of All-Digital QPSKCarrier Recovery Loop Combining Costas Loop andMaximum Likelihood Frequency Estimator

Kaiyu Wang Zhiming Song Xianwei Qi Qingxin Yan and Zhenan Tang

Dalian Institute of Semiconductor Technology and School of Electronic Science and TechnologyDalian University of Technology Dalian 116023 China

Correspondence should be addressed to Zhenan Tang tangzadluteducn

Received 27 June 2014 Revised 3 August 2014 Accepted 6 August 2014 Published 31 August 2014

Academic Editor Nadia Nedjah

Copyright copy 2014 Kaiyu Wang et al This is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK) The ADCRLcombines classic closed-loop carrier recovery circuit all digital Costas loop (ADCOL) with frequency feedward loop maximumlikelihood frequency estimator (MLFE) so as to make the best use of the advantages of the two types of carrier recovery loops andobtain amore robust performance in the procedure of carrier recovery Besides considering that forMLFE the accurate estimationof frequency offset is associated with the linear characteristic of its frequency discriminator (FD) the Coordinate Rotation DigitalComputer (CORDIC) algorithm is introduced into the FD based onMLFE to unwrap linearly phase differenceThe frequency offsetcontained within the phase difference unwrapped is estimated by the MLFE implemented just using some shifter and multiply-accumulate units to assist the ADCOL to lock quickly and precisely The joint simulation results of ModelSim and MATLAB showthat the performances of the proposed ADCRL in locked-in time and range are superior to those of the ADCOL On the otherhand a systematic design procedure based on FPGA for the proposed ADCRL is also presented

1 Introduction

Along with the continuous development of the technologiesof field programmable logic gate array (FPGA) and digitalsignal processing the FPGAs in possession of large capacityand low power dissipation make it possible to realize a truesoftware defined radio and integrate a whole digital commu-nication system into the chips in order to reconfigure flex-ibly the continuously evolving communication protocolsand minimize the volume of spacecraft A typical exampleapplying the software defined radio (SDR) based on FPGAto deep space communication is the National Aeronauticand Space Administration (NASA) Electra radio in whichthe baseband processing is entirely implemented in a FPGAVirtually any channel code modulation and data ratemay beaccommodated via suitable reprogramming of this SDR [1]

In communication system the style of modulation anddemodulation plays an important role and directly influencesthe performance of the system However in deep space com-munication both power efficiency and bandwidth efficiency

of a communication system should be simultaneously consid-ered Therefore the modulation and demodulation methodof QPSK have been widely used into deep space communica-tionWith respect toQPSK demodulator there are two differ-ent solutions to demodulate They are noncoherent demod-ulation and coherent demodulation respectively Comparedwith noncoherent demodulation coherent demodulation canbe implemented in a simpler structure so as to save thelogic resources of FPGA Hence this paper takes the QPSKcoherent demodulator as the object of our study

In QPSK coherent demodulator a special phase-lockedloop (PLL) namely Costas loop is used to synchronize thelocally generated carrier with the carrier contained in thereceived input buried by external noise It is well knownthat the PLL has an outstanding ability to restrain noiseas a result of its narrow-band characteristic Therefore itcan precisely realize carrier tracking Nonetheless in thedesign procedure of the PLL the pair of contradictionsbetween lock-in frequency range and tracking precision isalways difficult to reconcile In particular in deep space

Hindawi Publishing CorporationInternational Journal of Reconfigurable ComputingVolume 2014 Article ID 502942 15 pageshttpdxdoiorg1011552014502942

2 International Journal of Reconfigurable Computing

communication Doppler shift is common and will introducea considerable frequency offset between transmitter andreceiver In this situation for the PLL to increase lock-infrequency range loop noise bandwidth must be broadenedwhereas the precise tracking of its carrier in the condition ofa relatively low signal-to-noise ratio (SNR) is dependent ona narrow loop noise bandwidth So a large lock-in frequencyrange (loop noise bandwidth) and a high tracking precisioncannot be simultaneously satisfied [2] In practical designs acompromise between them is a best choice

Except for PLL there are also many kinds of methodsreferred to as automatic frequency control (AFC) for carrierrecovery such as the frequency recovery loop based onfeedback control [3] and the frequency offset estimator (FOE)based on estimation theory [4ndash6] They are usually used inburst communication where the speed of carrier recoverymust be very quick However a fatal flaw for these methodsis a relatively low tracking precision Thus in low SNR envi-ronments they do not present a perfect performance

To recover carrier quickly and precisely in the twosituations a large frequency offset and a relatively low SNRsome approaches combining PLL and AFC are proposed totake advantage of their ownmerits In [7] a kind of all-digitalphase-locked loop (ADPLL) for QPSK combining a first-order frequency recovery loop based on feedback controlwith a second-order phase-locked loop is proposed But dueto the use of the FD in possession of a sinusoid characteristic(nonlinear characteristic) namely the second algorithmshown in Table 1 extra noises are introduced into the loop inthe circumstance of a low SNR On the other side [8] appliesfast Fourier transformation (FFT) into the output of the phasediscriminator (PD) of QPSK ADCOL to roughly estimatefrequency offset and then speed up the procedure of thecarrier recovery of the ADCOL However when phase offsetis considerable its PD performs the nonlinear characteristicOn the other hand for FFT accurate frequency estimation isproportional to the number of its points which implies thatto estimate precisely frequency must consume many logicresources of FPGA From the above analysis we can see thatPD and FD also influence carrier recovery Therefore [9]proposes an all-digital phase-locked loop (ADPLL) takingHilbert transform andCORDIC algorithm as its PD resultingin that the locked-in range of the ADPLL is broadened tothe sample frequency of the system (Nyquist rate) Given thatour design is to combine MLFE with QPSK ADCOL andthen use the former to roughly estimate a large frequencyoffset to assist the latter to lock quickly and precisely whichmakes it possible for the ADCOL to operate within the linearrange of its PD we just draw our attention to the linercharacteristic of the FD of the MLFE Thus a kind of FDwhich can implement frequency discrimination linearly isproposed In other words our proposed design considersnot only the merits of the MLFE and the ADCOL but alsothe linear characteristic of the FD of the MLFE so thatcarrier can be recovered quickly and precisely Furthermorethe lock-in frequency range is also broadened so that thepair of contradictions hardly reconciled for ADCOL can bealleviated On the other hand the whole design process of theADCRL based on FPGA presented by us will also provide a

guideline for the readers anxious to implement an excellentFPGA-based ADCRL for QPSK which is hardly found inpublished literatures

In the following the design procedure of the ADCOLbased on FPGA is presented step by step Next our proposedthe FDof linear characteristicMLFE based on phase domainand the overall design of our QPSK ADCOL are describedin Section 3 In Section 4 simulation results and compara-tive analyses are given Finally conclusion and outlook areobtained in Section 5

2 FPGA-Based All-Digital QPSKPhase-Locked Loop

With respect to QPSK ADCOL there are three basic compo-nents They are PD loop filter and numerical control oscilla-tion (NCO) respectively Because it is also a kind of ADPLLthe design procedure of it is the same as the normal ADPLLTherefore it is indispensable to analyze the design procedureof the normal ADPLL The normal ADPLL is derived fromthe result of digitizing analogy PLL The analysis and designfor analogy PLL has been well known Some monographshave discussed some analogy PLLs which have differentorders [10] As it is sufficient for our QPSK demodulator touse a second-order ADPLL we just discuss the digitizingprocedure of a second-order analogy PLL

21 The Modeling for All-Digital Phase-Locked LoopFigure 1(a) shows the phase domain model of a second-orderanalogy PLL It consists of the PD modeled by a subtractorwith gain 119896119889 the loop filter which is modeled by a first-orderlow pass filter proportion integral filter with the 119904-domaintransfer function 119865(119904) = 119881119900(119904)119881119889(119904) = (1119904)((1205912119904 + 1)1205911)

to minimize the phase noise of the output of the PD 119881119889(119904)and a voltage control oscillator (VCO) tuned by 119881119889(119904) tomake the output phase 120579119900(119904) closed to the input phase 120579119894(119904)which acts like a radian frequency integrator as a result of119881119889(119904) = Δ119908119905 + Δ120601 and have the 119904-domain transfer function119881(119904) = 120579119900(119904)119881119888(119904) = 119896119900119904

From the above the analysis a set of equations describingthe 119904-domain transfer functions of the phase domain modelof a second-order analogy PLL can be obtained

119865 (119904) =119881119888 (119904)

119881119889 (119904)=1

119904

1205912119904 + 1

1205911

(1)

119881 (119904) =120579119900 (119904)

119881119888 (119904)=119870119900

119904 (2)

119867(119904) =120579119900 (119904)

120579119894 (119904)=

119870119889119865 (119904) 119881 (119904)

1 + 119870119889119865 (119904) 119881 (119904)=

2120585119908119899119904 + 1199082

119899

1199042 + 2120585119908119899119904 + 1199082119899

(3)

where119908119899 = radic1198961199001198961198891205911 is natural radian frequency 120585 = 12059121199081198992

is damping factor 119896119900 is the gain of the VCO 119896119889 is the gainof the PD 1205911 and 1205912 are time constants of the proportionintegral filter and 119867(119904) is the 119904-domain transfer function ofthe analogy PLL Please note that the above the equationsare just reasonable on the condition that the phase difference

International Journal of Reconfigurable Computing 3

Phasediscriminator

Loopfilter

Voltage controloscillator

120579i(s) ΔΦ(s)Kd F(s)

Vd(s) Vc(s)

120579o(s)

V(s) =Ko

s

(a) Phase domain model of a second-order analogy PLL

Phase discriminator

Loopfilter

Numericallycontrolled oscillator

120579i(z) ΔΦ(z)Kd F(z)

Vd(z) Vc(z)

120579o(z)

N(z)

(b) Phase domain model of a second-order ADPLL

Figure 1 The different modes of PLL

between 120579119894(119904) and 120579119900(119904)makes it possible for the PD to workwithin its linear range

To digitize the analogy PLL bilinear transformationwhich is often used to digitize analogy filter [11] is adoptedLetrsquos set the transformation as

119904 =2

119879119904

1 minus 119911minus1

1 + 119911minus1 (4)

where 119879119904 is the sample time of a discrete-time systemTaking (4) into (1) and (2) then we can obtain

119865 (119911) =119881119888 (119911)

119881119889 (119911)= 1198621 +

1198622

1 minus 119911minus1

119873 (119911) =120579119900 (119911)

119881119888 (119911)=

119896119900119911minus1

(1 minus 119911minus1)

(5)

where 1198621 = 12059121205911 minus 11987911990421205911 and 1198622 = 1198791199041205911Therefore as shown in Figure 1(b) the model of ADPLL

can be acquired On the basis of Figure 1(b) and the two equa-tions (5) the based-model discrete-time transfer function ofthe ADPLL can be expressed as

119867(119911) =120579119900 (119911)

120579119894 (119911)

=119896119889119896119900 (1198621 + 1198622) 119911

minus1minus 1198961198891198961199001198621119911

minus2

1 + [119896119889119896119900 (1198621 + 1198622) minus 2] 119911minus1 + (1 minus 1198961198891198961199001198621) 119911

minus2

(6)

22 Parameter Calculation of All-Digital Phase-Locked LoopForm (6) we can see that to obtain the based-model discrete-time transfer function of the ADPLL the values of theparameters 1198621 1198622 119896119889 and 119896119900 are needed However it isnot easy to calculate them after knowing about the model ofADPLL Nonetheless none of researches published presentthe procedure Thus in the following we will display how tocalculate them

First of all the method to acquire 1198621 and 1198622 is givenEquation (6) is just the 119911-domain transfer function based

on the model of Figure 1(b) and the two equations (5) Onthe other hand taking (4) into (3) and the 119911-domain transferfunction of the ADPLL based on bilinear transformation canbe obtained

119867(119885) = ([4120585119908119899119879119904 + (119908119899119879119904)2] + 2(119908119899119879119904)

2119911minus1

+ [(119908119899119879119904)2minus 4120585119908119899119879119904] 119911

minus2)

times ([4 + 4120585119908119899119879119904 + (119908119899119879119904)2] + [2(119908119899119879119904)

2minus 8] 119911

minus1

+ [4 + 4120585119908119899119879119904 + (119908119899119879119904)2] 119911minus2)minus1

(7)

Let us set the denominator of the two 119911-domain transferfunctions of the ADPLL (6) and (7) obtained by differentmethods to be equal and the two equations about 1198621 and 1198622can be given

1198621 =1

119870119889119870119889

8120585119908119899119879119904

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp2120585119908119899119879119904

119870119889119870119889

1198622 =1

119870119889119870119900

4(119908119899119879119904)2

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp(119908119899119879119904)

2

119870119889119870119900

(8)

where the two approximations are just true when 119908119899119879119904 ≪

1 Namely assuming that the PD of ADPLL lies in itslinear operation range and for ADPLL the characteristic offrequency response is within the range of its passband

Secondly on the basis of [12] when 120585 = 0707 second-order PLL can meet the optimal value of Wiener theory Sowe can get that 120585 = 0707

The third step is to determine 119908119899

4 International Journal of Reconfigurable Computing

For PLL the natural radian frequency 119908119899 determineslocked-in frequency range and the performance of sup-pressing noise The pair of contradictions between locked-in frequency range (loop noise bandwidth) and trackingprecision stem from it

In the following we are going to discuss the range of119908119899 from the two aspects fast capture bandwidth of ADPLLand its loop SNR so as to make a compromise between thelocked-in range and the tracking precision

In the case of ADPLL there are two kinds of noisesexternal phase noise and internal phase noise The externalnoise caused by additive white Gaussian noise (AWGN) isa main part which has an influence on the performance ofthe ADPLL and the internal noise caused by the finite wordlength effect can be improved by the reasonable selection ofword length Herein the impact on the selection of 119908119899 isexternal phase noise Thus we just take it into consideration

The channel of deep-space communication is quitebenign with AWGN being the dominating impairment [1]and thus the phase noise of ADPLL caused by AWGN can begiven by [13]

1205901205792= (

119878

119873)119894

minus1119861119871

119861119894

(9)

where 119861119894 is the bandwidth of input signal of the ADPLL(119878119873)119894 is its input SNR and 119861119871 is loop noise bandwidth

For the second-order ADPLL taking proportion integralfilter as its loop filter 119861119871 can be expressed as

119861119871 =119908119899

8120585(1 + 4120585

2) (10)

For ADPLL the ability to suppress noise can be reflectedby the loop SNR

(119878

119873)119871

=1

1205901205792= (

119878

119873)119894

119861119894

119861119871

(11)

It determines the size of phase jitter The result of linearanalysis [14] manifests that PLL cannot work normally until(119878119873)119871 ge 6119889119861

Taking (10) into (11) and considering that ADPLL canoperate normally the upper bound of 119908119899 can be expressedas

119908119899 le (119878

119873)119894

4120585119861119894

(1 + 41205852) 3 (12)

The tracking procedure of ADPLL contains frequencytracking and phase tracking and the former needs longertime than the latter In design of our ADCRL however wefirstly use maximum likelihood frequency offset estimator(MLFOE) to assist ADCOL to implement frequency trackingin that for MLFOE the speed of tracking a large frequencyoffset is superior to ADCOLTherefore we just take the phasetracking into consideration in the procedure of designing ourADCOL In the case of ADPLL the fast capture bandwidthis defined as the largest frequency offset which ensures that

ADPLL can be locked in the procedure of the phase trackingIt can be expressed as

Δ119908119897 = 2120585119908119899 (13)

To meet the frequency tracking in the presence withoutthe assistance of the MLFOE the lower bound of 119908119899 is givenby

119908119899 geΔ119908119897

2120585 (14)

Thus from (12) and (14) we can get acquire the range of 119908119899

Δ119908119897

2120585le 119908119899 le (

119878

119873)119894

4120585119861119894

(1 + 41205852) 3 (15)

Until now except for 119870119889 and 119870119900 the parameters neededfor calculating1198621 and1198622 have been acquired Because the119870119889and119870119900 are associated with some practical system parameterswe will discuss about them in the following

23 Parameter Calculation of All-Digital QPSK Phase-LockedLoop Based on FPGA In the above discussions we haveobtained the corresponding parameters for a normal ADPLLBut as mentioned at the beginning of Section 2 QPSKADCOL is also a kind of ADPLL Thus the above methodsare suitable for QPSK ADCOL

As shown in Figure 2 QPSK ADCOL is comprised ofthe PD covered by the shaded area loop filter surroundedby dashed line and numerically controlled oscillator (NCO)Now based on Figure 2 we begin to discuss how to obtain119870119889and119870119900

First of all the analogy-digital converter (ADC) shownin Figure 2 samples the modulated signals from transmitterRXIN(119905) and acquires a series of discrete-time signals sam-pled RXIN(119870119879119904)

RXIN (119896119879119904) =

119896

sum

119899=0

119868 (119899119879119904) cos (119908119894119899119879119904 + 120579119894)

+ 119876 (119899119879119904) sin (119908119894119899119879119904 + 120579119894)

(16)

where 119908119894 is the radian frequency of the signals sampled 120579119894is their initial phase and 119868(119899119879119904) and 119876(119899119879119904) are the QPSKsignals evaluated as plusmn1 in our design

Secondly the signals RXIN(119870119879119904) are mixed with the twooutputs of the NCO and then filtered to eliminate the doublefrequency components generated by the mixing The twosignals filtered can be expressed as

upper branch (in-phase branch)

119868119899 (119896119879119904) =1

2

119896

sum

119899=0

119868119899 (119899119879119904) cos (Δ119908119899119879119904 + Δ120579)

minus 119876119899 (119899119879119904) sin (Δ119908119899119879119904 + Δ120579)

(17)

International Journal of Reconfigurable Computing 5

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signal

from transmitter

0

1

Quadrature branch

In-phase branch

C1

C2

ud

timesminus1

timesminus1

Figure 2 Structure diagram of QPSK all-digital phase-locked loop

bottom branch (quadrature branch)

119876119899 (119896119879119904) =1

2

119896

sum

119899=0

119868119899 (119899119879119904) cos (Δ119908119899119879119904 + Δ120579)

+ 119876119899 (119899119879119904) sin (Δ119908119899119879119904 + Δ120579)

(18)

where Δ119908 is the radian frequency difference between signalssampled and the two outputs of the NCO and Δ120579 is theirinitial phase difference

Finally the function of the PD of the QPSK ADCOL isimplemented by the following

119906119889 (119896119879)= sign (119868119899 (119896119879119904)) 119876119899 (119896119879119904) minus sign (119876119899 (119896119879119904)) 119868119899 (119896119879119904) (19)

Herein to save hardware resources of FPGA the signdecision and the multiplication operation within (19) arereplaced by a multiplexer controlled by the most significantbit (MSB) of the outputs of the two low pass filtersand aninverter shown in Figure 2 (because the outputs of the twolow pass filters are signed numbers) Therefore the outputcharacteristic of the PD can be obtained

119906119889 (119870119879)

=

minus sin (Δ119908119870119879119904 + Δ120579) minus120587 lt Δ119908119870119879119904 + Δ120579 lt minus3

4120587

cos (Δ119908119870119879119904 + Δ120579) minus3

4120587 lt Δ119908119870119879119904 + Δ120579 lt minus

120587

4

sin (Δ119908119870119879119904 + Δ120579) minus120587

4lt Δ119908119870119879119904 + Δ120579 lt

120587

4

minus cos (Δ119908119870119879119904 + Δ120579)120587

4lt Δ119908119870119879119904 + Δ120579 lt

3

4120587

minus sin (Δ119908119870119879119904 + Δ120579)3

4120587 lt Δ119908119870119879119904 + Δ120579 lt 120587

(20)

0

0

02

04

06

08

Phase offset (radian)

Out

put a

mpl

itude

(V)

minus120587 minus31205874 minus1205874 1205874 31205874 120587

minus02

minus04

minus06

minus08

Figure 3 Phase offset versus output voltage amplitude of PD

Based on (20) the output characteristics curve of the PDcan be obtain and shown in Figure 3 From Figure 3 we cansee that only if the phase offset is within the linear range ofthe PD (minus1205874 sim 1205874) the gain 119870119889 of the PD approximatesto 1 namely the slope of the curve So this is also one reasonwhy we use MLFE to assist QPSK ADCOL to recover carrierquickly and precisely

Next we start with discussing the gain 119870119900 of the NCOIn [15] the authors implement NCO on a Xilinx FPGA in

three types of ways and the conclusion that themethod basedon Xilinx ROM is superior to the other two is acquiredThuswe select themethod based on Xilinx ROM to implement ourNCO [16]

On the basis of the principle of NCO the frequency of itsoutput signal can be expressed as

119891out =119891119904

2119873119908Δ120579 (119870119879119904) (21)

where 119891119904 = 1119879119904 is sample frequency 119882Δ120579(119870119879119904) is frequency

control word and 119873 is the bit width of the input signal of

6 International Journal of Reconfigurable Computing

0 5 10 15

0

10M

agni

tude

(dB)

minus10

minus20

times105Natural radian frequency wn (Hz)

(a) Frequency response characteristic

0 5 10 15

0

Phas

e (de

g)

minus50

minus100

times105Natural radian frequency wn (Hz)

(b) Phase response characteristic

Figure 4 QPSK ADCOL characteristic curve

NCO In our design119882Δ120579(119870119879119904) = 119882119888+119882119906119889 where119882119888 is a given

value determined by carrier frequency and its block diagramnamed as frequency controlword can be seen in Figure 2119882119906119889is the output of the loop filter that is tuned by the frequencyoffset between transmitter and receiver

So the radian frequency of NCO is given as

119882out = 2120587119891out =2120587119891119904

2119873119882Δ120579(119870119879

119904) (22)

On the basis of themodel of ADPLL shown in Figure 1(b)NCO is equivalent to a radian frequency integrator So theoutput phase of NCO is given as

120579out =2120587119891119904119879119894

2119873119882Δ120579(119870119879

119904) (23)

where 119879119894 is the update period of the frequency control word119882Δ120579(119870119879

119904) namely the sample period of the output of loop filter

119882119906119889 and is often set to be 8119879119904Therefore the gain 119870119900 of our NCO is given by

119870119900 =2120587119891119904

21198738119879119904 =

2120587

2119873minus3 (24)

So far we have obtained all methods to calculate theparameters of the QPSKADCOL whereas wemust note thatin our QPSK ADCOL based on FPGA shown in Figure 2 anextra gain will be introduced as the result of the changes ofthe bit width between the inputs and outputs of the differentmodules Regardless of the sign bit the bit width of the inputsof the two multipliers is 7 and the bit width of their outputsis 15 The bit width of the inputs of the two low pass filtersis 15 and the bit width of their outputs is 31 Thus the gainof the two multipliers is 215minus7 = 2

8 and the gain of the twolow pass filters is 231minus15 = 2

16 The rest of the parts showed inFigure 2 have no change in bit width between their inputs andoutputs Therefore the gain from the changes of bit width is28+16

= 224 and (8) should be rectified as

1198621 =1

119896119889119896119900224

8120585119908119899119879119904

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp2120585119908119899119879119904

119896119889119896119900224

1198621 =1

119896119889119896119900224

4(119908119899119879119904)2

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp(119908119899119879119904)

2

119896119889119896119900224

(25)

On the basis of the core idea of software defined radiothe parts of digital signal processing should be closed tothe front end of radio frequency (RF) as much as possibleTherefore we make our QPSK ADCOL operate in inter-mediate frequency (IF) namely the ADC sample frequency119891119904 = 26MHZ and carrier frequency (the output frequency ofNCO) 119891119888 = 4MHZ

On the other hand To ensure that our QPSKADCOL cannormally operate under the conditions of a large frequencyoffset and a low SNR let us set the fast capture bandwidthΔ119908119897 to be 100KHZ the least and the input SNR (119878119873) to be1 dB We have known that the gain of PD is 119870119889 = 1 and thedamping factor is 120585 asymp 0707 To decrease internal phase noisecaused by word length effect we set the bit width of inputsignal of NCO to be 119873 = 32 Therefore based on (15) (24)and (25) the range of the natural radian frequency119908119899 can beobtained and the one of the values is chosen as

119908119899 = 2120587 times 150 times 103= 0942 times 10

6(rads) (26)

Next take119870119889119870119900224 (25) and (26) into (6) we can obtain

themodel-based discrete-time transfer function of ourQPSKADCOL

119867(119911) =0053119911

minus1minus 0051119911

minus2

1 minus 1947119911minus1 + 0949119911minus2 (27)

From (27) the poles of our QPSK ADCOL can beobtained They are 0973 plusmn 0036119894 Based on the theory of thestability of discrete system the system is stable if all poles arelocated inside the unit circle Therefore our QPSK ADCOLis stable

Now the frequency response characteristic and phaseresponse characteristic of ourQPSKADCOL can be acquiredand shown in Figures 4(a) and 4(b) respectively

From Figures 4(a) and 4(b) we can see that when samplefrequency is 26MHZ the passband of our QPSK ADCOLranges from 0 to 200KHZ (namely 119908119899119879119904 ≪ 1 is true)and its margin of phase is 120 degree below Thus this alsoindicates that our QPSK ADCOL meets the conditions ofthe stability of negative feedback control system What ismore Figure 4(a) also displays that QPSK ADCOL is of theproperty of low pass

International Journal of Reconfigurable Computing 7

CORDICCORE

Maximum likelihood frequency estimator

Frequency discriminator

Qn(KTs)

In(KTs)

times2

times2

times4

timesminus1 Arctan (x) fsumΔ

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

Figure 5 The block diagram of the FD and MLFE (MLFOE)

Table 1 Two kinds of typical frequency discriminators

The algorithm used Frequency offset output Output characteristic Hardware complexitysig(lowastdot) times lowastcross(119896 minus 1)119879119904 minus 119896119879119904

sin[2(120579119896minus1 minus 120579119896)](119896 minus 1)119879119904 minus 119896119879119904

Nonlinear Moderate

cross(119896 minus 1)119879119904 minus 119896119879119904

sin(120579119896minus1 minus 120579119896)(119896 minus 1)119879119904 minus 119896119879119904

Nonlinear Simplelowastdot = 119868119899(119870119879119904) times 119868119899((119870 minus 1)119879119904) minus 119876119899(119870119879119904) times 119876119899((119870 minus 1)119879119904)lowastcross = 119868119899(119870119879119904) times 119876119899((119870 minus 1)119879119904) minus 119868119899((119870 minus 1)119879119904) times 119876119899(119870119879119904)

3 The Design of Phase Domain MaximumLikelihood Frequency Estimator and ItsFrequency Discriminator

31 The Frequency Discriminator of the Linear Characteris-tic To use MLFE to obtain an accurate frequency offsetthe performance of its FD is a key factor which must beconsidered Two kinds of FDs used widely are summarizedin Table 1 [17] From Table 1 we can see that they are allof nonlinear characteristic Because in the case of sin(Δ120579)sin(Δ120579) asymp Δ120579 is true only if Δ120579 varies within a small rangeHowever in deep space communication (or in the conditionthat a large Doppler shift is common) the approximation ishardly possible On the other hand to discriminate phaseoffset the dot product and cross-product from two samplepoints separated by a sample interval must be conductedand their results divide by the sample interval (120579 = 119908119905 =

2120587119891119905 namely 119891 = 1205792120587119905)Therefore we introduce a kind of FD in possession of lin-

ear characteristic and the ability to acquire the correspondingsignals of ourADCOL so as to transform them into the inputsof theMLFE Its block diagram surrounded by the dashed lineis shown in Figure 5

FromFigure 5 we can see that after a series of transforma-tions for the two equations (17) and (18) the two signals of thefront end of the CORDIC algorithm block can be obtainedThey are

cos (4Δ119908119870119879119904 + 4Δ120579) = cos (4 (2120587Δ119891119870119879119904 + Δ120579))

sin (4Δ119908119870119879119904 + 4Δ120579) = sin (4 (2120587Δ119891119870119879119904 + Δ120579)) (28)

Feed them into the CORDIC algorithm blockwhich implements the algorithm tanminus1(sin(4Δ119908119870119879119904 +

4Δ120579) cos(4Δ119908119870119879119904 + 4Δ120579)) and the phase offset4Δ119908119870119879119904 + 4Δ120579 = 4(2120587Δ119891119870119879119904 + Δ120579) can be acquiredAfter that the MLFE will be used to estimate the frequencyoffset Δ119891 It is clear that this is a procedure of resolvinglinearly frequency offset Because the CORDIC algorithmcan easily be implemented on FPGA just using snifters andadd operations [18] we just discuss about how to implementMLFE on FPGA using as few logic resources as possible

32 Phase Domain Maximum Likelihood Frequency Estima-tion Algorithm In the case of the FD shown in Figure 5a mapping transformation from Cartesian domain to phasedomain can be realized by CORDIC core and expressed as

119909 =

arctan(119876119896

119868119896

) 119868119896 gt 0

arctan(119876119896

119868119896

) minus 120587 119876119896 lt 0 119868119896 le 0

arctan(119876119896

119868119896

) + 120587 119876119896 gt 0 119868119896 le 0

(29)

where 119868119896 = cos(4Δ119908119870119879119904+4Δ120579) and119876119896 = sin(4Δ119908119870119879119904+4Δ120579)119909119896 is the discrete phase of 119896th sample point The amendmentof plusmn120587 is due to that the output range of our CORDIC core iswithin (minus120587 sim 120587)

To useMLFE for estimating frequency offset we first needto obtain the discrete phases of119872 continuous sample points(119909119896 0 le 119896 le 119872 minus 1) and then take the first sample point 1199090

8 International Journal of Reconfigurable Computing

as initial reference point to obtain119872 absolute phases whichcan be expressed as

119909119896 = 119909119896minus1 +

119909119896 minus 119909119896minus11003816100381610038161003816119909119896 minus 119909119896minus1

1003816100381610038161003816 lt 120587

119909119896 minus 119909119896minus1 + 2120587 119909119896 minus 119909119896minus1 lt minus120587

119909119896 minus 119909119896minus1 minus 2120587 119909119896 minus 119909119896minus1 gt 120587

1 le 119896 lt 119872 1199090 = 1199090

(30)

where 119909119896 (the output of our CORDIC core) is the discretephase of 119896th sample point and it ranges from minus120587 to 120587 119909119896 isan absolute phase of 119896th sample point which takes 1199090 as thepoint of reference and has no the limitation of phase rangingfrom minus120587 to 120587 The amendment of plusmn2120587 is due to the phasedifference between the (119896 minus 1)th sample point 119909119896minus1 and the119896th 119909119896 crosses over a cycle (2120587) of the outputof our CORDICcore

After that a recursive formula of the 119872 absolute phasescan be obtained

119909119896 = 4 times (2120587119870119879119904Δ119891 + Δ120579 + 119899119896) 0 le 119870 le 119872 minus 1 (31)

where 119899119896 is the phase noise caused by AWGN (for the sakeof simplicity we neglect it in (16) (17) (18) and (28)) 119879119904is the sample frequency Δ119891 is the frequency offset betweenthe output of the NCO and the modulated signal fromtransmitter and Δ120579 is initial phase difference of the twosignals When SNR is as low as 10 dB numerical results havebeen demonstrated that 119899119896 can be considered as the Gaussianapproximation accurate which has a zero mean and variance1205902 [19]Letrsquos set 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 to be 119911119896 namely

119911119896 = 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 0 le 119896 le 119872 minus 1 (32)

Equation (35) can be also written in vector form

119885 = Δ1198912120587119879119904120572 + Δ120579120573 + 119881 (33)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

= Δ1198912120587119879119904

[[[[[[

[

0

1

119872minus 2

119872 minus 1

]]]]]]

]

+ Δ120579

[[[[[

[

1

1

1

1

1

]]]]]

]

+

[[[[[[

[

11989901198991

119899119872minus2119899119872minus1

]]]]]]

]

(34)

Consequently 119885 is a Gaussian random vector with probabil-ity density function

119891119911 (119885) =1

radic(2120587)119872120590119872

exp[minus1003817100381710038171003817119885 minus Δ1198912120587119879119904120572 minus Δ120579120573

10038171003817100381710038172

21205902]

(35)

where sdot 2 = (119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)119879(119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)

The maximum likelihood estimators Δ119891 and Δ120579 can beobtained by equating the gradientnablaΔ119891Δ120579 log119891119911(119911) to zero andsolving a two-dimensional linear system

Δ119891(119911) =12

2120587119879119904 (119872 minus 1)119872 (119872 + 1)119865119879119885 (36)

120579 (119911) =6

119872 (119872 + 1)Θ119879119885 (37)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

119865 =

[[[[[[[[[[[[[

[

minus119872 minus 1

2

minus119872 minus 1

2+ 1

119872minus 1

2minus 1

119872 minus 1

2

]]]]]]]]]]]]]

]

Θ =

[[[[[[[[[[[[[

[

2119872 minus 1

32119872 minus 1

3minus 1

2119872 minus 1

3minus (119872 minus 2)

2119872 minus 1

3minus (119872 minus 1)

]]]]]]]]]]]]]

]

(38)

The maximum likelihood estimators in (36) and (37)are minimum variance unbiased estimations achieving theCramer Rao Bound [19 20] On the other side the higher theestimation accuracy is the larger the sample points 119872 andSNR are

Please note that (31) is 4119885119896 If we use (36) to estimatefrequency offset Δ119891 the value of estimation must multiply by4 In the case of FPGA the multiplication of 2119899 just needs toshift n bits towards the left

On the other hand in part 3 Section 2 we select updateperiod of frequency control word of the NCO to be 8119879119904Therefore to enable frequency offset estimation block shownin Figure 5 and the QPSK ADCOL shown in Figure 2 tooperate as synchronously as possible we set the number ofthe sample point of MLFE to be119872 = 8 Therefore based on(36) (34) (32) and (31) we can obtain the frequency offsetestimated

Δ119891 = 4Δ119891(119911) = 412

2120587119879119904 (8 minus 1) 8 (8 + 1)

times [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(39)

International Journal of Reconfigurable Computing 9

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 20dB

frequ

ency

offs

et (M

Hz)

(a) Signal-to-noise ratio is 20 dB

0 2 4 6 8 10

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 5dB

(b) Signal-to-noise ratio is 5 dB

Figure 6 Actual frequency offset versus estimation frequency offset under different signal-to-noise ratios

where119879119904 = 126MHZ is sample frequency and 119909119896 0 le 119870 le 7

is absolute phase generated by (30)Using Δ119891 to assist the QPSK ADCOL shown in Figure 2

to recover carrier quickly Δ119891 must be transformed intofrequency control world of the NCO On the basis of (21) wecan obtain frequency control world of Δ119891 that is

119908Δ119891 =Δ1198912119873

119891119904

(40)

Taking (39) into (40) we can get

119908Δ119891

=2119873

21120587[minus

8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(41)

where 119909119896 0 le 119870 le 7 are signed decimals which areexpressed as the fixed-point number with 3 bitsrsquo integernumber and 29 bitsrsquo decimal 119873 = 32 is bit width of inputsignal of the NCO Because frequency control world of NCOis an integer number the result of (41) should multiply by2minus29 so as to eliminate the affection of the decimal expressedby 29 bitsrsquo binary format Therefore actual frequency controlworld should be119908Δ119891

= 01213 [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(42)

Due to 01213 asymp 2minus3

minus 2minus8 maximum likelihood fre-

quency estimation can be implemented just using shifters andmultiply-accumulate units

In deep-space communication to confirm that the signalsburied by noise can be successfully detected by receiver aparameter named link margin is used to specify minimalSNR of the received signals In the practical design of thecommunication systems its value usually ranges from 3 dB to6 dB [21] In our design we select two types of linkmargins toinvestigate the performance of our frequency offset estimatorThey are the low linkmargin of 5 dB and the high linkmarginof 20 dB respectively Therefore we simulate our MLFEunder the condition of sample frequency 119891119879 = 26MHZ andcarrier frequency 119891119888 = 4MHZ by MATLAB The simulationresults are shown in Figure 6

From Figure 6 we can see that although the estimationrang of the frequency offset decreases along with the declineof SNR the range still approximates minus2MHZ sim 2MHZunder SRN = 5 dB In the case of low and mediumearth orbiting satellite where the greatest Doppler shiftsare plusmn100KHZ and plusmn200KHZ [22] respectively the rangcompletely meets as well

33 Entire Design of All-Digital Carrier Recovery Loop ofQPSK Figure 7 shows the block diagram of our ADCRLIt consists of the MLFOE in shadow and QPSK ADCOLsurrounded by dashed line respectively

First of all the frequency offset will be estimated roughlyand then transformed into the frequency control words ofthe NCO by MLFE to speed up QPSK ADCOL to quicklyimplement the tracking of the carrier

Secondly with the assistance of MLFOE the QPSKADCOL is locked quickly and then starts with tracking thecarrier precisely

FromFigure 7 we can see that the bit width of the outputsof the two low pass filters is 32 If we apply directly thewidth to MLFOE the cost of hardware resource for FPGAis considerable So in our design a truncated bit width willbe used To ensure that the impact of the truncation onthe performance of our system is minimal a simulation isconducted which uses different bit widths for the two inputsignals of MLFOE (the bit widths of the outputs of the twolow pass filters) and the widths range from 8 to 32 bits to test

10 International Journal of Reconfigurable Computing

ADC

Low pass filter

Low passfilter

RegReg

Numericallycontrolledoscillator

Frequency control word

01

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signalfrom transmitter

01

CORDICCORE

Maximumlikelihoodfrequencyestimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

Maximum likelihood frequency offset estimator

Qn(KTs)

In(KTs) times2

times2

times4

timesminus1 Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

timesminus1

timesminus1

k

sumn=0

cos(4ΔwnTs + 4120579)k

sumn=0

(4ΔwnTs + 4120579)

k

sumn=0

sin(4ΔwnTs + 4120579)

Figure 7 Block diagram of QPSK ADCRL

which one is the best for the frequency offset error Δ119891 =

100KHZ under the situations of SNR = 20 10 5 dB Thesimulation result is shown in Figure 8 From Figure 8 it isclear that when the bit width is equal to 11 the frequencyestimation value of the MLFOE is almost the same as that ofhaving bit width equal to 32 under the three types of SNRsThus we set the bit width of the two inputs of MLFOE to be11

4 Simulation Results andComparative Analysis

To verify that the proposed architecture is valid the FPGAsimulation tool ModelSim SE 65 is used to observe theimplementation performance of our proposed architecturebased on FPGA On the other hand MATLAB is also usedto generate the QPSK modulated signals with a frequencyoffset under the conditions of different SNRs and process thesimulation results generated by the ModelSim so as to have abetter visual comparison resulting from that the outputs ofthe ModelSim that are just some values of decimal or binaryformat

The data streams of the entire simulation procedure areshown in Figure 9

The input stream generated quantized and stored into thetextfile Textfile A by MATLAB is QPSK modulated signalswith the following specifications

5 10 15 20 25 30 3565

70

75

80

85

90

95

100

105

Quantization size (bit)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

(kH

z)

SNR = 5dBSNR = 10dBSNR = 20dB

Figure 8The quantization level of the two input signals of MLFOEunder the condition of the frequency offset errorΔ119891 = 100KHZ andSNR = 20 10 5 dB

(i) the number of symbols randomly evaluated as plusmn1 isequal to 1000

(ii) the frequency of symbols 119891119887 = 80KHZ(iii) the frequency of carrier 119891119888 = 39MHZ namely

frequency offset Δ119891 = 100KHZ(iv) SNRs are 20 dB and 5 dB

International Journal of Reconfigurable Computing 11

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

01

CORDICCORE

Maximum likelihood frequency estimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

The output

of loop

filter

The output

ofNCO

QPSK

modulated

signal

MATLAB simulation

ModelSim simulation

Maximum likelihood frequency offset estimatorTextfile A

Textfile B Textfile C

Qn(KTs)

In(KTs) times2

times4

times2

timesminus1

timesminus1

timesminus1

Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

MATLAB process AMATLAB process B

Figure 9 The data stream of entire simulation procedure

(v) quantization level of the 1000 QPSK modulated sig-nals is 8 bits to imitate the input signals of 8-bit ADC

(vi) sample frequency 119891119904 = 26MHZ

The output streams generated and stored into anothertwo textfiles Textfile B and Textfile C by ModelSim are theoutputs of the NCO and the loop filter with the followingspecifications

Textfile B(i) the frequency of carrier 119891119888 = 4MHZ namely output

frequency of NCO(ii) sample frequency 119891119904 = 26MHZ(iii) the quantization level of the output amplitude of the

NCO evaluated as plusmn1 is 8 bitsTextfile C

(i) sample frequency 119891119904 = 26MHZ(ii) the quantization level of the output of the loop filter is

32 bits

Textfile A is generated byMATLAB before startingMod-elSim simulation and then fed into QPSK ADCRL (to imitatethe output of the ADC) in the procedure of the simulation ofModelSimwhenTextfile B andTextfile C are simultaneouslygenerated by ModelSim At the end of the simulation of theModelSim the two files from the ModelSim Textfile B andTextfile C will be read into MATLAB in order to furtherprocess in the two procedures MATLAB process A andMATLAB process B

Because the traditional measure of the performance ofPLL is based on locked-in time steady-state phase error and

locked-in frequency range our QPSK ADCRL also uses themethods

Based on the principle of our QPSK ADCRL displayedin Figure 7 when there exists the frequency offset betweenthe input of the QPSK modulated signals (Textfile A) andthe local carrier signals (the output of NCO) the offset canbe obtained through taking the output of the loop filter(Textfile C) into (21) In our design the carrier frequency ofthe input modulated signals is 39MHZ and the frequencyof the output of the NCO is 4MHZ Therefore the frequencyoffset is 100KHZ

If our QPSK ADCRL is locked the frequency offsetevaluated through taking the output of loop filter into (21) willapproximate to 100KHZ At the same time the output phaseof the NCO (Textfile B) should be equal or approximate tothe phase of the QPSK modulated signals (Textfile A)

On the basis of above discussion as shown in Figures 1011 12 and 13 (a) and (b) are the outputs of the loop filter fromModelSim simulation and its results processed by MATLAB(MATLAB process B shown in Figure 8) respectively (c) isthe result of the phase comparison of the two signals QPSKmodulated signals and the outputs of theNCOwhich is fromthe simulation ofModelSim and then processed byMATLAB(MATLAB process A shown in Figure 9)

Figures 10 and 11 are the simulation results of the classicQPSK ADCOL shown in Figure 2 without the assistance ofMLFOE shown in Figure 6 under the two conditions of SNR= 20 and 5 dB

From the two figures Figures 10(b) and 10(c) we can seethat when SNR is equal to 20 dB the tracking time is about015ms and the maximal steady-state phase error approxi-mates to 0 degree

12 International Journal of Reconfigurable Computing

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

0

10

20

Time (ms)

Freq

uenc

y off

set (

Hz)

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1N

orm

aliz

ed v

olta

ge (V

)

MATLAB outputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 10 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for the QPSK ADCOL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 11 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for the QPSK ADCOL

As shown in the two figures Figures 11(b) and 11(c) whenSNR is equal to 5 dB the tracking time is about 03ms and themaximal steady-state phase error approximates to 2 degree

Figures 12 and 13 are the simulation results under the twoconditions of SNR = 20 and 5 dB where theMLFOE has beenenabled

In contrast to Figures 10 and 11 after enabling theMLFOEfrom the two figures Figures 12(b) and 12(c) we can seethat when SNR is equal to 20 dB the locked-in time isabout 005ms and the maximal steady-state phase error alsoapproximates to 0 degree As shown in the two figuresFigures 13(b) and 13(c) when SNR is equal to 5 dB the lock-in

International Journal of Reconfigurable Computing 13

(a) ModelSim output of loop filter

0 005 01 015 02 025

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0

0

05 1 15 2 25 3 35 4

051

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

minus05

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 12 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

20

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 13 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for our QPSK ADCRL

time is about 01ms and themaximal steady-state phase errorapproximates to 3 degree

On the other hand in the case of the four figures Figures10(b) 11(b) 12(b) and 13(b) when QPSK ADCRL is lockedall frequency offset evaluated by the output of loop filter areequal to 100KHZ

From the above simulation results it is clear that after theMLFOE is enabled whether SNR is high or not the perform-ance of our QPSK ADCRL in locked-in time is two times

faster than that of the QPSK ADCOL without the assistanceof the MLFOE while the maximal steady-state phase error isalmost stable

On the other hand in the two conditions of SNR =20 dB and 5 dB we test the maximal frequency offset whichenables our QPSK ADCRL and the QPSK ADCOL withoutthe assistance of MLFOE to be locked and the correspondinglocked-in time and steady-phase error The results are shownin Table 2 From Table 2 we can see that after the MLFOE

14 International Journal of Reconfigurable Computing

Table 2 The performance advantage of our QPSK ADCRL in locked-in frequency range

SNR Architecture Maximal locked-in Locked-in time (ms) Steady-phase error (degree)Frequency Range (KHZ)

20 db QPSK ADCOL plusmn170 018 Approximating to 020 db Our QPSK ADCRL plusmn680 005 Approximating to 05 db QPSK ADCOL plusmn120 04 Approximating to 25 db Our QPSK ADCRL plusmn510 013 Approximating to 4

Table 3 The hardware cost of the different modules for our QPSK ADCRL

Module Number of slice registers Number of slice LUTs Number used as logicQPSK ADCOL 174 out of 28800 580 out of 28800 612 out of 28800

MLFOE FD 875 out of 28800 892 out of 28800 790 out of 28800MLFE 603 out of 28800 516 out of 28800 592 out of 28800

Total hardware cost 1652 out of 28800 1988 out of 28800 1994 out of 28800

Table 4 The power consumption of our QPSK ADCRL for different operating frequencies

Clock frequency (MHZ) Dynamic power (W) Quiescent power (W) Total power (W) Junction temp (C)312 0060 0526 0594 509250 0058 0526 0583 51200 0048 0525 0574 51150 0039 0525 0564 509

is enabled except for the advantage in locked-in time thelocked-in frequency range of our QPSKADCRL is four timeswider than that of the QPSK ADCOL Therefore our QPSKADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision which are hardlyreconciled for the QPSK ADCOL

There is no doubt that our QPSK ADCRL has a morerobust performance than the QPSK ADCOL without theMLFOE What is more to obtain the same improvement inperformance as our ADCRL for the existing QPSK ADCOL[23 24] the simple revision is to add the MLFOE shown inFigure 4 to the QPSK ADCOLs

Finally in order to acquire their hardware cost for thedifferent modules of our QPSK ADCRL based on FPGA theFPGA synthesis tool ISE Design Suite 122 from FPGA ven-dor Xilinx is used and its chip of Virtex5 family XC5VLX50which supports dynamic reconfiguration technology seenas a core technology to implement SDR [25] on FPGA isselected The synthesis results are given in Table 3 FromTable 3 we can see that although the MLFOE consumesmore logic resources than QPSK ADCOL (because manymultiplication operations are used and a pipelined CORDICarchitecture [26] is adopted so as to meet the requirement ofthe latency time) this is worthy for some applications whichneed a more robust QPSK ADCRL

On the other hand we can also see that the hardware costof the whole QPSK ADCRL just make up a small part of logicresources for the FPGA chip selected

Except for the hardware cost of our QPSK ADCRL wealso investigate its power consumption for the different

operating frequencies by the power analysis tool from Xil-inx XPower which is also important very much in someapplications where communication systems need to workcontinuously bymeans of a portable power sourceThe resultsare shown in Table 4 Form Table 4 we can see that when ourQPSK ADCRL operates under the condition of maximumclock frequency 312MHZ which is from the logic synthesisrsquosresult of ISE 122 the total power is just 0594 (W)

5 Conclusion and Outlook

In this paper an efficient QPSK ADCRL is proposed and asystematic procedure of designing the carrier recovery loopbased on FPGA is displayed On the other hand a FD in pos-session of linear characteristic is introduced to supply a moreprecise frequency offset to MLFE which is implemented justusing shifters and multiply-accumulate units to estimate thefrequency offset and assist QPSK ADCOL to lock quicklyThe joint simulation results of ModelSim and MATLAB hasproved that our proposed architecture can smoothly operateon FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOLSynthesis result has shown that the hardware cost of FPGAfor our QPSK ADCRL is very few and the result of the poweranalysis also has proved that our design is valid in powerconsumption

Looking at the future the exploration aiming at deepspace must be the tendency of the human developmentand the FPGA-based soft defined radio suitable for the

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

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Page 2: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

2 International Journal of Reconfigurable Computing

communication Doppler shift is common and will introducea considerable frequency offset between transmitter andreceiver In this situation for the PLL to increase lock-infrequency range loop noise bandwidth must be broadenedwhereas the precise tracking of its carrier in the condition ofa relatively low signal-to-noise ratio (SNR) is dependent ona narrow loop noise bandwidth So a large lock-in frequencyrange (loop noise bandwidth) and a high tracking precisioncannot be simultaneously satisfied [2] In practical designs acompromise between them is a best choice

Except for PLL there are also many kinds of methodsreferred to as automatic frequency control (AFC) for carrierrecovery such as the frequency recovery loop based onfeedback control [3] and the frequency offset estimator (FOE)based on estimation theory [4ndash6] They are usually used inburst communication where the speed of carrier recoverymust be very quick However a fatal flaw for these methodsis a relatively low tracking precision Thus in low SNR envi-ronments they do not present a perfect performance

To recover carrier quickly and precisely in the twosituations a large frequency offset and a relatively low SNRsome approaches combining PLL and AFC are proposed totake advantage of their ownmerits In [7] a kind of all-digitalphase-locked loop (ADPLL) for QPSK combining a first-order frequency recovery loop based on feedback controlwith a second-order phase-locked loop is proposed But dueto the use of the FD in possession of a sinusoid characteristic(nonlinear characteristic) namely the second algorithmshown in Table 1 extra noises are introduced into the loop inthe circumstance of a low SNR On the other side [8] appliesfast Fourier transformation (FFT) into the output of the phasediscriminator (PD) of QPSK ADCOL to roughly estimatefrequency offset and then speed up the procedure of thecarrier recovery of the ADCOL However when phase offsetis considerable its PD performs the nonlinear characteristicOn the other hand for FFT accurate frequency estimation isproportional to the number of its points which implies thatto estimate precisely frequency must consume many logicresources of FPGA From the above analysis we can see thatPD and FD also influence carrier recovery Therefore [9]proposes an all-digital phase-locked loop (ADPLL) takingHilbert transform andCORDIC algorithm as its PD resultingin that the locked-in range of the ADPLL is broadened tothe sample frequency of the system (Nyquist rate) Given thatour design is to combine MLFE with QPSK ADCOL andthen use the former to roughly estimate a large frequencyoffset to assist the latter to lock quickly and precisely whichmakes it possible for the ADCOL to operate within the linearrange of its PD we just draw our attention to the linercharacteristic of the FD of the MLFE Thus a kind of FDwhich can implement frequency discrimination linearly isproposed In other words our proposed design considersnot only the merits of the MLFE and the ADCOL but alsothe linear characteristic of the FD of the MLFE so thatcarrier can be recovered quickly and precisely Furthermorethe lock-in frequency range is also broadened so that thepair of contradictions hardly reconciled for ADCOL can bealleviated On the other hand the whole design process of theADCRL based on FPGA presented by us will also provide a

guideline for the readers anxious to implement an excellentFPGA-based ADCRL for QPSK which is hardly found inpublished literatures

In the following the design procedure of the ADCOLbased on FPGA is presented step by step Next our proposedthe FDof linear characteristicMLFE based on phase domainand the overall design of our QPSK ADCOL are describedin Section 3 In Section 4 simulation results and compara-tive analyses are given Finally conclusion and outlook areobtained in Section 5

2 FPGA-Based All-Digital QPSKPhase-Locked Loop

With respect to QPSK ADCOL there are three basic compo-nents They are PD loop filter and numerical control oscilla-tion (NCO) respectively Because it is also a kind of ADPLLthe design procedure of it is the same as the normal ADPLLTherefore it is indispensable to analyze the design procedureof the normal ADPLL The normal ADPLL is derived fromthe result of digitizing analogy PLL The analysis and designfor analogy PLL has been well known Some monographshave discussed some analogy PLLs which have differentorders [10] As it is sufficient for our QPSK demodulator touse a second-order ADPLL we just discuss the digitizingprocedure of a second-order analogy PLL

21 The Modeling for All-Digital Phase-Locked LoopFigure 1(a) shows the phase domain model of a second-orderanalogy PLL It consists of the PD modeled by a subtractorwith gain 119896119889 the loop filter which is modeled by a first-orderlow pass filter proportion integral filter with the 119904-domaintransfer function 119865(119904) = 119881119900(119904)119881119889(119904) = (1119904)((1205912119904 + 1)1205911)

to minimize the phase noise of the output of the PD 119881119889(119904)and a voltage control oscillator (VCO) tuned by 119881119889(119904) tomake the output phase 120579119900(119904) closed to the input phase 120579119894(119904)which acts like a radian frequency integrator as a result of119881119889(119904) = Δ119908119905 + Δ120601 and have the 119904-domain transfer function119881(119904) = 120579119900(119904)119881119888(119904) = 119896119900119904

From the above the analysis a set of equations describingthe 119904-domain transfer functions of the phase domain modelof a second-order analogy PLL can be obtained

119865 (119904) =119881119888 (119904)

119881119889 (119904)=1

119904

1205912119904 + 1

1205911

(1)

119881 (119904) =120579119900 (119904)

119881119888 (119904)=119870119900

119904 (2)

119867(119904) =120579119900 (119904)

120579119894 (119904)=

119870119889119865 (119904) 119881 (119904)

1 + 119870119889119865 (119904) 119881 (119904)=

2120585119908119899119904 + 1199082

119899

1199042 + 2120585119908119899119904 + 1199082119899

(3)

where119908119899 = radic1198961199001198961198891205911 is natural radian frequency 120585 = 12059121199081198992

is damping factor 119896119900 is the gain of the VCO 119896119889 is the gainof the PD 1205911 and 1205912 are time constants of the proportionintegral filter and 119867(119904) is the 119904-domain transfer function ofthe analogy PLL Please note that the above the equationsare just reasonable on the condition that the phase difference

International Journal of Reconfigurable Computing 3

Phasediscriminator

Loopfilter

Voltage controloscillator

120579i(s) ΔΦ(s)Kd F(s)

Vd(s) Vc(s)

120579o(s)

V(s) =Ko

s

(a) Phase domain model of a second-order analogy PLL

Phase discriminator

Loopfilter

Numericallycontrolled oscillator

120579i(z) ΔΦ(z)Kd F(z)

Vd(z) Vc(z)

120579o(z)

N(z)

(b) Phase domain model of a second-order ADPLL

Figure 1 The different modes of PLL

between 120579119894(119904) and 120579119900(119904)makes it possible for the PD to workwithin its linear range

To digitize the analogy PLL bilinear transformationwhich is often used to digitize analogy filter [11] is adoptedLetrsquos set the transformation as

119904 =2

119879119904

1 minus 119911minus1

1 + 119911minus1 (4)

where 119879119904 is the sample time of a discrete-time systemTaking (4) into (1) and (2) then we can obtain

119865 (119911) =119881119888 (119911)

119881119889 (119911)= 1198621 +

1198622

1 minus 119911minus1

119873 (119911) =120579119900 (119911)

119881119888 (119911)=

119896119900119911minus1

(1 minus 119911minus1)

(5)

where 1198621 = 12059121205911 minus 11987911990421205911 and 1198622 = 1198791199041205911Therefore as shown in Figure 1(b) the model of ADPLL

can be acquired On the basis of Figure 1(b) and the two equa-tions (5) the based-model discrete-time transfer function ofthe ADPLL can be expressed as

119867(119911) =120579119900 (119911)

120579119894 (119911)

=119896119889119896119900 (1198621 + 1198622) 119911

minus1minus 1198961198891198961199001198621119911

minus2

1 + [119896119889119896119900 (1198621 + 1198622) minus 2] 119911minus1 + (1 minus 1198961198891198961199001198621) 119911

minus2

(6)

22 Parameter Calculation of All-Digital Phase-Locked LoopForm (6) we can see that to obtain the based-model discrete-time transfer function of the ADPLL the values of theparameters 1198621 1198622 119896119889 and 119896119900 are needed However it isnot easy to calculate them after knowing about the model ofADPLL Nonetheless none of researches published presentthe procedure Thus in the following we will display how tocalculate them

First of all the method to acquire 1198621 and 1198622 is givenEquation (6) is just the 119911-domain transfer function based

on the model of Figure 1(b) and the two equations (5) Onthe other hand taking (4) into (3) and the 119911-domain transferfunction of the ADPLL based on bilinear transformation canbe obtained

119867(119885) = ([4120585119908119899119879119904 + (119908119899119879119904)2] + 2(119908119899119879119904)

2119911minus1

+ [(119908119899119879119904)2minus 4120585119908119899119879119904] 119911

minus2)

times ([4 + 4120585119908119899119879119904 + (119908119899119879119904)2] + [2(119908119899119879119904)

2minus 8] 119911

minus1

+ [4 + 4120585119908119899119879119904 + (119908119899119879119904)2] 119911minus2)minus1

(7)

Let us set the denominator of the two 119911-domain transferfunctions of the ADPLL (6) and (7) obtained by differentmethods to be equal and the two equations about 1198621 and 1198622can be given

1198621 =1

119870119889119870119889

8120585119908119899119879119904

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp2120585119908119899119879119904

119870119889119870119889

1198622 =1

119870119889119870119900

4(119908119899119879119904)2

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp(119908119899119879119904)

2

119870119889119870119900

(8)

where the two approximations are just true when 119908119899119879119904 ≪

1 Namely assuming that the PD of ADPLL lies in itslinear operation range and for ADPLL the characteristic offrequency response is within the range of its passband

Secondly on the basis of [12] when 120585 = 0707 second-order PLL can meet the optimal value of Wiener theory Sowe can get that 120585 = 0707

The third step is to determine 119908119899

4 International Journal of Reconfigurable Computing

For PLL the natural radian frequency 119908119899 determineslocked-in frequency range and the performance of sup-pressing noise The pair of contradictions between locked-in frequency range (loop noise bandwidth) and trackingprecision stem from it

In the following we are going to discuss the range of119908119899 from the two aspects fast capture bandwidth of ADPLLand its loop SNR so as to make a compromise between thelocked-in range and the tracking precision

In the case of ADPLL there are two kinds of noisesexternal phase noise and internal phase noise The externalnoise caused by additive white Gaussian noise (AWGN) isa main part which has an influence on the performance ofthe ADPLL and the internal noise caused by the finite wordlength effect can be improved by the reasonable selection ofword length Herein the impact on the selection of 119908119899 isexternal phase noise Thus we just take it into consideration

The channel of deep-space communication is quitebenign with AWGN being the dominating impairment [1]and thus the phase noise of ADPLL caused by AWGN can begiven by [13]

1205901205792= (

119878

119873)119894

minus1119861119871

119861119894

(9)

where 119861119894 is the bandwidth of input signal of the ADPLL(119878119873)119894 is its input SNR and 119861119871 is loop noise bandwidth

For the second-order ADPLL taking proportion integralfilter as its loop filter 119861119871 can be expressed as

119861119871 =119908119899

8120585(1 + 4120585

2) (10)

For ADPLL the ability to suppress noise can be reflectedby the loop SNR

(119878

119873)119871

=1

1205901205792= (

119878

119873)119894

119861119894

119861119871

(11)

It determines the size of phase jitter The result of linearanalysis [14] manifests that PLL cannot work normally until(119878119873)119871 ge 6119889119861

Taking (10) into (11) and considering that ADPLL canoperate normally the upper bound of 119908119899 can be expressedas

119908119899 le (119878

119873)119894

4120585119861119894

(1 + 41205852) 3 (12)

The tracking procedure of ADPLL contains frequencytracking and phase tracking and the former needs longertime than the latter In design of our ADCRL however wefirstly use maximum likelihood frequency offset estimator(MLFOE) to assist ADCOL to implement frequency trackingin that for MLFOE the speed of tracking a large frequencyoffset is superior to ADCOLTherefore we just take the phasetracking into consideration in the procedure of designing ourADCOL In the case of ADPLL the fast capture bandwidthis defined as the largest frequency offset which ensures that

ADPLL can be locked in the procedure of the phase trackingIt can be expressed as

Δ119908119897 = 2120585119908119899 (13)

To meet the frequency tracking in the presence withoutthe assistance of the MLFOE the lower bound of 119908119899 is givenby

119908119899 geΔ119908119897

2120585 (14)

Thus from (12) and (14) we can get acquire the range of 119908119899

Δ119908119897

2120585le 119908119899 le (

119878

119873)119894

4120585119861119894

(1 + 41205852) 3 (15)

Until now except for 119870119889 and 119870119900 the parameters neededfor calculating1198621 and1198622 have been acquired Because the119870119889and119870119900 are associated with some practical system parameterswe will discuss about them in the following

23 Parameter Calculation of All-Digital QPSK Phase-LockedLoop Based on FPGA In the above discussions we haveobtained the corresponding parameters for a normal ADPLLBut as mentioned at the beginning of Section 2 QPSKADCOL is also a kind of ADPLL Thus the above methodsare suitable for QPSK ADCOL

As shown in Figure 2 QPSK ADCOL is comprised ofthe PD covered by the shaded area loop filter surroundedby dashed line and numerically controlled oscillator (NCO)Now based on Figure 2 we begin to discuss how to obtain119870119889and119870119900

First of all the analogy-digital converter (ADC) shownin Figure 2 samples the modulated signals from transmitterRXIN(119905) and acquires a series of discrete-time signals sam-pled RXIN(119870119879119904)

RXIN (119896119879119904) =

119896

sum

119899=0

119868 (119899119879119904) cos (119908119894119899119879119904 + 120579119894)

+ 119876 (119899119879119904) sin (119908119894119899119879119904 + 120579119894)

(16)

where 119908119894 is the radian frequency of the signals sampled 120579119894is their initial phase and 119868(119899119879119904) and 119876(119899119879119904) are the QPSKsignals evaluated as plusmn1 in our design

Secondly the signals RXIN(119870119879119904) are mixed with the twooutputs of the NCO and then filtered to eliminate the doublefrequency components generated by the mixing The twosignals filtered can be expressed as

upper branch (in-phase branch)

119868119899 (119896119879119904) =1

2

119896

sum

119899=0

119868119899 (119899119879119904) cos (Δ119908119899119879119904 + Δ120579)

minus 119876119899 (119899119879119904) sin (Δ119908119899119879119904 + Δ120579)

(17)

International Journal of Reconfigurable Computing 5

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signal

from transmitter

0

1

Quadrature branch

In-phase branch

C1

C2

ud

timesminus1

timesminus1

Figure 2 Structure diagram of QPSK all-digital phase-locked loop

bottom branch (quadrature branch)

119876119899 (119896119879119904) =1

2

119896

sum

119899=0

119868119899 (119899119879119904) cos (Δ119908119899119879119904 + Δ120579)

+ 119876119899 (119899119879119904) sin (Δ119908119899119879119904 + Δ120579)

(18)

where Δ119908 is the radian frequency difference between signalssampled and the two outputs of the NCO and Δ120579 is theirinitial phase difference

Finally the function of the PD of the QPSK ADCOL isimplemented by the following

119906119889 (119896119879)= sign (119868119899 (119896119879119904)) 119876119899 (119896119879119904) minus sign (119876119899 (119896119879119904)) 119868119899 (119896119879119904) (19)

Herein to save hardware resources of FPGA the signdecision and the multiplication operation within (19) arereplaced by a multiplexer controlled by the most significantbit (MSB) of the outputs of the two low pass filtersand aninverter shown in Figure 2 (because the outputs of the twolow pass filters are signed numbers) Therefore the outputcharacteristic of the PD can be obtained

119906119889 (119870119879)

=

minus sin (Δ119908119870119879119904 + Δ120579) minus120587 lt Δ119908119870119879119904 + Δ120579 lt minus3

4120587

cos (Δ119908119870119879119904 + Δ120579) minus3

4120587 lt Δ119908119870119879119904 + Δ120579 lt minus

120587

4

sin (Δ119908119870119879119904 + Δ120579) minus120587

4lt Δ119908119870119879119904 + Δ120579 lt

120587

4

minus cos (Δ119908119870119879119904 + Δ120579)120587

4lt Δ119908119870119879119904 + Δ120579 lt

3

4120587

minus sin (Δ119908119870119879119904 + Δ120579)3

4120587 lt Δ119908119870119879119904 + Δ120579 lt 120587

(20)

0

0

02

04

06

08

Phase offset (radian)

Out

put a

mpl

itude

(V)

minus120587 minus31205874 minus1205874 1205874 31205874 120587

minus02

minus04

minus06

minus08

Figure 3 Phase offset versus output voltage amplitude of PD

Based on (20) the output characteristics curve of the PDcan be obtain and shown in Figure 3 From Figure 3 we cansee that only if the phase offset is within the linear range ofthe PD (minus1205874 sim 1205874) the gain 119870119889 of the PD approximatesto 1 namely the slope of the curve So this is also one reasonwhy we use MLFE to assist QPSK ADCOL to recover carrierquickly and precisely

Next we start with discussing the gain 119870119900 of the NCOIn [15] the authors implement NCO on a Xilinx FPGA in

three types of ways and the conclusion that themethod basedon Xilinx ROM is superior to the other two is acquiredThuswe select themethod based on Xilinx ROM to implement ourNCO [16]

On the basis of the principle of NCO the frequency of itsoutput signal can be expressed as

119891out =119891119904

2119873119908Δ120579 (119870119879119904) (21)

where 119891119904 = 1119879119904 is sample frequency 119882Δ120579(119870119879119904) is frequency

control word and 119873 is the bit width of the input signal of

6 International Journal of Reconfigurable Computing

0 5 10 15

0

10M

agni

tude

(dB)

minus10

minus20

times105Natural radian frequency wn (Hz)

(a) Frequency response characteristic

0 5 10 15

0

Phas

e (de

g)

minus50

minus100

times105Natural radian frequency wn (Hz)

(b) Phase response characteristic

Figure 4 QPSK ADCOL characteristic curve

NCO In our design119882Δ120579(119870119879119904) = 119882119888+119882119906119889 where119882119888 is a given

value determined by carrier frequency and its block diagramnamed as frequency controlword can be seen in Figure 2119882119906119889is the output of the loop filter that is tuned by the frequencyoffset between transmitter and receiver

So the radian frequency of NCO is given as

119882out = 2120587119891out =2120587119891119904

2119873119882Δ120579(119870119879

119904) (22)

On the basis of themodel of ADPLL shown in Figure 1(b)NCO is equivalent to a radian frequency integrator So theoutput phase of NCO is given as

120579out =2120587119891119904119879119894

2119873119882Δ120579(119870119879

119904) (23)

where 119879119894 is the update period of the frequency control word119882Δ120579(119870119879

119904) namely the sample period of the output of loop filter

119882119906119889 and is often set to be 8119879119904Therefore the gain 119870119900 of our NCO is given by

119870119900 =2120587119891119904

21198738119879119904 =

2120587

2119873minus3 (24)

So far we have obtained all methods to calculate theparameters of the QPSKADCOL whereas wemust note thatin our QPSK ADCOL based on FPGA shown in Figure 2 anextra gain will be introduced as the result of the changes ofthe bit width between the inputs and outputs of the differentmodules Regardless of the sign bit the bit width of the inputsof the two multipliers is 7 and the bit width of their outputsis 15 The bit width of the inputs of the two low pass filtersis 15 and the bit width of their outputs is 31 Thus the gainof the two multipliers is 215minus7 = 2

8 and the gain of the twolow pass filters is 231minus15 = 2

16 The rest of the parts showed inFigure 2 have no change in bit width between their inputs andoutputs Therefore the gain from the changes of bit width is28+16

= 224 and (8) should be rectified as

1198621 =1

119896119889119896119900224

8120585119908119899119879119904

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp2120585119908119899119879119904

119896119889119896119900224

1198621 =1

119896119889119896119900224

4(119908119899119879119904)2

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp(119908119899119879119904)

2

119896119889119896119900224

(25)

On the basis of the core idea of software defined radiothe parts of digital signal processing should be closed tothe front end of radio frequency (RF) as much as possibleTherefore we make our QPSK ADCOL operate in inter-mediate frequency (IF) namely the ADC sample frequency119891119904 = 26MHZ and carrier frequency (the output frequency ofNCO) 119891119888 = 4MHZ

On the other hand To ensure that our QPSKADCOL cannormally operate under the conditions of a large frequencyoffset and a low SNR let us set the fast capture bandwidthΔ119908119897 to be 100KHZ the least and the input SNR (119878119873) to be1 dB We have known that the gain of PD is 119870119889 = 1 and thedamping factor is 120585 asymp 0707 To decrease internal phase noisecaused by word length effect we set the bit width of inputsignal of NCO to be 119873 = 32 Therefore based on (15) (24)and (25) the range of the natural radian frequency119908119899 can beobtained and the one of the values is chosen as

119908119899 = 2120587 times 150 times 103= 0942 times 10

6(rads) (26)

Next take119870119889119870119900224 (25) and (26) into (6) we can obtain

themodel-based discrete-time transfer function of ourQPSKADCOL

119867(119911) =0053119911

minus1minus 0051119911

minus2

1 minus 1947119911minus1 + 0949119911minus2 (27)

From (27) the poles of our QPSK ADCOL can beobtained They are 0973 plusmn 0036119894 Based on the theory of thestability of discrete system the system is stable if all poles arelocated inside the unit circle Therefore our QPSK ADCOLis stable

Now the frequency response characteristic and phaseresponse characteristic of ourQPSKADCOL can be acquiredand shown in Figures 4(a) and 4(b) respectively

From Figures 4(a) and 4(b) we can see that when samplefrequency is 26MHZ the passband of our QPSK ADCOLranges from 0 to 200KHZ (namely 119908119899119879119904 ≪ 1 is true)and its margin of phase is 120 degree below Thus this alsoindicates that our QPSK ADCOL meets the conditions ofthe stability of negative feedback control system What ismore Figure 4(a) also displays that QPSK ADCOL is of theproperty of low pass

International Journal of Reconfigurable Computing 7

CORDICCORE

Maximum likelihood frequency estimator

Frequency discriminator

Qn(KTs)

In(KTs)

times2

times2

times4

timesminus1 Arctan (x) fsumΔ

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

Figure 5 The block diagram of the FD and MLFE (MLFOE)

Table 1 Two kinds of typical frequency discriminators

The algorithm used Frequency offset output Output characteristic Hardware complexitysig(lowastdot) times lowastcross(119896 minus 1)119879119904 minus 119896119879119904

sin[2(120579119896minus1 minus 120579119896)](119896 minus 1)119879119904 minus 119896119879119904

Nonlinear Moderate

cross(119896 minus 1)119879119904 minus 119896119879119904

sin(120579119896minus1 minus 120579119896)(119896 minus 1)119879119904 minus 119896119879119904

Nonlinear Simplelowastdot = 119868119899(119870119879119904) times 119868119899((119870 minus 1)119879119904) minus 119876119899(119870119879119904) times 119876119899((119870 minus 1)119879119904)lowastcross = 119868119899(119870119879119904) times 119876119899((119870 minus 1)119879119904) minus 119868119899((119870 minus 1)119879119904) times 119876119899(119870119879119904)

3 The Design of Phase Domain MaximumLikelihood Frequency Estimator and ItsFrequency Discriminator

31 The Frequency Discriminator of the Linear Characteris-tic To use MLFE to obtain an accurate frequency offsetthe performance of its FD is a key factor which must beconsidered Two kinds of FDs used widely are summarizedin Table 1 [17] From Table 1 we can see that they are allof nonlinear characteristic Because in the case of sin(Δ120579)sin(Δ120579) asymp Δ120579 is true only if Δ120579 varies within a small rangeHowever in deep space communication (or in the conditionthat a large Doppler shift is common) the approximation ishardly possible On the other hand to discriminate phaseoffset the dot product and cross-product from two samplepoints separated by a sample interval must be conductedand their results divide by the sample interval (120579 = 119908119905 =

2120587119891119905 namely 119891 = 1205792120587119905)Therefore we introduce a kind of FD in possession of lin-

ear characteristic and the ability to acquire the correspondingsignals of ourADCOL so as to transform them into the inputsof theMLFE Its block diagram surrounded by the dashed lineis shown in Figure 5

FromFigure 5 we can see that after a series of transforma-tions for the two equations (17) and (18) the two signals of thefront end of the CORDIC algorithm block can be obtainedThey are

cos (4Δ119908119870119879119904 + 4Δ120579) = cos (4 (2120587Δ119891119870119879119904 + Δ120579))

sin (4Δ119908119870119879119904 + 4Δ120579) = sin (4 (2120587Δ119891119870119879119904 + Δ120579)) (28)

Feed them into the CORDIC algorithm blockwhich implements the algorithm tanminus1(sin(4Δ119908119870119879119904 +

4Δ120579) cos(4Δ119908119870119879119904 + 4Δ120579)) and the phase offset4Δ119908119870119879119904 + 4Δ120579 = 4(2120587Δ119891119870119879119904 + Δ120579) can be acquiredAfter that the MLFE will be used to estimate the frequencyoffset Δ119891 It is clear that this is a procedure of resolvinglinearly frequency offset Because the CORDIC algorithmcan easily be implemented on FPGA just using snifters andadd operations [18] we just discuss about how to implementMLFE on FPGA using as few logic resources as possible

32 Phase Domain Maximum Likelihood Frequency Estima-tion Algorithm In the case of the FD shown in Figure 5a mapping transformation from Cartesian domain to phasedomain can be realized by CORDIC core and expressed as

119909 =

arctan(119876119896

119868119896

) 119868119896 gt 0

arctan(119876119896

119868119896

) minus 120587 119876119896 lt 0 119868119896 le 0

arctan(119876119896

119868119896

) + 120587 119876119896 gt 0 119868119896 le 0

(29)

where 119868119896 = cos(4Δ119908119870119879119904+4Δ120579) and119876119896 = sin(4Δ119908119870119879119904+4Δ120579)119909119896 is the discrete phase of 119896th sample point The amendmentof plusmn120587 is due to that the output range of our CORDIC core iswithin (minus120587 sim 120587)

To useMLFE for estimating frequency offset we first needto obtain the discrete phases of119872 continuous sample points(119909119896 0 le 119896 le 119872 minus 1) and then take the first sample point 1199090

8 International Journal of Reconfigurable Computing

as initial reference point to obtain119872 absolute phases whichcan be expressed as

119909119896 = 119909119896minus1 +

119909119896 minus 119909119896minus11003816100381610038161003816119909119896 minus 119909119896minus1

1003816100381610038161003816 lt 120587

119909119896 minus 119909119896minus1 + 2120587 119909119896 minus 119909119896minus1 lt minus120587

119909119896 minus 119909119896minus1 minus 2120587 119909119896 minus 119909119896minus1 gt 120587

1 le 119896 lt 119872 1199090 = 1199090

(30)

where 119909119896 (the output of our CORDIC core) is the discretephase of 119896th sample point and it ranges from minus120587 to 120587 119909119896 isan absolute phase of 119896th sample point which takes 1199090 as thepoint of reference and has no the limitation of phase rangingfrom minus120587 to 120587 The amendment of plusmn2120587 is due to the phasedifference between the (119896 minus 1)th sample point 119909119896minus1 and the119896th 119909119896 crosses over a cycle (2120587) of the outputof our CORDICcore

After that a recursive formula of the 119872 absolute phasescan be obtained

119909119896 = 4 times (2120587119870119879119904Δ119891 + Δ120579 + 119899119896) 0 le 119870 le 119872 minus 1 (31)

where 119899119896 is the phase noise caused by AWGN (for the sakeof simplicity we neglect it in (16) (17) (18) and (28)) 119879119904is the sample frequency Δ119891 is the frequency offset betweenthe output of the NCO and the modulated signal fromtransmitter and Δ120579 is initial phase difference of the twosignals When SNR is as low as 10 dB numerical results havebeen demonstrated that 119899119896 can be considered as the Gaussianapproximation accurate which has a zero mean and variance1205902 [19]Letrsquos set 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 to be 119911119896 namely

119911119896 = 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 0 le 119896 le 119872 minus 1 (32)

Equation (35) can be also written in vector form

119885 = Δ1198912120587119879119904120572 + Δ120579120573 + 119881 (33)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

= Δ1198912120587119879119904

[[[[[[

[

0

1

119872minus 2

119872 minus 1

]]]]]]

]

+ Δ120579

[[[[[

[

1

1

1

1

1

]]]]]

]

+

[[[[[[

[

11989901198991

119899119872minus2119899119872minus1

]]]]]]

]

(34)

Consequently 119885 is a Gaussian random vector with probabil-ity density function

119891119911 (119885) =1

radic(2120587)119872120590119872

exp[minus1003817100381710038171003817119885 minus Δ1198912120587119879119904120572 minus Δ120579120573

10038171003817100381710038172

21205902]

(35)

where sdot 2 = (119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)119879(119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)

The maximum likelihood estimators Δ119891 and Δ120579 can beobtained by equating the gradientnablaΔ119891Δ120579 log119891119911(119911) to zero andsolving a two-dimensional linear system

Δ119891(119911) =12

2120587119879119904 (119872 minus 1)119872 (119872 + 1)119865119879119885 (36)

120579 (119911) =6

119872 (119872 + 1)Θ119879119885 (37)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

119865 =

[[[[[[[[[[[[[

[

minus119872 minus 1

2

minus119872 minus 1

2+ 1

119872minus 1

2minus 1

119872 minus 1

2

]]]]]]]]]]]]]

]

Θ =

[[[[[[[[[[[[[

[

2119872 minus 1

32119872 minus 1

3minus 1

2119872 minus 1

3minus (119872 minus 2)

2119872 minus 1

3minus (119872 minus 1)

]]]]]]]]]]]]]

]

(38)

The maximum likelihood estimators in (36) and (37)are minimum variance unbiased estimations achieving theCramer Rao Bound [19 20] On the other side the higher theestimation accuracy is the larger the sample points 119872 andSNR are

Please note that (31) is 4119885119896 If we use (36) to estimatefrequency offset Δ119891 the value of estimation must multiply by4 In the case of FPGA the multiplication of 2119899 just needs toshift n bits towards the left

On the other hand in part 3 Section 2 we select updateperiod of frequency control word of the NCO to be 8119879119904Therefore to enable frequency offset estimation block shownin Figure 5 and the QPSK ADCOL shown in Figure 2 tooperate as synchronously as possible we set the number ofthe sample point of MLFE to be119872 = 8 Therefore based on(36) (34) (32) and (31) we can obtain the frequency offsetestimated

Δ119891 = 4Δ119891(119911) = 412

2120587119879119904 (8 minus 1) 8 (8 + 1)

times [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(39)

International Journal of Reconfigurable Computing 9

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 20dB

frequ

ency

offs

et (M

Hz)

(a) Signal-to-noise ratio is 20 dB

0 2 4 6 8 10

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 5dB

(b) Signal-to-noise ratio is 5 dB

Figure 6 Actual frequency offset versus estimation frequency offset under different signal-to-noise ratios

where119879119904 = 126MHZ is sample frequency and 119909119896 0 le 119870 le 7

is absolute phase generated by (30)Using Δ119891 to assist the QPSK ADCOL shown in Figure 2

to recover carrier quickly Δ119891 must be transformed intofrequency control world of the NCO On the basis of (21) wecan obtain frequency control world of Δ119891 that is

119908Δ119891 =Δ1198912119873

119891119904

(40)

Taking (39) into (40) we can get

119908Δ119891

=2119873

21120587[minus

8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(41)

where 119909119896 0 le 119870 le 7 are signed decimals which areexpressed as the fixed-point number with 3 bitsrsquo integernumber and 29 bitsrsquo decimal 119873 = 32 is bit width of inputsignal of the NCO Because frequency control world of NCOis an integer number the result of (41) should multiply by2minus29 so as to eliminate the affection of the decimal expressedby 29 bitsrsquo binary format Therefore actual frequency controlworld should be119908Δ119891

= 01213 [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(42)

Due to 01213 asymp 2minus3

minus 2minus8 maximum likelihood fre-

quency estimation can be implemented just using shifters andmultiply-accumulate units

In deep-space communication to confirm that the signalsburied by noise can be successfully detected by receiver aparameter named link margin is used to specify minimalSNR of the received signals In the practical design of thecommunication systems its value usually ranges from 3 dB to6 dB [21] In our design we select two types of linkmargins toinvestigate the performance of our frequency offset estimatorThey are the low linkmargin of 5 dB and the high linkmarginof 20 dB respectively Therefore we simulate our MLFEunder the condition of sample frequency 119891119879 = 26MHZ andcarrier frequency 119891119888 = 4MHZ by MATLAB The simulationresults are shown in Figure 6

From Figure 6 we can see that although the estimationrang of the frequency offset decreases along with the declineof SNR the range still approximates minus2MHZ sim 2MHZunder SRN = 5 dB In the case of low and mediumearth orbiting satellite where the greatest Doppler shiftsare plusmn100KHZ and plusmn200KHZ [22] respectively the rangcompletely meets as well

33 Entire Design of All-Digital Carrier Recovery Loop ofQPSK Figure 7 shows the block diagram of our ADCRLIt consists of the MLFOE in shadow and QPSK ADCOLsurrounded by dashed line respectively

First of all the frequency offset will be estimated roughlyand then transformed into the frequency control words ofthe NCO by MLFE to speed up QPSK ADCOL to quicklyimplement the tracking of the carrier

Secondly with the assistance of MLFOE the QPSKADCOL is locked quickly and then starts with tracking thecarrier precisely

FromFigure 7 we can see that the bit width of the outputsof the two low pass filters is 32 If we apply directly thewidth to MLFOE the cost of hardware resource for FPGAis considerable So in our design a truncated bit width willbe used To ensure that the impact of the truncation onthe performance of our system is minimal a simulation isconducted which uses different bit widths for the two inputsignals of MLFOE (the bit widths of the outputs of the twolow pass filters) and the widths range from 8 to 32 bits to test

10 International Journal of Reconfigurable Computing

ADC

Low pass filter

Low passfilter

RegReg

Numericallycontrolledoscillator

Frequency control word

01

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signalfrom transmitter

01

CORDICCORE

Maximumlikelihoodfrequencyestimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

Maximum likelihood frequency offset estimator

Qn(KTs)

In(KTs) times2

times2

times4

timesminus1 Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

timesminus1

timesminus1

k

sumn=0

cos(4ΔwnTs + 4120579)k

sumn=0

(4ΔwnTs + 4120579)

k

sumn=0

sin(4ΔwnTs + 4120579)

Figure 7 Block diagram of QPSK ADCRL

which one is the best for the frequency offset error Δ119891 =

100KHZ under the situations of SNR = 20 10 5 dB Thesimulation result is shown in Figure 8 From Figure 8 it isclear that when the bit width is equal to 11 the frequencyestimation value of the MLFOE is almost the same as that ofhaving bit width equal to 32 under the three types of SNRsThus we set the bit width of the two inputs of MLFOE to be11

4 Simulation Results andComparative Analysis

To verify that the proposed architecture is valid the FPGAsimulation tool ModelSim SE 65 is used to observe theimplementation performance of our proposed architecturebased on FPGA On the other hand MATLAB is also usedto generate the QPSK modulated signals with a frequencyoffset under the conditions of different SNRs and process thesimulation results generated by the ModelSim so as to have abetter visual comparison resulting from that the outputs ofthe ModelSim that are just some values of decimal or binaryformat

The data streams of the entire simulation procedure areshown in Figure 9

The input stream generated quantized and stored into thetextfile Textfile A by MATLAB is QPSK modulated signalswith the following specifications

5 10 15 20 25 30 3565

70

75

80

85

90

95

100

105

Quantization size (bit)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

(kH

z)

SNR = 5dBSNR = 10dBSNR = 20dB

Figure 8The quantization level of the two input signals of MLFOEunder the condition of the frequency offset errorΔ119891 = 100KHZ andSNR = 20 10 5 dB

(i) the number of symbols randomly evaluated as plusmn1 isequal to 1000

(ii) the frequency of symbols 119891119887 = 80KHZ(iii) the frequency of carrier 119891119888 = 39MHZ namely

frequency offset Δ119891 = 100KHZ(iv) SNRs are 20 dB and 5 dB

International Journal of Reconfigurable Computing 11

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

01

CORDICCORE

Maximum likelihood frequency estimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

The output

of loop

filter

The output

ofNCO

QPSK

modulated

signal

MATLAB simulation

ModelSim simulation

Maximum likelihood frequency offset estimatorTextfile A

Textfile B Textfile C

Qn(KTs)

In(KTs) times2

times4

times2

timesminus1

timesminus1

timesminus1

Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

MATLAB process AMATLAB process B

Figure 9 The data stream of entire simulation procedure

(v) quantization level of the 1000 QPSK modulated sig-nals is 8 bits to imitate the input signals of 8-bit ADC

(vi) sample frequency 119891119904 = 26MHZ

The output streams generated and stored into anothertwo textfiles Textfile B and Textfile C by ModelSim are theoutputs of the NCO and the loop filter with the followingspecifications

Textfile B(i) the frequency of carrier 119891119888 = 4MHZ namely output

frequency of NCO(ii) sample frequency 119891119904 = 26MHZ(iii) the quantization level of the output amplitude of the

NCO evaluated as plusmn1 is 8 bitsTextfile C

(i) sample frequency 119891119904 = 26MHZ(ii) the quantization level of the output of the loop filter is

32 bits

Textfile A is generated byMATLAB before startingMod-elSim simulation and then fed into QPSK ADCRL (to imitatethe output of the ADC) in the procedure of the simulation ofModelSimwhenTextfile B andTextfile C are simultaneouslygenerated by ModelSim At the end of the simulation of theModelSim the two files from the ModelSim Textfile B andTextfile C will be read into MATLAB in order to furtherprocess in the two procedures MATLAB process A andMATLAB process B

Because the traditional measure of the performance ofPLL is based on locked-in time steady-state phase error and

locked-in frequency range our QPSK ADCRL also uses themethods

Based on the principle of our QPSK ADCRL displayedin Figure 7 when there exists the frequency offset betweenthe input of the QPSK modulated signals (Textfile A) andthe local carrier signals (the output of NCO) the offset canbe obtained through taking the output of the loop filter(Textfile C) into (21) In our design the carrier frequency ofthe input modulated signals is 39MHZ and the frequencyof the output of the NCO is 4MHZ Therefore the frequencyoffset is 100KHZ

If our QPSK ADCRL is locked the frequency offsetevaluated through taking the output of loop filter into (21) willapproximate to 100KHZ At the same time the output phaseof the NCO (Textfile B) should be equal or approximate tothe phase of the QPSK modulated signals (Textfile A)

On the basis of above discussion as shown in Figures 1011 12 and 13 (a) and (b) are the outputs of the loop filter fromModelSim simulation and its results processed by MATLAB(MATLAB process B shown in Figure 8) respectively (c) isthe result of the phase comparison of the two signals QPSKmodulated signals and the outputs of theNCOwhich is fromthe simulation ofModelSim and then processed byMATLAB(MATLAB process A shown in Figure 9)

Figures 10 and 11 are the simulation results of the classicQPSK ADCOL shown in Figure 2 without the assistance ofMLFOE shown in Figure 6 under the two conditions of SNR= 20 and 5 dB

From the two figures Figures 10(b) and 10(c) we can seethat when SNR is equal to 20 dB the tracking time is about015ms and the maximal steady-state phase error approxi-mates to 0 degree

12 International Journal of Reconfigurable Computing

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

0

10

20

Time (ms)

Freq

uenc

y off

set (

Hz)

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1N

orm

aliz

ed v

olta

ge (V

)

MATLAB outputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 10 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for the QPSK ADCOL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 11 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for the QPSK ADCOL

As shown in the two figures Figures 11(b) and 11(c) whenSNR is equal to 5 dB the tracking time is about 03ms and themaximal steady-state phase error approximates to 2 degree

Figures 12 and 13 are the simulation results under the twoconditions of SNR = 20 and 5 dB where theMLFOE has beenenabled

In contrast to Figures 10 and 11 after enabling theMLFOEfrom the two figures Figures 12(b) and 12(c) we can seethat when SNR is equal to 20 dB the locked-in time isabout 005ms and the maximal steady-state phase error alsoapproximates to 0 degree As shown in the two figuresFigures 13(b) and 13(c) when SNR is equal to 5 dB the lock-in

International Journal of Reconfigurable Computing 13

(a) ModelSim output of loop filter

0 005 01 015 02 025

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0

0

05 1 15 2 25 3 35 4

051

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

minus05

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 12 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

20

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 13 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for our QPSK ADCRL

time is about 01ms and themaximal steady-state phase errorapproximates to 3 degree

On the other hand in the case of the four figures Figures10(b) 11(b) 12(b) and 13(b) when QPSK ADCRL is lockedall frequency offset evaluated by the output of loop filter areequal to 100KHZ

From the above simulation results it is clear that after theMLFOE is enabled whether SNR is high or not the perform-ance of our QPSK ADCRL in locked-in time is two times

faster than that of the QPSK ADCOL without the assistanceof the MLFOE while the maximal steady-state phase error isalmost stable

On the other hand in the two conditions of SNR =20 dB and 5 dB we test the maximal frequency offset whichenables our QPSK ADCRL and the QPSK ADCOL withoutthe assistance of MLFOE to be locked and the correspondinglocked-in time and steady-phase error The results are shownin Table 2 From Table 2 we can see that after the MLFOE

14 International Journal of Reconfigurable Computing

Table 2 The performance advantage of our QPSK ADCRL in locked-in frequency range

SNR Architecture Maximal locked-in Locked-in time (ms) Steady-phase error (degree)Frequency Range (KHZ)

20 db QPSK ADCOL plusmn170 018 Approximating to 020 db Our QPSK ADCRL plusmn680 005 Approximating to 05 db QPSK ADCOL plusmn120 04 Approximating to 25 db Our QPSK ADCRL plusmn510 013 Approximating to 4

Table 3 The hardware cost of the different modules for our QPSK ADCRL

Module Number of slice registers Number of slice LUTs Number used as logicQPSK ADCOL 174 out of 28800 580 out of 28800 612 out of 28800

MLFOE FD 875 out of 28800 892 out of 28800 790 out of 28800MLFE 603 out of 28800 516 out of 28800 592 out of 28800

Total hardware cost 1652 out of 28800 1988 out of 28800 1994 out of 28800

Table 4 The power consumption of our QPSK ADCRL for different operating frequencies

Clock frequency (MHZ) Dynamic power (W) Quiescent power (W) Total power (W) Junction temp (C)312 0060 0526 0594 509250 0058 0526 0583 51200 0048 0525 0574 51150 0039 0525 0564 509

is enabled except for the advantage in locked-in time thelocked-in frequency range of our QPSKADCRL is four timeswider than that of the QPSK ADCOL Therefore our QPSKADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision which are hardlyreconciled for the QPSK ADCOL

There is no doubt that our QPSK ADCRL has a morerobust performance than the QPSK ADCOL without theMLFOE What is more to obtain the same improvement inperformance as our ADCRL for the existing QPSK ADCOL[23 24] the simple revision is to add the MLFOE shown inFigure 4 to the QPSK ADCOLs

Finally in order to acquire their hardware cost for thedifferent modules of our QPSK ADCRL based on FPGA theFPGA synthesis tool ISE Design Suite 122 from FPGA ven-dor Xilinx is used and its chip of Virtex5 family XC5VLX50which supports dynamic reconfiguration technology seenas a core technology to implement SDR [25] on FPGA isselected The synthesis results are given in Table 3 FromTable 3 we can see that although the MLFOE consumesmore logic resources than QPSK ADCOL (because manymultiplication operations are used and a pipelined CORDICarchitecture [26] is adopted so as to meet the requirement ofthe latency time) this is worthy for some applications whichneed a more robust QPSK ADCRL

On the other hand we can also see that the hardware costof the whole QPSK ADCRL just make up a small part of logicresources for the FPGA chip selected

Except for the hardware cost of our QPSK ADCRL wealso investigate its power consumption for the different

operating frequencies by the power analysis tool from Xil-inx XPower which is also important very much in someapplications where communication systems need to workcontinuously bymeans of a portable power sourceThe resultsare shown in Table 4 Form Table 4 we can see that when ourQPSK ADCRL operates under the condition of maximumclock frequency 312MHZ which is from the logic synthesisrsquosresult of ISE 122 the total power is just 0594 (W)

5 Conclusion and Outlook

In this paper an efficient QPSK ADCRL is proposed and asystematic procedure of designing the carrier recovery loopbased on FPGA is displayed On the other hand a FD in pos-session of linear characteristic is introduced to supply a moreprecise frequency offset to MLFE which is implemented justusing shifters and multiply-accumulate units to estimate thefrequency offset and assist QPSK ADCOL to lock quicklyThe joint simulation results of ModelSim and MATLAB hasproved that our proposed architecture can smoothly operateon FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOLSynthesis result has shown that the hardware cost of FPGAfor our QPSK ADCRL is very few and the result of the poweranalysis also has proved that our design is valid in powerconsumption

Looking at the future the exploration aiming at deepspace must be the tendency of the human developmentand the FPGA-based soft defined radio suitable for the

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

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Page 3: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

International Journal of Reconfigurable Computing 3

Phasediscriminator

Loopfilter

Voltage controloscillator

120579i(s) ΔΦ(s)Kd F(s)

Vd(s) Vc(s)

120579o(s)

V(s) =Ko

s

(a) Phase domain model of a second-order analogy PLL

Phase discriminator

Loopfilter

Numericallycontrolled oscillator

120579i(z) ΔΦ(z)Kd F(z)

Vd(z) Vc(z)

120579o(z)

N(z)

(b) Phase domain model of a second-order ADPLL

Figure 1 The different modes of PLL

between 120579119894(119904) and 120579119900(119904)makes it possible for the PD to workwithin its linear range

To digitize the analogy PLL bilinear transformationwhich is often used to digitize analogy filter [11] is adoptedLetrsquos set the transformation as

119904 =2

119879119904

1 minus 119911minus1

1 + 119911minus1 (4)

where 119879119904 is the sample time of a discrete-time systemTaking (4) into (1) and (2) then we can obtain

119865 (119911) =119881119888 (119911)

119881119889 (119911)= 1198621 +

1198622

1 minus 119911minus1

119873 (119911) =120579119900 (119911)

119881119888 (119911)=

119896119900119911minus1

(1 minus 119911minus1)

(5)

where 1198621 = 12059121205911 minus 11987911990421205911 and 1198622 = 1198791199041205911Therefore as shown in Figure 1(b) the model of ADPLL

can be acquired On the basis of Figure 1(b) and the two equa-tions (5) the based-model discrete-time transfer function ofthe ADPLL can be expressed as

119867(119911) =120579119900 (119911)

120579119894 (119911)

=119896119889119896119900 (1198621 + 1198622) 119911

minus1minus 1198961198891198961199001198621119911

minus2

1 + [119896119889119896119900 (1198621 + 1198622) minus 2] 119911minus1 + (1 minus 1198961198891198961199001198621) 119911

minus2

(6)

22 Parameter Calculation of All-Digital Phase-Locked LoopForm (6) we can see that to obtain the based-model discrete-time transfer function of the ADPLL the values of theparameters 1198621 1198622 119896119889 and 119896119900 are needed However it isnot easy to calculate them after knowing about the model ofADPLL Nonetheless none of researches published presentthe procedure Thus in the following we will display how tocalculate them

First of all the method to acquire 1198621 and 1198622 is givenEquation (6) is just the 119911-domain transfer function based

on the model of Figure 1(b) and the two equations (5) Onthe other hand taking (4) into (3) and the 119911-domain transferfunction of the ADPLL based on bilinear transformation canbe obtained

119867(119885) = ([4120585119908119899119879119904 + (119908119899119879119904)2] + 2(119908119899119879119904)

2119911minus1

+ [(119908119899119879119904)2minus 4120585119908119899119879119904] 119911

minus2)

times ([4 + 4120585119908119899119879119904 + (119908119899119879119904)2] + [2(119908119899119879119904)

2minus 8] 119911

minus1

+ [4 + 4120585119908119899119879119904 + (119908119899119879119904)2] 119911minus2)minus1

(7)

Let us set the denominator of the two 119911-domain transferfunctions of the ADPLL (6) and (7) obtained by differentmethods to be equal and the two equations about 1198621 and 1198622can be given

1198621 =1

119870119889119870119889

8120585119908119899119879119904

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp2120585119908119899119879119904

119870119889119870119889

1198622 =1

119870119889119870119900

4(119908119899119879119904)2

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp(119908119899119879119904)

2

119870119889119870119900

(8)

where the two approximations are just true when 119908119899119879119904 ≪

1 Namely assuming that the PD of ADPLL lies in itslinear operation range and for ADPLL the characteristic offrequency response is within the range of its passband

Secondly on the basis of [12] when 120585 = 0707 second-order PLL can meet the optimal value of Wiener theory Sowe can get that 120585 = 0707

The third step is to determine 119908119899

4 International Journal of Reconfigurable Computing

For PLL the natural radian frequency 119908119899 determineslocked-in frequency range and the performance of sup-pressing noise The pair of contradictions between locked-in frequency range (loop noise bandwidth) and trackingprecision stem from it

In the following we are going to discuss the range of119908119899 from the two aspects fast capture bandwidth of ADPLLand its loop SNR so as to make a compromise between thelocked-in range and the tracking precision

In the case of ADPLL there are two kinds of noisesexternal phase noise and internal phase noise The externalnoise caused by additive white Gaussian noise (AWGN) isa main part which has an influence on the performance ofthe ADPLL and the internal noise caused by the finite wordlength effect can be improved by the reasonable selection ofword length Herein the impact on the selection of 119908119899 isexternal phase noise Thus we just take it into consideration

The channel of deep-space communication is quitebenign with AWGN being the dominating impairment [1]and thus the phase noise of ADPLL caused by AWGN can begiven by [13]

1205901205792= (

119878

119873)119894

minus1119861119871

119861119894

(9)

where 119861119894 is the bandwidth of input signal of the ADPLL(119878119873)119894 is its input SNR and 119861119871 is loop noise bandwidth

For the second-order ADPLL taking proportion integralfilter as its loop filter 119861119871 can be expressed as

119861119871 =119908119899

8120585(1 + 4120585

2) (10)

For ADPLL the ability to suppress noise can be reflectedby the loop SNR

(119878

119873)119871

=1

1205901205792= (

119878

119873)119894

119861119894

119861119871

(11)

It determines the size of phase jitter The result of linearanalysis [14] manifests that PLL cannot work normally until(119878119873)119871 ge 6119889119861

Taking (10) into (11) and considering that ADPLL canoperate normally the upper bound of 119908119899 can be expressedas

119908119899 le (119878

119873)119894

4120585119861119894

(1 + 41205852) 3 (12)

The tracking procedure of ADPLL contains frequencytracking and phase tracking and the former needs longertime than the latter In design of our ADCRL however wefirstly use maximum likelihood frequency offset estimator(MLFOE) to assist ADCOL to implement frequency trackingin that for MLFOE the speed of tracking a large frequencyoffset is superior to ADCOLTherefore we just take the phasetracking into consideration in the procedure of designing ourADCOL In the case of ADPLL the fast capture bandwidthis defined as the largest frequency offset which ensures that

ADPLL can be locked in the procedure of the phase trackingIt can be expressed as

Δ119908119897 = 2120585119908119899 (13)

To meet the frequency tracking in the presence withoutthe assistance of the MLFOE the lower bound of 119908119899 is givenby

119908119899 geΔ119908119897

2120585 (14)

Thus from (12) and (14) we can get acquire the range of 119908119899

Δ119908119897

2120585le 119908119899 le (

119878

119873)119894

4120585119861119894

(1 + 41205852) 3 (15)

Until now except for 119870119889 and 119870119900 the parameters neededfor calculating1198621 and1198622 have been acquired Because the119870119889and119870119900 are associated with some practical system parameterswe will discuss about them in the following

23 Parameter Calculation of All-Digital QPSK Phase-LockedLoop Based on FPGA In the above discussions we haveobtained the corresponding parameters for a normal ADPLLBut as mentioned at the beginning of Section 2 QPSKADCOL is also a kind of ADPLL Thus the above methodsare suitable for QPSK ADCOL

As shown in Figure 2 QPSK ADCOL is comprised ofthe PD covered by the shaded area loop filter surroundedby dashed line and numerically controlled oscillator (NCO)Now based on Figure 2 we begin to discuss how to obtain119870119889and119870119900

First of all the analogy-digital converter (ADC) shownin Figure 2 samples the modulated signals from transmitterRXIN(119905) and acquires a series of discrete-time signals sam-pled RXIN(119870119879119904)

RXIN (119896119879119904) =

119896

sum

119899=0

119868 (119899119879119904) cos (119908119894119899119879119904 + 120579119894)

+ 119876 (119899119879119904) sin (119908119894119899119879119904 + 120579119894)

(16)

where 119908119894 is the radian frequency of the signals sampled 120579119894is their initial phase and 119868(119899119879119904) and 119876(119899119879119904) are the QPSKsignals evaluated as plusmn1 in our design

Secondly the signals RXIN(119870119879119904) are mixed with the twooutputs of the NCO and then filtered to eliminate the doublefrequency components generated by the mixing The twosignals filtered can be expressed as

upper branch (in-phase branch)

119868119899 (119896119879119904) =1

2

119896

sum

119899=0

119868119899 (119899119879119904) cos (Δ119908119899119879119904 + Δ120579)

minus 119876119899 (119899119879119904) sin (Δ119908119899119879119904 + Δ120579)

(17)

International Journal of Reconfigurable Computing 5

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signal

from transmitter

0

1

Quadrature branch

In-phase branch

C1

C2

ud

timesminus1

timesminus1

Figure 2 Structure diagram of QPSK all-digital phase-locked loop

bottom branch (quadrature branch)

119876119899 (119896119879119904) =1

2

119896

sum

119899=0

119868119899 (119899119879119904) cos (Δ119908119899119879119904 + Δ120579)

+ 119876119899 (119899119879119904) sin (Δ119908119899119879119904 + Δ120579)

(18)

where Δ119908 is the radian frequency difference between signalssampled and the two outputs of the NCO and Δ120579 is theirinitial phase difference

Finally the function of the PD of the QPSK ADCOL isimplemented by the following

119906119889 (119896119879)= sign (119868119899 (119896119879119904)) 119876119899 (119896119879119904) minus sign (119876119899 (119896119879119904)) 119868119899 (119896119879119904) (19)

Herein to save hardware resources of FPGA the signdecision and the multiplication operation within (19) arereplaced by a multiplexer controlled by the most significantbit (MSB) of the outputs of the two low pass filtersand aninverter shown in Figure 2 (because the outputs of the twolow pass filters are signed numbers) Therefore the outputcharacteristic of the PD can be obtained

119906119889 (119870119879)

=

minus sin (Δ119908119870119879119904 + Δ120579) minus120587 lt Δ119908119870119879119904 + Δ120579 lt minus3

4120587

cos (Δ119908119870119879119904 + Δ120579) minus3

4120587 lt Δ119908119870119879119904 + Δ120579 lt minus

120587

4

sin (Δ119908119870119879119904 + Δ120579) minus120587

4lt Δ119908119870119879119904 + Δ120579 lt

120587

4

minus cos (Δ119908119870119879119904 + Δ120579)120587

4lt Δ119908119870119879119904 + Δ120579 lt

3

4120587

minus sin (Δ119908119870119879119904 + Δ120579)3

4120587 lt Δ119908119870119879119904 + Δ120579 lt 120587

(20)

0

0

02

04

06

08

Phase offset (radian)

Out

put a

mpl

itude

(V)

minus120587 minus31205874 minus1205874 1205874 31205874 120587

minus02

minus04

minus06

minus08

Figure 3 Phase offset versus output voltage amplitude of PD

Based on (20) the output characteristics curve of the PDcan be obtain and shown in Figure 3 From Figure 3 we cansee that only if the phase offset is within the linear range ofthe PD (minus1205874 sim 1205874) the gain 119870119889 of the PD approximatesto 1 namely the slope of the curve So this is also one reasonwhy we use MLFE to assist QPSK ADCOL to recover carrierquickly and precisely

Next we start with discussing the gain 119870119900 of the NCOIn [15] the authors implement NCO on a Xilinx FPGA in

three types of ways and the conclusion that themethod basedon Xilinx ROM is superior to the other two is acquiredThuswe select themethod based on Xilinx ROM to implement ourNCO [16]

On the basis of the principle of NCO the frequency of itsoutput signal can be expressed as

119891out =119891119904

2119873119908Δ120579 (119870119879119904) (21)

where 119891119904 = 1119879119904 is sample frequency 119882Δ120579(119870119879119904) is frequency

control word and 119873 is the bit width of the input signal of

6 International Journal of Reconfigurable Computing

0 5 10 15

0

10M

agni

tude

(dB)

minus10

minus20

times105Natural radian frequency wn (Hz)

(a) Frequency response characteristic

0 5 10 15

0

Phas

e (de

g)

minus50

minus100

times105Natural radian frequency wn (Hz)

(b) Phase response characteristic

Figure 4 QPSK ADCOL characteristic curve

NCO In our design119882Δ120579(119870119879119904) = 119882119888+119882119906119889 where119882119888 is a given

value determined by carrier frequency and its block diagramnamed as frequency controlword can be seen in Figure 2119882119906119889is the output of the loop filter that is tuned by the frequencyoffset between transmitter and receiver

So the radian frequency of NCO is given as

119882out = 2120587119891out =2120587119891119904

2119873119882Δ120579(119870119879

119904) (22)

On the basis of themodel of ADPLL shown in Figure 1(b)NCO is equivalent to a radian frequency integrator So theoutput phase of NCO is given as

120579out =2120587119891119904119879119894

2119873119882Δ120579(119870119879

119904) (23)

where 119879119894 is the update period of the frequency control word119882Δ120579(119870119879

119904) namely the sample period of the output of loop filter

119882119906119889 and is often set to be 8119879119904Therefore the gain 119870119900 of our NCO is given by

119870119900 =2120587119891119904

21198738119879119904 =

2120587

2119873minus3 (24)

So far we have obtained all methods to calculate theparameters of the QPSKADCOL whereas wemust note thatin our QPSK ADCOL based on FPGA shown in Figure 2 anextra gain will be introduced as the result of the changes ofthe bit width between the inputs and outputs of the differentmodules Regardless of the sign bit the bit width of the inputsof the two multipliers is 7 and the bit width of their outputsis 15 The bit width of the inputs of the two low pass filtersis 15 and the bit width of their outputs is 31 Thus the gainof the two multipliers is 215minus7 = 2

8 and the gain of the twolow pass filters is 231minus15 = 2

16 The rest of the parts showed inFigure 2 have no change in bit width between their inputs andoutputs Therefore the gain from the changes of bit width is28+16

= 224 and (8) should be rectified as

1198621 =1

119896119889119896119900224

8120585119908119899119879119904

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp2120585119908119899119879119904

119896119889119896119900224

1198621 =1

119896119889119896119900224

4(119908119899119879119904)2

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp(119908119899119879119904)

2

119896119889119896119900224

(25)

On the basis of the core idea of software defined radiothe parts of digital signal processing should be closed tothe front end of radio frequency (RF) as much as possibleTherefore we make our QPSK ADCOL operate in inter-mediate frequency (IF) namely the ADC sample frequency119891119904 = 26MHZ and carrier frequency (the output frequency ofNCO) 119891119888 = 4MHZ

On the other hand To ensure that our QPSKADCOL cannormally operate under the conditions of a large frequencyoffset and a low SNR let us set the fast capture bandwidthΔ119908119897 to be 100KHZ the least and the input SNR (119878119873) to be1 dB We have known that the gain of PD is 119870119889 = 1 and thedamping factor is 120585 asymp 0707 To decrease internal phase noisecaused by word length effect we set the bit width of inputsignal of NCO to be 119873 = 32 Therefore based on (15) (24)and (25) the range of the natural radian frequency119908119899 can beobtained and the one of the values is chosen as

119908119899 = 2120587 times 150 times 103= 0942 times 10

6(rads) (26)

Next take119870119889119870119900224 (25) and (26) into (6) we can obtain

themodel-based discrete-time transfer function of ourQPSKADCOL

119867(119911) =0053119911

minus1minus 0051119911

minus2

1 minus 1947119911minus1 + 0949119911minus2 (27)

From (27) the poles of our QPSK ADCOL can beobtained They are 0973 plusmn 0036119894 Based on the theory of thestability of discrete system the system is stable if all poles arelocated inside the unit circle Therefore our QPSK ADCOLis stable

Now the frequency response characteristic and phaseresponse characteristic of ourQPSKADCOL can be acquiredand shown in Figures 4(a) and 4(b) respectively

From Figures 4(a) and 4(b) we can see that when samplefrequency is 26MHZ the passband of our QPSK ADCOLranges from 0 to 200KHZ (namely 119908119899119879119904 ≪ 1 is true)and its margin of phase is 120 degree below Thus this alsoindicates that our QPSK ADCOL meets the conditions ofthe stability of negative feedback control system What ismore Figure 4(a) also displays that QPSK ADCOL is of theproperty of low pass

International Journal of Reconfigurable Computing 7

CORDICCORE

Maximum likelihood frequency estimator

Frequency discriminator

Qn(KTs)

In(KTs)

times2

times2

times4

timesminus1 Arctan (x) fsumΔ

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

Figure 5 The block diagram of the FD and MLFE (MLFOE)

Table 1 Two kinds of typical frequency discriminators

The algorithm used Frequency offset output Output characteristic Hardware complexitysig(lowastdot) times lowastcross(119896 minus 1)119879119904 minus 119896119879119904

sin[2(120579119896minus1 minus 120579119896)](119896 minus 1)119879119904 minus 119896119879119904

Nonlinear Moderate

cross(119896 minus 1)119879119904 minus 119896119879119904

sin(120579119896minus1 minus 120579119896)(119896 minus 1)119879119904 minus 119896119879119904

Nonlinear Simplelowastdot = 119868119899(119870119879119904) times 119868119899((119870 minus 1)119879119904) minus 119876119899(119870119879119904) times 119876119899((119870 minus 1)119879119904)lowastcross = 119868119899(119870119879119904) times 119876119899((119870 minus 1)119879119904) minus 119868119899((119870 minus 1)119879119904) times 119876119899(119870119879119904)

3 The Design of Phase Domain MaximumLikelihood Frequency Estimator and ItsFrequency Discriminator

31 The Frequency Discriminator of the Linear Characteris-tic To use MLFE to obtain an accurate frequency offsetthe performance of its FD is a key factor which must beconsidered Two kinds of FDs used widely are summarizedin Table 1 [17] From Table 1 we can see that they are allof nonlinear characteristic Because in the case of sin(Δ120579)sin(Δ120579) asymp Δ120579 is true only if Δ120579 varies within a small rangeHowever in deep space communication (or in the conditionthat a large Doppler shift is common) the approximation ishardly possible On the other hand to discriminate phaseoffset the dot product and cross-product from two samplepoints separated by a sample interval must be conductedand their results divide by the sample interval (120579 = 119908119905 =

2120587119891119905 namely 119891 = 1205792120587119905)Therefore we introduce a kind of FD in possession of lin-

ear characteristic and the ability to acquire the correspondingsignals of ourADCOL so as to transform them into the inputsof theMLFE Its block diagram surrounded by the dashed lineis shown in Figure 5

FromFigure 5 we can see that after a series of transforma-tions for the two equations (17) and (18) the two signals of thefront end of the CORDIC algorithm block can be obtainedThey are

cos (4Δ119908119870119879119904 + 4Δ120579) = cos (4 (2120587Δ119891119870119879119904 + Δ120579))

sin (4Δ119908119870119879119904 + 4Δ120579) = sin (4 (2120587Δ119891119870119879119904 + Δ120579)) (28)

Feed them into the CORDIC algorithm blockwhich implements the algorithm tanminus1(sin(4Δ119908119870119879119904 +

4Δ120579) cos(4Δ119908119870119879119904 + 4Δ120579)) and the phase offset4Δ119908119870119879119904 + 4Δ120579 = 4(2120587Δ119891119870119879119904 + Δ120579) can be acquiredAfter that the MLFE will be used to estimate the frequencyoffset Δ119891 It is clear that this is a procedure of resolvinglinearly frequency offset Because the CORDIC algorithmcan easily be implemented on FPGA just using snifters andadd operations [18] we just discuss about how to implementMLFE on FPGA using as few logic resources as possible

32 Phase Domain Maximum Likelihood Frequency Estima-tion Algorithm In the case of the FD shown in Figure 5a mapping transformation from Cartesian domain to phasedomain can be realized by CORDIC core and expressed as

119909 =

arctan(119876119896

119868119896

) 119868119896 gt 0

arctan(119876119896

119868119896

) minus 120587 119876119896 lt 0 119868119896 le 0

arctan(119876119896

119868119896

) + 120587 119876119896 gt 0 119868119896 le 0

(29)

where 119868119896 = cos(4Δ119908119870119879119904+4Δ120579) and119876119896 = sin(4Δ119908119870119879119904+4Δ120579)119909119896 is the discrete phase of 119896th sample point The amendmentof plusmn120587 is due to that the output range of our CORDIC core iswithin (minus120587 sim 120587)

To useMLFE for estimating frequency offset we first needto obtain the discrete phases of119872 continuous sample points(119909119896 0 le 119896 le 119872 minus 1) and then take the first sample point 1199090

8 International Journal of Reconfigurable Computing

as initial reference point to obtain119872 absolute phases whichcan be expressed as

119909119896 = 119909119896minus1 +

119909119896 minus 119909119896minus11003816100381610038161003816119909119896 minus 119909119896minus1

1003816100381610038161003816 lt 120587

119909119896 minus 119909119896minus1 + 2120587 119909119896 minus 119909119896minus1 lt minus120587

119909119896 minus 119909119896minus1 minus 2120587 119909119896 minus 119909119896minus1 gt 120587

1 le 119896 lt 119872 1199090 = 1199090

(30)

where 119909119896 (the output of our CORDIC core) is the discretephase of 119896th sample point and it ranges from minus120587 to 120587 119909119896 isan absolute phase of 119896th sample point which takes 1199090 as thepoint of reference and has no the limitation of phase rangingfrom minus120587 to 120587 The amendment of plusmn2120587 is due to the phasedifference between the (119896 minus 1)th sample point 119909119896minus1 and the119896th 119909119896 crosses over a cycle (2120587) of the outputof our CORDICcore

After that a recursive formula of the 119872 absolute phasescan be obtained

119909119896 = 4 times (2120587119870119879119904Δ119891 + Δ120579 + 119899119896) 0 le 119870 le 119872 minus 1 (31)

where 119899119896 is the phase noise caused by AWGN (for the sakeof simplicity we neglect it in (16) (17) (18) and (28)) 119879119904is the sample frequency Δ119891 is the frequency offset betweenthe output of the NCO and the modulated signal fromtransmitter and Δ120579 is initial phase difference of the twosignals When SNR is as low as 10 dB numerical results havebeen demonstrated that 119899119896 can be considered as the Gaussianapproximation accurate which has a zero mean and variance1205902 [19]Letrsquos set 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 to be 119911119896 namely

119911119896 = 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 0 le 119896 le 119872 minus 1 (32)

Equation (35) can be also written in vector form

119885 = Δ1198912120587119879119904120572 + Δ120579120573 + 119881 (33)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

= Δ1198912120587119879119904

[[[[[[

[

0

1

119872minus 2

119872 minus 1

]]]]]]

]

+ Δ120579

[[[[[

[

1

1

1

1

1

]]]]]

]

+

[[[[[[

[

11989901198991

119899119872minus2119899119872minus1

]]]]]]

]

(34)

Consequently 119885 is a Gaussian random vector with probabil-ity density function

119891119911 (119885) =1

radic(2120587)119872120590119872

exp[minus1003817100381710038171003817119885 minus Δ1198912120587119879119904120572 minus Δ120579120573

10038171003817100381710038172

21205902]

(35)

where sdot 2 = (119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)119879(119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)

The maximum likelihood estimators Δ119891 and Δ120579 can beobtained by equating the gradientnablaΔ119891Δ120579 log119891119911(119911) to zero andsolving a two-dimensional linear system

Δ119891(119911) =12

2120587119879119904 (119872 minus 1)119872 (119872 + 1)119865119879119885 (36)

120579 (119911) =6

119872 (119872 + 1)Θ119879119885 (37)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

119865 =

[[[[[[[[[[[[[

[

minus119872 minus 1

2

minus119872 minus 1

2+ 1

119872minus 1

2minus 1

119872 minus 1

2

]]]]]]]]]]]]]

]

Θ =

[[[[[[[[[[[[[

[

2119872 minus 1

32119872 minus 1

3minus 1

2119872 minus 1

3minus (119872 minus 2)

2119872 minus 1

3minus (119872 minus 1)

]]]]]]]]]]]]]

]

(38)

The maximum likelihood estimators in (36) and (37)are minimum variance unbiased estimations achieving theCramer Rao Bound [19 20] On the other side the higher theestimation accuracy is the larger the sample points 119872 andSNR are

Please note that (31) is 4119885119896 If we use (36) to estimatefrequency offset Δ119891 the value of estimation must multiply by4 In the case of FPGA the multiplication of 2119899 just needs toshift n bits towards the left

On the other hand in part 3 Section 2 we select updateperiod of frequency control word of the NCO to be 8119879119904Therefore to enable frequency offset estimation block shownin Figure 5 and the QPSK ADCOL shown in Figure 2 tooperate as synchronously as possible we set the number ofthe sample point of MLFE to be119872 = 8 Therefore based on(36) (34) (32) and (31) we can obtain the frequency offsetestimated

Δ119891 = 4Δ119891(119911) = 412

2120587119879119904 (8 minus 1) 8 (8 + 1)

times [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(39)

International Journal of Reconfigurable Computing 9

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 20dB

frequ

ency

offs

et (M

Hz)

(a) Signal-to-noise ratio is 20 dB

0 2 4 6 8 10

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 5dB

(b) Signal-to-noise ratio is 5 dB

Figure 6 Actual frequency offset versus estimation frequency offset under different signal-to-noise ratios

where119879119904 = 126MHZ is sample frequency and 119909119896 0 le 119870 le 7

is absolute phase generated by (30)Using Δ119891 to assist the QPSK ADCOL shown in Figure 2

to recover carrier quickly Δ119891 must be transformed intofrequency control world of the NCO On the basis of (21) wecan obtain frequency control world of Δ119891 that is

119908Δ119891 =Δ1198912119873

119891119904

(40)

Taking (39) into (40) we can get

119908Δ119891

=2119873

21120587[minus

8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(41)

where 119909119896 0 le 119870 le 7 are signed decimals which areexpressed as the fixed-point number with 3 bitsrsquo integernumber and 29 bitsrsquo decimal 119873 = 32 is bit width of inputsignal of the NCO Because frequency control world of NCOis an integer number the result of (41) should multiply by2minus29 so as to eliminate the affection of the decimal expressedby 29 bitsrsquo binary format Therefore actual frequency controlworld should be119908Δ119891

= 01213 [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(42)

Due to 01213 asymp 2minus3

minus 2minus8 maximum likelihood fre-

quency estimation can be implemented just using shifters andmultiply-accumulate units

In deep-space communication to confirm that the signalsburied by noise can be successfully detected by receiver aparameter named link margin is used to specify minimalSNR of the received signals In the practical design of thecommunication systems its value usually ranges from 3 dB to6 dB [21] In our design we select two types of linkmargins toinvestigate the performance of our frequency offset estimatorThey are the low linkmargin of 5 dB and the high linkmarginof 20 dB respectively Therefore we simulate our MLFEunder the condition of sample frequency 119891119879 = 26MHZ andcarrier frequency 119891119888 = 4MHZ by MATLAB The simulationresults are shown in Figure 6

From Figure 6 we can see that although the estimationrang of the frequency offset decreases along with the declineof SNR the range still approximates minus2MHZ sim 2MHZunder SRN = 5 dB In the case of low and mediumearth orbiting satellite where the greatest Doppler shiftsare plusmn100KHZ and plusmn200KHZ [22] respectively the rangcompletely meets as well

33 Entire Design of All-Digital Carrier Recovery Loop ofQPSK Figure 7 shows the block diagram of our ADCRLIt consists of the MLFOE in shadow and QPSK ADCOLsurrounded by dashed line respectively

First of all the frequency offset will be estimated roughlyand then transformed into the frequency control words ofthe NCO by MLFE to speed up QPSK ADCOL to quicklyimplement the tracking of the carrier

Secondly with the assistance of MLFOE the QPSKADCOL is locked quickly and then starts with tracking thecarrier precisely

FromFigure 7 we can see that the bit width of the outputsof the two low pass filters is 32 If we apply directly thewidth to MLFOE the cost of hardware resource for FPGAis considerable So in our design a truncated bit width willbe used To ensure that the impact of the truncation onthe performance of our system is minimal a simulation isconducted which uses different bit widths for the two inputsignals of MLFOE (the bit widths of the outputs of the twolow pass filters) and the widths range from 8 to 32 bits to test

10 International Journal of Reconfigurable Computing

ADC

Low pass filter

Low passfilter

RegReg

Numericallycontrolledoscillator

Frequency control word

01

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signalfrom transmitter

01

CORDICCORE

Maximumlikelihoodfrequencyestimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

Maximum likelihood frequency offset estimator

Qn(KTs)

In(KTs) times2

times2

times4

timesminus1 Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

timesminus1

timesminus1

k

sumn=0

cos(4ΔwnTs + 4120579)k

sumn=0

(4ΔwnTs + 4120579)

k

sumn=0

sin(4ΔwnTs + 4120579)

Figure 7 Block diagram of QPSK ADCRL

which one is the best for the frequency offset error Δ119891 =

100KHZ under the situations of SNR = 20 10 5 dB Thesimulation result is shown in Figure 8 From Figure 8 it isclear that when the bit width is equal to 11 the frequencyestimation value of the MLFOE is almost the same as that ofhaving bit width equal to 32 under the three types of SNRsThus we set the bit width of the two inputs of MLFOE to be11

4 Simulation Results andComparative Analysis

To verify that the proposed architecture is valid the FPGAsimulation tool ModelSim SE 65 is used to observe theimplementation performance of our proposed architecturebased on FPGA On the other hand MATLAB is also usedto generate the QPSK modulated signals with a frequencyoffset under the conditions of different SNRs and process thesimulation results generated by the ModelSim so as to have abetter visual comparison resulting from that the outputs ofthe ModelSim that are just some values of decimal or binaryformat

The data streams of the entire simulation procedure areshown in Figure 9

The input stream generated quantized and stored into thetextfile Textfile A by MATLAB is QPSK modulated signalswith the following specifications

5 10 15 20 25 30 3565

70

75

80

85

90

95

100

105

Quantization size (bit)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

(kH

z)

SNR = 5dBSNR = 10dBSNR = 20dB

Figure 8The quantization level of the two input signals of MLFOEunder the condition of the frequency offset errorΔ119891 = 100KHZ andSNR = 20 10 5 dB

(i) the number of symbols randomly evaluated as plusmn1 isequal to 1000

(ii) the frequency of symbols 119891119887 = 80KHZ(iii) the frequency of carrier 119891119888 = 39MHZ namely

frequency offset Δ119891 = 100KHZ(iv) SNRs are 20 dB and 5 dB

International Journal of Reconfigurable Computing 11

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

01

CORDICCORE

Maximum likelihood frequency estimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

The output

of loop

filter

The output

ofNCO

QPSK

modulated

signal

MATLAB simulation

ModelSim simulation

Maximum likelihood frequency offset estimatorTextfile A

Textfile B Textfile C

Qn(KTs)

In(KTs) times2

times4

times2

timesminus1

timesminus1

timesminus1

Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

MATLAB process AMATLAB process B

Figure 9 The data stream of entire simulation procedure

(v) quantization level of the 1000 QPSK modulated sig-nals is 8 bits to imitate the input signals of 8-bit ADC

(vi) sample frequency 119891119904 = 26MHZ

The output streams generated and stored into anothertwo textfiles Textfile B and Textfile C by ModelSim are theoutputs of the NCO and the loop filter with the followingspecifications

Textfile B(i) the frequency of carrier 119891119888 = 4MHZ namely output

frequency of NCO(ii) sample frequency 119891119904 = 26MHZ(iii) the quantization level of the output amplitude of the

NCO evaluated as plusmn1 is 8 bitsTextfile C

(i) sample frequency 119891119904 = 26MHZ(ii) the quantization level of the output of the loop filter is

32 bits

Textfile A is generated byMATLAB before startingMod-elSim simulation and then fed into QPSK ADCRL (to imitatethe output of the ADC) in the procedure of the simulation ofModelSimwhenTextfile B andTextfile C are simultaneouslygenerated by ModelSim At the end of the simulation of theModelSim the two files from the ModelSim Textfile B andTextfile C will be read into MATLAB in order to furtherprocess in the two procedures MATLAB process A andMATLAB process B

Because the traditional measure of the performance ofPLL is based on locked-in time steady-state phase error and

locked-in frequency range our QPSK ADCRL also uses themethods

Based on the principle of our QPSK ADCRL displayedin Figure 7 when there exists the frequency offset betweenthe input of the QPSK modulated signals (Textfile A) andthe local carrier signals (the output of NCO) the offset canbe obtained through taking the output of the loop filter(Textfile C) into (21) In our design the carrier frequency ofthe input modulated signals is 39MHZ and the frequencyof the output of the NCO is 4MHZ Therefore the frequencyoffset is 100KHZ

If our QPSK ADCRL is locked the frequency offsetevaluated through taking the output of loop filter into (21) willapproximate to 100KHZ At the same time the output phaseof the NCO (Textfile B) should be equal or approximate tothe phase of the QPSK modulated signals (Textfile A)

On the basis of above discussion as shown in Figures 1011 12 and 13 (a) and (b) are the outputs of the loop filter fromModelSim simulation and its results processed by MATLAB(MATLAB process B shown in Figure 8) respectively (c) isthe result of the phase comparison of the two signals QPSKmodulated signals and the outputs of theNCOwhich is fromthe simulation ofModelSim and then processed byMATLAB(MATLAB process A shown in Figure 9)

Figures 10 and 11 are the simulation results of the classicQPSK ADCOL shown in Figure 2 without the assistance ofMLFOE shown in Figure 6 under the two conditions of SNR= 20 and 5 dB

From the two figures Figures 10(b) and 10(c) we can seethat when SNR is equal to 20 dB the tracking time is about015ms and the maximal steady-state phase error approxi-mates to 0 degree

12 International Journal of Reconfigurable Computing

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

0

10

20

Time (ms)

Freq

uenc

y off

set (

Hz)

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1N

orm

aliz

ed v

olta

ge (V

)

MATLAB outputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 10 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for the QPSK ADCOL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 11 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for the QPSK ADCOL

As shown in the two figures Figures 11(b) and 11(c) whenSNR is equal to 5 dB the tracking time is about 03ms and themaximal steady-state phase error approximates to 2 degree

Figures 12 and 13 are the simulation results under the twoconditions of SNR = 20 and 5 dB where theMLFOE has beenenabled

In contrast to Figures 10 and 11 after enabling theMLFOEfrom the two figures Figures 12(b) and 12(c) we can seethat when SNR is equal to 20 dB the locked-in time isabout 005ms and the maximal steady-state phase error alsoapproximates to 0 degree As shown in the two figuresFigures 13(b) and 13(c) when SNR is equal to 5 dB the lock-in

International Journal of Reconfigurable Computing 13

(a) ModelSim output of loop filter

0 005 01 015 02 025

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0

0

05 1 15 2 25 3 35 4

051

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

minus05

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 12 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

20

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 13 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for our QPSK ADCRL

time is about 01ms and themaximal steady-state phase errorapproximates to 3 degree

On the other hand in the case of the four figures Figures10(b) 11(b) 12(b) and 13(b) when QPSK ADCRL is lockedall frequency offset evaluated by the output of loop filter areequal to 100KHZ

From the above simulation results it is clear that after theMLFOE is enabled whether SNR is high or not the perform-ance of our QPSK ADCRL in locked-in time is two times

faster than that of the QPSK ADCOL without the assistanceof the MLFOE while the maximal steady-state phase error isalmost stable

On the other hand in the two conditions of SNR =20 dB and 5 dB we test the maximal frequency offset whichenables our QPSK ADCRL and the QPSK ADCOL withoutthe assistance of MLFOE to be locked and the correspondinglocked-in time and steady-phase error The results are shownin Table 2 From Table 2 we can see that after the MLFOE

14 International Journal of Reconfigurable Computing

Table 2 The performance advantage of our QPSK ADCRL in locked-in frequency range

SNR Architecture Maximal locked-in Locked-in time (ms) Steady-phase error (degree)Frequency Range (KHZ)

20 db QPSK ADCOL plusmn170 018 Approximating to 020 db Our QPSK ADCRL plusmn680 005 Approximating to 05 db QPSK ADCOL plusmn120 04 Approximating to 25 db Our QPSK ADCRL plusmn510 013 Approximating to 4

Table 3 The hardware cost of the different modules for our QPSK ADCRL

Module Number of slice registers Number of slice LUTs Number used as logicQPSK ADCOL 174 out of 28800 580 out of 28800 612 out of 28800

MLFOE FD 875 out of 28800 892 out of 28800 790 out of 28800MLFE 603 out of 28800 516 out of 28800 592 out of 28800

Total hardware cost 1652 out of 28800 1988 out of 28800 1994 out of 28800

Table 4 The power consumption of our QPSK ADCRL for different operating frequencies

Clock frequency (MHZ) Dynamic power (W) Quiescent power (W) Total power (W) Junction temp (C)312 0060 0526 0594 509250 0058 0526 0583 51200 0048 0525 0574 51150 0039 0525 0564 509

is enabled except for the advantage in locked-in time thelocked-in frequency range of our QPSKADCRL is four timeswider than that of the QPSK ADCOL Therefore our QPSKADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision which are hardlyreconciled for the QPSK ADCOL

There is no doubt that our QPSK ADCRL has a morerobust performance than the QPSK ADCOL without theMLFOE What is more to obtain the same improvement inperformance as our ADCRL for the existing QPSK ADCOL[23 24] the simple revision is to add the MLFOE shown inFigure 4 to the QPSK ADCOLs

Finally in order to acquire their hardware cost for thedifferent modules of our QPSK ADCRL based on FPGA theFPGA synthesis tool ISE Design Suite 122 from FPGA ven-dor Xilinx is used and its chip of Virtex5 family XC5VLX50which supports dynamic reconfiguration technology seenas a core technology to implement SDR [25] on FPGA isselected The synthesis results are given in Table 3 FromTable 3 we can see that although the MLFOE consumesmore logic resources than QPSK ADCOL (because manymultiplication operations are used and a pipelined CORDICarchitecture [26] is adopted so as to meet the requirement ofthe latency time) this is worthy for some applications whichneed a more robust QPSK ADCRL

On the other hand we can also see that the hardware costof the whole QPSK ADCRL just make up a small part of logicresources for the FPGA chip selected

Except for the hardware cost of our QPSK ADCRL wealso investigate its power consumption for the different

operating frequencies by the power analysis tool from Xil-inx XPower which is also important very much in someapplications where communication systems need to workcontinuously bymeans of a portable power sourceThe resultsare shown in Table 4 Form Table 4 we can see that when ourQPSK ADCRL operates under the condition of maximumclock frequency 312MHZ which is from the logic synthesisrsquosresult of ISE 122 the total power is just 0594 (W)

5 Conclusion and Outlook

In this paper an efficient QPSK ADCRL is proposed and asystematic procedure of designing the carrier recovery loopbased on FPGA is displayed On the other hand a FD in pos-session of linear characteristic is introduced to supply a moreprecise frequency offset to MLFE which is implemented justusing shifters and multiply-accumulate units to estimate thefrequency offset and assist QPSK ADCOL to lock quicklyThe joint simulation results of ModelSim and MATLAB hasproved that our proposed architecture can smoothly operateon FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOLSynthesis result has shown that the hardware cost of FPGAfor our QPSK ADCRL is very few and the result of the poweranalysis also has proved that our design is valid in powerconsumption

Looking at the future the exploration aiming at deepspace must be the tendency of the human developmentand the FPGA-based soft defined radio suitable for the

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

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Page 4: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

4 International Journal of Reconfigurable Computing

For PLL the natural radian frequency 119908119899 determineslocked-in frequency range and the performance of sup-pressing noise The pair of contradictions between locked-in frequency range (loop noise bandwidth) and trackingprecision stem from it

In the following we are going to discuss the range of119908119899 from the two aspects fast capture bandwidth of ADPLLand its loop SNR so as to make a compromise between thelocked-in range and the tracking precision

In the case of ADPLL there are two kinds of noisesexternal phase noise and internal phase noise The externalnoise caused by additive white Gaussian noise (AWGN) isa main part which has an influence on the performance ofthe ADPLL and the internal noise caused by the finite wordlength effect can be improved by the reasonable selection ofword length Herein the impact on the selection of 119908119899 isexternal phase noise Thus we just take it into consideration

The channel of deep-space communication is quitebenign with AWGN being the dominating impairment [1]and thus the phase noise of ADPLL caused by AWGN can begiven by [13]

1205901205792= (

119878

119873)119894

minus1119861119871

119861119894

(9)

where 119861119894 is the bandwidth of input signal of the ADPLL(119878119873)119894 is its input SNR and 119861119871 is loop noise bandwidth

For the second-order ADPLL taking proportion integralfilter as its loop filter 119861119871 can be expressed as

119861119871 =119908119899

8120585(1 + 4120585

2) (10)

For ADPLL the ability to suppress noise can be reflectedby the loop SNR

(119878

119873)119871

=1

1205901205792= (

119878

119873)119894

119861119894

119861119871

(11)

It determines the size of phase jitter The result of linearanalysis [14] manifests that PLL cannot work normally until(119878119873)119871 ge 6119889119861

Taking (10) into (11) and considering that ADPLL canoperate normally the upper bound of 119908119899 can be expressedas

119908119899 le (119878

119873)119894

4120585119861119894

(1 + 41205852) 3 (12)

The tracking procedure of ADPLL contains frequencytracking and phase tracking and the former needs longertime than the latter In design of our ADCRL however wefirstly use maximum likelihood frequency offset estimator(MLFOE) to assist ADCOL to implement frequency trackingin that for MLFOE the speed of tracking a large frequencyoffset is superior to ADCOLTherefore we just take the phasetracking into consideration in the procedure of designing ourADCOL In the case of ADPLL the fast capture bandwidthis defined as the largest frequency offset which ensures that

ADPLL can be locked in the procedure of the phase trackingIt can be expressed as

Δ119908119897 = 2120585119908119899 (13)

To meet the frequency tracking in the presence withoutthe assistance of the MLFOE the lower bound of 119908119899 is givenby

119908119899 geΔ119908119897

2120585 (14)

Thus from (12) and (14) we can get acquire the range of 119908119899

Δ119908119897

2120585le 119908119899 le (

119878

119873)119894

4120585119861119894

(1 + 41205852) 3 (15)

Until now except for 119870119889 and 119870119900 the parameters neededfor calculating1198621 and1198622 have been acquired Because the119870119889and119870119900 are associated with some practical system parameterswe will discuss about them in the following

23 Parameter Calculation of All-Digital QPSK Phase-LockedLoop Based on FPGA In the above discussions we haveobtained the corresponding parameters for a normal ADPLLBut as mentioned at the beginning of Section 2 QPSKADCOL is also a kind of ADPLL Thus the above methodsare suitable for QPSK ADCOL

As shown in Figure 2 QPSK ADCOL is comprised ofthe PD covered by the shaded area loop filter surroundedby dashed line and numerically controlled oscillator (NCO)Now based on Figure 2 we begin to discuss how to obtain119870119889and119870119900

First of all the analogy-digital converter (ADC) shownin Figure 2 samples the modulated signals from transmitterRXIN(119905) and acquires a series of discrete-time signals sam-pled RXIN(119870119879119904)

RXIN (119896119879119904) =

119896

sum

119899=0

119868 (119899119879119904) cos (119908119894119899119879119904 + 120579119894)

+ 119876 (119899119879119904) sin (119908119894119899119879119904 + 120579119894)

(16)

where 119908119894 is the radian frequency of the signals sampled 120579119894is their initial phase and 119868(119899119879119904) and 119876(119899119879119904) are the QPSKsignals evaluated as plusmn1 in our design

Secondly the signals RXIN(119870119879119904) are mixed with the twooutputs of the NCO and then filtered to eliminate the doublefrequency components generated by the mixing The twosignals filtered can be expressed as

upper branch (in-phase branch)

119868119899 (119896119879119904) =1

2

119896

sum

119899=0

119868119899 (119899119879119904) cos (Δ119908119899119879119904 + Δ120579)

minus 119876119899 (119899119879119904) sin (Δ119908119899119879119904 + Δ120579)

(17)

International Journal of Reconfigurable Computing 5

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signal

from transmitter

0

1

Quadrature branch

In-phase branch

C1

C2

ud

timesminus1

timesminus1

Figure 2 Structure diagram of QPSK all-digital phase-locked loop

bottom branch (quadrature branch)

119876119899 (119896119879119904) =1

2

119896

sum

119899=0

119868119899 (119899119879119904) cos (Δ119908119899119879119904 + Δ120579)

+ 119876119899 (119899119879119904) sin (Δ119908119899119879119904 + Δ120579)

(18)

where Δ119908 is the radian frequency difference between signalssampled and the two outputs of the NCO and Δ120579 is theirinitial phase difference

Finally the function of the PD of the QPSK ADCOL isimplemented by the following

119906119889 (119896119879)= sign (119868119899 (119896119879119904)) 119876119899 (119896119879119904) minus sign (119876119899 (119896119879119904)) 119868119899 (119896119879119904) (19)

Herein to save hardware resources of FPGA the signdecision and the multiplication operation within (19) arereplaced by a multiplexer controlled by the most significantbit (MSB) of the outputs of the two low pass filtersand aninverter shown in Figure 2 (because the outputs of the twolow pass filters are signed numbers) Therefore the outputcharacteristic of the PD can be obtained

119906119889 (119870119879)

=

minus sin (Δ119908119870119879119904 + Δ120579) minus120587 lt Δ119908119870119879119904 + Δ120579 lt minus3

4120587

cos (Δ119908119870119879119904 + Δ120579) minus3

4120587 lt Δ119908119870119879119904 + Δ120579 lt minus

120587

4

sin (Δ119908119870119879119904 + Δ120579) minus120587

4lt Δ119908119870119879119904 + Δ120579 lt

120587

4

minus cos (Δ119908119870119879119904 + Δ120579)120587

4lt Δ119908119870119879119904 + Δ120579 lt

3

4120587

minus sin (Δ119908119870119879119904 + Δ120579)3

4120587 lt Δ119908119870119879119904 + Δ120579 lt 120587

(20)

0

0

02

04

06

08

Phase offset (radian)

Out

put a

mpl

itude

(V)

minus120587 minus31205874 minus1205874 1205874 31205874 120587

minus02

minus04

minus06

minus08

Figure 3 Phase offset versus output voltage amplitude of PD

Based on (20) the output characteristics curve of the PDcan be obtain and shown in Figure 3 From Figure 3 we cansee that only if the phase offset is within the linear range ofthe PD (minus1205874 sim 1205874) the gain 119870119889 of the PD approximatesto 1 namely the slope of the curve So this is also one reasonwhy we use MLFE to assist QPSK ADCOL to recover carrierquickly and precisely

Next we start with discussing the gain 119870119900 of the NCOIn [15] the authors implement NCO on a Xilinx FPGA in

three types of ways and the conclusion that themethod basedon Xilinx ROM is superior to the other two is acquiredThuswe select themethod based on Xilinx ROM to implement ourNCO [16]

On the basis of the principle of NCO the frequency of itsoutput signal can be expressed as

119891out =119891119904

2119873119908Δ120579 (119870119879119904) (21)

where 119891119904 = 1119879119904 is sample frequency 119882Δ120579(119870119879119904) is frequency

control word and 119873 is the bit width of the input signal of

6 International Journal of Reconfigurable Computing

0 5 10 15

0

10M

agni

tude

(dB)

minus10

minus20

times105Natural radian frequency wn (Hz)

(a) Frequency response characteristic

0 5 10 15

0

Phas

e (de

g)

minus50

minus100

times105Natural radian frequency wn (Hz)

(b) Phase response characteristic

Figure 4 QPSK ADCOL characteristic curve

NCO In our design119882Δ120579(119870119879119904) = 119882119888+119882119906119889 where119882119888 is a given

value determined by carrier frequency and its block diagramnamed as frequency controlword can be seen in Figure 2119882119906119889is the output of the loop filter that is tuned by the frequencyoffset between transmitter and receiver

So the radian frequency of NCO is given as

119882out = 2120587119891out =2120587119891119904

2119873119882Δ120579(119870119879

119904) (22)

On the basis of themodel of ADPLL shown in Figure 1(b)NCO is equivalent to a radian frequency integrator So theoutput phase of NCO is given as

120579out =2120587119891119904119879119894

2119873119882Δ120579(119870119879

119904) (23)

where 119879119894 is the update period of the frequency control word119882Δ120579(119870119879

119904) namely the sample period of the output of loop filter

119882119906119889 and is often set to be 8119879119904Therefore the gain 119870119900 of our NCO is given by

119870119900 =2120587119891119904

21198738119879119904 =

2120587

2119873minus3 (24)

So far we have obtained all methods to calculate theparameters of the QPSKADCOL whereas wemust note thatin our QPSK ADCOL based on FPGA shown in Figure 2 anextra gain will be introduced as the result of the changes ofthe bit width between the inputs and outputs of the differentmodules Regardless of the sign bit the bit width of the inputsof the two multipliers is 7 and the bit width of their outputsis 15 The bit width of the inputs of the two low pass filtersis 15 and the bit width of their outputs is 31 Thus the gainof the two multipliers is 215minus7 = 2

8 and the gain of the twolow pass filters is 231minus15 = 2

16 The rest of the parts showed inFigure 2 have no change in bit width between their inputs andoutputs Therefore the gain from the changes of bit width is28+16

= 224 and (8) should be rectified as

1198621 =1

119896119889119896119900224

8120585119908119899119879119904

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp2120585119908119899119879119904

119896119889119896119900224

1198621 =1

119896119889119896119900224

4(119908119899119879119904)2

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp(119908119899119879119904)

2

119896119889119896119900224

(25)

On the basis of the core idea of software defined radiothe parts of digital signal processing should be closed tothe front end of radio frequency (RF) as much as possibleTherefore we make our QPSK ADCOL operate in inter-mediate frequency (IF) namely the ADC sample frequency119891119904 = 26MHZ and carrier frequency (the output frequency ofNCO) 119891119888 = 4MHZ

On the other hand To ensure that our QPSKADCOL cannormally operate under the conditions of a large frequencyoffset and a low SNR let us set the fast capture bandwidthΔ119908119897 to be 100KHZ the least and the input SNR (119878119873) to be1 dB We have known that the gain of PD is 119870119889 = 1 and thedamping factor is 120585 asymp 0707 To decrease internal phase noisecaused by word length effect we set the bit width of inputsignal of NCO to be 119873 = 32 Therefore based on (15) (24)and (25) the range of the natural radian frequency119908119899 can beobtained and the one of the values is chosen as

119908119899 = 2120587 times 150 times 103= 0942 times 10

6(rads) (26)

Next take119870119889119870119900224 (25) and (26) into (6) we can obtain

themodel-based discrete-time transfer function of ourQPSKADCOL

119867(119911) =0053119911

minus1minus 0051119911

minus2

1 minus 1947119911minus1 + 0949119911minus2 (27)

From (27) the poles of our QPSK ADCOL can beobtained They are 0973 plusmn 0036119894 Based on the theory of thestability of discrete system the system is stable if all poles arelocated inside the unit circle Therefore our QPSK ADCOLis stable

Now the frequency response characteristic and phaseresponse characteristic of ourQPSKADCOL can be acquiredand shown in Figures 4(a) and 4(b) respectively

From Figures 4(a) and 4(b) we can see that when samplefrequency is 26MHZ the passband of our QPSK ADCOLranges from 0 to 200KHZ (namely 119908119899119879119904 ≪ 1 is true)and its margin of phase is 120 degree below Thus this alsoindicates that our QPSK ADCOL meets the conditions ofthe stability of negative feedback control system What ismore Figure 4(a) also displays that QPSK ADCOL is of theproperty of low pass

International Journal of Reconfigurable Computing 7

CORDICCORE

Maximum likelihood frequency estimator

Frequency discriminator

Qn(KTs)

In(KTs)

times2

times2

times4

timesminus1 Arctan (x) fsumΔ

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

Figure 5 The block diagram of the FD and MLFE (MLFOE)

Table 1 Two kinds of typical frequency discriminators

The algorithm used Frequency offset output Output characteristic Hardware complexitysig(lowastdot) times lowastcross(119896 minus 1)119879119904 minus 119896119879119904

sin[2(120579119896minus1 minus 120579119896)](119896 minus 1)119879119904 minus 119896119879119904

Nonlinear Moderate

cross(119896 minus 1)119879119904 minus 119896119879119904

sin(120579119896minus1 minus 120579119896)(119896 minus 1)119879119904 minus 119896119879119904

Nonlinear Simplelowastdot = 119868119899(119870119879119904) times 119868119899((119870 minus 1)119879119904) minus 119876119899(119870119879119904) times 119876119899((119870 minus 1)119879119904)lowastcross = 119868119899(119870119879119904) times 119876119899((119870 minus 1)119879119904) minus 119868119899((119870 minus 1)119879119904) times 119876119899(119870119879119904)

3 The Design of Phase Domain MaximumLikelihood Frequency Estimator and ItsFrequency Discriminator

31 The Frequency Discriminator of the Linear Characteris-tic To use MLFE to obtain an accurate frequency offsetthe performance of its FD is a key factor which must beconsidered Two kinds of FDs used widely are summarizedin Table 1 [17] From Table 1 we can see that they are allof nonlinear characteristic Because in the case of sin(Δ120579)sin(Δ120579) asymp Δ120579 is true only if Δ120579 varies within a small rangeHowever in deep space communication (or in the conditionthat a large Doppler shift is common) the approximation ishardly possible On the other hand to discriminate phaseoffset the dot product and cross-product from two samplepoints separated by a sample interval must be conductedand their results divide by the sample interval (120579 = 119908119905 =

2120587119891119905 namely 119891 = 1205792120587119905)Therefore we introduce a kind of FD in possession of lin-

ear characteristic and the ability to acquire the correspondingsignals of ourADCOL so as to transform them into the inputsof theMLFE Its block diagram surrounded by the dashed lineis shown in Figure 5

FromFigure 5 we can see that after a series of transforma-tions for the two equations (17) and (18) the two signals of thefront end of the CORDIC algorithm block can be obtainedThey are

cos (4Δ119908119870119879119904 + 4Δ120579) = cos (4 (2120587Δ119891119870119879119904 + Δ120579))

sin (4Δ119908119870119879119904 + 4Δ120579) = sin (4 (2120587Δ119891119870119879119904 + Δ120579)) (28)

Feed them into the CORDIC algorithm blockwhich implements the algorithm tanminus1(sin(4Δ119908119870119879119904 +

4Δ120579) cos(4Δ119908119870119879119904 + 4Δ120579)) and the phase offset4Δ119908119870119879119904 + 4Δ120579 = 4(2120587Δ119891119870119879119904 + Δ120579) can be acquiredAfter that the MLFE will be used to estimate the frequencyoffset Δ119891 It is clear that this is a procedure of resolvinglinearly frequency offset Because the CORDIC algorithmcan easily be implemented on FPGA just using snifters andadd operations [18] we just discuss about how to implementMLFE on FPGA using as few logic resources as possible

32 Phase Domain Maximum Likelihood Frequency Estima-tion Algorithm In the case of the FD shown in Figure 5a mapping transformation from Cartesian domain to phasedomain can be realized by CORDIC core and expressed as

119909 =

arctan(119876119896

119868119896

) 119868119896 gt 0

arctan(119876119896

119868119896

) minus 120587 119876119896 lt 0 119868119896 le 0

arctan(119876119896

119868119896

) + 120587 119876119896 gt 0 119868119896 le 0

(29)

where 119868119896 = cos(4Δ119908119870119879119904+4Δ120579) and119876119896 = sin(4Δ119908119870119879119904+4Δ120579)119909119896 is the discrete phase of 119896th sample point The amendmentof plusmn120587 is due to that the output range of our CORDIC core iswithin (minus120587 sim 120587)

To useMLFE for estimating frequency offset we first needto obtain the discrete phases of119872 continuous sample points(119909119896 0 le 119896 le 119872 minus 1) and then take the first sample point 1199090

8 International Journal of Reconfigurable Computing

as initial reference point to obtain119872 absolute phases whichcan be expressed as

119909119896 = 119909119896minus1 +

119909119896 minus 119909119896minus11003816100381610038161003816119909119896 minus 119909119896minus1

1003816100381610038161003816 lt 120587

119909119896 minus 119909119896minus1 + 2120587 119909119896 minus 119909119896minus1 lt minus120587

119909119896 minus 119909119896minus1 minus 2120587 119909119896 minus 119909119896minus1 gt 120587

1 le 119896 lt 119872 1199090 = 1199090

(30)

where 119909119896 (the output of our CORDIC core) is the discretephase of 119896th sample point and it ranges from minus120587 to 120587 119909119896 isan absolute phase of 119896th sample point which takes 1199090 as thepoint of reference and has no the limitation of phase rangingfrom minus120587 to 120587 The amendment of plusmn2120587 is due to the phasedifference between the (119896 minus 1)th sample point 119909119896minus1 and the119896th 119909119896 crosses over a cycle (2120587) of the outputof our CORDICcore

After that a recursive formula of the 119872 absolute phasescan be obtained

119909119896 = 4 times (2120587119870119879119904Δ119891 + Δ120579 + 119899119896) 0 le 119870 le 119872 minus 1 (31)

where 119899119896 is the phase noise caused by AWGN (for the sakeof simplicity we neglect it in (16) (17) (18) and (28)) 119879119904is the sample frequency Δ119891 is the frequency offset betweenthe output of the NCO and the modulated signal fromtransmitter and Δ120579 is initial phase difference of the twosignals When SNR is as low as 10 dB numerical results havebeen demonstrated that 119899119896 can be considered as the Gaussianapproximation accurate which has a zero mean and variance1205902 [19]Letrsquos set 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 to be 119911119896 namely

119911119896 = 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 0 le 119896 le 119872 minus 1 (32)

Equation (35) can be also written in vector form

119885 = Δ1198912120587119879119904120572 + Δ120579120573 + 119881 (33)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

= Δ1198912120587119879119904

[[[[[[

[

0

1

119872minus 2

119872 minus 1

]]]]]]

]

+ Δ120579

[[[[[

[

1

1

1

1

1

]]]]]

]

+

[[[[[[

[

11989901198991

119899119872minus2119899119872minus1

]]]]]]

]

(34)

Consequently 119885 is a Gaussian random vector with probabil-ity density function

119891119911 (119885) =1

radic(2120587)119872120590119872

exp[minus1003817100381710038171003817119885 minus Δ1198912120587119879119904120572 minus Δ120579120573

10038171003817100381710038172

21205902]

(35)

where sdot 2 = (119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)119879(119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)

The maximum likelihood estimators Δ119891 and Δ120579 can beobtained by equating the gradientnablaΔ119891Δ120579 log119891119911(119911) to zero andsolving a two-dimensional linear system

Δ119891(119911) =12

2120587119879119904 (119872 minus 1)119872 (119872 + 1)119865119879119885 (36)

120579 (119911) =6

119872 (119872 + 1)Θ119879119885 (37)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

119865 =

[[[[[[[[[[[[[

[

minus119872 minus 1

2

minus119872 minus 1

2+ 1

119872minus 1

2minus 1

119872 minus 1

2

]]]]]]]]]]]]]

]

Θ =

[[[[[[[[[[[[[

[

2119872 minus 1

32119872 minus 1

3minus 1

2119872 minus 1

3minus (119872 minus 2)

2119872 minus 1

3minus (119872 minus 1)

]]]]]]]]]]]]]

]

(38)

The maximum likelihood estimators in (36) and (37)are minimum variance unbiased estimations achieving theCramer Rao Bound [19 20] On the other side the higher theestimation accuracy is the larger the sample points 119872 andSNR are

Please note that (31) is 4119885119896 If we use (36) to estimatefrequency offset Δ119891 the value of estimation must multiply by4 In the case of FPGA the multiplication of 2119899 just needs toshift n bits towards the left

On the other hand in part 3 Section 2 we select updateperiod of frequency control word of the NCO to be 8119879119904Therefore to enable frequency offset estimation block shownin Figure 5 and the QPSK ADCOL shown in Figure 2 tooperate as synchronously as possible we set the number ofthe sample point of MLFE to be119872 = 8 Therefore based on(36) (34) (32) and (31) we can obtain the frequency offsetestimated

Δ119891 = 4Δ119891(119911) = 412

2120587119879119904 (8 minus 1) 8 (8 + 1)

times [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(39)

International Journal of Reconfigurable Computing 9

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 20dB

frequ

ency

offs

et (M

Hz)

(a) Signal-to-noise ratio is 20 dB

0 2 4 6 8 10

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 5dB

(b) Signal-to-noise ratio is 5 dB

Figure 6 Actual frequency offset versus estimation frequency offset under different signal-to-noise ratios

where119879119904 = 126MHZ is sample frequency and 119909119896 0 le 119870 le 7

is absolute phase generated by (30)Using Δ119891 to assist the QPSK ADCOL shown in Figure 2

to recover carrier quickly Δ119891 must be transformed intofrequency control world of the NCO On the basis of (21) wecan obtain frequency control world of Δ119891 that is

119908Δ119891 =Δ1198912119873

119891119904

(40)

Taking (39) into (40) we can get

119908Δ119891

=2119873

21120587[minus

8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(41)

where 119909119896 0 le 119870 le 7 are signed decimals which areexpressed as the fixed-point number with 3 bitsrsquo integernumber and 29 bitsrsquo decimal 119873 = 32 is bit width of inputsignal of the NCO Because frequency control world of NCOis an integer number the result of (41) should multiply by2minus29 so as to eliminate the affection of the decimal expressedby 29 bitsrsquo binary format Therefore actual frequency controlworld should be119908Δ119891

= 01213 [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(42)

Due to 01213 asymp 2minus3

minus 2minus8 maximum likelihood fre-

quency estimation can be implemented just using shifters andmultiply-accumulate units

In deep-space communication to confirm that the signalsburied by noise can be successfully detected by receiver aparameter named link margin is used to specify minimalSNR of the received signals In the practical design of thecommunication systems its value usually ranges from 3 dB to6 dB [21] In our design we select two types of linkmargins toinvestigate the performance of our frequency offset estimatorThey are the low linkmargin of 5 dB and the high linkmarginof 20 dB respectively Therefore we simulate our MLFEunder the condition of sample frequency 119891119879 = 26MHZ andcarrier frequency 119891119888 = 4MHZ by MATLAB The simulationresults are shown in Figure 6

From Figure 6 we can see that although the estimationrang of the frequency offset decreases along with the declineof SNR the range still approximates minus2MHZ sim 2MHZunder SRN = 5 dB In the case of low and mediumearth orbiting satellite where the greatest Doppler shiftsare plusmn100KHZ and plusmn200KHZ [22] respectively the rangcompletely meets as well

33 Entire Design of All-Digital Carrier Recovery Loop ofQPSK Figure 7 shows the block diagram of our ADCRLIt consists of the MLFOE in shadow and QPSK ADCOLsurrounded by dashed line respectively

First of all the frequency offset will be estimated roughlyand then transformed into the frequency control words ofthe NCO by MLFE to speed up QPSK ADCOL to quicklyimplement the tracking of the carrier

Secondly with the assistance of MLFOE the QPSKADCOL is locked quickly and then starts with tracking thecarrier precisely

FromFigure 7 we can see that the bit width of the outputsof the two low pass filters is 32 If we apply directly thewidth to MLFOE the cost of hardware resource for FPGAis considerable So in our design a truncated bit width willbe used To ensure that the impact of the truncation onthe performance of our system is minimal a simulation isconducted which uses different bit widths for the two inputsignals of MLFOE (the bit widths of the outputs of the twolow pass filters) and the widths range from 8 to 32 bits to test

10 International Journal of Reconfigurable Computing

ADC

Low pass filter

Low passfilter

RegReg

Numericallycontrolledoscillator

Frequency control word

01

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signalfrom transmitter

01

CORDICCORE

Maximumlikelihoodfrequencyestimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

Maximum likelihood frequency offset estimator

Qn(KTs)

In(KTs) times2

times2

times4

timesminus1 Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

timesminus1

timesminus1

k

sumn=0

cos(4ΔwnTs + 4120579)k

sumn=0

(4ΔwnTs + 4120579)

k

sumn=0

sin(4ΔwnTs + 4120579)

Figure 7 Block diagram of QPSK ADCRL

which one is the best for the frequency offset error Δ119891 =

100KHZ under the situations of SNR = 20 10 5 dB Thesimulation result is shown in Figure 8 From Figure 8 it isclear that when the bit width is equal to 11 the frequencyestimation value of the MLFOE is almost the same as that ofhaving bit width equal to 32 under the three types of SNRsThus we set the bit width of the two inputs of MLFOE to be11

4 Simulation Results andComparative Analysis

To verify that the proposed architecture is valid the FPGAsimulation tool ModelSim SE 65 is used to observe theimplementation performance of our proposed architecturebased on FPGA On the other hand MATLAB is also usedto generate the QPSK modulated signals with a frequencyoffset under the conditions of different SNRs and process thesimulation results generated by the ModelSim so as to have abetter visual comparison resulting from that the outputs ofthe ModelSim that are just some values of decimal or binaryformat

The data streams of the entire simulation procedure areshown in Figure 9

The input stream generated quantized and stored into thetextfile Textfile A by MATLAB is QPSK modulated signalswith the following specifications

5 10 15 20 25 30 3565

70

75

80

85

90

95

100

105

Quantization size (bit)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

(kH

z)

SNR = 5dBSNR = 10dBSNR = 20dB

Figure 8The quantization level of the two input signals of MLFOEunder the condition of the frequency offset errorΔ119891 = 100KHZ andSNR = 20 10 5 dB

(i) the number of symbols randomly evaluated as plusmn1 isequal to 1000

(ii) the frequency of symbols 119891119887 = 80KHZ(iii) the frequency of carrier 119891119888 = 39MHZ namely

frequency offset Δ119891 = 100KHZ(iv) SNRs are 20 dB and 5 dB

International Journal of Reconfigurable Computing 11

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

01

CORDICCORE

Maximum likelihood frequency estimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

The output

of loop

filter

The output

ofNCO

QPSK

modulated

signal

MATLAB simulation

ModelSim simulation

Maximum likelihood frequency offset estimatorTextfile A

Textfile B Textfile C

Qn(KTs)

In(KTs) times2

times4

times2

timesminus1

timesminus1

timesminus1

Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

MATLAB process AMATLAB process B

Figure 9 The data stream of entire simulation procedure

(v) quantization level of the 1000 QPSK modulated sig-nals is 8 bits to imitate the input signals of 8-bit ADC

(vi) sample frequency 119891119904 = 26MHZ

The output streams generated and stored into anothertwo textfiles Textfile B and Textfile C by ModelSim are theoutputs of the NCO and the loop filter with the followingspecifications

Textfile B(i) the frequency of carrier 119891119888 = 4MHZ namely output

frequency of NCO(ii) sample frequency 119891119904 = 26MHZ(iii) the quantization level of the output amplitude of the

NCO evaluated as plusmn1 is 8 bitsTextfile C

(i) sample frequency 119891119904 = 26MHZ(ii) the quantization level of the output of the loop filter is

32 bits

Textfile A is generated byMATLAB before startingMod-elSim simulation and then fed into QPSK ADCRL (to imitatethe output of the ADC) in the procedure of the simulation ofModelSimwhenTextfile B andTextfile C are simultaneouslygenerated by ModelSim At the end of the simulation of theModelSim the two files from the ModelSim Textfile B andTextfile C will be read into MATLAB in order to furtherprocess in the two procedures MATLAB process A andMATLAB process B

Because the traditional measure of the performance ofPLL is based on locked-in time steady-state phase error and

locked-in frequency range our QPSK ADCRL also uses themethods

Based on the principle of our QPSK ADCRL displayedin Figure 7 when there exists the frequency offset betweenthe input of the QPSK modulated signals (Textfile A) andthe local carrier signals (the output of NCO) the offset canbe obtained through taking the output of the loop filter(Textfile C) into (21) In our design the carrier frequency ofthe input modulated signals is 39MHZ and the frequencyof the output of the NCO is 4MHZ Therefore the frequencyoffset is 100KHZ

If our QPSK ADCRL is locked the frequency offsetevaluated through taking the output of loop filter into (21) willapproximate to 100KHZ At the same time the output phaseof the NCO (Textfile B) should be equal or approximate tothe phase of the QPSK modulated signals (Textfile A)

On the basis of above discussion as shown in Figures 1011 12 and 13 (a) and (b) are the outputs of the loop filter fromModelSim simulation and its results processed by MATLAB(MATLAB process B shown in Figure 8) respectively (c) isthe result of the phase comparison of the two signals QPSKmodulated signals and the outputs of theNCOwhich is fromthe simulation ofModelSim and then processed byMATLAB(MATLAB process A shown in Figure 9)

Figures 10 and 11 are the simulation results of the classicQPSK ADCOL shown in Figure 2 without the assistance ofMLFOE shown in Figure 6 under the two conditions of SNR= 20 and 5 dB

From the two figures Figures 10(b) and 10(c) we can seethat when SNR is equal to 20 dB the tracking time is about015ms and the maximal steady-state phase error approxi-mates to 0 degree

12 International Journal of Reconfigurable Computing

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

0

10

20

Time (ms)

Freq

uenc

y off

set (

Hz)

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1N

orm

aliz

ed v

olta

ge (V

)

MATLAB outputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 10 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for the QPSK ADCOL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 11 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for the QPSK ADCOL

As shown in the two figures Figures 11(b) and 11(c) whenSNR is equal to 5 dB the tracking time is about 03ms and themaximal steady-state phase error approximates to 2 degree

Figures 12 and 13 are the simulation results under the twoconditions of SNR = 20 and 5 dB where theMLFOE has beenenabled

In contrast to Figures 10 and 11 after enabling theMLFOEfrom the two figures Figures 12(b) and 12(c) we can seethat when SNR is equal to 20 dB the locked-in time isabout 005ms and the maximal steady-state phase error alsoapproximates to 0 degree As shown in the two figuresFigures 13(b) and 13(c) when SNR is equal to 5 dB the lock-in

International Journal of Reconfigurable Computing 13

(a) ModelSim output of loop filter

0 005 01 015 02 025

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0

0

05 1 15 2 25 3 35 4

051

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

minus05

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 12 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

20

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 13 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for our QPSK ADCRL

time is about 01ms and themaximal steady-state phase errorapproximates to 3 degree

On the other hand in the case of the four figures Figures10(b) 11(b) 12(b) and 13(b) when QPSK ADCRL is lockedall frequency offset evaluated by the output of loop filter areequal to 100KHZ

From the above simulation results it is clear that after theMLFOE is enabled whether SNR is high or not the perform-ance of our QPSK ADCRL in locked-in time is two times

faster than that of the QPSK ADCOL without the assistanceof the MLFOE while the maximal steady-state phase error isalmost stable

On the other hand in the two conditions of SNR =20 dB and 5 dB we test the maximal frequency offset whichenables our QPSK ADCRL and the QPSK ADCOL withoutthe assistance of MLFOE to be locked and the correspondinglocked-in time and steady-phase error The results are shownin Table 2 From Table 2 we can see that after the MLFOE

14 International Journal of Reconfigurable Computing

Table 2 The performance advantage of our QPSK ADCRL in locked-in frequency range

SNR Architecture Maximal locked-in Locked-in time (ms) Steady-phase error (degree)Frequency Range (KHZ)

20 db QPSK ADCOL plusmn170 018 Approximating to 020 db Our QPSK ADCRL plusmn680 005 Approximating to 05 db QPSK ADCOL plusmn120 04 Approximating to 25 db Our QPSK ADCRL plusmn510 013 Approximating to 4

Table 3 The hardware cost of the different modules for our QPSK ADCRL

Module Number of slice registers Number of slice LUTs Number used as logicQPSK ADCOL 174 out of 28800 580 out of 28800 612 out of 28800

MLFOE FD 875 out of 28800 892 out of 28800 790 out of 28800MLFE 603 out of 28800 516 out of 28800 592 out of 28800

Total hardware cost 1652 out of 28800 1988 out of 28800 1994 out of 28800

Table 4 The power consumption of our QPSK ADCRL for different operating frequencies

Clock frequency (MHZ) Dynamic power (W) Quiescent power (W) Total power (W) Junction temp (C)312 0060 0526 0594 509250 0058 0526 0583 51200 0048 0525 0574 51150 0039 0525 0564 509

is enabled except for the advantage in locked-in time thelocked-in frequency range of our QPSKADCRL is four timeswider than that of the QPSK ADCOL Therefore our QPSKADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision which are hardlyreconciled for the QPSK ADCOL

There is no doubt that our QPSK ADCRL has a morerobust performance than the QPSK ADCOL without theMLFOE What is more to obtain the same improvement inperformance as our ADCRL for the existing QPSK ADCOL[23 24] the simple revision is to add the MLFOE shown inFigure 4 to the QPSK ADCOLs

Finally in order to acquire their hardware cost for thedifferent modules of our QPSK ADCRL based on FPGA theFPGA synthesis tool ISE Design Suite 122 from FPGA ven-dor Xilinx is used and its chip of Virtex5 family XC5VLX50which supports dynamic reconfiguration technology seenas a core technology to implement SDR [25] on FPGA isselected The synthesis results are given in Table 3 FromTable 3 we can see that although the MLFOE consumesmore logic resources than QPSK ADCOL (because manymultiplication operations are used and a pipelined CORDICarchitecture [26] is adopted so as to meet the requirement ofthe latency time) this is worthy for some applications whichneed a more robust QPSK ADCRL

On the other hand we can also see that the hardware costof the whole QPSK ADCRL just make up a small part of logicresources for the FPGA chip selected

Except for the hardware cost of our QPSK ADCRL wealso investigate its power consumption for the different

operating frequencies by the power analysis tool from Xil-inx XPower which is also important very much in someapplications where communication systems need to workcontinuously bymeans of a portable power sourceThe resultsare shown in Table 4 Form Table 4 we can see that when ourQPSK ADCRL operates under the condition of maximumclock frequency 312MHZ which is from the logic synthesisrsquosresult of ISE 122 the total power is just 0594 (W)

5 Conclusion and Outlook

In this paper an efficient QPSK ADCRL is proposed and asystematic procedure of designing the carrier recovery loopbased on FPGA is displayed On the other hand a FD in pos-session of linear characteristic is introduced to supply a moreprecise frequency offset to MLFE which is implemented justusing shifters and multiply-accumulate units to estimate thefrequency offset and assist QPSK ADCOL to lock quicklyThe joint simulation results of ModelSim and MATLAB hasproved that our proposed architecture can smoothly operateon FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOLSynthesis result has shown that the hardware cost of FPGAfor our QPSK ADCRL is very few and the result of the poweranalysis also has proved that our design is valid in powerconsumption

Looking at the future the exploration aiming at deepspace must be the tendency of the human developmentand the FPGA-based soft defined radio suitable for the

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

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Page 5: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

International Journal of Reconfigurable Computing 5

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signal

from transmitter

0

1

Quadrature branch

In-phase branch

C1

C2

ud

timesminus1

timesminus1

Figure 2 Structure diagram of QPSK all-digital phase-locked loop

bottom branch (quadrature branch)

119876119899 (119896119879119904) =1

2

119896

sum

119899=0

119868119899 (119899119879119904) cos (Δ119908119899119879119904 + Δ120579)

+ 119876119899 (119899119879119904) sin (Δ119908119899119879119904 + Δ120579)

(18)

where Δ119908 is the radian frequency difference between signalssampled and the two outputs of the NCO and Δ120579 is theirinitial phase difference

Finally the function of the PD of the QPSK ADCOL isimplemented by the following

119906119889 (119896119879)= sign (119868119899 (119896119879119904)) 119876119899 (119896119879119904) minus sign (119876119899 (119896119879119904)) 119868119899 (119896119879119904) (19)

Herein to save hardware resources of FPGA the signdecision and the multiplication operation within (19) arereplaced by a multiplexer controlled by the most significantbit (MSB) of the outputs of the two low pass filtersand aninverter shown in Figure 2 (because the outputs of the twolow pass filters are signed numbers) Therefore the outputcharacteristic of the PD can be obtained

119906119889 (119870119879)

=

minus sin (Δ119908119870119879119904 + Δ120579) minus120587 lt Δ119908119870119879119904 + Δ120579 lt minus3

4120587

cos (Δ119908119870119879119904 + Δ120579) minus3

4120587 lt Δ119908119870119879119904 + Δ120579 lt minus

120587

4

sin (Δ119908119870119879119904 + Δ120579) minus120587

4lt Δ119908119870119879119904 + Δ120579 lt

120587

4

minus cos (Δ119908119870119879119904 + Δ120579)120587

4lt Δ119908119870119879119904 + Δ120579 lt

3

4120587

minus sin (Δ119908119870119879119904 + Δ120579)3

4120587 lt Δ119908119870119879119904 + Δ120579 lt 120587

(20)

0

0

02

04

06

08

Phase offset (radian)

Out

put a

mpl

itude

(V)

minus120587 minus31205874 minus1205874 1205874 31205874 120587

minus02

minus04

minus06

minus08

Figure 3 Phase offset versus output voltage amplitude of PD

Based on (20) the output characteristics curve of the PDcan be obtain and shown in Figure 3 From Figure 3 we cansee that only if the phase offset is within the linear range ofthe PD (minus1205874 sim 1205874) the gain 119870119889 of the PD approximatesto 1 namely the slope of the curve So this is also one reasonwhy we use MLFE to assist QPSK ADCOL to recover carrierquickly and precisely

Next we start with discussing the gain 119870119900 of the NCOIn [15] the authors implement NCO on a Xilinx FPGA in

three types of ways and the conclusion that themethod basedon Xilinx ROM is superior to the other two is acquiredThuswe select themethod based on Xilinx ROM to implement ourNCO [16]

On the basis of the principle of NCO the frequency of itsoutput signal can be expressed as

119891out =119891119904

2119873119908Δ120579 (119870119879119904) (21)

where 119891119904 = 1119879119904 is sample frequency 119882Δ120579(119870119879119904) is frequency

control word and 119873 is the bit width of the input signal of

6 International Journal of Reconfigurable Computing

0 5 10 15

0

10M

agni

tude

(dB)

minus10

minus20

times105Natural radian frequency wn (Hz)

(a) Frequency response characteristic

0 5 10 15

0

Phas

e (de

g)

minus50

minus100

times105Natural radian frequency wn (Hz)

(b) Phase response characteristic

Figure 4 QPSK ADCOL characteristic curve

NCO In our design119882Δ120579(119870119879119904) = 119882119888+119882119906119889 where119882119888 is a given

value determined by carrier frequency and its block diagramnamed as frequency controlword can be seen in Figure 2119882119906119889is the output of the loop filter that is tuned by the frequencyoffset between transmitter and receiver

So the radian frequency of NCO is given as

119882out = 2120587119891out =2120587119891119904

2119873119882Δ120579(119870119879

119904) (22)

On the basis of themodel of ADPLL shown in Figure 1(b)NCO is equivalent to a radian frequency integrator So theoutput phase of NCO is given as

120579out =2120587119891119904119879119894

2119873119882Δ120579(119870119879

119904) (23)

where 119879119894 is the update period of the frequency control word119882Δ120579(119870119879

119904) namely the sample period of the output of loop filter

119882119906119889 and is often set to be 8119879119904Therefore the gain 119870119900 of our NCO is given by

119870119900 =2120587119891119904

21198738119879119904 =

2120587

2119873minus3 (24)

So far we have obtained all methods to calculate theparameters of the QPSKADCOL whereas wemust note thatin our QPSK ADCOL based on FPGA shown in Figure 2 anextra gain will be introduced as the result of the changes ofthe bit width between the inputs and outputs of the differentmodules Regardless of the sign bit the bit width of the inputsof the two multipliers is 7 and the bit width of their outputsis 15 The bit width of the inputs of the two low pass filtersis 15 and the bit width of their outputs is 31 Thus the gainof the two multipliers is 215minus7 = 2

8 and the gain of the twolow pass filters is 231minus15 = 2

16 The rest of the parts showed inFigure 2 have no change in bit width between their inputs andoutputs Therefore the gain from the changes of bit width is28+16

= 224 and (8) should be rectified as

1198621 =1

119896119889119896119900224

8120585119908119899119879119904

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp2120585119908119899119879119904

119896119889119896119900224

1198621 =1

119896119889119896119900224

4(119908119899119879119904)2

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp(119908119899119879119904)

2

119896119889119896119900224

(25)

On the basis of the core idea of software defined radiothe parts of digital signal processing should be closed tothe front end of radio frequency (RF) as much as possibleTherefore we make our QPSK ADCOL operate in inter-mediate frequency (IF) namely the ADC sample frequency119891119904 = 26MHZ and carrier frequency (the output frequency ofNCO) 119891119888 = 4MHZ

On the other hand To ensure that our QPSKADCOL cannormally operate under the conditions of a large frequencyoffset and a low SNR let us set the fast capture bandwidthΔ119908119897 to be 100KHZ the least and the input SNR (119878119873) to be1 dB We have known that the gain of PD is 119870119889 = 1 and thedamping factor is 120585 asymp 0707 To decrease internal phase noisecaused by word length effect we set the bit width of inputsignal of NCO to be 119873 = 32 Therefore based on (15) (24)and (25) the range of the natural radian frequency119908119899 can beobtained and the one of the values is chosen as

119908119899 = 2120587 times 150 times 103= 0942 times 10

6(rads) (26)

Next take119870119889119870119900224 (25) and (26) into (6) we can obtain

themodel-based discrete-time transfer function of ourQPSKADCOL

119867(119911) =0053119911

minus1minus 0051119911

minus2

1 minus 1947119911minus1 + 0949119911minus2 (27)

From (27) the poles of our QPSK ADCOL can beobtained They are 0973 plusmn 0036119894 Based on the theory of thestability of discrete system the system is stable if all poles arelocated inside the unit circle Therefore our QPSK ADCOLis stable

Now the frequency response characteristic and phaseresponse characteristic of ourQPSKADCOL can be acquiredand shown in Figures 4(a) and 4(b) respectively

From Figures 4(a) and 4(b) we can see that when samplefrequency is 26MHZ the passband of our QPSK ADCOLranges from 0 to 200KHZ (namely 119908119899119879119904 ≪ 1 is true)and its margin of phase is 120 degree below Thus this alsoindicates that our QPSK ADCOL meets the conditions ofthe stability of negative feedback control system What ismore Figure 4(a) also displays that QPSK ADCOL is of theproperty of low pass

International Journal of Reconfigurable Computing 7

CORDICCORE

Maximum likelihood frequency estimator

Frequency discriminator

Qn(KTs)

In(KTs)

times2

times2

times4

timesminus1 Arctan (x) fsumΔ

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

Figure 5 The block diagram of the FD and MLFE (MLFOE)

Table 1 Two kinds of typical frequency discriminators

The algorithm used Frequency offset output Output characteristic Hardware complexitysig(lowastdot) times lowastcross(119896 minus 1)119879119904 minus 119896119879119904

sin[2(120579119896minus1 minus 120579119896)](119896 minus 1)119879119904 minus 119896119879119904

Nonlinear Moderate

cross(119896 minus 1)119879119904 minus 119896119879119904

sin(120579119896minus1 minus 120579119896)(119896 minus 1)119879119904 minus 119896119879119904

Nonlinear Simplelowastdot = 119868119899(119870119879119904) times 119868119899((119870 minus 1)119879119904) minus 119876119899(119870119879119904) times 119876119899((119870 minus 1)119879119904)lowastcross = 119868119899(119870119879119904) times 119876119899((119870 minus 1)119879119904) minus 119868119899((119870 minus 1)119879119904) times 119876119899(119870119879119904)

3 The Design of Phase Domain MaximumLikelihood Frequency Estimator and ItsFrequency Discriminator

31 The Frequency Discriminator of the Linear Characteris-tic To use MLFE to obtain an accurate frequency offsetthe performance of its FD is a key factor which must beconsidered Two kinds of FDs used widely are summarizedin Table 1 [17] From Table 1 we can see that they are allof nonlinear characteristic Because in the case of sin(Δ120579)sin(Δ120579) asymp Δ120579 is true only if Δ120579 varies within a small rangeHowever in deep space communication (or in the conditionthat a large Doppler shift is common) the approximation ishardly possible On the other hand to discriminate phaseoffset the dot product and cross-product from two samplepoints separated by a sample interval must be conductedand their results divide by the sample interval (120579 = 119908119905 =

2120587119891119905 namely 119891 = 1205792120587119905)Therefore we introduce a kind of FD in possession of lin-

ear characteristic and the ability to acquire the correspondingsignals of ourADCOL so as to transform them into the inputsof theMLFE Its block diagram surrounded by the dashed lineis shown in Figure 5

FromFigure 5 we can see that after a series of transforma-tions for the two equations (17) and (18) the two signals of thefront end of the CORDIC algorithm block can be obtainedThey are

cos (4Δ119908119870119879119904 + 4Δ120579) = cos (4 (2120587Δ119891119870119879119904 + Δ120579))

sin (4Δ119908119870119879119904 + 4Δ120579) = sin (4 (2120587Δ119891119870119879119904 + Δ120579)) (28)

Feed them into the CORDIC algorithm blockwhich implements the algorithm tanminus1(sin(4Δ119908119870119879119904 +

4Δ120579) cos(4Δ119908119870119879119904 + 4Δ120579)) and the phase offset4Δ119908119870119879119904 + 4Δ120579 = 4(2120587Δ119891119870119879119904 + Δ120579) can be acquiredAfter that the MLFE will be used to estimate the frequencyoffset Δ119891 It is clear that this is a procedure of resolvinglinearly frequency offset Because the CORDIC algorithmcan easily be implemented on FPGA just using snifters andadd operations [18] we just discuss about how to implementMLFE on FPGA using as few logic resources as possible

32 Phase Domain Maximum Likelihood Frequency Estima-tion Algorithm In the case of the FD shown in Figure 5a mapping transformation from Cartesian domain to phasedomain can be realized by CORDIC core and expressed as

119909 =

arctan(119876119896

119868119896

) 119868119896 gt 0

arctan(119876119896

119868119896

) minus 120587 119876119896 lt 0 119868119896 le 0

arctan(119876119896

119868119896

) + 120587 119876119896 gt 0 119868119896 le 0

(29)

where 119868119896 = cos(4Δ119908119870119879119904+4Δ120579) and119876119896 = sin(4Δ119908119870119879119904+4Δ120579)119909119896 is the discrete phase of 119896th sample point The amendmentof plusmn120587 is due to that the output range of our CORDIC core iswithin (minus120587 sim 120587)

To useMLFE for estimating frequency offset we first needto obtain the discrete phases of119872 continuous sample points(119909119896 0 le 119896 le 119872 minus 1) and then take the first sample point 1199090

8 International Journal of Reconfigurable Computing

as initial reference point to obtain119872 absolute phases whichcan be expressed as

119909119896 = 119909119896minus1 +

119909119896 minus 119909119896minus11003816100381610038161003816119909119896 minus 119909119896minus1

1003816100381610038161003816 lt 120587

119909119896 minus 119909119896minus1 + 2120587 119909119896 minus 119909119896minus1 lt minus120587

119909119896 minus 119909119896minus1 minus 2120587 119909119896 minus 119909119896minus1 gt 120587

1 le 119896 lt 119872 1199090 = 1199090

(30)

where 119909119896 (the output of our CORDIC core) is the discretephase of 119896th sample point and it ranges from minus120587 to 120587 119909119896 isan absolute phase of 119896th sample point which takes 1199090 as thepoint of reference and has no the limitation of phase rangingfrom minus120587 to 120587 The amendment of plusmn2120587 is due to the phasedifference between the (119896 minus 1)th sample point 119909119896minus1 and the119896th 119909119896 crosses over a cycle (2120587) of the outputof our CORDICcore

After that a recursive formula of the 119872 absolute phasescan be obtained

119909119896 = 4 times (2120587119870119879119904Δ119891 + Δ120579 + 119899119896) 0 le 119870 le 119872 minus 1 (31)

where 119899119896 is the phase noise caused by AWGN (for the sakeof simplicity we neglect it in (16) (17) (18) and (28)) 119879119904is the sample frequency Δ119891 is the frequency offset betweenthe output of the NCO and the modulated signal fromtransmitter and Δ120579 is initial phase difference of the twosignals When SNR is as low as 10 dB numerical results havebeen demonstrated that 119899119896 can be considered as the Gaussianapproximation accurate which has a zero mean and variance1205902 [19]Letrsquos set 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 to be 119911119896 namely

119911119896 = 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 0 le 119896 le 119872 minus 1 (32)

Equation (35) can be also written in vector form

119885 = Δ1198912120587119879119904120572 + Δ120579120573 + 119881 (33)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

= Δ1198912120587119879119904

[[[[[[

[

0

1

119872minus 2

119872 minus 1

]]]]]]

]

+ Δ120579

[[[[[

[

1

1

1

1

1

]]]]]

]

+

[[[[[[

[

11989901198991

119899119872minus2119899119872minus1

]]]]]]

]

(34)

Consequently 119885 is a Gaussian random vector with probabil-ity density function

119891119911 (119885) =1

radic(2120587)119872120590119872

exp[minus1003817100381710038171003817119885 minus Δ1198912120587119879119904120572 minus Δ120579120573

10038171003817100381710038172

21205902]

(35)

where sdot 2 = (119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)119879(119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)

The maximum likelihood estimators Δ119891 and Δ120579 can beobtained by equating the gradientnablaΔ119891Δ120579 log119891119911(119911) to zero andsolving a two-dimensional linear system

Δ119891(119911) =12

2120587119879119904 (119872 minus 1)119872 (119872 + 1)119865119879119885 (36)

120579 (119911) =6

119872 (119872 + 1)Θ119879119885 (37)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

119865 =

[[[[[[[[[[[[[

[

minus119872 minus 1

2

minus119872 minus 1

2+ 1

119872minus 1

2minus 1

119872 minus 1

2

]]]]]]]]]]]]]

]

Θ =

[[[[[[[[[[[[[

[

2119872 minus 1

32119872 minus 1

3minus 1

2119872 minus 1

3minus (119872 minus 2)

2119872 minus 1

3minus (119872 minus 1)

]]]]]]]]]]]]]

]

(38)

The maximum likelihood estimators in (36) and (37)are minimum variance unbiased estimations achieving theCramer Rao Bound [19 20] On the other side the higher theestimation accuracy is the larger the sample points 119872 andSNR are

Please note that (31) is 4119885119896 If we use (36) to estimatefrequency offset Δ119891 the value of estimation must multiply by4 In the case of FPGA the multiplication of 2119899 just needs toshift n bits towards the left

On the other hand in part 3 Section 2 we select updateperiod of frequency control word of the NCO to be 8119879119904Therefore to enable frequency offset estimation block shownin Figure 5 and the QPSK ADCOL shown in Figure 2 tooperate as synchronously as possible we set the number ofthe sample point of MLFE to be119872 = 8 Therefore based on(36) (34) (32) and (31) we can obtain the frequency offsetestimated

Δ119891 = 4Δ119891(119911) = 412

2120587119879119904 (8 minus 1) 8 (8 + 1)

times [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(39)

International Journal of Reconfigurable Computing 9

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 20dB

frequ

ency

offs

et (M

Hz)

(a) Signal-to-noise ratio is 20 dB

0 2 4 6 8 10

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 5dB

(b) Signal-to-noise ratio is 5 dB

Figure 6 Actual frequency offset versus estimation frequency offset under different signal-to-noise ratios

where119879119904 = 126MHZ is sample frequency and 119909119896 0 le 119870 le 7

is absolute phase generated by (30)Using Δ119891 to assist the QPSK ADCOL shown in Figure 2

to recover carrier quickly Δ119891 must be transformed intofrequency control world of the NCO On the basis of (21) wecan obtain frequency control world of Δ119891 that is

119908Δ119891 =Δ1198912119873

119891119904

(40)

Taking (39) into (40) we can get

119908Δ119891

=2119873

21120587[minus

8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(41)

where 119909119896 0 le 119870 le 7 are signed decimals which areexpressed as the fixed-point number with 3 bitsrsquo integernumber and 29 bitsrsquo decimal 119873 = 32 is bit width of inputsignal of the NCO Because frequency control world of NCOis an integer number the result of (41) should multiply by2minus29 so as to eliminate the affection of the decimal expressedby 29 bitsrsquo binary format Therefore actual frequency controlworld should be119908Δ119891

= 01213 [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(42)

Due to 01213 asymp 2minus3

minus 2minus8 maximum likelihood fre-

quency estimation can be implemented just using shifters andmultiply-accumulate units

In deep-space communication to confirm that the signalsburied by noise can be successfully detected by receiver aparameter named link margin is used to specify minimalSNR of the received signals In the practical design of thecommunication systems its value usually ranges from 3 dB to6 dB [21] In our design we select two types of linkmargins toinvestigate the performance of our frequency offset estimatorThey are the low linkmargin of 5 dB and the high linkmarginof 20 dB respectively Therefore we simulate our MLFEunder the condition of sample frequency 119891119879 = 26MHZ andcarrier frequency 119891119888 = 4MHZ by MATLAB The simulationresults are shown in Figure 6

From Figure 6 we can see that although the estimationrang of the frequency offset decreases along with the declineof SNR the range still approximates minus2MHZ sim 2MHZunder SRN = 5 dB In the case of low and mediumearth orbiting satellite where the greatest Doppler shiftsare plusmn100KHZ and plusmn200KHZ [22] respectively the rangcompletely meets as well

33 Entire Design of All-Digital Carrier Recovery Loop ofQPSK Figure 7 shows the block diagram of our ADCRLIt consists of the MLFOE in shadow and QPSK ADCOLsurrounded by dashed line respectively

First of all the frequency offset will be estimated roughlyand then transformed into the frequency control words ofthe NCO by MLFE to speed up QPSK ADCOL to quicklyimplement the tracking of the carrier

Secondly with the assistance of MLFOE the QPSKADCOL is locked quickly and then starts with tracking thecarrier precisely

FromFigure 7 we can see that the bit width of the outputsof the two low pass filters is 32 If we apply directly thewidth to MLFOE the cost of hardware resource for FPGAis considerable So in our design a truncated bit width willbe used To ensure that the impact of the truncation onthe performance of our system is minimal a simulation isconducted which uses different bit widths for the two inputsignals of MLFOE (the bit widths of the outputs of the twolow pass filters) and the widths range from 8 to 32 bits to test

10 International Journal of Reconfigurable Computing

ADC

Low pass filter

Low passfilter

RegReg

Numericallycontrolledoscillator

Frequency control word

01

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signalfrom transmitter

01

CORDICCORE

Maximumlikelihoodfrequencyestimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

Maximum likelihood frequency offset estimator

Qn(KTs)

In(KTs) times2

times2

times4

timesminus1 Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

timesminus1

timesminus1

k

sumn=0

cos(4ΔwnTs + 4120579)k

sumn=0

(4ΔwnTs + 4120579)

k

sumn=0

sin(4ΔwnTs + 4120579)

Figure 7 Block diagram of QPSK ADCRL

which one is the best for the frequency offset error Δ119891 =

100KHZ under the situations of SNR = 20 10 5 dB Thesimulation result is shown in Figure 8 From Figure 8 it isclear that when the bit width is equal to 11 the frequencyestimation value of the MLFOE is almost the same as that ofhaving bit width equal to 32 under the three types of SNRsThus we set the bit width of the two inputs of MLFOE to be11

4 Simulation Results andComparative Analysis

To verify that the proposed architecture is valid the FPGAsimulation tool ModelSim SE 65 is used to observe theimplementation performance of our proposed architecturebased on FPGA On the other hand MATLAB is also usedto generate the QPSK modulated signals with a frequencyoffset under the conditions of different SNRs and process thesimulation results generated by the ModelSim so as to have abetter visual comparison resulting from that the outputs ofthe ModelSim that are just some values of decimal or binaryformat

The data streams of the entire simulation procedure areshown in Figure 9

The input stream generated quantized and stored into thetextfile Textfile A by MATLAB is QPSK modulated signalswith the following specifications

5 10 15 20 25 30 3565

70

75

80

85

90

95

100

105

Quantization size (bit)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

(kH

z)

SNR = 5dBSNR = 10dBSNR = 20dB

Figure 8The quantization level of the two input signals of MLFOEunder the condition of the frequency offset errorΔ119891 = 100KHZ andSNR = 20 10 5 dB

(i) the number of symbols randomly evaluated as plusmn1 isequal to 1000

(ii) the frequency of symbols 119891119887 = 80KHZ(iii) the frequency of carrier 119891119888 = 39MHZ namely

frequency offset Δ119891 = 100KHZ(iv) SNRs are 20 dB and 5 dB

International Journal of Reconfigurable Computing 11

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

01

CORDICCORE

Maximum likelihood frequency estimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

The output

of loop

filter

The output

ofNCO

QPSK

modulated

signal

MATLAB simulation

ModelSim simulation

Maximum likelihood frequency offset estimatorTextfile A

Textfile B Textfile C

Qn(KTs)

In(KTs) times2

times4

times2

timesminus1

timesminus1

timesminus1

Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

MATLAB process AMATLAB process B

Figure 9 The data stream of entire simulation procedure

(v) quantization level of the 1000 QPSK modulated sig-nals is 8 bits to imitate the input signals of 8-bit ADC

(vi) sample frequency 119891119904 = 26MHZ

The output streams generated and stored into anothertwo textfiles Textfile B and Textfile C by ModelSim are theoutputs of the NCO and the loop filter with the followingspecifications

Textfile B(i) the frequency of carrier 119891119888 = 4MHZ namely output

frequency of NCO(ii) sample frequency 119891119904 = 26MHZ(iii) the quantization level of the output amplitude of the

NCO evaluated as plusmn1 is 8 bitsTextfile C

(i) sample frequency 119891119904 = 26MHZ(ii) the quantization level of the output of the loop filter is

32 bits

Textfile A is generated byMATLAB before startingMod-elSim simulation and then fed into QPSK ADCRL (to imitatethe output of the ADC) in the procedure of the simulation ofModelSimwhenTextfile B andTextfile C are simultaneouslygenerated by ModelSim At the end of the simulation of theModelSim the two files from the ModelSim Textfile B andTextfile C will be read into MATLAB in order to furtherprocess in the two procedures MATLAB process A andMATLAB process B

Because the traditional measure of the performance ofPLL is based on locked-in time steady-state phase error and

locked-in frequency range our QPSK ADCRL also uses themethods

Based on the principle of our QPSK ADCRL displayedin Figure 7 when there exists the frequency offset betweenthe input of the QPSK modulated signals (Textfile A) andthe local carrier signals (the output of NCO) the offset canbe obtained through taking the output of the loop filter(Textfile C) into (21) In our design the carrier frequency ofthe input modulated signals is 39MHZ and the frequencyof the output of the NCO is 4MHZ Therefore the frequencyoffset is 100KHZ

If our QPSK ADCRL is locked the frequency offsetevaluated through taking the output of loop filter into (21) willapproximate to 100KHZ At the same time the output phaseof the NCO (Textfile B) should be equal or approximate tothe phase of the QPSK modulated signals (Textfile A)

On the basis of above discussion as shown in Figures 1011 12 and 13 (a) and (b) are the outputs of the loop filter fromModelSim simulation and its results processed by MATLAB(MATLAB process B shown in Figure 8) respectively (c) isthe result of the phase comparison of the two signals QPSKmodulated signals and the outputs of theNCOwhich is fromthe simulation ofModelSim and then processed byMATLAB(MATLAB process A shown in Figure 9)

Figures 10 and 11 are the simulation results of the classicQPSK ADCOL shown in Figure 2 without the assistance ofMLFOE shown in Figure 6 under the two conditions of SNR= 20 and 5 dB

From the two figures Figures 10(b) and 10(c) we can seethat when SNR is equal to 20 dB the tracking time is about015ms and the maximal steady-state phase error approxi-mates to 0 degree

12 International Journal of Reconfigurable Computing

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

0

10

20

Time (ms)

Freq

uenc

y off

set (

Hz)

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1N

orm

aliz

ed v

olta

ge (V

)

MATLAB outputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 10 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for the QPSK ADCOL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 11 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for the QPSK ADCOL

As shown in the two figures Figures 11(b) and 11(c) whenSNR is equal to 5 dB the tracking time is about 03ms and themaximal steady-state phase error approximates to 2 degree

Figures 12 and 13 are the simulation results under the twoconditions of SNR = 20 and 5 dB where theMLFOE has beenenabled

In contrast to Figures 10 and 11 after enabling theMLFOEfrom the two figures Figures 12(b) and 12(c) we can seethat when SNR is equal to 20 dB the locked-in time isabout 005ms and the maximal steady-state phase error alsoapproximates to 0 degree As shown in the two figuresFigures 13(b) and 13(c) when SNR is equal to 5 dB the lock-in

International Journal of Reconfigurable Computing 13

(a) ModelSim output of loop filter

0 005 01 015 02 025

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0

0

05 1 15 2 25 3 35 4

051

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

minus05

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 12 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

20

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 13 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for our QPSK ADCRL

time is about 01ms and themaximal steady-state phase errorapproximates to 3 degree

On the other hand in the case of the four figures Figures10(b) 11(b) 12(b) and 13(b) when QPSK ADCRL is lockedall frequency offset evaluated by the output of loop filter areequal to 100KHZ

From the above simulation results it is clear that after theMLFOE is enabled whether SNR is high or not the perform-ance of our QPSK ADCRL in locked-in time is two times

faster than that of the QPSK ADCOL without the assistanceof the MLFOE while the maximal steady-state phase error isalmost stable

On the other hand in the two conditions of SNR =20 dB and 5 dB we test the maximal frequency offset whichenables our QPSK ADCRL and the QPSK ADCOL withoutthe assistance of MLFOE to be locked and the correspondinglocked-in time and steady-phase error The results are shownin Table 2 From Table 2 we can see that after the MLFOE

14 International Journal of Reconfigurable Computing

Table 2 The performance advantage of our QPSK ADCRL in locked-in frequency range

SNR Architecture Maximal locked-in Locked-in time (ms) Steady-phase error (degree)Frequency Range (KHZ)

20 db QPSK ADCOL plusmn170 018 Approximating to 020 db Our QPSK ADCRL plusmn680 005 Approximating to 05 db QPSK ADCOL plusmn120 04 Approximating to 25 db Our QPSK ADCRL plusmn510 013 Approximating to 4

Table 3 The hardware cost of the different modules for our QPSK ADCRL

Module Number of slice registers Number of slice LUTs Number used as logicQPSK ADCOL 174 out of 28800 580 out of 28800 612 out of 28800

MLFOE FD 875 out of 28800 892 out of 28800 790 out of 28800MLFE 603 out of 28800 516 out of 28800 592 out of 28800

Total hardware cost 1652 out of 28800 1988 out of 28800 1994 out of 28800

Table 4 The power consumption of our QPSK ADCRL for different operating frequencies

Clock frequency (MHZ) Dynamic power (W) Quiescent power (W) Total power (W) Junction temp (C)312 0060 0526 0594 509250 0058 0526 0583 51200 0048 0525 0574 51150 0039 0525 0564 509

is enabled except for the advantage in locked-in time thelocked-in frequency range of our QPSKADCRL is four timeswider than that of the QPSK ADCOL Therefore our QPSKADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision which are hardlyreconciled for the QPSK ADCOL

There is no doubt that our QPSK ADCRL has a morerobust performance than the QPSK ADCOL without theMLFOE What is more to obtain the same improvement inperformance as our ADCRL for the existing QPSK ADCOL[23 24] the simple revision is to add the MLFOE shown inFigure 4 to the QPSK ADCOLs

Finally in order to acquire their hardware cost for thedifferent modules of our QPSK ADCRL based on FPGA theFPGA synthesis tool ISE Design Suite 122 from FPGA ven-dor Xilinx is used and its chip of Virtex5 family XC5VLX50which supports dynamic reconfiguration technology seenas a core technology to implement SDR [25] on FPGA isselected The synthesis results are given in Table 3 FromTable 3 we can see that although the MLFOE consumesmore logic resources than QPSK ADCOL (because manymultiplication operations are used and a pipelined CORDICarchitecture [26] is adopted so as to meet the requirement ofthe latency time) this is worthy for some applications whichneed a more robust QPSK ADCRL

On the other hand we can also see that the hardware costof the whole QPSK ADCRL just make up a small part of logicresources for the FPGA chip selected

Except for the hardware cost of our QPSK ADCRL wealso investigate its power consumption for the different

operating frequencies by the power analysis tool from Xil-inx XPower which is also important very much in someapplications where communication systems need to workcontinuously bymeans of a portable power sourceThe resultsare shown in Table 4 Form Table 4 we can see that when ourQPSK ADCRL operates under the condition of maximumclock frequency 312MHZ which is from the logic synthesisrsquosresult of ISE 122 the total power is just 0594 (W)

5 Conclusion and Outlook

In this paper an efficient QPSK ADCRL is proposed and asystematic procedure of designing the carrier recovery loopbased on FPGA is displayed On the other hand a FD in pos-session of linear characteristic is introduced to supply a moreprecise frequency offset to MLFE which is implemented justusing shifters and multiply-accumulate units to estimate thefrequency offset and assist QPSK ADCOL to lock quicklyThe joint simulation results of ModelSim and MATLAB hasproved that our proposed architecture can smoothly operateon FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOLSynthesis result has shown that the hardware cost of FPGAfor our QPSK ADCRL is very few and the result of the poweranalysis also has proved that our design is valid in powerconsumption

Looking at the future the exploration aiming at deepspace must be the tendency of the human developmentand the FPGA-based soft defined radio suitable for the

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

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International Journal of

Page 6: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

6 International Journal of Reconfigurable Computing

0 5 10 15

0

10M

agni

tude

(dB)

minus10

minus20

times105Natural radian frequency wn (Hz)

(a) Frequency response characteristic

0 5 10 15

0

Phas

e (de

g)

minus50

minus100

times105Natural radian frequency wn (Hz)

(b) Phase response characteristic

Figure 4 QPSK ADCOL characteristic curve

NCO In our design119882Δ120579(119870119879119904) = 119882119888+119882119906119889 where119882119888 is a given

value determined by carrier frequency and its block diagramnamed as frequency controlword can be seen in Figure 2119882119906119889is the output of the loop filter that is tuned by the frequencyoffset between transmitter and receiver

So the radian frequency of NCO is given as

119882out = 2120587119891out =2120587119891119904

2119873119882Δ120579(119870119879

119904) (22)

On the basis of themodel of ADPLL shown in Figure 1(b)NCO is equivalent to a radian frequency integrator So theoutput phase of NCO is given as

120579out =2120587119891119904119879119894

2119873119882Δ120579(119870119879

119904) (23)

where 119879119894 is the update period of the frequency control word119882Δ120579(119870119879

119904) namely the sample period of the output of loop filter

119882119906119889 and is often set to be 8119879119904Therefore the gain 119870119900 of our NCO is given by

119870119900 =2120587119891119904

21198738119879119904 =

2120587

2119873minus3 (24)

So far we have obtained all methods to calculate theparameters of the QPSKADCOL whereas wemust note thatin our QPSK ADCOL based on FPGA shown in Figure 2 anextra gain will be introduced as the result of the changes ofthe bit width between the inputs and outputs of the differentmodules Regardless of the sign bit the bit width of the inputsof the two multipliers is 7 and the bit width of their outputsis 15 The bit width of the inputs of the two low pass filtersis 15 and the bit width of their outputs is 31 Thus the gainof the two multipliers is 215minus7 = 2

8 and the gain of the twolow pass filters is 231minus15 = 2

16 The rest of the parts showed inFigure 2 have no change in bit width between their inputs andoutputs Therefore the gain from the changes of bit width is28+16

= 224 and (8) should be rectified as

1198621 =1

119896119889119896119900224

8120585119908119899119879119904

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp2120585119908119899119879119904

119896119889119896119900224

1198621 =1

119896119889119896119900224

4(119908119899119879119904)2

4 + 4120585119908119899119879119904 + (119908119899119879119904)2asymp(119908119899119879119904)

2

119896119889119896119900224

(25)

On the basis of the core idea of software defined radiothe parts of digital signal processing should be closed tothe front end of radio frequency (RF) as much as possibleTherefore we make our QPSK ADCOL operate in inter-mediate frequency (IF) namely the ADC sample frequency119891119904 = 26MHZ and carrier frequency (the output frequency ofNCO) 119891119888 = 4MHZ

On the other hand To ensure that our QPSKADCOL cannormally operate under the conditions of a large frequencyoffset and a low SNR let us set the fast capture bandwidthΔ119908119897 to be 100KHZ the least and the input SNR (119878119873) to be1 dB We have known that the gain of PD is 119870119889 = 1 and thedamping factor is 120585 asymp 0707 To decrease internal phase noisecaused by word length effect we set the bit width of inputsignal of NCO to be 119873 = 32 Therefore based on (15) (24)and (25) the range of the natural radian frequency119908119899 can beobtained and the one of the values is chosen as

119908119899 = 2120587 times 150 times 103= 0942 times 10

6(rads) (26)

Next take119870119889119870119900224 (25) and (26) into (6) we can obtain

themodel-based discrete-time transfer function of ourQPSKADCOL

119867(119911) =0053119911

minus1minus 0051119911

minus2

1 minus 1947119911minus1 + 0949119911minus2 (27)

From (27) the poles of our QPSK ADCOL can beobtained They are 0973 plusmn 0036119894 Based on the theory of thestability of discrete system the system is stable if all poles arelocated inside the unit circle Therefore our QPSK ADCOLis stable

Now the frequency response characteristic and phaseresponse characteristic of ourQPSKADCOL can be acquiredand shown in Figures 4(a) and 4(b) respectively

From Figures 4(a) and 4(b) we can see that when samplefrequency is 26MHZ the passband of our QPSK ADCOLranges from 0 to 200KHZ (namely 119908119899119879119904 ≪ 1 is true)and its margin of phase is 120 degree below Thus this alsoindicates that our QPSK ADCOL meets the conditions ofthe stability of negative feedback control system What ismore Figure 4(a) also displays that QPSK ADCOL is of theproperty of low pass

International Journal of Reconfigurable Computing 7

CORDICCORE

Maximum likelihood frequency estimator

Frequency discriminator

Qn(KTs)

In(KTs)

times2

times2

times4

timesminus1 Arctan (x) fsumΔ

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

Figure 5 The block diagram of the FD and MLFE (MLFOE)

Table 1 Two kinds of typical frequency discriminators

The algorithm used Frequency offset output Output characteristic Hardware complexitysig(lowastdot) times lowastcross(119896 minus 1)119879119904 minus 119896119879119904

sin[2(120579119896minus1 minus 120579119896)](119896 minus 1)119879119904 minus 119896119879119904

Nonlinear Moderate

cross(119896 minus 1)119879119904 minus 119896119879119904

sin(120579119896minus1 minus 120579119896)(119896 minus 1)119879119904 minus 119896119879119904

Nonlinear Simplelowastdot = 119868119899(119870119879119904) times 119868119899((119870 minus 1)119879119904) minus 119876119899(119870119879119904) times 119876119899((119870 minus 1)119879119904)lowastcross = 119868119899(119870119879119904) times 119876119899((119870 minus 1)119879119904) minus 119868119899((119870 minus 1)119879119904) times 119876119899(119870119879119904)

3 The Design of Phase Domain MaximumLikelihood Frequency Estimator and ItsFrequency Discriminator

31 The Frequency Discriminator of the Linear Characteris-tic To use MLFE to obtain an accurate frequency offsetthe performance of its FD is a key factor which must beconsidered Two kinds of FDs used widely are summarizedin Table 1 [17] From Table 1 we can see that they are allof nonlinear characteristic Because in the case of sin(Δ120579)sin(Δ120579) asymp Δ120579 is true only if Δ120579 varies within a small rangeHowever in deep space communication (or in the conditionthat a large Doppler shift is common) the approximation ishardly possible On the other hand to discriminate phaseoffset the dot product and cross-product from two samplepoints separated by a sample interval must be conductedand their results divide by the sample interval (120579 = 119908119905 =

2120587119891119905 namely 119891 = 1205792120587119905)Therefore we introduce a kind of FD in possession of lin-

ear characteristic and the ability to acquire the correspondingsignals of ourADCOL so as to transform them into the inputsof theMLFE Its block diagram surrounded by the dashed lineis shown in Figure 5

FromFigure 5 we can see that after a series of transforma-tions for the two equations (17) and (18) the two signals of thefront end of the CORDIC algorithm block can be obtainedThey are

cos (4Δ119908119870119879119904 + 4Δ120579) = cos (4 (2120587Δ119891119870119879119904 + Δ120579))

sin (4Δ119908119870119879119904 + 4Δ120579) = sin (4 (2120587Δ119891119870119879119904 + Δ120579)) (28)

Feed them into the CORDIC algorithm blockwhich implements the algorithm tanminus1(sin(4Δ119908119870119879119904 +

4Δ120579) cos(4Δ119908119870119879119904 + 4Δ120579)) and the phase offset4Δ119908119870119879119904 + 4Δ120579 = 4(2120587Δ119891119870119879119904 + Δ120579) can be acquiredAfter that the MLFE will be used to estimate the frequencyoffset Δ119891 It is clear that this is a procedure of resolvinglinearly frequency offset Because the CORDIC algorithmcan easily be implemented on FPGA just using snifters andadd operations [18] we just discuss about how to implementMLFE on FPGA using as few logic resources as possible

32 Phase Domain Maximum Likelihood Frequency Estima-tion Algorithm In the case of the FD shown in Figure 5a mapping transformation from Cartesian domain to phasedomain can be realized by CORDIC core and expressed as

119909 =

arctan(119876119896

119868119896

) 119868119896 gt 0

arctan(119876119896

119868119896

) minus 120587 119876119896 lt 0 119868119896 le 0

arctan(119876119896

119868119896

) + 120587 119876119896 gt 0 119868119896 le 0

(29)

where 119868119896 = cos(4Δ119908119870119879119904+4Δ120579) and119876119896 = sin(4Δ119908119870119879119904+4Δ120579)119909119896 is the discrete phase of 119896th sample point The amendmentof plusmn120587 is due to that the output range of our CORDIC core iswithin (minus120587 sim 120587)

To useMLFE for estimating frequency offset we first needto obtain the discrete phases of119872 continuous sample points(119909119896 0 le 119896 le 119872 minus 1) and then take the first sample point 1199090

8 International Journal of Reconfigurable Computing

as initial reference point to obtain119872 absolute phases whichcan be expressed as

119909119896 = 119909119896minus1 +

119909119896 minus 119909119896minus11003816100381610038161003816119909119896 minus 119909119896minus1

1003816100381610038161003816 lt 120587

119909119896 minus 119909119896minus1 + 2120587 119909119896 minus 119909119896minus1 lt minus120587

119909119896 minus 119909119896minus1 minus 2120587 119909119896 minus 119909119896minus1 gt 120587

1 le 119896 lt 119872 1199090 = 1199090

(30)

where 119909119896 (the output of our CORDIC core) is the discretephase of 119896th sample point and it ranges from minus120587 to 120587 119909119896 isan absolute phase of 119896th sample point which takes 1199090 as thepoint of reference and has no the limitation of phase rangingfrom minus120587 to 120587 The amendment of plusmn2120587 is due to the phasedifference between the (119896 minus 1)th sample point 119909119896minus1 and the119896th 119909119896 crosses over a cycle (2120587) of the outputof our CORDICcore

After that a recursive formula of the 119872 absolute phasescan be obtained

119909119896 = 4 times (2120587119870119879119904Δ119891 + Δ120579 + 119899119896) 0 le 119870 le 119872 minus 1 (31)

where 119899119896 is the phase noise caused by AWGN (for the sakeof simplicity we neglect it in (16) (17) (18) and (28)) 119879119904is the sample frequency Δ119891 is the frequency offset betweenthe output of the NCO and the modulated signal fromtransmitter and Δ120579 is initial phase difference of the twosignals When SNR is as low as 10 dB numerical results havebeen demonstrated that 119899119896 can be considered as the Gaussianapproximation accurate which has a zero mean and variance1205902 [19]Letrsquos set 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 to be 119911119896 namely

119911119896 = 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 0 le 119896 le 119872 minus 1 (32)

Equation (35) can be also written in vector form

119885 = Δ1198912120587119879119904120572 + Δ120579120573 + 119881 (33)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

= Δ1198912120587119879119904

[[[[[[

[

0

1

119872minus 2

119872 minus 1

]]]]]]

]

+ Δ120579

[[[[[

[

1

1

1

1

1

]]]]]

]

+

[[[[[[

[

11989901198991

119899119872minus2119899119872minus1

]]]]]]

]

(34)

Consequently 119885 is a Gaussian random vector with probabil-ity density function

119891119911 (119885) =1

radic(2120587)119872120590119872

exp[minus1003817100381710038171003817119885 minus Δ1198912120587119879119904120572 minus Δ120579120573

10038171003817100381710038172

21205902]

(35)

where sdot 2 = (119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)119879(119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)

The maximum likelihood estimators Δ119891 and Δ120579 can beobtained by equating the gradientnablaΔ119891Δ120579 log119891119911(119911) to zero andsolving a two-dimensional linear system

Δ119891(119911) =12

2120587119879119904 (119872 minus 1)119872 (119872 + 1)119865119879119885 (36)

120579 (119911) =6

119872 (119872 + 1)Θ119879119885 (37)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

119865 =

[[[[[[[[[[[[[

[

minus119872 minus 1

2

minus119872 minus 1

2+ 1

119872minus 1

2minus 1

119872 minus 1

2

]]]]]]]]]]]]]

]

Θ =

[[[[[[[[[[[[[

[

2119872 minus 1

32119872 minus 1

3minus 1

2119872 minus 1

3minus (119872 minus 2)

2119872 minus 1

3minus (119872 minus 1)

]]]]]]]]]]]]]

]

(38)

The maximum likelihood estimators in (36) and (37)are minimum variance unbiased estimations achieving theCramer Rao Bound [19 20] On the other side the higher theestimation accuracy is the larger the sample points 119872 andSNR are

Please note that (31) is 4119885119896 If we use (36) to estimatefrequency offset Δ119891 the value of estimation must multiply by4 In the case of FPGA the multiplication of 2119899 just needs toshift n bits towards the left

On the other hand in part 3 Section 2 we select updateperiod of frequency control word of the NCO to be 8119879119904Therefore to enable frequency offset estimation block shownin Figure 5 and the QPSK ADCOL shown in Figure 2 tooperate as synchronously as possible we set the number ofthe sample point of MLFE to be119872 = 8 Therefore based on(36) (34) (32) and (31) we can obtain the frequency offsetestimated

Δ119891 = 4Δ119891(119911) = 412

2120587119879119904 (8 minus 1) 8 (8 + 1)

times [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(39)

International Journal of Reconfigurable Computing 9

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 20dB

frequ

ency

offs

et (M

Hz)

(a) Signal-to-noise ratio is 20 dB

0 2 4 6 8 10

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 5dB

(b) Signal-to-noise ratio is 5 dB

Figure 6 Actual frequency offset versus estimation frequency offset under different signal-to-noise ratios

where119879119904 = 126MHZ is sample frequency and 119909119896 0 le 119870 le 7

is absolute phase generated by (30)Using Δ119891 to assist the QPSK ADCOL shown in Figure 2

to recover carrier quickly Δ119891 must be transformed intofrequency control world of the NCO On the basis of (21) wecan obtain frequency control world of Δ119891 that is

119908Δ119891 =Δ1198912119873

119891119904

(40)

Taking (39) into (40) we can get

119908Δ119891

=2119873

21120587[minus

8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(41)

where 119909119896 0 le 119870 le 7 are signed decimals which areexpressed as the fixed-point number with 3 bitsrsquo integernumber and 29 bitsrsquo decimal 119873 = 32 is bit width of inputsignal of the NCO Because frequency control world of NCOis an integer number the result of (41) should multiply by2minus29 so as to eliminate the affection of the decimal expressedby 29 bitsrsquo binary format Therefore actual frequency controlworld should be119908Δ119891

= 01213 [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(42)

Due to 01213 asymp 2minus3

minus 2minus8 maximum likelihood fre-

quency estimation can be implemented just using shifters andmultiply-accumulate units

In deep-space communication to confirm that the signalsburied by noise can be successfully detected by receiver aparameter named link margin is used to specify minimalSNR of the received signals In the practical design of thecommunication systems its value usually ranges from 3 dB to6 dB [21] In our design we select two types of linkmargins toinvestigate the performance of our frequency offset estimatorThey are the low linkmargin of 5 dB and the high linkmarginof 20 dB respectively Therefore we simulate our MLFEunder the condition of sample frequency 119891119879 = 26MHZ andcarrier frequency 119891119888 = 4MHZ by MATLAB The simulationresults are shown in Figure 6

From Figure 6 we can see that although the estimationrang of the frequency offset decreases along with the declineof SNR the range still approximates minus2MHZ sim 2MHZunder SRN = 5 dB In the case of low and mediumearth orbiting satellite where the greatest Doppler shiftsare plusmn100KHZ and plusmn200KHZ [22] respectively the rangcompletely meets as well

33 Entire Design of All-Digital Carrier Recovery Loop ofQPSK Figure 7 shows the block diagram of our ADCRLIt consists of the MLFOE in shadow and QPSK ADCOLsurrounded by dashed line respectively

First of all the frequency offset will be estimated roughlyand then transformed into the frequency control words ofthe NCO by MLFE to speed up QPSK ADCOL to quicklyimplement the tracking of the carrier

Secondly with the assistance of MLFOE the QPSKADCOL is locked quickly and then starts with tracking thecarrier precisely

FromFigure 7 we can see that the bit width of the outputsof the two low pass filters is 32 If we apply directly thewidth to MLFOE the cost of hardware resource for FPGAis considerable So in our design a truncated bit width willbe used To ensure that the impact of the truncation onthe performance of our system is minimal a simulation isconducted which uses different bit widths for the two inputsignals of MLFOE (the bit widths of the outputs of the twolow pass filters) and the widths range from 8 to 32 bits to test

10 International Journal of Reconfigurable Computing

ADC

Low pass filter

Low passfilter

RegReg

Numericallycontrolledoscillator

Frequency control word

01

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signalfrom transmitter

01

CORDICCORE

Maximumlikelihoodfrequencyestimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

Maximum likelihood frequency offset estimator

Qn(KTs)

In(KTs) times2

times2

times4

timesminus1 Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

timesminus1

timesminus1

k

sumn=0

cos(4ΔwnTs + 4120579)k

sumn=0

(4ΔwnTs + 4120579)

k

sumn=0

sin(4ΔwnTs + 4120579)

Figure 7 Block diagram of QPSK ADCRL

which one is the best for the frequency offset error Δ119891 =

100KHZ under the situations of SNR = 20 10 5 dB Thesimulation result is shown in Figure 8 From Figure 8 it isclear that when the bit width is equal to 11 the frequencyestimation value of the MLFOE is almost the same as that ofhaving bit width equal to 32 under the three types of SNRsThus we set the bit width of the two inputs of MLFOE to be11

4 Simulation Results andComparative Analysis

To verify that the proposed architecture is valid the FPGAsimulation tool ModelSim SE 65 is used to observe theimplementation performance of our proposed architecturebased on FPGA On the other hand MATLAB is also usedto generate the QPSK modulated signals with a frequencyoffset under the conditions of different SNRs and process thesimulation results generated by the ModelSim so as to have abetter visual comparison resulting from that the outputs ofthe ModelSim that are just some values of decimal or binaryformat

The data streams of the entire simulation procedure areshown in Figure 9

The input stream generated quantized and stored into thetextfile Textfile A by MATLAB is QPSK modulated signalswith the following specifications

5 10 15 20 25 30 3565

70

75

80

85

90

95

100

105

Quantization size (bit)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

(kH

z)

SNR = 5dBSNR = 10dBSNR = 20dB

Figure 8The quantization level of the two input signals of MLFOEunder the condition of the frequency offset errorΔ119891 = 100KHZ andSNR = 20 10 5 dB

(i) the number of symbols randomly evaluated as plusmn1 isequal to 1000

(ii) the frequency of symbols 119891119887 = 80KHZ(iii) the frequency of carrier 119891119888 = 39MHZ namely

frequency offset Δ119891 = 100KHZ(iv) SNRs are 20 dB and 5 dB

International Journal of Reconfigurable Computing 11

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

01

CORDICCORE

Maximum likelihood frequency estimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

The output

of loop

filter

The output

ofNCO

QPSK

modulated

signal

MATLAB simulation

ModelSim simulation

Maximum likelihood frequency offset estimatorTextfile A

Textfile B Textfile C

Qn(KTs)

In(KTs) times2

times4

times2

timesminus1

timesminus1

timesminus1

Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

MATLAB process AMATLAB process B

Figure 9 The data stream of entire simulation procedure

(v) quantization level of the 1000 QPSK modulated sig-nals is 8 bits to imitate the input signals of 8-bit ADC

(vi) sample frequency 119891119904 = 26MHZ

The output streams generated and stored into anothertwo textfiles Textfile B and Textfile C by ModelSim are theoutputs of the NCO and the loop filter with the followingspecifications

Textfile B(i) the frequency of carrier 119891119888 = 4MHZ namely output

frequency of NCO(ii) sample frequency 119891119904 = 26MHZ(iii) the quantization level of the output amplitude of the

NCO evaluated as plusmn1 is 8 bitsTextfile C

(i) sample frequency 119891119904 = 26MHZ(ii) the quantization level of the output of the loop filter is

32 bits

Textfile A is generated byMATLAB before startingMod-elSim simulation and then fed into QPSK ADCRL (to imitatethe output of the ADC) in the procedure of the simulation ofModelSimwhenTextfile B andTextfile C are simultaneouslygenerated by ModelSim At the end of the simulation of theModelSim the two files from the ModelSim Textfile B andTextfile C will be read into MATLAB in order to furtherprocess in the two procedures MATLAB process A andMATLAB process B

Because the traditional measure of the performance ofPLL is based on locked-in time steady-state phase error and

locked-in frequency range our QPSK ADCRL also uses themethods

Based on the principle of our QPSK ADCRL displayedin Figure 7 when there exists the frequency offset betweenthe input of the QPSK modulated signals (Textfile A) andthe local carrier signals (the output of NCO) the offset canbe obtained through taking the output of the loop filter(Textfile C) into (21) In our design the carrier frequency ofthe input modulated signals is 39MHZ and the frequencyof the output of the NCO is 4MHZ Therefore the frequencyoffset is 100KHZ

If our QPSK ADCRL is locked the frequency offsetevaluated through taking the output of loop filter into (21) willapproximate to 100KHZ At the same time the output phaseof the NCO (Textfile B) should be equal or approximate tothe phase of the QPSK modulated signals (Textfile A)

On the basis of above discussion as shown in Figures 1011 12 and 13 (a) and (b) are the outputs of the loop filter fromModelSim simulation and its results processed by MATLAB(MATLAB process B shown in Figure 8) respectively (c) isthe result of the phase comparison of the two signals QPSKmodulated signals and the outputs of theNCOwhich is fromthe simulation ofModelSim and then processed byMATLAB(MATLAB process A shown in Figure 9)

Figures 10 and 11 are the simulation results of the classicQPSK ADCOL shown in Figure 2 without the assistance ofMLFOE shown in Figure 6 under the two conditions of SNR= 20 and 5 dB

From the two figures Figures 10(b) and 10(c) we can seethat when SNR is equal to 20 dB the tracking time is about015ms and the maximal steady-state phase error approxi-mates to 0 degree

12 International Journal of Reconfigurable Computing

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

0

10

20

Time (ms)

Freq

uenc

y off

set (

Hz)

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1N

orm

aliz

ed v

olta

ge (V

)

MATLAB outputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 10 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for the QPSK ADCOL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 11 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for the QPSK ADCOL

As shown in the two figures Figures 11(b) and 11(c) whenSNR is equal to 5 dB the tracking time is about 03ms and themaximal steady-state phase error approximates to 2 degree

Figures 12 and 13 are the simulation results under the twoconditions of SNR = 20 and 5 dB where theMLFOE has beenenabled

In contrast to Figures 10 and 11 after enabling theMLFOEfrom the two figures Figures 12(b) and 12(c) we can seethat when SNR is equal to 20 dB the locked-in time isabout 005ms and the maximal steady-state phase error alsoapproximates to 0 degree As shown in the two figuresFigures 13(b) and 13(c) when SNR is equal to 5 dB the lock-in

International Journal of Reconfigurable Computing 13

(a) ModelSim output of loop filter

0 005 01 015 02 025

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0

0

05 1 15 2 25 3 35 4

051

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

minus05

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 12 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

20

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 13 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for our QPSK ADCRL

time is about 01ms and themaximal steady-state phase errorapproximates to 3 degree

On the other hand in the case of the four figures Figures10(b) 11(b) 12(b) and 13(b) when QPSK ADCRL is lockedall frequency offset evaluated by the output of loop filter areequal to 100KHZ

From the above simulation results it is clear that after theMLFOE is enabled whether SNR is high or not the perform-ance of our QPSK ADCRL in locked-in time is two times

faster than that of the QPSK ADCOL without the assistanceof the MLFOE while the maximal steady-state phase error isalmost stable

On the other hand in the two conditions of SNR =20 dB and 5 dB we test the maximal frequency offset whichenables our QPSK ADCRL and the QPSK ADCOL withoutthe assistance of MLFOE to be locked and the correspondinglocked-in time and steady-phase error The results are shownin Table 2 From Table 2 we can see that after the MLFOE

14 International Journal of Reconfigurable Computing

Table 2 The performance advantage of our QPSK ADCRL in locked-in frequency range

SNR Architecture Maximal locked-in Locked-in time (ms) Steady-phase error (degree)Frequency Range (KHZ)

20 db QPSK ADCOL plusmn170 018 Approximating to 020 db Our QPSK ADCRL plusmn680 005 Approximating to 05 db QPSK ADCOL plusmn120 04 Approximating to 25 db Our QPSK ADCRL plusmn510 013 Approximating to 4

Table 3 The hardware cost of the different modules for our QPSK ADCRL

Module Number of slice registers Number of slice LUTs Number used as logicQPSK ADCOL 174 out of 28800 580 out of 28800 612 out of 28800

MLFOE FD 875 out of 28800 892 out of 28800 790 out of 28800MLFE 603 out of 28800 516 out of 28800 592 out of 28800

Total hardware cost 1652 out of 28800 1988 out of 28800 1994 out of 28800

Table 4 The power consumption of our QPSK ADCRL for different operating frequencies

Clock frequency (MHZ) Dynamic power (W) Quiescent power (W) Total power (W) Junction temp (C)312 0060 0526 0594 509250 0058 0526 0583 51200 0048 0525 0574 51150 0039 0525 0564 509

is enabled except for the advantage in locked-in time thelocked-in frequency range of our QPSKADCRL is four timeswider than that of the QPSK ADCOL Therefore our QPSKADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision which are hardlyreconciled for the QPSK ADCOL

There is no doubt that our QPSK ADCRL has a morerobust performance than the QPSK ADCOL without theMLFOE What is more to obtain the same improvement inperformance as our ADCRL for the existing QPSK ADCOL[23 24] the simple revision is to add the MLFOE shown inFigure 4 to the QPSK ADCOLs

Finally in order to acquire their hardware cost for thedifferent modules of our QPSK ADCRL based on FPGA theFPGA synthesis tool ISE Design Suite 122 from FPGA ven-dor Xilinx is used and its chip of Virtex5 family XC5VLX50which supports dynamic reconfiguration technology seenas a core technology to implement SDR [25] on FPGA isselected The synthesis results are given in Table 3 FromTable 3 we can see that although the MLFOE consumesmore logic resources than QPSK ADCOL (because manymultiplication operations are used and a pipelined CORDICarchitecture [26] is adopted so as to meet the requirement ofthe latency time) this is worthy for some applications whichneed a more robust QPSK ADCRL

On the other hand we can also see that the hardware costof the whole QPSK ADCRL just make up a small part of logicresources for the FPGA chip selected

Except for the hardware cost of our QPSK ADCRL wealso investigate its power consumption for the different

operating frequencies by the power analysis tool from Xil-inx XPower which is also important very much in someapplications where communication systems need to workcontinuously bymeans of a portable power sourceThe resultsare shown in Table 4 Form Table 4 we can see that when ourQPSK ADCRL operates under the condition of maximumclock frequency 312MHZ which is from the logic synthesisrsquosresult of ISE 122 the total power is just 0594 (W)

5 Conclusion and Outlook

In this paper an efficient QPSK ADCRL is proposed and asystematic procedure of designing the carrier recovery loopbased on FPGA is displayed On the other hand a FD in pos-session of linear characteristic is introduced to supply a moreprecise frequency offset to MLFE which is implemented justusing shifters and multiply-accumulate units to estimate thefrequency offset and assist QPSK ADCOL to lock quicklyThe joint simulation results of ModelSim and MATLAB hasproved that our proposed architecture can smoothly operateon FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOLSynthesis result has shown that the hardware cost of FPGAfor our QPSK ADCRL is very few and the result of the poweranalysis also has proved that our design is valid in powerconsumption

Looking at the future the exploration aiming at deepspace must be the tendency of the human developmentand the FPGA-based soft defined radio suitable for the

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

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Page 7: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

International Journal of Reconfigurable Computing 7

CORDICCORE

Maximum likelihood frequency estimator

Frequency discriminator

Qn(KTs)

In(KTs)

times2

times2

times4

timesminus1 Arctan (x) fsumΔ

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

Figure 5 The block diagram of the FD and MLFE (MLFOE)

Table 1 Two kinds of typical frequency discriminators

The algorithm used Frequency offset output Output characteristic Hardware complexitysig(lowastdot) times lowastcross(119896 minus 1)119879119904 minus 119896119879119904

sin[2(120579119896minus1 minus 120579119896)](119896 minus 1)119879119904 minus 119896119879119904

Nonlinear Moderate

cross(119896 minus 1)119879119904 minus 119896119879119904

sin(120579119896minus1 minus 120579119896)(119896 minus 1)119879119904 minus 119896119879119904

Nonlinear Simplelowastdot = 119868119899(119870119879119904) times 119868119899((119870 minus 1)119879119904) minus 119876119899(119870119879119904) times 119876119899((119870 minus 1)119879119904)lowastcross = 119868119899(119870119879119904) times 119876119899((119870 minus 1)119879119904) minus 119868119899((119870 minus 1)119879119904) times 119876119899(119870119879119904)

3 The Design of Phase Domain MaximumLikelihood Frequency Estimator and ItsFrequency Discriminator

31 The Frequency Discriminator of the Linear Characteris-tic To use MLFE to obtain an accurate frequency offsetthe performance of its FD is a key factor which must beconsidered Two kinds of FDs used widely are summarizedin Table 1 [17] From Table 1 we can see that they are allof nonlinear characteristic Because in the case of sin(Δ120579)sin(Δ120579) asymp Δ120579 is true only if Δ120579 varies within a small rangeHowever in deep space communication (or in the conditionthat a large Doppler shift is common) the approximation ishardly possible On the other hand to discriminate phaseoffset the dot product and cross-product from two samplepoints separated by a sample interval must be conductedand their results divide by the sample interval (120579 = 119908119905 =

2120587119891119905 namely 119891 = 1205792120587119905)Therefore we introduce a kind of FD in possession of lin-

ear characteristic and the ability to acquire the correspondingsignals of ourADCOL so as to transform them into the inputsof theMLFE Its block diagram surrounded by the dashed lineis shown in Figure 5

FromFigure 5 we can see that after a series of transforma-tions for the two equations (17) and (18) the two signals of thefront end of the CORDIC algorithm block can be obtainedThey are

cos (4Δ119908119870119879119904 + 4Δ120579) = cos (4 (2120587Δ119891119870119879119904 + Δ120579))

sin (4Δ119908119870119879119904 + 4Δ120579) = sin (4 (2120587Δ119891119870119879119904 + Δ120579)) (28)

Feed them into the CORDIC algorithm blockwhich implements the algorithm tanminus1(sin(4Δ119908119870119879119904 +

4Δ120579) cos(4Δ119908119870119879119904 + 4Δ120579)) and the phase offset4Δ119908119870119879119904 + 4Δ120579 = 4(2120587Δ119891119870119879119904 + Δ120579) can be acquiredAfter that the MLFE will be used to estimate the frequencyoffset Δ119891 It is clear that this is a procedure of resolvinglinearly frequency offset Because the CORDIC algorithmcan easily be implemented on FPGA just using snifters andadd operations [18] we just discuss about how to implementMLFE on FPGA using as few logic resources as possible

32 Phase Domain Maximum Likelihood Frequency Estima-tion Algorithm In the case of the FD shown in Figure 5a mapping transformation from Cartesian domain to phasedomain can be realized by CORDIC core and expressed as

119909 =

arctan(119876119896

119868119896

) 119868119896 gt 0

arctan(119876119896

119868119896

) minus 120587 119876119896 lt 0 119868119896 le 0

arctan(119876119896

119868119896

) + 120587 119876119896 gt 0 119868119896 le 0

(29)

where 119868119896 = cos(4Δ119908119870119879119904+4Δ120579) and119876119896 = sin(4Δ119908119870119879119904+4Δ120579)119909119896 is the discrete phase of 119896th sample point The amendmentof plusmn120587 is due to that the output range of our CORDIC core iswithin (minus120587 sim 120587)

To useMLFE for estimating frequency offset we first needto obtain the discrete phases of119872 continuous sample points(119909119896 0 le 119896 le 119872 minus 1) and then take the first sample point 1199090

8 International Journal of Reconfigurable Computing

as initial reference point to obtain119872 absolute phases whichcan be expressed as

119909119896 = 119909119896minus1 +

119909119896 minus 119909119896minus11003816100381610038161003816119909119896 minus 119909119896minus1

1003816100381610038161003816 lt 120587

119909119896 minus 119909119896minus1 + 2120587 119909119896 minus 119909119896minus1 lt minus120587

119909119896 minus 119909119896minus1 minus 2120587 119909119896 minus 119909119896minus1 gt 120587

1 le 119896 lt 119872 1199090 = 1199090

(30)

where 119909119896 (the output of our CORDIC core) is the discretephase of 119896th sample point and it ranges from minus120587 to 120587 119909119896 isan absolute phase of 119896th sample point which takes 1199090 as thepoint of reference and has no the limitation of phase rangingfrom minus120587 to 120587 The amendment of plusmn2120587 is due to the phasedifference between the (119896 minus 1)th sample point 119909119896minus1 and the119896th 119909119896 crosses over a cycle (2120587) of the outputof our CORDICcore

After that a recursive formula of the 119872 absolute phasescan be obtained

119909119896 = 4 times (2120587119870119879119904Δ119891 + Δ120579 + 119899119896) 0 le 119870 le 119872 minus 1 (31)

where 119899119896 is the phase noise caused by AWGN (for the sakeof simplicity we neglect it in (16) (17) (18) and (28)) 119879119904is the sample frequency Δ119891 is the frequency offset betweenthe output of the NCO and the modulated signal fromtransmitter and Δ120579 is initial phase difference of the twosignals When SNR is as low as 10 dB numerical results havebeen demonstrated that 119899119896 can be considered as the Gaussianapproximation accurate which has a zero mean and variance1205902 [19]Letrsquos set 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 to be 119911119896 namely

119911119896 = 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 0 le 119896 le 119872 minus 1 (32)

Equation (35) can be also written in vector form

119885 = Δ1198912120587119879119904120572 + Δ120579120573 + 119881 (33)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

= Δ1198912120587119879119904

[[[[[[

[

0

1

119872minus 2

119872 minus 1

]]]]]]

]

+ Δ120579

[[[[[

[

1

1

1

1

1

]]]]]

]

+

[[[[[[

[

11989901198991

119899119872minus2119899119872minus1

]]]]]]

]

(34)

Consequently 119885 is a Gaussian random vector with probabil-ity density function

119891119911 (119885) =1

radic(2120587)119872120590119872

exp[minus1003817100381710038171003817119885 minus Δ1198912120587119879119904120572 minus Δ120579120573

10038171003817100381710038172

21205902]

(35)

where sdot 2 = (119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)119879(119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)

The maximum likelihood estimators Δ119891 and Δ120579 can beobtained by equating the gradientnablaΔ119891Δ120579 log119891119911(119911) to zero andsolving a two-dimensional linear system

Δ119891(119911) =12

2120587119879119904 (119872 minus 1)119872 (119872 + 1)119865119879119885 (36)

120579 (119911) =6

119872 (119872 + 1)Θ119879119885 (37)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

119865 =

[[[[[[[[[[[[[

[

minus119872 minus 1

2

minus119872 minus 1

2+ 1

119872minus 1

2minus 1

119872 minus 1

2

]]]]]]]]]]]]]

]

Θ =

[[[[[[[[[[[[[

[

2119872 minus 1

32119872 minus 1

3minus 1

2119872 minus 1

3minus (119872 minus 2)

2119872 minus 1

3minus (119872 minus 1)

]]]]]]]]]]]]]

]

(38)

The maximum likelihood estimators in (36) and (37)are minimum variance unbiased estimations achieving theCramer Rao Bound [19 20] On the other side the higher theestimation accuracy is the larger the sample points 119872 andSNR are

Please note that (31) is 4119885119896 If we use (36) to estimatefrequency offset Δ119891 the value of estimation must multiply by4 In the case of FPGA the multiplication of 2119899 just needs toshift n bits towards the left

On the other hand in part 3 Section 2 we select updateperiod of frequency control word of the NCO to be 8119879119904Therefore to enable frequency offset estimation block shownin Figure 5 and the QPSK ADCOL shown in Figure 2 tooperate as synchronously as possible we set the number ofthe sample point of MLFE to be119872 = 8 Therefore based on(36) (34) (32) and (31) we can obtain the frequency offsetestimated

Δ119891 = 4Δ119891(119911) = 412

2120587119879119904 (8 minus 1) 8 (8 + 1)

times [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(39)

International Journal of Reconfigurable Computing 9

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 20dB

frequ

ency

offs

et (M

Hz)

(a) Signal-to-noise ratio is 20 dB

0 2 4 6 8 10

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 5dB

(b) Signal-to-noise ratio is 5 dB

Figure 6 Actual frequency offset versus estimation frequency offset under different signal-to-noise ratios

where119879119904 = 126MHZ is sample frequency and 119909119896 0 le 119870 le 7

is absolute phase generated by (30)Using Δ119891 to assist the QPSK ADCOL shown in Figure 2

to recover carrier quickly Δ119891 must be transformed intofrequency control world of the NCO On the basis of (21) wecan obtain frequency control world of Δ119891 that is

119908Δ119891 =Δ1198912119873

119891119904

(40)

Taking (39) into (40) we can get

119908Δ119891

=2119873

21120587[minus

8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(41)

where 119909119896 0 le 119870 le 7 are signed decimals which areexpressed as the fixed-point number with 3 bitsrsquo integernumber and 29 bitsrsquo decimal 119873 = 32 is bit width of inputsignal of the NCO Because frequency control world of NCOis an integer number the result of (41) should multiply by2minus29 so as to eliminate the affection of the decimal expressedby 29 bitsrsquo binary format Therefore actual frequency controlworld should be119908Δ119891

= 01213 [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(42)

Due to 01213 asymp 2minus3

minus 2minus8 maximum likelihood fre-

quency estimation can be implemented just using shifters andmultiply-accumulate units

In deep-space communication to confirm that the signalsburied by noise can be successfully detected by receiver aparameter named link margin is used to specify minimalSNR of the received signals In the practical design of thecommunication systems its value usually ranges from 3 dB to6 dB [21] In our design we select two types of linkmargins toinvestigate the performance of our frequency offset estimatorThey are the low linkmargin of 5 dB and the high linkmarginof 20 dB respectively Therefore we simulate our MLFEunder the condition of sample frequency 119891119879 = 26MHZ andcarrier frequency 119891119888 = 4MHZ by MATLAB The simulationresults are shown in Figure 6

From Figure 6 we can see that although the estimationrang of the frequency offset decreases along with the declineof SNR the range still approximates minus2MHZ sim 2MHZunder SRN = 5 dB In the case of low and mediumearth orbiting satellite where the greatest Doppler shiftsare plusmn100KHZ and plusmn200KHZ [22] respectively the rangcompletely meets as well

33 Entire Design of All-Digital Carrier Recovery Loop ofQPSK Figure 7 shows the block diagram of our ADCRLIt consists of the MLFOE in shadow and QPSK ADCOLsurrounded by dashed line respectively

First of all the frequency offset will be estimated roughlyand then transformed into the frequency control words ofthe NCO by MLFE to speed up QPSK ADCOL to quicklyimplement the tracking of the carrier

Secondly with the assistance of MLFOE the QPSKADCOL is locked quickly and then starts with tracking thecarrier precisely

FromFigure 7 we can see that the bit width of the outputsof the two low pass filters is 32 If we apply directly thewidth to MLFOE the cost of hardware resource for FPGAis considerable So in our design a truncated bit width willbe used To ensure that the impact of the truncation onthe performance of our system is minimal a simulation isconducted which uses different bit widths for the two inputsignals of MLFOE (the bit widths of the outputs of the twolow pass filters) and the widths range from 8 to 32 bits to test

10 International Journal of Reconfigurable Computing

ADC

Low pass filter

Low passfilter

RegReg

Numericallycontrolledoscillator

Frequency control word

01

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signalfrom transmitter

01

CORDICCORE

Maximumlikelihoodfrequencyestimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

Maximum likelihood frequency offset estimator

Qn(KTs)

In(KTs) times2

times2

times4

timesminus1 Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

timesminus1

timesminus1

k

sumn=0

cos(4ΔwnTs + 4120579)k

sumn=0

(4ΔwnTs + 4120579)

k

sumn=0

sin(4ΔwnTs + 4120579)

Figure 7 Block diagram of QPSK ADCRL

which one is the best for the frequency offset error Δ119891 =

100KHZ under the situations of SNR = 20 10 5 dB Thesimulation result is shown in Figure 8 From Figure 8 it isclear that when the bit width is equal to 11 the frequencyestimation value of the MLFOE is almost the same as that ofhaving bit width equal to 32 under the three types of SNRsThus we set the bit width of the two inputs of MLFOE to be11

4 Simulation Results andComparative Analysis

To verify that the proposed architecture is valid the FPGAsimulation tool ModelSim SE 65 is used to observe theimplementation performance of our proposed architecturebased on FPGA On the other hand MATLAB is also usedto generate the QPSK modulated signals with a frequencyoffset under the conditions of different SNRs and process thesimulation results generated by the ModelSim so as to have abetter visual comparison resulting from that the outputs ofthe ModelSim that are just some values of decimal or binaryformat

The data streams of the entire simulation procedure areshown in Figure 9

The input stream generated quantized and stored into thetextfile Textfile A by MATLAB is QPSK modulated signalswith the following specifications

5 10 15 20 25 30 3565

70

75

80

85

90

95

100

105

Quantization size (bit)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

(kH

z)

SNR = 5dBSNR = 10dBSNR = 20dB

Figure 8The quantization level of the two input signals of MLFOEunder the condition of the frequency offset errorΔ119891 = 100KHZ andSNR = 20 10 5 dB

(i) the number of symbols randomly evaluated as plusmn1 isequal to 1000

(ii) the frequency of symbols 119891119887 = 80KHZ(iii) the frequency of carrier 119891119888 = 39MHZ namely

frequency offset Δ119891 = 100KHZ(iv) SNRs are 20 dB and 5 dB

International Journal of Reconfigurable Computing 11

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

01

CORDICCORE

Maximum likelihood frequency estimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

The output

of loop

filter

The output

ofNCO

QPSK

modulated

signal

MATLAB simulation

ModelSim simulation

Maximum likelihood frequency offset estimatorTextfile A

Textfile B Textfile C

Qn(KTs)

In(KTs) times2

times4

times2

timesminus1

timesminus1

timesminus1

Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

MATLAB process AMATLAB process B

Figure 9 The data stream of entire simulation procedure

(v) quantization level of the 1000 QPSK modulated sig-nals is 8 bits to imitate the input signals of 8-bit ADC

(vi) sample frequency 119891119904 = 26MHZ

The output streams generated and stored into anothertwo textfiles Textfile B and Textfile C by ModelSim are theoutputs of the NCO and the loop filter with the followingspecifications

Textfile B(i) the frequency of carrier 119891119888 = 4MHZ namely output

frequency of NCO(ii) sample frequency 119891119904 = 26MHZ(iii) the quantization level of the output amplitude of the

NCO evaluated as plusmn1 is 8 bitsTextfile C

(i) sample frequency 119891119904 = 26MHZ(ii) the quantization level of the output of the loop filter is

32 bits

Textfile A is generated byMATLAB before startingMod-elSim simulation and then fed into QPSK ADCRL (to imitatethe output of the ADC) in the procedure of the simulation ofModelSimwhenTextfile B andTextfile C are simultaneouslygenerated by ModelSim At the end of the simulation of theModelSim the two files from the ModelSim Textfile B andTextfile C will be read into MATLAB in order to furtherprocess in the two procedures MATLAB process A andMATLAB process B

Because the traditional measure of the performance ofPLL is based on locked-in time steady-state phase error and

locked-in frequency range our QPSK ADCRL also uses themethods

Based on the principle of our QPSK ADCRL displayedin Figure 7 when there exists the frequency offset betweenthe input of the QPSK modulated signals (Textfile A) andthe local carrier signals (the output of NCO) the offset canbe obtained through taking the output of the loop filter(Textfile C) into (21) In our design the carrier frequency ofthe input modulated signals is 39MHZ and the frequencyof the output of the NCO is 4MHZ Therefore the frequencyoffset is 100KHZ

If our QPSK ADCRL is locked the frequency offsetevaluated through taking the output of loop filter into (21) willapproximate to 100KHZ At the same time the output phaseof the NCO (Textfile B) should be equal or approximate tothe phase of the QPSK modulated signals (Textfile A)

On the basis of above discussion as shown in Figures 1011 12 and 13 (a) and (b) are the outputs of the loop filter fromModelSim simulation and its results processed by MATLAB(MATLAB process B shown in Figure 8) respectively (c) isthe result of the phase comparison of the two signals QPSKmodulated signals and the outputs of theNCOwhich is fromthe simulation ofModelSim and then processed byMATLAB(MATLAB process A shown in Figure 9)

Figures 10 and 11 are the simulation results of the classicQPSK ADCOL shown in Figure 2 without the assistance ofMLFOE shown in Figure 6 under the two conditions of SNR= 20 and 5 dB

From the two figures Figures 10(b) and 10(c) we can seethat when SNR is equal to 20 dB the tracking time is about015ms and the maximal steady-state phase error approxi-mates to 0 degree

12 International Journal of Reconfigurable Computing

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

0

10

20

Time (ms)

Freq

uenc

y off

set (

Hz)

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1N

orm

aliz

ed v

olta

ge (V

)

MATLAB outputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 10 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for the QPSK ADCOL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 11 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for the QPSK ADCOL

As shown in the two figures Figures 11(b) and 11(c) whenSNR is equal to 5 dB the tracking time is about 03ms and themaximal steady-state phase error approximates to 2 degree

Figures 12 and 13 are the simulation results under the twoconditions of SNR = 20 and 5 dB where theMLFOE has beenenabled

In contrast to Figures 10 and 11 after enabling theMLFOEfrom the two figures Figures 12(b) and 12(c) we can seethat when SNR is equal to 20 dB the locked-in time isabout 005ms and the maximal steady-state phase error alsoapproximates to 0 degree As shown in the two figuresFigures 13(b) and 13(c) when SNR is equal to 5 dB the lock-in

International Journal of Reconfigurable Computing 13

(a) ModelSim output of loop filter

0 005 01 015 02 025

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0

0

05 1 15 2 25 3 35 4

051

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

minus05

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 12 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

20

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 13 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for our QPSK ADCRL

time is about 01ms and themaximal steady-state phase errorapproximates to 3 degree

On the other hand in the case of the four figures Figures10(b) 11(b) 12(b) and 13(b) when QPSK ADCRL is lockedall frequency offset evaluated by the output of loop filter areequal to 100KHZ

From the above simulation results it is clear that after theMLFOE is enabled whether SNR is high or not the perform-ance of our QPSK ADCRL in locked-in time is two times

faster than that of the QPSK ADCOL without the assistanceof the MLFOE while the maximal steady-state phase error isalmost stable

On the other hand in the two conditions of SNR =20 dB and 5 dB we test the maximal frequency offset whichenables our QPSK ADCRL and the QPSK ADCOL withoutthe assistance of MLFOE to be locked and the correspondinglocked-in time and steady-phase error The results are shownin Table 2 From Table 2 we can see that after the MLFOE

14 International Journal of Reconfigurable Computing

Table 2 The performance advantage of our QPSK ADCRL in locked-in frequency range

SNR Architecture Maximal locked-in Locked-in time (ms) Steady-phase error (degree)Frequency Range (KHZ)

20 db QPSK ADCOL plusmn170 018 Approximating to 020 db Our QPSK ADCRL plusmn680 005 Approximating to 05 db QPSK ADCOL plusmn120 04 Approximating to 25 db Our QPSK ADCRL plusmn510 013 Approximating to 4

Table 3 The hardware cost of the different modules for our QPSK ADCRL

Module Number of slice registers Number of slice LUTs Number used as logicQPSK ADCOL 174 out of 28800 580 out of 28800 612 out of 28800

MLFOE FD 875 out of 28800 892 out of 28800 790 out of 28800MLFE 603 out of 28800 516 out of 28800 592 out of 28800

Total hardware cost 1652 out of 28800 1988 out of 28800 1994 out of 28800

Table 4 The power consumption of our QPSK ADCRL for different operating frequencies

Clock frequency (MHZ) Dynamic power (W) Quiescent power (W) Total power (W) Junction temp (C)312 0060 0526 0594 509250 0058 0526 0583 51200 0048 0525 0574 51150 0039 0525 0564 509

is enabled except for the advantage in locked-in time thelocked-in frequency range of our QPSKADCRL is four timeswider than that of the QPSK ADCOL Therefore our QPSKADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision which are hardlyreconciled for the QPSK ADCOL

There is no doubt that our QPSK ADCRL has a morerobust performance than the QPSK ADCOL without theMLFOE What is more to obtain the same improvement inperformance as our ADCRL for the existing QPSK ADCOL[23 24] the simple revision is to add the MLFOE shown inFigure 4 to the QPSK ADCOLs

Finally in order to acquire their hardware cost for thedifferent modules of our QPSK ADCRL based on FPGA theFPGA synthesis tool ISE Design Suite 122 from FPGA ven-dor Xilinx is used and its chip of Virtex5 family XC5VLX50which supports dynamic reconfiguration technology seenas a core technology to implement SDR [25] on FPGA isselected The synthesis results are given in Table 3 FromTable 3 we can see that although the MLFOE consumesmore logic resources than QPSK ADCOL (because manymultiplication operations are used and a pipelined CORDICarchitecture [26] is adopted so as to meet the requirement ofthe latency time) this is worthy for some applications whichneed a more robust QPSK ADCRL

On the other hand we can also see that the hardware costof the whole QPSK ADCRL just make up a small part of logicresources for the FPGA chip selected

Except for the hardware cost of our QPSK ADCRL wealso investigate its power consumption for the different

operating frequencies by the power analysis tool from Xil-inx XPower which is also important very much in someapplications where communication systems need to workcontinuously bymeans of a portable power sourceThe resultsare shown in Table 4 Form Table 4 we can see that when ourQPSK ADCRL operates under the condition of maximumclock frequency 312MHZ which is from the logic synthesisrsquosresult of ISE 122 the total power is just 0594 (W)

5 Conclusion and Outlook

In this paper an efficient QPSK ADCRL is proposed and asystematic procedure of designing the carrier recovery loopbased on FPGA is displayed On the other hand a FD in pos-session of linear characteristic is introduced to supply a moreprecise frequency offset to MLFE which is implemented justusing shifters and multiply-accumulate units to estimate thefrequency offset and assist QPSK ADCOL to lock quicklyThe joint simulation results of ModelSim and MATLAB hasproved that our proposed architecture can smoothly operateon FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOLSynthesis result has shown that the hardware cost of FPGAfor our QPSK ADCRL is very few and the result of the poweranalysis also has proved that our design is valid in powerconsumption

Looking at the future the exploration aiming at deepspace must be the tendency of the human developmentand the FPGA-based soft defined radio suitable for the

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

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International Journal of

Page 8: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

8 International Journal of Reconfigurable Computing

as initial reference point to obtain119872 absolute phases whichcan be expressed as

119909119896 = 119909119896minus1 +

119909119896 minus 119909119896minus11003816100381610038161003816119909119896 minus 119909119896minus1

1003816100381610038161003816 lt 120587

119909119896 minus 119909119896minus1 + 2120587 119909119896 minus 119909119896minus1 lt minus120587

119909119896 minus 119909119896minus1 minus 2120587 119909119896 minus 119909119896minus1 gt 120587

1 le 119896 lt 119872 1199090 = 1199090

(30)

where 119909119896 (the output of our CORDIC core) is the discretephase of 119896th sample point and it ranges from minus120587 to 120587 119909119896 isan absolute phase of 119896th sample point which takes 1199090 as thepoint of reference and has no the limitation of phase rangingfrom minus120587 to 120587 The amendment of plusmn2120587 is due to the phasedifference between the (119896 minus 1)th sample point 119909119896minus1 and the119896th 119909119896 crosses over a cycle (2120587) of the outputof our CORDICcore

After that a recursive formula of the 119872 absolute phasescan be obtained

119909119896 = 4 times (2120587119870119879119904Δ119891 + Δ120579 + 119899119896) 0 le 119870 le 119872 minus 1 (31)

where 119899119896 is the phase noise caused by AWGN (for the sakeof simplicity we neglect it in (16) (17) (18) and (28)) 119879119904is the sample frequency Δ119891 is the frequency offset betweenthe output of the NCO and the modulated signal fromtransmitter and Δ120579 is initial phase difference of the twosignals When SNR is as low as 10 dB numerical results havebeen demonstrated that 119899119896 can be considered as the Gaussianapproximation accurate which has a zero mean and variance1205902 [19]Letrsquos set 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 to be 119911119896 namely

119911119896 = 2120587119870119879119904Δ119891 + Δ120579 + 119899119896 0 le 119896 le 119872 minus 1 (32)

Equation (35) can be also written in vector form

119885 = Δ1198912120587119879119904120572 + Δ120579120573 + 119881 (33)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

= Δ1198912120587119879119904

[[[[[[

[

0

1

119872minus 2

119872 minus 1

]]]]]]

]

+ Δ120579

[[[[[

[

1

1

1

1

1

]]]]]

]

+

[[[[[[

[

11989901198991

119899119872minus2119899119872minus1

]]]]]]

]

(34)

Consequently 119885 is a Gaussian random vector with probabil-ity density function

119891119911 (119885) =1

radic(2120587)119872120590119872

exp[minus1003817100381710038171003817119885 minus Δ1198912120587119879119904120572 minus Δ120579120573

10038171003817100381710038172

21205902]

(35)

where sdot 2 = (119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)119879(119885 minus Δ1198912120587119879119904120572 minus Δ120579120573)

The maximum likelihood estimators Δ119891 and Δ120579 can beobtained by equating the gradientnablaΔ119891Δ120579 log119891119911(119911) to zero andsolving a two-dimensional linear system

Δ119891(119911) =12

2120587119879119904 (119872 minus 1)119872 (119872 + 1)119865119879119885 (36)

120579 (119911) =6

119872 (119872 + 1)Θ119879119885 (37)

where

119885 =

[[[[[[

[

11991101199111

119911119872minus2119911119872minus1

]]]]]]

]

119865 =

[[[[[[[[[[[[[

[

minus119872 minus 1

2

minus119872 minus 1

2+ 1

119872minus 1

2minus 1

119872 minus 1

2

]]]]]]]]]]]]]

]

Θ =

[[[[[[[[[[[[[

[

2119872 minus 1

32119872 minus 1

3minus 1

2119872 minus 1

3minus (119872 minus 2)

2119872 minus 1

3minus (119872 minus 1)

]]]]]]]]]]]]]

]

(38)

The maximum likelihood estimators in (36) and (37)are minimum variance unbiased estimations achieving theCramer Rao Bound [19 20] On the other side the higher theestimation accuracy is the larger the sample points 119872 andSNR are

Please note that (31) is 4119885119896 If we use (36) to estimatefrequency offset Δ119891 the value of estimation must multiply by4 In the case of FPGA the multiplication of 2119899 just needs toshift n bits towards the left

On the other hand in part 3 Section 2 we select updateperiod of frequency control word of the NCO to be 8119879119904Therefore to enable frequency offset estimation block shownin Figure 5 and the QPSK ADCOL shown in Figure 2 tooperate as synchronously as possible we set the number ofthe sample point of MLFE to be119872 = 8 Therefore based on(36) (34) (32) and (31) we can obtain the frequency offsetestimated

Δ119891 = 4Δ119891(119911) = 412

2120587119879119904 (8 minus 1) 8 (8 + 1)

times [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(39)

International Journal of Reconfigurable Computing 9

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 20dB

frequ

ency

offs

et (M

Hz)

(a) Signal-to-noise ratio is 20 dB

0 2 4 6 8 10

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 5dB

(b) Signal-to-noise ratio is 5 dB

Figure 6 Actual frequency offset versus estimation frequency offset under different signal-to-noise ratios

where119879119904 = 126MHZ is sample frequency and 119909119896 0 le 119870 le 7

is absolute phase generated by (30)Using Δ119891 to assist the QPSK ADCOL shown in Figure 2

to recover carrier quickly Δ119891 must be transformed intofrequency control world of the NCO On the basis of (21) wecan obtain frequency control world of Δ119891 that is

119908Δ119891 =Δ1198912119873

119891119904

(40)

Taking (39) into (40) we can get

119908Δ119891

=2119873

21120587[minus

8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(41)

where 119909119896 0 le 119870 le 7 are signed decimals which areexpressed as the fixed-point number with 3 bitsrsquo integernumber and 29 bitsrsquo decimal 119873 = 32 is bit width of inputsignal of the NCO Because frequency control world of NCOis an integer number the result of (41) should multiply by2minus29 so as to eliminate the affection of the decimal expressedby 29 bitsrsquo binary format Therefore actual frequency controlworld should be119908Δ119891

= 01213 [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(42)

Due to 01213 asymp 2minus3

minus 2minus8 maximum likelihood fre-

quency estimation can be implemented just using shifters andmultiply-accumulate units

In deep-space communication to confirm that the signalsburied by noise can be successfully detected by receiver aparameter named link margin is used to specify minimalSNR of the received signals In the practical design of thecommunication systems its value usually ranges from 3 dB to6 dB [21] In our design we select two types of linkmargins toinvestigate the performance of our frequency offset estimatorThey are the low linkmargin of 5 dB and the high linkmarginof 20 dB respectively Therefore we simulate our MLFEunder the condition of sample frequency 119891119879 = 26MHZ andcarrier frequency 119891119888 = 4MHZ by MATLAB The simulationresults are shown in Figure 6

From Figure 6 we can see that although the estimationrang of the frequency offset decreases along with the declineof SNR the range still approximates minus2MHZ sim 2MHZunder SRN = 5 dB In the case of low and mediumearth orbiting satellite where the greatest Doppler shiftsare plusmn100KHZ and plusmn200KHZ [22] respectively the rangcompletely meets as well

33 Entire Design of All-Digital Carrier Recovery Loop ofQPSK Figure 7 shows the block diagram of our ADCRLIt consists of the MLFOE in shadow and QPSK ADCOLsurrounded by dashed line respectively

First of all the frequency offset will be estimated roughlyand then transformed into the frequency control words ofthe NCO by MLFE to speed up QPSK ADCOL to quicklyimplement the tracking of the carrier

Secondly with the assistance of MLFOE the QPSKADCOL is locked quickly and then starts with tracking thecarrier precisely

FromFigure 7 we can see that the bit width of the outputsof the two low pass filters is 32 If we apply directly thewidth to MLFOE the cost of hardware resource for FPGAis considerable So in our design a truncated bit width willbe used To ensure that the impact of the truncation onthe performance of our system is minimal a simulation isconducted which uses different bit widths for the two inputsignals of MLFOE (the bit widths of the outputs of the twolow pass filters) and the widths range from 8 to 32 bits to test

10 International Journal of Reconfigurable Computing

ADC

Low pass filter

Low passfilter

RegReg

Numericallycontrolledoscillator

Frequency control word

01

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signalfrom transmitter

01

CORDICCORE

Maximumlikelihoodfrequencyestimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

Maximum likelihood frequency offset estimator

Qn(KTs)

In(KTs) times2

times2

times4

timesminus1 Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

timesminus1

timesminus1

k

sumn=0

cos(4ΔwnTs + 4120579)k

sumn=0

(4ΔwnTs + 4120579)

k

sumn=0

sin(4ΔwnTs + 4120579)

Figure 7 Block diagram of QPSK ADCRL

which one is the best for the frequency offset error Δ119891 =

100KHZ under the situations of SNR = 20 10 5 dB Thesimulation result is shown in Figure 8 From Figure 8 it isclear that when the bit width is equal to 11 the frequencyestimation value of the MLFOE is almost the same as that ofhaving bit width equal to 32 under the three types of SNRsThus we set the bit width of the two inputs of MLFOE to be11

4 Simulation Results andComparative Analysis

To verify that the proposed architecture is valid the FPGAsimulation tool ModelSim SE 65 is used to observe theimplementation performance of our proposed architecturebased on FPGA On the other hand MATLAB is also usedto generate the QPSK modulated signals with a frequencyoffset under the conditions of different SNRs and process thesimulation results generated by the ModelSim so as to have abetter visual comparison resulting from that the outputs ofthe ModelSim that are just some values of decimal or binaryformat

The data streams of the entire simulation procedure areshown in Figure 9

The input stream generated quantized and stored into thetextfile Textfile A by MATLAB is QPSK modulated signalswith the following specifications

5 10 15 20 25 30 3565

70

75

80

85

90

95

100

105

Quantization size (bit)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

(kH

z)

SNR = 5dBSNR = 10dBSNR = 20dB

Figure 8The quantization level of the two input signals of MLFOEunder the condition of the frequency offset errorΔ119891 = 100KHZ andSNR = 20 10 5 dB

(i) the number of symbols randomly evaluated as plusmn1 isequal to 1000

(ii) the frequency of symbols 119891119887 = 80KHZ(iii) the frequency of carrier 119891119888 = 39MHZ namely

frequency offset Δ119891 = 100KHZ(iv) SNRs are 20 dB and 5 dB

International Journal of Reconfigurable Computing 11

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

01

CORDICCORE

Maximum likelihood frequency estimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

The output

of loop

filter

The output

ofNCO

QPSK

modulated

signal

MATLAB simulation

ModelSim simulation

Maximum likelihood frequency offset estimatorTextfile A

Textfile B Textfile C

Qn(KTs)

In(KTs) times2

times4

times2

timesminus1

timesminus1

timesminus1

Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

MATLAB process AMATLAB process B

Figure 9 The data stream of entire simulation procedure

(v) quantization level of the 1000 QPSK modulated sig-nals is 8 bits to imitate the input signals of 8-bit ADC

(vi) sample frequency 119891119904 = 26MHZ

The output streams generated and stored into anothertwo textfiles Textfile B and Textfile C by ModelSim are theoutputs of the NCO and the loop filter with the followingspecifications

Textfile B(i) the frequency of carrier 119891119888 = 4MHZ namely output

frequency of NCO(ii) sample frequency 119891119904 = 26MHZ(iii) the quantization level of the output amplitude of the

NCO evaluated as plusmn1 is 8 bitsTextfile C

(i) sample frequency 119891119904 = 26MHZ(ii) the quantization level of the output of the loop filter is

32 bits

Textfile A is generated byMATLAB before startingMod-elSim simulation and then fed into QPSK ADCRL (to imitatethe output of the ADC) in the procedure of the simulation ofModelSimwhenTextfile B andTextfile C are simultaneouslygenerated by ModelSim At the end of the simulation of theModelSim the two files from the ModelSim Textfile B andTextfile C will be read into MATLAB in order to furtherprocess in the two procedures MATLAB process A andMATLAB process B

Because the traditional measure of the performance ofPLL is based on locked-in time steady-state phase error and

locked-in frequency range our QPSK ADCRL also uses themethods

Based on the principle of our QPSK ADCRL displayedin Figure 7 when there exists the frequency offset betweenthe input of the QPSK modulated signals (Textfile A) andthe local carrier signals (the output of NCO) the offset canbe obtained through taking the output of the loop filter(Textfile C) into (21) In our design the carrier frequency ofthe input modulated signals is 39MHZ and the frequencyof the output of the NCO is 4MHZ Therefore the frequencyoffset is 100KHZ

If our QPSK ADCRL is locked the frequency offsetevaluated through taking the output of loop filter into (21) willapproximate to 100KHZ At the same time the output phaseof the NCO (Textfile B) should be equal or approximate tothe phase of the QPSK modulated signals (Textfile A)

On the basis of above discussion as shown in Figures 1011 12 and 13 (a) and (b) are the outputs of the loop filter fromModelSim simulation and its results processed by MATLAB(MATLAB process B shown in Figure 8) respectively (c) isthe result of the phase comparison of the two signals QPSKmodulated signals and the outputs of theNCOwhich is fromthe simulation ofModelSim and then processed byMATLAB(MATLAB process A shown in Figure 9)

Figures 10 and 11 are the simulation results of the classicQPSK ADCOL shown in Figure 2 without the assistance ofMLFOE shown in Figure 6 under the two conditions of SNR= 20 and 5 dB

From the two figures Figures 10(b) and 10(c) we can seethat when SNR is equal to 20 dB the tracking time is about015ms and the maximal steady-state phase error approxi-mates to 0 degree

12 International Journal of Reconfigurable Computing

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

0

10

20

Time (ms)

Freq

uenc

y off

set (

Hz)

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1N

orm

aliz

ed v

olta

ge (V

)

MATLAB outputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 10 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for the QPSK ADCOL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 11 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for the QPSK ADCOL

As shown in the two figures Figures 11(b) and 11(c) whenSNR is equal to 5 dB the tracking time is about 03ms and themaximal steady-state phase error approximates to 2 degree

Figures 12 and 13 are the simulation results under the twoconditions of SNR = 20 and 5 dB where theMLFOE has beenenabled

In contrast to Figures 10 and 11 after enabling theMLFOEfrom the two figures Figures 12(b) and 12(c) we can seethat when SNR is equal to 20 dB the locked-in time isabout 005ms and the maximal steady-state phase error alsoapproximates to 0 degree As shown in the two figuresFigures 13(b) and 13(c) when SNR is equal to 5 dB the lock-in

International Journal of Reconfigurable Computing 13

(a) ModelSim output of loop filter

0 005 01 015 02 025

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0

0

05 1 15 2 25 3 35 4

051

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

minus05

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 12 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

20

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 13 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for our QPSK ADCRL

time is about 01ms and themaximal steady-state phase errorapproximates to 3 degree

On the other hand in the case of the four figures Figures10(b) 11(b) 12(b) and 13(b) when QPSK ADCRL is lockedall frequency offset evaluated by the output of loop filter areequal to 100KHZ

From the above simulation results it is clear that after theMLFOE is enabled whether SNR is high or not the perform-ance of our QPSK ADCRL in locked-in time is two times

faster than that of the QPSK ADCOL without the assistanceof the MLFOE while the maximal steady-state phase error isalmost stable

On the other hand in the two conditions of SNR =20 dB and 5 dB we test the maximal frequency offset whichenables our QPSK ADCRL and the QPSK ADCOL withoutthe assistance of MLFOE to be locked and the correspondinglocked-in time and steady-phase error The results are shownin Table 2 From Table 2 we can see that after the MLFOE

14 International Journal of Reconfigurable Computing

Table 2 The performance advantage of our QPSK ADCRL in locked-in frequency range

SNR Architecture Maximal locked-in Locked-in time (ms) Steady-phase error (degree)Frequency Range (KHZ)

20 db QPSK ADCOL plusmn170 018 Approximating to 020 db Our QPSK ADCRL plusmn680 005 Approximating to 05 db QPSK ADCOL plusmn120 04 Approximating to 25 db Our QPSK ADCRL plusmn510 013 Approximating to 4

Table 3 The hardware cost of the different modules for our QPSK ADCRL

Module Number of slice registers Number of slice LUTs Number used as logicQPSK ADCOL 174 out of 28800 580 out of 28800 612 out of 28800

MLFOE FD 875 out of 28800 892 out of 28800 790 out of 28800MLFE 603 out of 28800 516 out of 28800 592 out of 28800

Total hardware cost 1652 out of 28800 1988 out of 28800 1994 out of 28800

Table 4 The power consumption of our QPSK ADCRL for different operating frequencies

Clock frequency (MHZ) Dynamic power (W) Quiescent power (W) Total power (W) Junction temp (C)312 0060 0526 0594 509250 0058 0526 0583 51200 0048 0525 0574 51150 0039 0525 0564 509

is enabled except for the advantage in locked-in time thelocked-in frequency range of our QPSKADCRL is four timeswider than that of the QPSK ADCOL Therefore our QPSKADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision which are hardlyreconciled for the QPSK ADCOL

There is no doubt that our QPSK ADCRL has a morerobust performance than the QPSK ADCOL without theMLFOE What is more to obtain the same improvement inperformance as our ADCRL for the existing QPSK ADCOL[23 24] the simple revision is to add the MLFOE shown inFigure 4 to the QPSK ADCOLs

Finally in order to acquire their hardware cost for thedifferent modules of our QPSK ADCRL based on FPGA theFPGA synthesis tool ISE Design Suite 122 from FPGA ven-dor Xilinx is used and its chip of Virtex5 family XC5VLX50which supports dynamic reconfiguration technology seenas a core technology to implement SDR [25] on FPGA isselected The synthesis results are given in Table 3 FromTable 3 we can see that although the MLFOE consumesmore logic resources than QPSK ADCOL (because manymultiplication operations are used and a pipelined CORDICarchitecture [26] is adopted so as to meet the requirement ofthe latency time) this is worthy for some applications whichneed a more robust QPSK ADCRL

On the other hand we can also see that the hardware costof the whole QPSK ADCRL just make up a small part of logicresources for the FPGA chip selected

Except for the hardware cost of our QPSK ADCRL wealso investigate its power consumption for the different

operating frequencies by the power analysis tool from Xil-inx XPower which is also important very much in someapplications where communication systems need to workcontinuously bymeans of a portable power sourceThe resultsare shown in Table 4 Form Table 4 we can see that when ourQPSK ADCRL operates under the condition of maximumclock frequency 312MHZ which is from the logic synthesisrsquosresult of ISE 122 the total power is just 0594 (W)

5 Conclusion and Outlook

In this paper an efficient QPSK ADCRL is proposed and asystematic procedure of designing the carrier recovery loopbased on FPGA is displayed On the other hand a FD in pos-session of linear characteristic is introduced to supply a moreprecise frequency offset to MLFE which is implemented justusing shifters and multiply-accumulate units to estimate thefrequency offset and assist QPSK ADCOL to lock quicklyThe joint simulation results of ModelSim and MATLAB hasproved that our proposed architecture can smoothly operateon FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOLSynthesis result has shown that the hardware cost of FPGAfor our QPSK ADCRL is very few and the result of the poweranalysis also has proved that our design is valid in powerconsumption

Looking at the future the exploration aiming at deepspace must be the tendency of the human developmentand the FPGA-based soft defined radio suitable for the

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

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International Journal of

Page 9: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

International Journal of Reconfigurable Computing 9

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 20dB

frequ

ency

offs

et (M

Hz)

(a) Signal-to-noise ratio is 20 dB

0 2 4 6 8 10

0

5

10

Actual frequency offset (MHz)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

minus10 minus8 minus6 minus4 minus2minus10

minus5

SNR = 5dB

(b) Signal-to-noise ratio is 5 dB

Figure 6 Actual frequency offset versus estimation frequency offset under different signal-to-noise ratios

where119879119904 = 126MHZ is sample frequency and 119909119896 0 le 119870 le 7

is absolute phase generated by (30)Using Δ119891 to assist the QPSK ADCOL shown in Figure 2

to recover carrier quickly Δ119891 must be transformed intofrequency control world of the NCO On the basis of (21) wecan obtain frequency control world of Δ119891 that is

119908Δ119891 =Δ1198912119873

119891119904

(40)

Taking (39) into (40) we can get

119908Δ119891

=2119873

21120587[minus

8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(41)

where 119909119896 0 le 119870 le 7 are signed decimals which areexpressed as the fixed-point number with 3 bitsrsquo integernumber and 29 bitsrsquo decimal 119873 = 32 is bit width of inputsignal of the NCO Because frequency control world of NCOis an integer number the result of (41) should multiply by2minus29 so as to eliminate the affection of the decimal expressedby 29 bitsrsquo binary format Therefore actual frequency controlworld should be119908Δ119891

= 01213 [minus8 minus 1

2 minus8 minus 1

2+ 1

8 minus 1

2minus 1

8 minus 1

2]

[[[[[[

[

1199090119909111990961199097

]]]]]]

]

(42)

Due to 01213 asymp 2minus3

minus 2minus8 maximum likelihood fre-

quency estimation can be implemented just using shifters andmultiply-accumulate units

In deep-space communication to confirm that the signalsburied by noise can be successfully detected by receiver aparameter named link margin is used to specify minimalSNR of the received signals In the practical design of thecommunication systems its value usually ranges from 3 dB to6 dB [21] In our design we select two types of linkmargins toinvestigate the performance of our frequency offset estimatorThey are the low linkmargin of 5 dB and the high linkmarginof 20 dB respectively Therefore we simulate our MLFEunder the condition of sample frequency 119891119879 = 26MHZ andcarrier frequency 119891119888 = 4MHZ by MATLAB The simulationresults are shown in Figure 6

From Figure 6 we can see that although the estimationrang of the frequency offset decreases along with the declineof SNR the range still approximates minus2MHZ sim 2MHZunder SRN = 5 dB In the case of low and mediumearth orbiting satellite where the greatest Doppler shiftsare plusmn100KHZ and plusmn200KHZ [22] respectively the rangcompletely meets as well

33 Entire Design of All-Digital Carrier Recovery Loop ofQPSK Figure 7 shows the block diagram of our ADCRLIt consists of the MLFOE in shadow and QPSK ADCOLsurrounded by dashed line respectively

First of all the frequency offset will be estimated roughlyand then transformed into the frequency control words ofthe NCO by MLFE to speed up QPSK ADCOL to quicklyimplement the tracking of the carrier

Secondly with the assistance of MLFOE the QPSKADCOL is locked quickly and then starts with tracking thecarrier precisely

FromFigure 7 we can see that the bit width of the outputsof the two low pass filters is 32 If we apply directly thewidth to MLFOE the cost of hardware resource for FPGAis considerable So in our design a truncated bit width willbe used To ensure that the impact of the truncation onthe performance of our system is minimal a simulation isconducted which uses different bit widths for the two inputsignals of MLFOE (the bit widths of the outputs of the twolow pass filters) and the widths range from 8 to 32 bits to test

10 International Journal of Reconfigurable Computing

ADC

Low pass filter

Low passfilter

RegReg

Numericallycontrolledoscillator

Frequency control word

01

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signalfrom transmitter

01

CORDICCORE

Maximumlikelihoodfrequencyestimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

Maximum likelihood frequency offset estimator

Qn(KTs)

In(KTs) times2

times2

times4

timesminus1 Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

timesminus1

timesminus1

k

sumn=0

cos(4ΔwnTs + 4120579)k

sumn=0

(4ΔwnTs + 4120579)

k

sumn=0

sin(4ΔwnTs + 4120579)

Figure 7 Block diagram of QPSK ADCRL

which one is the best for the frequency offset error Δ119891 =

100KHZ under the situations of SNR = 20 10 5 dB Thesimulation result is shown in Figure 8 From Figure 8 it isclear that when the bit width is equal to 11 the frequencyestimation value of the MLFOE is almost the same as that ofhaving bit width equal to 32 under the three types of SNRsThus we set the bit width of the two inputs of MLFOE to be11

4 Simulation Results andComparative Analysis

To verify that the proposed architecture is valid the FPGAsimulation tool ModelSim SE 65 is used to observe theimplementation performance of our proposed architecturebased on FPGA On the other hand MATLAB is also usedto generate the QPSK modulated signals with a frequencyoffset under the conditions of different SNRs and process thesimulation results generated by the ModelSim so as to have abetter visual comparison resulting from that the outputs ofthe ModelSim that are just some values of decimal or binaryformat

The data streams of the entire simulation procedure areshown in Figure 9

The input stream generated quantized and stored into thetextfile Textfile A by MATLAB is QPSK modulated signalswith the following specifications

5 10 15 20 25 30 3565

70

75

80

85

90

95

100

105

Quantization size (bit)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

(kH

z)

SNR = 5dBSNR = 10dBSNR = 20dB

Figure 8The quantization level of the two input signals of MLFOEunder the condition of the frequency offset errorΔ119891 = 100KHZ andSNR = 20 10 5 dB

(i) the number of symbols randomly evaluated as plusmn1 isequal to 1000

(ii) the frequency of symbols 119891119887 = 80KHZ(iii) the frequency of carrier 119891119888 = 39MHZ namely

frequency offset Δ119891 = 100KHZ(iv) SNRs are 20 dB and 5 dB

International Journal of Reconfigurable Computing 11

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

01

CORDICCORE

Maximum likelihood frequency estimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

The output

of loop

filter

The output

ofNCO

QPSK

modulated

signal

MATLAB simulation

ModelSim simulation

Maximum likelihood frequency offset estimatorTextfile A

Textfile B Textfile C

Qn(KTs)

In(KTs) times2

times4

times2

timesminus1

timesminus1

timesminus1

Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

MATLAB process AMATLAB process B

Figure 9 The data stream of entire simulation procedure

(v) quantization level of the 1000 QPSK modulated sig-nals is 8 bits to imitate the input signals of 8-bit ADC

(vi) sample frequency 119891119904 = 26MHZ

The output streams generated and stored into anothertwo textfiles Textfile B and Textfile C by ModelSim are theoutputs of the NCO and the loop filter with the followingspecifications

Textfile B(i) the frequency of carrier 119891119888 = 4MHZ namely output

frequency of NCO(ii) sample frequency 119891119904 = 26MHZ(iii) the quantization level of the output amplitude of the

NCO evaluated as plusmn1 is 8 bitsTextfile C

(i) sample frequency 119891119904 = 26MHZ(ii) the quantization level of the output of the loop filter is

32 bits

Textfile A is generated byMATLAB before startingMod-elSim simulation and then fed into QPSK ADCRL (to imitatethe output of the ADC) in the procedure of the simulation ofModelSimwhenTextfile B andTextfile C are simultaneouslygenerated by ModelSim At the end of the simulation of theModelSim the two files from the ModelSim Textfile B andTextfile C will be read into MATLAB in order to furtherprocess in the two procedures MATLAB process A andMATLAB process B

Because the traditional measure of the performance ofPLL is based on locked-in time steady-state phase error and

locked-in frequency range our QPSK ADCRL also uses themethods

Based on the principle of our QPSK ADCRL displayedin Figure 7 when there exists the frequency offset betweenthe input of the QPSK modulated signals (Textfile A) andthe local carrier signals (the output of NCO) the offset canbe obtained through taking the output of the loop filter(Textfile C) into (21) In our design the carrier frequency ofthe input modulated signals is 39MHZ and the frequencyof the output of the NCO is 4MHZ Therefore the frequencyoffset is 100KHZ

If our QPSK ADCRL is locked the frequency offsetevaluated through taking the output of loop filter into (21) willapproximate to 100KHZ At the same time the output phaseof the NCO (Textfile B) should be equal or approximate tothe phase of the QPSK modulated signals (Textfile A)

On the basis of above discussion as shown in Figures 1011 12 and 13 (a) and (b) are the outputs of the loop filter fromModelSim simulation and its results processed by MATLAB(MATLAB process B shown in Figure 8) respectively (c) isthe result of the phase comparison of the two signals QPSKmodulated signals and the outputs of theNCOwhich is fromthe simulation ofModelSim and then processed byMATLAB(MATLAB process A shown in Figure 9)

Figures 10 and 11 are the simulation results of the classicQPSK ADCOL shown in Figure 2 without the assistance ofMLFOE shown in Figure 6 under the two conditions of SNR= 20 and 5 dB

From the two figures Figures 10(b) and 10(c) we can seethat when SNR is equal to 20 dB the tracking time is about015ms and the maximal steady-state phase error approxi-mates to 0 degree

12 International Journal of Reconfigurable Computing

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

0

10

20

Time (ms)

Freq

uenc

y off

set (

Hz)

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1N

orm

aliz

ed v

olta

ge (V

)

MATLAB outputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 10 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for the QPSK ADCOL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 11 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for the QPSK ADCOL

As shown in the two figures Figures 11(b) and 11(c) whenSNR is equal to 5 dB the tracking time is about 03ms and themaximal steady-state phase error approximates to 2 degree

Figures 12 and 13 are the simulation results under the twoconditions of SNR = 20 and 5 dB where theMLFOE has beenenabled

In contrast to Figures 10 and 11 after enabling theMLFOEfrom the two figures Figures 12(b) and 12(c) we can seethat when SNR is equal to 20 dB the locked-in time isabout 005ms and the maximal steady-state phase error alsoapproximates to 0 degree As shown in the two figuresFigures 13(b) and 13(c) when SNR is equal to 5 dB the lock-in

International Journal of Reconfigurable Computing 13

(a) ModelSim output of loop filter

0 005 01 015 02 025

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0

0

05 1 15 2 25 3 35 4

051

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

minus05

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 12 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

20

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 13 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for our QPSK ADCRL

time is about 01ms and themaximal steady-state phase errorapproximates to 3 degree

On the other hand in the case of the four figures Figures10(b) 11(b) 12(b) and 13(b) when QPSK ADCRL is lockedall frequency offset evaluated by the output of loop filter areequal to 100KHZ

From the above simulation results it is clear that after theMLFOE is enabled whether SNR is high or not the perform-ance of our QPSK ADCRL in locked-in time is two times

faster than that of the QPSK ADCOL without the assistanceof the MLFOE while the maximal steady-state phase error isalmost stable

On the other hand in the two conditions of SNR =20 dB and 5 dB we test the maximal frequency offset whichenables our QPSK ADCRL and the QPSK ADCOL withoutthe assistance of MLFOE to be locked and the correspondinglocked-in time and steady-phase error The results are shownin Table 2 From Table 2 we can see that after the MLFOE

14 International Journal of Reconfigurable Computing

Table 2 The performance advantage of our QPSK ADCRL in locked-in frequency range

SNR Architecture Maximal locked-in Locked-in time (ms) Steady-phase error (degree)Frequency Range (KHZ)

20 db QPSK ADCOL plusmn170 018 Approximating to 020 db Our QPSK ADCRL plusmn680 005 Approximating to 05 db QPSK ADCOL plusmn120 04 Approximating to 25 db Our QPSK ADCRL plusmn510 013 Approximating to 4

Table 3 The hardware cost of the different modules for our QPSK ADCRL

Module Number of slice registers Number of slice LUTs Number used as logicQPSK ADCOL 174 out of 28800 580 out of 28800 612 out of 28800

MLFOE FD 875 out of 28800 892 out of 28800 790 out of 28800MLFE 603 out of 28800 516 out of 28800 592 out of 28800

Total hardware cost 1652 out of 28800 1988 out of 28800 1994 out of 28800

Table 4 The power consumption of our QPSK ADCRL for different operating frequencies

Clock frequency (MHZ) Dynamic power (W) Quiescent power (W) Total power (W) Junction temp (C)312 0060 0526 0594 509250 0058 0526 0583 51200 0048 0525 0574 51150 0039 0525 0564 509

is enabled except for the advantage in locked-in time thelocked-in frequency range of our QPSKADCRL is four timeswider than that of the QPSK ADCOL Therefore our QPSKADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision which are hardlyreconciled for the QPSK ADCOL

There is no doubt that our QPSK ADCRL has a morerobust performance than the QPSK ADCOL without theMLFOE What is more to obtain the same improvement inperformance as our ADCRL for the existing QPSK ADCOL[23 24] the simple revision is to add the MLFOE shown inFigure 4 to the QPSK ADCOLs

Finally in order to acquire their hardware cost for thedifferent modules of our QPSK ADCRL based on FPGA theFPGA synthesis tool ISE Design Suite 122 from FPGA ven-dor Xilinx is used and its chip of Virtex5 family XC5VLX50which supports dynamic reconfiguration technology seenas a core technology to implement SDR [25] on FPGA isselected The synthesis results are given in Table 3 FromTable 3 we can see that although the MLFOE consumesmore logic resources than QPSK ADCOL (because manymultiplication operations are used and a pipelined CORDICarchitecture [26] is adopted so as to meet the requirement ofthe latency time) this is worthy for some applications whichneed a more robust QPSK ADCRL

On the other hand we can also see that the hardware costof the whole QPSK ADCRL just make up a small part of logicresources for the FPGA chip selected

Except for the hardware cost of our QPSK ADCRL wealso investigate its power consumption for the different

operating frequencies by the power analysis tool from Xil-inx XPower which is also important very much in someapplications where communication systems need to workcontinuously bymeans of a portable power sourceThe resultsare shown in Table 4 Form Table 4 we can see that when ourQPSK ADCRL operates under the condition of maximumclock frequency 312MHZ which is from the logic synthesisrsquosresult of ISE 122 the total power is just 0594 (W)

5 Conclusion and Outlook

In this paper an efficient QPSK ADCRL is proposed and asystematic procedure of designing the carrier recovery loopbased on FPGA is displayed On the other hand a FD in pos-session of linear characteristic is introduced to supply a moreprecise frequency offset to MLFE which is implemented justusing shifters and multiply-accumulate units to estimate thefrequency offset and assist QPSK ADCOL to lock quicklyThe joint simulation results of ModelSim and MATLAB hasproved that our proposed architecture can smoothly operateon FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOLSynthesis result has shown that the hardware cost of FPGAfor our QPSK ADCRL is very few and the result of the poweranalysis also has proved that our design is valid in powerconsumption

Looking at the future the exploration aiming at deepspace must be the tendency of the human developmentand the FPGA-based soft defined radio suitable for the

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

International Journal of

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DistributedSensor Networks

International Journal of

Page 10: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

10 International Journal of Reconfigurable Computing

ADC

Low pass filter

Low passfilter

RegReg

Numericallycontrolledoscillator

Frequency control word

01

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

Modulated signalfrom transmitter

01

CORDICCORE

Maximumlikelihoodfrequencyestimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

Maximum likelihood frequency offset estimator

Qn(KTs)

In(KTs) times2

times2

times4

timesminus1 Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

timesminus1

timesminus1

k

sumn=0

cos(4ΔwnTs + 4120579)k

sumn=0

(4ΔwnTs + 4120579)

k

sumn=0

sin(4ΔwnTs + 4120579)

Figure 7 Block diagram of QPSK ADCRL

which one is the best for the frequency offset error Δ119891 =

100KHZ under the situations of SNR = 20 10 5 dB Thesimulation result is shown in Figure 8 From Figure 8 it isclear that when the bit width is equal to 11 the frequencyestimation value of the MLFOE is almost the same as that ofhaving bit width equal to 32 under the three types of SNRsThus we set the bit width of the two inputs of MLFOE to be11

4 Simulation Results andComparative Analysis

To verify that the proposed architecture is valid the FPGAsimulation tool ModelSim SE 65 is used to observe theimplementation performance of our proposed architecturebased on FPGA On the other hand MATLAB is also usedto generate the QPSK modulated signals with a frequencyoffset under the conditions of different SNRs and process thesimulation results generated by the ModelSim so as to have abetter visual comparison resulting from that the outputs ofthe ModelSim that are just some values of decimal or binaryformat

The data streams of the entire simulation procedure areshown in Figure 9

The input stream generated quantized and stored into thetextfile Textfile A by MATLAB is QPSK modulated signalswith the following specifications

5 10 15 20 25 30 3565

70

75

80

85

90

95

100

105

Quantization size (bit)

Estim

atio

n va

lue o

f fre

quen

cy o

ffset

(kH

z)

SNR = 5dBSNR = 10dBSNR = 20dB

Figure 8The quantization level of the two input signals of MLFOEunder the condition of the frequency offset errorΔ119891 = 100KHZ andSNR = 20 10 5 dB

(i) the number of symbols randomly evaluated as plusmn1 isequal to 1000

(ii) the frequency of symbols 119891119887 = 80KHZ(iii) the frequency of carrier 119891119888 = 39MHZ namely

frequency offset Δ119891 = 100KHZ(iv) SNRs are 20 dB and 5 dB

International Journal of Reconfigurable Computing 11

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

01

CORDICCORE

Maximum likelihood frequency estimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

The output

of loop

filter

The output

ofNCO

QPSK

modulated

signal

MATLAB simulation

ModelSim simulation

Maximum likelihood frequency offset estimatorTextfile A

Textfile B Textfile C

Qn(KTs)

In(KTs) times2

times4

times2

timesminus1

timesminus1

timesminus1

Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

MATLAB process AMATLAB process B

Figure 9 The data stream of entire simulation procedure

(v) quantization level of the 1000 QPSK modulated sig-nals is 8 bits to imitate the input signals of 8-bit ADC

(vi) sample frequency 119891119904 = 26MHZ

The output streams generated and stored into anothertwo textfiles Textfile B and Textfile C by ModelSim are theoutputs of the NCO and the loop filter with the followingspecifications

Textfile B(i) the frequency of carrier 119891119888 = 4MHZ namely output

frequency of NCO(ii) sample frequency 119891119904 = 26MHZ(iii) the quantization level of the output amplitude of the

NCO evaluated as plusmn1 is 8 bitsTextfile C

(i) sample frequency 119891119904 = 26MHZ(ii) the quantization level of the output of the loop filter is

32 bits

Textfile A is generated byMATLAB before startingMod-elSim simulation and then fed into QPSK ADCRL (to imitatethe output of the ADC) in the procedure of the simulation ofModelSimwhenTextfile B andTextfile C are simultaneouslygenerated by ModelSim At the end of the simulation of theModelSim the two files from the ModelSim Textfile B andTextfile C will be read into MATLAB in order to furtherprocess in the two procedures MATLAB process A andMATLAB process B

Because the traditional measure of the performance ofPLL is based on locked-in time steady-state phase error and

locked-in frequency range our QPSK ADCRL also uses themethods

Based on the principle of our QPSK ADCRL displayedin Figure 7 when there exists the frequency offset betweenthe input of the QPSK modulated signals (Textfile A) andthe local carrier signals (the output of NCO) the offset canbe obtained through taking the output of the loop filter(Textfile C) into (21) In our design the carrier frequency ofthe input modulated signals is 39MHZ and the frequencyof the output of the NCO is 4MHZ Therefore the frequencyoffset is 100KHZ

If our QPSK ADCRL is locked the frequency offsetevaluated through taking the output of loop filter into (21) willapproximate to 100KHZ At the same time the output phaseof the NCO (Textfile B) should be equal or approximate tothe phase of the QPSK modulated signals (Textfile A)

On the basis of above discussion as shown in Figures 1011 12 and 13 (a) and (b) are the outputs of the loop filter fromModelSim simulation and its results processed by MATLAB(MATLAB process B shown in Figure 8) respectively (c) isthe result of the phase comparison of the two signals QPSKmodulated signals and the outputs of theNCOwhich is fromthe simulation ofModelSim and then processed byMATLAB(MATLAB process A shown in Figure 9)

Figures 10 and 11 are the simulation results of the classicQPSK ADCOL shown in Figure 2 without the assistance ofMLFOE shown in Figure 6 under the two conditions of SNR= 20 and 5 dB

From the two figures Figures 10(b) and 10(c) we can seethat when SNR is equal to 20 dB the tracking time is about015ms and the maximal steady-state phase error approxi-mates to 0 degree

12 International Journal of Reconfigurable Computing

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

0

10

20

Time (ms)

Freq

uenc

y off

set (

Hz)

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1N

orm

aliz

ed v

olta

ge (V

)

MATLAB outputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 10 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for the QPSK ADCOL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 11 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for the QPSK ADCOL

As shown in the two figures Figures 11(b) and 11(c) whenSNR is equal to 5 dB the tracking time is about 03ms and themaximal steady-state phase error approximates to 2 degree

Figures 12 and 13 are the simulation results under the twoconditions of SNR = 20 and 5 dB where theMLFOE has beenenabled

In contrast to Figures 10 and 11 after enabling theMLFOEfrom the two figures Figures 12(b) and 12(c) we can seethat when SNR is equal to 20 dB the locked-in time isabout 005ms and the maximal steady-state phase error alsoapproximates to 0 degree As shown in the two figuresFigures 13(b) and 13(c) when SNR is equal to 5 dB the lock-in

International Journal of Reconfigurable Computing 13

(a) ModelSim output of loop filter

0 005 01 015 02 025

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0

0

05 1 15 2 25 3 35 4

051

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

minus05

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 12 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

20

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 13 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for our QPSK ADCRL

time is about 01ms and themaximal steady-state phase errorapproximates to 3 degree

On the other hand in the case of the four figures Figures10(b) 11(b) 12(b) and 13(b) when QPSK ADCRL is lockedall frequency offset evaluated by the output of loop filter areequal to 100KHZ

From the above simulation results it is clear that after theMLFOE is enabled whether SNR is high or not the perform-ance of our QPSK ADCRL in locked-in time is two times

faster than that of the QPSK ADCOL without the assistanceof the MLFOE while the maximal steady-state phase error isalmost stable

On the other hand in the two conditions of SNR =20 dB and 5 dB we test the maximal frequency offset whichenables our QPSK ADCRL and the QPSK ADCOL withoutthe assistance of MLFOE to be locked and the correspondinglocked-in time and steady-phase error The results are shownin Table 2 From Table 2 we can see that after the MLFOE

14 International Journal of Reconfigurable Computing

Table 2 The performance advantage of our QPSK ADCRL in locked-in frequency range

SNR Architecture Maximal locked-in Locked-in time (ms) Steady-phase error (degree)Frequency Range (KHZ)

20 db QPSK ADCOL plusmn170 018 Approximating to 020 db Our QPSK ADCRL plusmn680 005 Approximating to 05 db QPSK ADCOL plusmn120 04 Approximating to 25 db Our QPSK ADCRL plusmn510 013 Approximating to 4

Table 3 The hardware cost of the different modules for our QPSK ADCRL

Module Number of slice registers Number of slice LUTs Number used as logicQPSK ADCOL 174 out of 28800 580 out of 28800 612 out of 28800

MLFOE FD 875 out of 28800 892 out of 28800 790 out of 28800MLFE 603 out of 28800 516 out of 28800 592 out of 28800

Total hardware cost 1652 out of 28800 1988 out of 28800 1994 out of 28800

Table 4 The power consumption of our QPSK ADCRL for different operating frequencies

Clock frequency (MHZ) Dynamic power (W) Quiescent power (W) Total power (W) Junction temp (C)312 0060 0526 0594 509250 0058 0526 0583 51200 0048 0525 0574 51150 0039 0525 0564 509

is enabled except for the advantage in locked-in time thelocked-in frequency range of our QPSKADCRL is four timeswider than that of the QPSK ADCOL Therefore our QPSKADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision which are hardlyreconciled for the QPSK ADCOL

There is no doubt that our QPSK ADCRL has a morerobust performance than the QPSK ADCOL without theMLFOE What is more to obtain the same improvement inperformance as our ADCRL for the existing QPSK ADCOL[23 24] the simple revision is to add the MLFOE shown inFigure 4 to the QPSK ADCOLs

Finally in order to acquire their hardware cost for thedifferent modules of our QPSK ADCRL based on FPGA theFPGA synthesis tool ISE Design Suite 122 from FPGA ven-dor Xilinx is used and its chip of Virtex5 family XC5VLX50which supports dynamic reconfiguration technology seenas a core technology to implement SDR [25] on FPGA isselected The synthesis results are given in Table 3 FromTable 3 we can see that although the MLFOE consumesmore logic resources than QPSK ADCOL (because manymultiplication operations are used and a pipelined CORDICarchitecture [26] is adopted so as to meet the requirement ofthe latency time) this is worthy for some applications whichneed a more robust QPSK ADCRL

On the other hand we can also see that the hardware costof the whole QPSK ADCRL just make up a small part of logicresources for the FPGA chip selected

Except for the hardware cost of our QPSK ADCRL wealso investigate its power consumption for the different

operating frequencies by the power analysis tool from Xil-inx XPower which is also important very much in someapplications where communication systems need to workcontinuously bymeans of a portable power sourceThe resultsare shown in Table 4 Form Table 4 we can see that when ourQPSK ADCRL operates under the condition of maximumclock frequency 312MHZ which is from the logic synthesisrsquosresult of ISE 122 the total power is just 0594 (W)

5 Conclusion and Outlook

In this paper an efficient QPSK ADCRL is proposed and asystematic procedure of designing the carrier recovery loopbased on FPGA is displayed On the other hand a FD in pos-session of linear characteristic is introduced to supply a moreprecise frequency offset to MLFE which is implemented justusing shifters and multiply-accumulate units to estimate thefrequency offset and assist QPSK ADCOL to lock quicklyThe joint simulation results of ModelSim and MATLAB hasproved that our proposed architecture can smoothly operateon FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOLSynthesis result has shown that the hardware cost of FPGAfor our QPSK ADCRL is very few and the result of the poweranalysis also has proved that our design is valid in powerconsumption

Looking at the future the exploration aiming at deepspace must be the tendency of the human developmentand the FPGA-based soft defined radio suitable for the

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

Page 11: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

International Journal of Reconfigurable Computing 11

ADC

Low pass filter

Low pass filter

Reg

RegNumerically controlledoscillator

Frequency control word

0

1

Shifter

Shifter

8

8

8

8

16

16 32

32

32

32

32

32

MSB 1

MSB 1

01

CORDICCORE

Maximum likelihood frequency estimator

11

11

22

22

22

44

44

44

32

32

QPSK phase-locked loop

The output

of loop

filter

The output

ofNCO

QPSK

modulated

signal

MATLAB simulation

ModelSim simulation

Maximum likelihood frequency offset estimatorTextfile A

Textfile B Textfile C

Qn(KTs)

In(KTs) times2

times4

times2

timesminus1

timesminus1

timesminus1

Arctan (x)

Quadrature branch (Q)

In-phase branch (I)

C1

C2

k

sumn=0

cos(4ΔwnTs + 4Δ120579)

k

sumn=0

(4ΔwnTs + 4Δ120579)

k

sumn=0

sin(4ΔwnTs + 4Δ120579)

MATLAB process AMATLAB process B

Figure 9 The data stream of entire simulation procedure

(v) quantization level of the 1000 QPSK modulated sig-nals is 8 bits to imitate the input signals of 8-bit ADC

(vi) sample frequency 119891119904 = 26MHZ

The output streams generated and stored into anothertwo textfiles Textfile B and Textfile C by ModelSim are theoutputs of the NCO and the loop filter with the followingspecifications

Textfile B(i) the frequency of carrier 119891119888 = 4MHZ namely output

frequency of NCO(ii) sample frequency 119891119904 = 26MHZ(iii) the quantization level of the output amplitude of the

NCO evaluated as plusmn1 is 8 bitsTextfile C

(i) sample frequency 119891119904 = 26MHZ(ii) the quantization level of the output of the loop filter is

32 bits

Textfile A is generated byMATLAB before startingMod-elSim simulation and then fed into QPSK ADCRL (to imitatethe output of the ADC) in the procedure of the simulation ofModelSimwhenTextfile B andTextfile C are simultaneouslygenerated by ModelSim At the end of the simulation of theModelSim the two files from the ModelSim Textfile B andTextfile C will be read into MATLAB in order to furtherprocess in the two procedures MATLAB process A andMATLAB process B

Because the traditional measure of the performance ofPLL is based on locked-in time steady-state phase error and

locked-in frequency range our QPSK ADCRL also uses themethods

Based on the principle of our QPSK ADCRL displayedin Figure 7 when there exists the frequency offset betweenthe input of the QPSK modulated signals (Textfile A) andthe local carrier signals (the output of NCO) the offset canbe obtained through taking the output of the loop filter(Textfile C) into (21) In our design the carrier frequency ofthe input modulated signals is 39MHZ and the frequencyof the output of the NCO is 4MHZ Therefore the frequencyoffset is 100KHZ

If our QPSK ADCRL is locked the frequency offsetevaluated through taking the output of loop filter into (21) willapproximate to 100KHZ At the same time the output phaseof the NCO (Textfile B) should be equal or approximate tothe phase of the QPSK modulated signals (Textfile A)

On the basis of above discussion as shown in Figures 1011 12 and 13 (a) and (b) are the outputs of the loop filter fromModelSim simulation and its results processed by MATLAB(MATLAB process B shown in Figure 8) respectively (c) isthe result of the phase comparison of the two signals QPSKmodulated signals and the outputs of theNCOwhich is fromthe simulation ofModelSim and then processed byMATLAB(MATLAB process A shown in Figure 9)

Figures 10 and 11 are the simulation results of the classicQPSK ADCOL shown in Figure 2 without the assistance ofMLFOE shown in Figure 6 under the two conditions of SNR= 20 and 5 dB

From the two figures Figures 10(b) and 10(c) we can seethat when SNR is equal to 20 dB the tracking time is about015ms and the maximal steady-state phase error approxi-mates to 0 degree

12 International Journal of Reconfigurable Computing

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

0

10

20

Time (ms)

Freq

uenc

y off

set (

Hz)

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1N

orm

aliz

ed v

olta

ge (V

)

MATLAB outputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 10 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for the QPSK ADCOL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 11 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for the QPSK ADCOL

As shown in the two figures Figures 11(b) and 11(c) whenSNR is equal to 5 dB the tracking time is about 03ms and themaximal steady-state phase error approximates to 2 degree

Figures 12 and 13 are the simulation results under the twoconditions of SNR = 20 and 5 dB where theMLFOE has beenenabled

In contrast to Figures 10 and 11 after enabling theMLFOEfrom the two figures Figures 12(b) and 12(c) we can seethat when SNR is equal to 20 dB the locked-in time isabout 005ms and the maximal steady-state phase error alsoapproximates to 0 degree As shown in the two figuresFigures 13(b) and 13(c) when SNR is equal to 5 dB the lock-in

International Journal of Reconfigurable Computing 13

(a) ModelSim output of loop filter

0 005 01 015 02 025

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0

0

05 1 15 2 25 3 35 4

051

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

minus05

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 12 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

20

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 13 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for our QPSK ADCRL

time is about 01ms and themaximal steady-state phase errorapproximates to 3 degree

On the other hand in the case of the four figures Figures10(b) 11(b) 12(b) and 13(b) when QPSK ADCRL is lockedall frequency offset evaluated by the output of loop filter areequal to 100KHZ

From the above simulation results it is clear that after theMLFOE is enabled whether SNR is high or not the perform-ance of our QPSK ADCRL in locked-in time is two times

faster than that of the QPSK ADCOL without the assistanceof the MLFOE while the maximal steady-state phase error isalmost stable

On the other hand in the two conditions of SNR =20 dB and 5 dB we test the maximal frequency offset whichenables our QPSK ADCRL and the QPSK ADCOL withoutthe assistance of MLFOE to be locked and the correspondinglocked-in time and steady-phase error The results are shownin Table 2 From Table 2 we can see that after the MLFOE

14 International Journal of Reconfigurable Computing

Table 2 The performance advantage of our QPSK ADCRL in locked-in frequency range

SNR Architecture Maximal locked-in Locked-in time (ms) Steady-phase error (degree)Frequency Range (KHZ)

20 db QPSK ADCOL plusmn170 018 Approximating to 020 db Our QPSK ADCRL plusmn680 005 Approximating to 05 db QPSK ADCOL plusmn120 04 Approximating to 25 db Our QPSK ADCRL plusmn510 013 Approximating to 4

Table 3 The hardware cost of the different modules for our QPSK ADCRL

Module Number of slice registers Number of slice LUTs Number used as logicQPSK ADCOL 174 out of 28800 580 out of 28800 612 out of 28800

MLFOE FD 875 out of 28800 892 out of 28800 790 out of 28800MLFE 603 out of 28800 516 out of 28800 592 out of 28800

Total hardware cost 1652 out of 28800 1988 out of 28800 1994 out of 28800

Table 4 The power consumption of our QPSK ADCRL for different operating frequencies

Clock frequency (MHZ) Dynamic power (W) Quiescent power (W) Total power (W) Junction temp (C)312 0060 0526 0594 509250 0058 0526 0583 51200 0048 0525 0574 51150 0039 0525 0564 509

is enabled except for the advantage in locked-in time thelocked-in frequency range of our QPSKADCRL is four timeswider than that of the QPSK ADCOL Therefore our QPSKADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision which are hardlyreconciled for the QPSK ADCOL

There is no doubt that our QPSK ADCRL has a morerobust performance than the QPSK ADCOL without theMLFOE What is more to obtain the same improvement inperformance as our ADCRL for the existing QPSK ADCOL[23 24] the simple revision is to add the MLFOE shown inFigure 4 to the QPSK ADCOLs

Finally in order to acquire their hardware cost for thedifferent modules of our QPSK ADCRL based on FPGA theFPGA synthesis tool ISE Design Suite 122 from FPGA ven-dor Xilinx is used and its chip of Virtex5 family XC5VLX50which supports dynamic reconfiguration technology seenas a core technology to implement SDR [25] on FPGA isselected The synthesis results are given in Table 3 FromTable 3 we can see that although the MLFOE consumesmore logic resources than QPSK ADCOL (because manymultiplication operations are used and a pipelined CORDICarchitecture [26] is adopted so as to meet the requirement ofthe latency time) this is worthy for some applications whichneed a more robust QPSK ADCRL

On the other hand we can also see that the hardware costof the whole QPSK ADCRL just make up a small part of logicresources for the FPGA chip selected

Except for the hardware cost of our QPSK ADCRL wealso investigate its power consumption for the different

operating frequencies by the power analysis tool from Xil-inx XPower which is also important very much in someapplications where communication systems need to workcontinuously bymeans of a portable power sourceThe resultsare shown in Table 4 Form Table 4 we can see that when ourQPSK ADCRL operates under the condition of maximumclock frequency 312MHZ which is from the logic synthesisrsquosresult of ISE 122 the total power is just 0594 (W)

5 Conclusion and Outlook

In this paper an efficient QPSK ADCRL is proposed and asystematic procedure of designing the carrier recovery loopbased on FPGA is displayed On the other hand a FD in pos-session of linear characteristic is introduced to supply a moreprecise frequency offset to MLFE which is implemented justusing shifters and multiply-accumulate units to estimate thefrequency offset and assist QPSK ADCOL to lock quicklyThe joint simulation results of ModelSim and MATLAB hasproved that our proposed architecture can smoothly operateon FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOLSynthesis result has shown that the hardware cost of FPGAfor our QPSK ADCRL is very few and the result of the poweranalysis also has proved that our design is valid in powerconsumption

Looking at the future the exploration aiming at deepspace must be the tendency of the human developmentand the FPGA-based soft defined radio suitable for the

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

Page 12: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

12 International Journal of Reconfigurable Computing

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

0

10

20

Time (ms)

Freq

uenc

y off

set (

Hz)

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1N

orm

aliz

ed v

olta

ge (V

)

MATLAB outputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 10 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for the QPSK ADCOL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03 035

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 11 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for the QPSK ADCOL

As shown in the two figures Figures 11(b) and 11(c) whenSNR is equal to 5 dB the tracking time is about 03ms and themaximal steady-state phase error approximates to 2 degree

Figures 12 and 13 are the simulation results under the twoconditions of SNR = 20 and 5 dB where theMLFOE has beenenabled

In contrast to Figures 10 and 11 after enabling theMLFOEfrom the two figures Figures 12(b) and 12(c) we can seethat when SNR is equal to 20 dB the locked-in time isabout 005ms and the maximal steady-state phase error alsoapproximates to 0 degree As shown in the two figuresFigures 13(b) and 13(c) when SNR is equal to 5 dB the lock-in

International Journal of Reconfigurable Computing 13

(a) ModelSim output of loop filter

0 005 01 015 02 025

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0

0

05 1 15 2 25 3 35 4

051

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

minus05

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 12 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

20

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 13 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for our QPSK ADCRL

time is about 01ms and themaximal steady-state phase errorapproximates to 3 degree

On the other hand in the case of the four figures Figures10(b) 11(b) 12(b) and 13(b) when QPSK ADCRL is lockedall frequency offset evaluated by the output of loop filter areequal to 100KHZ

From the above simulation results it is clear that after theMLFOE is enabled whether SNR is high or not the perform-ance of our QPSK ADCRL in locked-in time is two times

faster than that of the QPSK ADCOL without the assistanceof the MLFOE while the maximal steady-state phase error isalmost stable

On the other hand in the two conditions of SNR =20 dB and 5 dB we test the maximal frequency offset whichenables our QPSK ADCRL and the QPSK ADCOL withoutthe assistance of MLFOE to be locked and the correspondinglocked-in time and steady-phase error The results are shownin Table 2 From Table 2 we can see that after the MLFOE

14 International Journal of Reconfigurable Computing

Table 2 The performance advantage of our QPSK ADCRL in locked-in frequency range

SNR Architecture Maximal locked-in Locked-in time (ms) Steady-phase error (degree)Frequency Range (KHZ)

20 db QPSK ADCOL plusmn170 018 Approximating to 020 db Our QPSK ADCRL plusmn680 005 Approximating to 05 db QPSK ADCOL plusmn120 04 Approximating to 25 db Our QPSK ADCRL plusmn510 013 Approximating to 4

Table 3 The hardware cost of the different modules for our QPSK ADCRL

Module Number of slice registers Number of slice LUTs Number used as logicQPSK ADCOL 174 out of 28800 580 out of 28800 612 out of 28800

MLFOE FD 875 out of 28800 892 out of 28800 790 out of 28800MLFE 603 out of 28800 516 out of 28800 592 out of 28800

Total hardware cost 1652 out of 28800 1988 out of 28800 1994 out of 28800

Table 4 The power consumption of our QPSK ADCRL for different operating frequencies

Clock frequency (MHZ) Dynamic power (W) Quiescent power (W) Total power (W) Junction temp (C)312 0060 0526 0594 509250 0058 0526 0583 51200 0048 0525 0574 51150 0039 0525 0564 509

is enabled except for the advantage in locked-in time thelocked-in frequency range of our QPSKADCRL is four timeswider than that of the QPSK ADCOL Therefore our QPSKADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision which are hardlyreconciled for the QPSK ADCOL

There is no doubt that our QPSK ADCRL has a morerobust performance than the QPSK ADCOL without theMLFOE What is more to obtain the same improvement inperformance as our ADCRL for the existing QPSK ADCOL[23 24] the simple revision is to add the MLFOE shown inFigure 4 to the QPSK ADCOLs

Finally in order to acquire their hardware cost for thedifferent modules of our QPSK ADCRL based on FPGA theFPGA synthesis tool ISE Design Suite 122 from FPGA ven-dor Xilinx is used and its chip of Virtex5 family XC5VLX50which supports dynamic reconfiguration technology seenas a core technology to implement SDR [25] on FPGA isselected The synthesis results are given in Table 3 FromTable 3 we can see that although the MLFOE consumesmore logic resources than QPSK ADCOL (because manymultiplication operations are used and a pipelined CORDICarchitecture [26] is adopted so as to meet the requirement ofthe latency time) this is worthy for some applications whichneed a more robust QPSK ADCRL

On the other hand we can also see that the hardware costof the whole QPSK ADCRL just make up a small part of logicresources for the FPGA chip selected

Except for the hardware cost of our QPSK ADCRL wealso investigate its power consumption for the different

operating frequencies by the power analysis tool from Xil-inx XPower which is also important very much in someapplications where communication systems need to workcontinuously bymeans of a portable power sourceThe resultsare shown in Table 4 Form Table 4 we can see that when ourQPSK ADCRL operates under the condition of maximumclock frequency 312MHZ which is from the logic synthesisrsquosresult of ISE 122 the total power is just 0594 (W)

5 Conclusion and Outlook

In this paper an efficient QPSK ADCRL is proposed and asystematic procedure of designing the carrier recovery loopbased on FPGA is displayed On the other hand a FD in pos-session of linear characteristic is introduced to supply a moreprecise frequency offset to MLFE which is implemented justusing shifters and multiply-accumulate units to estimate thefrequency offset and assist QPSK ADCOL to lock quicklyThe joint simulation results of ModelSim and MATLAB hasproved that our proposed architecture can smoothly operateon FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOLSynthesis result has shown that the hardware cost of FPGAfor our QPSK ADCRL is very few and the result of the poweranalysis also has proved that our design is valid in powerconsumption

Looking at the future the exploration aiming at deepspace must be the tendency of the human developmentand the FPGA-based soft defined radio suitable for the

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

Page 13: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

International Journal of Reconfigurable Computing 13

(a) ModelSim output of loop filter

0 005 01 015 02 025

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

minus5

times104

(b) MATLAB processing of output of loop filter

0

0

05 1 15 2 25 3 35 4

051

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

minus05

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 12 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL

(a) ModelSim output of loop filter

0 005 01 015 02 025 03

05

1015

Time (ms)

Freq

uenc

y off

set (

Hz)

20

minus5

times104

(b) MATLAB processing of output of loop filter

0 05 1 15 2 25 3 35 4

0

1

Nor

mal

ized

vol

tage

(V)

MATLAB inputNCO output

minus1

times10minus6Time (120583s)

(c) MATLAB processing of ModelSim the output of NCO and input ofQPSK modulated signal

Figure 13 The joint simulation result of ModelSim and MATLAB under the condition of SNR = 5 dB for our QPSK ADCRL

time is about 01ms and themaximal steady-state phase errorapproximates to 3 degree

On the other hand in the case of the four figures Figures10(b) 11(b) 12(b) and 13(b) when QPSK ADCRL is lockedall frequency offset evaluated by the output of loop filter areequal to 100KHZ

From the above simulation results it is clear that after theMLFOE is enabled whether SNR is high or not the perform-ance of our QPSK ADCRL in locked-in time is two times

faster than that of the QPSK ADCOL without the assistanceof the MLFOE while the maximal steady-state phase error isalmost stable

On the other hand in the two conditions of SNR =20 dB and 5 dB we test the maximal frequency offset whichenables our QPSK ADCRL and the QPSK ADCOL withoutthe assistance of MLFOE to be locked and the correspondinglocked-in time and steady-phase error The results are shownin Table 2 From Table 2 we can see that after the MLFOE

14 International Journal of Reconfigurable Computing

Table 2 The performance advantage of our QPSK ADCRL in locked-in frequency range

SNR Architecture Maximal locked-in Locked-in time (ms) Steady-phase error (degree)Frequency Range (KHZ)

20 db QPSK ADCOL plusmn170 018 Approximating to 020 db Our QPSK ADCRL plusmn680 005 Approximating to 05 db QPSK ADCOL plusmn120 04 Approximating to 25 db Our QPSK ADCRL plusmn510 013 Approximating to 4

Table 3 The hardware cost of the different modules for our QPSK ADCRL

Module Number of slice registers Number of slice LUTs Number used as logicQPSK ADCOL 174 out of 28800 580 out of 28800 612 out of 28800

MLFOE FD 875 out of 28800 892 out of 28800 790 out of 28800MLFE 603 out of 28800 516 out of 28800 592 out of 28800

Total hardware cost 1652 out of 28800 1988 out of 28800 1994 out of 28800

Table 4 The power consumption of our QPSK ADCRL for different operating frequencies

Clock frequency (MHZ) Dynamic power (W) Quiescent power (W) Total power (W) Junction temp (C)312 0060 0526 0594 509250 0058 0526 0583 51200 0048 0525 0574 51150 0039 0525 0564 509

is enabled except for the advantage in locked-in time thelocked-in frequency range of our QPSKADCRL is four timeswider than that of the QPSK ADCOL Therefore our QPSKADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision which are hardlyreconciled for the QPSK ADCOL

There is no doubt that our QPSK ADCRL has a morerobust performance than the QPSK ADCOL without theMLFOE What is more to obtain the same improvement inperformance as our ADCRL for the existing QPSK ADCOL[23 24] the simple revision is to add the MLFOE shown inFigure 4 to the QPSK ADCOLs

Finally in order to acquire their hardware cost for thedifferent modules of our QPSK ADCRL based on FPGA theFPGA synthesis tool ISE Design Suite 122 from FPGA ven-dor Xilinx is used and its chip of Virtex5 family XC5VLX50which supports dynamic reconfiguration technology seenas a core technology to implement SDR [25] on FPGA isselected The synthesis results are given in Table 3 FromTable 3 we can see that although the MLFOE consumesmore logic resources than QPSK ADCOL (because manymultiplication operations are used and a pipelined CORDICarchitecture [26] is adopted so as to meet the requirement ofthe latency time) this is worthy for some applications whichneed a more robust QPSK ADCRL

On the other hand we can also see that the hardware costof the whole QPSK ADCRL just make up a small part of logicresources for the FPGA chip selected

Except for the hardware cost of our QPSK ADCRL wealso investigate its power consumption for the different

operating frequencies by the power analysis tool from Xil-inx XPower which is also important very much in someapplications where communication systems need to workcontinuously bymeans of a portable power sourceThe resultsare shown in Table 4 Form Table 4 we can see that when ourQPSK ADCRL operates under the condition of maximumclock frequency 312MHZ which is from the logic synthesisrsquosresult of ISE 122 the total power is just 0594 (W)

5 Conclusion and Outlook

In this paper an efficient QPSK ADCRL is proposed and asystematic procedure of designing the carrier recovery loopbased on FPGA is displayed On the other hand a FD in pos-session of linear characteristic is introduced to supply a moreprecise frequency offset to MLFE which is implemented justusing shifters and multiply-accumulate units to estimate thefrequency offset and assist QPSK ADCOL to lock quicklyThe joint simulation results of ModelSim and MATLAB hasproved that our proposed architecture can smoothly operateon FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOLSynthesis result has shown that the hardware cost of FPGAfor our QPSK ADCRL is very few and the result of the poweranalysis also has proved that our design is valid in powerconsumption

Looking at the future the exploration aiming at deepspace must be the tendency of the human developmentand the FPGA-based soft defined radio suitable for the

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

Page 14: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

14 International Journal of Reconfigurable Computing

Table 2 The performance advantage of our QPSK ADCRL in locked-in frequency range

SNR Architecture Maximal locked-in Locked-in time (ms) Steady-phase error (degree)Frequency Range (KHZ)

20 db QPSK ADCOL plusmn170 018 Approximating to 020 db Our QPSK ADCRL plusmn680 005 Approximating to 05 db QPSK ADCOL plusmn120 04 Approximating to 25 db Our QPSK ADCRL plusmn510 013 Approximating to 4

Table 3 The hardware cost of the different modules for our QPSK ADCRL

Module Number of slice registers Number of slice LUTs Number used as logicQPSK ADCOL 174 out of 28800 580 out of 28800 612 out of 28800

MLFOE FD 875 out of 28800 892 out of 28800 790 out of 28800MLFE 603 out of 28800 516 out of 28800 592 out of 28800

Total hardware cost 1652 out of 28800 1988 out of 28800 1994 out of 28800

Table 4 The power consumption of our QPSK ADCRL for different operating frequencies

Clock frequency (MHZ) Dynamic power (W) Quiescent power (W) Total power (W) Junction temp (C)312 0060 0526 0594 509250 0058 0526 0583 51200 0048 0525 0574 51150 0039 0525 0564 509

is enabled except for the advantage in locked-in time thelocked-in frequency range of our QPSKADCRL is four timeswider than that of the QPSK ADCOL Therefore our QPSKADCRL can alleviate the pair of contradictions between lock-in frequency range and tracking precision which are hardlyreconciled for the QPSK ADCOL

There is no doubt that our QPSK ADCRL has a morerobust performance than the QPSK ADCOL without theMLFOE What is more to obtain the same improvement inperformance as our ADCRL for the existing QPSK ADCOL[23 24] the simple revision is to add the MLFOE shown inFigure 4 to the QPSK ADCOLs

Finally in order to acquire their hardware cost for thedifferent modules of our QPSK ADCRL based on FPGA theFPGA synthesis tool ISE Design Suite 122 from FPGA ven-dor Xilinx is used and its chip of Virtex5 family XC5VLX50which supports dynamic reconfiguration technology seenas a core technology to implement SDR [25] on FPGA isselected The synthesis results are given in Table 3 FromTable 3 we can see that although the MLFOE consumesmore logic resources than QPSK ADCOL (because manymultiplication operations are used and a pipelined CORDICarchitecture [26] is adopted so as to meet the requirement ofthe latency time) this is worthy for some applications whichneed a more robust QPSK ADCRL

On the other hand we can also see that the hardware costof the whole QPSK ADCRL just make up a small part of logicresources for the FPGA chip selected

Except for the hardware cost of our QPSK ADCRL wealso investigate its power consumption for the different

operating frequencies by the power analysis tool from Xil-inx XPower which is also important very much in someapplications where communication systems need to workcontinuously bymeans of a portable power sourceThe resultsare shown in Table 4 Form Table 4 we can see that when ourQPSK ADCRL operates under the condition of maximumclock frequency 312MHZ which is from the logic synthesisrsquosresult of ISE 122 the total power is just 0594 (W)

5 Conclusion and Outlook

In this paper an efficient QPSK ADCRL is proposed and asystematic procedure of designing the carrier recovery loopbased on FPGA is displayed On the other hand a FD in pos-session of linear characteristic is introduced to supply a moreprecise frequency offset to MLFE which is implemented justusing shifters and multiply-accumulate units to estimate thefrequency offset and assist QPSK ADCOL to lock quicklyThe joint simulation results of ModelSim and MATLAB hasproved that our proposed architecture can smoothly operateon FPGA and its performances in locked-in time and locked-in range are more excellent than the classic QPSK ADCOLSynthesis result has shown that the hardware cost of FPGAfor our QPSK ADCRL is very few and the result of the poweranalysis also has proved that our design is valid in powerconsumption

Looking at the future the exploration aiming at deepspace must be the tendency of the human developmentand the FPGA-based soft defined radio suitable for the

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

Page 15: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

International Journal of Reconfigurable Computing 15

environment will be also more widely applied and furtherstudied

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] J Yuen Autonomous Software-Defined Radio Receivers for DeepSpace Applications Wiley 2006

[2] N Kim and I Ha ldquoDesign of ADPLL for both large lock-inrange and good tracking performancerdquo IEEE Transactions onCircuits and Systems II Analog andDigital Signal Processing vol46 no 9 pp 1192ndash1204 1999

[3] C Cahn ldquoImproving frequency acquisition of a Costas looprdquoIEEE Transactions on Communications vol 25 no 12 pp 1453ndash1459 1977

[4] E Frantzeskakis C Papathanasiou D Doumenis et al ldquoSin-gle chip OQPSK modem appropriate for wireless burst datacommunicationsrdquo in Proceedings of the International Conferenceon Signal Processing Applications and Technology Orlando FlaUSA November 1999

[5] W Le W Zhu-gang and X Wei-ming ldquoHigh-accurate carrieracquisition based onmaximum likelihood estimation of refinedfrequencyrdquo Telecommunication Engineering vol 53 no 1 pp39ndash43 2013

[6] F Cheng and Q Cheng ldquoThe large sample performance ofa maximum likelihood method for OFDM carrier frequencyoffset estimationrdquo Wireless Personal Communications vol 72no 1 pp 227ndash244 2013

[7] S Tao L Huijie and L Xuwen ldquoA kind of all digital phaselocked loop used in the situation of tremendous frequencyoffset error and low signal to noiserdquo Journal of Electronics andInformation Technology vol 27 no 8 2005

[8] L Baowei C Shijing H Yuanjie and G HongTao ldquoThe designof QPSK carrier recovery loop in the environment of enormousfrequency offset error and low signal to noiserdquo The Journal ofRadio Engineering vol 39 no 4 pp 51ndash54 2009

[9] M Kumm H Klingbeil and P Zipf ldquoAn FPGA-based linearall-digital phase-locked looprdquo IEEETransactions onCircuits andSystems I Regular Papers vol 57 no 9 pp 2487ndash2497 2010

[10] E B Roland Phase-Locked Loop Simulation and ApplicationsMcGraw-Hill New York NY USA 5th edition 2003

[11] S K Mitra Digital Signal Processing A Computer-BasedApproach McGraw-Hill New York NY USA 2001

[12] R Jaffe and E Rechtin ldquoDesign and performance of false-lock loops capable of near-optimum performance over a widerange of input signal and noise levelsrdquo IRE Transactions onInformation Theory vol 1 no 3 pp 66ndash72 1965

[13] A J Viterbi Principles of Coherent Communications chapter 2McGraw-Hill New York NY USA 1966

[14] Z Juesheng Y Zhengju and P wanxin Locked Phase Tech-nology Xian University of Electronic Science and TechnologyPress Xian China 1998

[15] A I Ahmed S H Rahman and O A Mohamed ldquoFPGA im-plementation and performance evaluation of a digital carriersynchronizer using different numerically controlled oscillatorsrdquoin Proceedings of the Canadian Conference on Electrical andComputer Engineering (CCECD rsquo07) pp 1243ndash1246 April 2007

[16] Xilinx LogiCORE IPDDSCompiler v40 Product SpecificationXilinx April 2010

[17] E D Kaplan and C J Hegarty Understanding GPS Principlesand Applications Artech House Norwood Mass USA 2005

[18] P K Meher J Valls T B Juang and K Maharatna ldquo50 yearsof CORDIC algorithms architectures and applicationsrdquo IEEETransactions on Circuits and Systems I Regular Papers vol 56no 9 pp 1893ndash1907 2009

[19] E Frantzeskakis and P Koukoulas ldquoPhase domain maximumlikelihood carrier recovery framework and application inwireless TDMA systemsrdquo in Proceedings of the 50th Fall IEEEVTS 50th Vehicular Technology Conference lsquoGateway to 21stCentury Communications Villagersquo (VTC rsquo99) pp 2571ndash2575IEEE September 1999

[20] M Luise and R Reggiannini ldquoCarrier frequency recoveryin all-digital modems for burst-mode transmissionsrdquo IEEETransactions onCommunications vol 43 no 2ndash4 pp 1169ndash11781995

[21] L Guojun and H Decong ldquoThe calculation of link margin ofsatellite communication in SKTrdquoThe Journal of Space ElectronicTechonology vol 1 no 12 pp 68ndash72 2012

[22] W Shiqi W Tingyong and Z Ningxing An Introduction toSatellite Communications Electronic Industry Press BeijingChina 2rd edition 2006

[23] Y Dangui T Ruijun X Min and Z Chengchang ldquoAn optimalmethod for costas loop design based on FPGArdquo in Proceedingsof the 4th International Conference onDigitalManufacturing andAutomation (ICDMA 13) pp 175ndash179 Qingdao China June2013

[24] H Yuan X Hu and J Huang ldquoDesign and implementationof costas loop based on FPGArdquo in Proceedings of the 3rd IEEEConference on Industrial Electronics and Applications (ICIEA08) pp 2383ndash2388 Singapore June 2008

[25] K He L Crockett and R Stewart ldquoDynamic reconfigurationtechnologies based on FPGA in software defined radio systemrdquoJournal of Signal Processing Systems vol 69 no 1 pp 75ndash852012

[26] T Adiono and R S Purba ldquoScalable pipelined CORDIC archi-tecture design and implementation in FPGArdquo in Proceedingsof the International Conference on Electrical Engineering andInformatics (ICEEI rsquo09) vol 2 pp 646ndash649 August 2009

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

Page 16: Research Article FPGA-Based Implementation of All-Digital ...downloads.hindawi.com/journals/ijrc/2014/502942.pdf · Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of