Research Article Performance Analysis of Modified Drain ...downloads.hindawi.com/journals/vlsi/2014/380362.pdfhigher performance. A trade-o is achieved between power and delay so as

Research ArticlePerformance Analysis of Modified Drain Gating Techniques forLow Power and High Speed Arithmetic Circuits

Shikha Panwar Mayuresh Piske and Aatreya Vivek Madgula

School of Electronics Engineering (SENSE) VIT University Vandalur-Kelambakkam Road Chennai 600127 India

Correspondence should be addressed to Shikha Panwar shikhapanwar24gmailcom

Received 2 May 2014 Accepted 27 June 2014 Published 15 July 2014

Academic Editor Yu-Cheng Fan

Copyright copy 2014 Shikha Panwar et alThis is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

This paper presents several high performance and low power techniques for CMOS circuits In these design methodologies draingating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps infaster discharge and thereby providing higher speed In order to achieve high performance the proposed design techniques tradepower for performance in the delay critical sections of the circuit Intensive simulations are performed using Cadence Virtuoso ina 45 nm standard CMOS technology at room temperature with supply voltage of 12 V Comparative analysis of the present circuitswith standard CMOS circuits shows smaller propagation delay and lesser power consumption

1 Introduction

As we move on to finer MOSFET technologies transistordelay has decreased remarkably which helped in achiev-ing higher performance in CMOS VLSI processors Withtechnology scaling it is required to reduce the thresholdand power supply voltages As square of power supplyvoltage is directly proportional to dynamic power dissipationto achieve less consumption of power supply voltage hasto be reduced Static power and dynamic power are twomain components of total power dissipation Static powerconsumption is calculated in the form of leakage currentthrough each device Substantial increase has been observedin subthreshold leakage current with scaling of thresholdvoltage [1] Subthreshold current 119868ST is given by [1]

119868ST = 1205830Cox(119882

119871) (119898 minus 1) (119881119879)

2times 119890(119881119892minus119881th)119898119881119879

times (1 minus 119890minus119881DS119881119879)

(1)

where

119898 = 1 +CdmCox (2)

where thermal voltage 119881119879= 119870119879119902 120583

0is the mobility 119881

119892

is the gate voltage 119881th is the threshold voltage 119881DS is

termed as drain to source voltage and 119898 is the body effectcoefficient Cdm and Cox are the depletion layer and gateoxide capacitances respectively

To counteract the excessive leakage in CMOS circuitmany architectural techniques have been proposed over theyears Power gating [2] and stacking effect [3] are two well-known techniques for reducing leakage power dissipationPower gating normally makes use of sleep transistors thatare connected either between the power supply and thepull-up network (PUN) or between the pull-down network(PDN) and ground Sleep transistors are switched on whenthe circuit is evaluating and they are switched off in standbymode to conserve the leakage power in the logic circuitMulti-threshold-CMOS (MTCMOS) [4] technique is alsoan effective way to achieve considerable decline in leakagepower consumption In MTCMOS technique high 119881th sleeptransistors are added in the circuit whereas PUN and PDNuse low 119881th devices In dual threshold circuits [5] low 119881thdevices are used in the delay critical sections and high 119881thdevices are used to reduce the leakage current in the circuitry

Stacking of transistor in series reduces the subthresholdleakage currentwhenone transistor is in the off state Stackingeffect is used in sleepy stack technique [6] and force stacktechnique [7] Sleepy stack technique provides better resultsthan forced stack technique In forced stack an extra sleep

Hindawi Publishing CorporationVLSI DesignVolume 2014 Article ID 380362 5 pageshttpdxdoiorg1011552014380362

2 VLSI Design

S

Pull-downnetwork

S998400

Pull-upnetwork

(a)

S

Pull-downnetwork

S998400

Pull-upnetwork

(b)

S

Pull-downnetwork

S998400

Pull-upnetwork

(c)

S

Pull-downnetwork

S998400

Pull-upnetwork

(d)

Figure 1 (a) Drain gating (b) power gating (c) drain-header and power-footer gating (DHPF) and (d) drain-footer and power-headergating (DFPH)

transistor is inserted for each input of the gate both in PUNand in PDN resulting in higher delay and area In sleepy stackan additional sleep transistor is connected in parallel with thetransistor stack This reduces the leakage current but at thesame time delay in the circuit is increased

LECTOR [8] and GALEOR [9] are also two leakagetolerant techniques LECTOR makes use of two leakagecontrol transistors (LCTs) that are connected between thePUN and PDN In the same time GALEOR technique makesuse of gated leakage transistors (GLTs) Both LCTs and GLTsreduce leakage by increasing the resistance between supplyvoltage and ground

Another efficient technique to counter the leakage currentproblem is drain gating and its variation [10] explained indetail in Section 2 The modified circuits are proposed inSection 3 Simulation results taking NAND gate 1-bit fulladder and 8-bit RCA (Ripple carry adder) as test benchcircuits are enumerated in Section 4 and Section 5 providesthe final conclusion

2 Drain Gating Technique andIts Variant Circuits

In drain gating technique [10] shown in Figure 1(a) twosleep transistors are added between the PUN and PDNPMOS transistor with sleep input (S) is connected betweenPUN and output node whereas NMOS transistor withsleep input (S1015840) is inserted between the output node andPDN When the circuit is in evaluation mode the NMOSand PMOS sleep transistors are turned on resulting in lowresistance conducting path When the circuit is in standbyboth transistors are switched off to reduce the standby powerOther variant circuits of drain gating are namely powergating drain-header and power-footer gating (DHPF) anddrain-footer and power-header gating (DFPH) In powergating technique PMOS sleep transistor with input (S) is

added between the power supply and the PUN whereasNMOS sleep transistor with input (S1015840) is added betweenthe PDN and ground as shown in Figure 1(b) The twomixed techniques DHPF and DFPH are shown in Figures1(c) and 1(d) respectively As the name suggests in DHPFa PMOS sleep switch is inserted between PUN and outputnode and anNMOS sleep switch is inserted between the PDNand ground rail DFPH consists of an NMOS sleep switchbetween output node and PDN and a PMOS sleep switchbetween the power supply and the PUN Comparative resultsin Section 4 indicate that power gating technique is the bestleakage tolerant technique whereas drain gating techniquehas the least delay among the previously proposed circuits

3 The Proposed High SpeedCircuit Techniques

The proposed circuits are aimed at reducing the propagationdelay incurred by drain gating technique and its variationsFour different circuit techniques namely high speed draingating (HS-drain gating) HS-power gating HS-DHPF andHS-DFPH as shown in Figures 2(a) 2(b) 2(c) and 2(d)respectively are proposed in this section In HS-drain gatingtechnique an additional sleep transistor with sleep input (S)is connected at the output node parallel to the NMOS sleeptransistor (S1015840) and PDN During the active mode when thelogic circuit evaluates the circuits output the added NMOSsleep transistor (S) provides an additional discharging path inthe circuit This added transistor helps in speedy evaluationhence providing higher speed In a similar fashion anadditional NMOS sleep transistor with sleep input (S) isadded to power gating DHPF and DFPH circuits

The proposed cicuits have been verified by taking NANDgate 1-bit full adder and 8-bit RCA as test bench circuitsExperimental results in Section 4 prove that the modifiedHS-drain gating technique has the the least delay among

VLSI Design 3

Pull-upnetwork

Pull-downnetwork

S

SS998400

(a)

Pull-upnetwork

network

S

S

S998400

Pull-down

(b)

S

S

S998400

Pull-upnetwork

networkPull-down

(c)

S

SS998400

Pull-upnetwork

networkPull-down

(d)

Figure 2 (a) HS-drain gating (b) HS-power gating (c) HS-DHPF and (d) HS-DFPH

Table 1 Power and delay values of NAND gate FA and 8-bit RCAusing various techniques

Circuittechniques

NAND gate FA 8-bit RCAPower(nW)

Delay(ps)

Power(nW)

Delay(ps)

Power(uW)

Delay(ps)

StandardCMOS 2232 451198903 211198903 301198903 522 2371198903

Draingating 1263 251198903 393 151198903 753 8851198903

Powergating 873 2051198903 238 1501198903 239 2051198903

DHPF 1108 801198903 340 251198903 302 121198903

DFPH 871 1751198903 245 1501198903 402 1551198903

HS-draingating 1842 222 250 1508 697 103

HS-powergating 1657 1176 246 499 213 214

HS-DHPF 1670 63 248 3597 415 119

HS-DFPH 1664 1171 247 4487 292 17

the existing and proposed architectural techniques as shownin Figure 5 Also HS-power gating technique has the lowestpower as compared to standard CMOS circuit and the newlyproposed circuits as shown in Table 1 The ratio of PMOS toNMOS size is set to be equal to 2

Two-input NAND gate using HS-drain gating operates intwo modes namely sleep or standby mode and active modeWhen the circuit is in active mode sleep input (S) is in lowstate and output node gets charged to power supply voltageBoth NMOS and PMOS sleep transistors connected betweenPUN and PDN are turned on and output is evaluated Forexample if we provide input to the PUN as 0(XX) where XXstands for input vectors (00 01 10 11) outputwill be high forthe first three cases and low for the fourth case for the NANDgate Sleep signal should be provided in the form of alternatehigh and low signalsWhen sleep signal (S = 1) both PMOS

a

c

b

a

b

a

b

c

a b

CarrySum

a b cc

a

b

c

a b c

a

b

c

Figure 3 1-bit CMOS full adder

andNMOS sleep transistors between PUN and PDNnetworkturn off and additional NMOS sleep transistor is turned ondischarging the output node to ground thereby resulting inhigher performance A trade-off is achieved between powerand delay so as to maintain high speed in the proposedcircuits

4 Simulations and Results

Two-input NAND gate 1-bit full adder and 8-bit RCA areimplemented using the proposed high speed architecturaltechniques The circuit diagrams for 1-bit full adder and 8-bitRCA are shown in Figures 3 and 4 respectively Each stage in8-bit RCA consists of a 1-bit full adder (FA) Each FA circuitconsists of 28 transistors In RCA carry is propagated fromone stage to another and final carry is obtained as C

8shown

in Figure 4

4 VLSI Design

FA1FA7 FA0

Sleep

B7

C8

C1

S8 S1 S0

A7 B1 A1B0 A0

Cin

Figure 4 8-bit RCA

The total power consumption and propagation delay ofvarious existing and proposed techniques for NAND gateFA and 8-bit RCA are compared in Table 1 HS-drain gatingtechnique has the least delay HS-power gating HS-DFPHand HS-DHPF suffer from 50 39 and 13 propagationdelay with respect to HS-drain gating technique Standarddrain gating and its variants circuit techniques suffer from99 propagation delay in comparison with HS-drain gatingtechnique Circuits employing HS-power gating techniquehave very low power consumption Power savings of nearly85 are achieved in arithmetic architectures employing HS-power gating technique HS-drain gating technique has theleast power saving among the proposed circuits HS-DHPFand HS-DFPH techniques optimize the power and delay inCMOS arithmetic circuits

The corner analysis for the drain gating design and itsvariants is plotted along with that of the modified high speedcounterparts Figure 5 shows the temperature versus thepropagation delay graph for 8-bit RCA using the existingtechniques and the proposed techniques

Similarly Figure 6 shows the plot of process cornersversus the propagation delay of 8-bit RCA using the existingtechniques and the proposed techniques

On observing the comparative graph shown in Figures 5and 6 we can infer that the designs made using the modifiedhigh speed drain gating technique and its correspondingvariants have substantial reduction in the propagation delaywhen compared to the designs made using the CMOS draingating technique and its variants

5 Conclusions

In this paper we have tabulated the total power consumptionand the propagation delay for certain circuits using the exist-ing low power and performance enhancing techniques andthe newly proposed ones Also we have made a comparativestudy of these techniques for the parameters like temperatureprocess corners and propagation delay Simulation resultsshow that the proposed circuits work effectively even atextreme temperature and at different transistor configura-tions

From the above mentioned experimental data we canobserve that by implementing the high speed modifieddesigns for the drain gating technique and its variants we areable to enhance the performance of the design at lower power

1 2 3 4 5 6 7

Prop

agat

ion

delay

(s)

Power gatingHS-drain gatingHS-power gatingHS-DFPHHS-DHPF

CMOSDFPHDrain gatingDHPF

Temperature (∘C)

100E minus 12

100E minus 11

100E minus 10

100E minus 09

100E minus 08

100E minus 07

Figure 5 Temperature versus the propagation delay for the existingand the proposed techniques

FF SNFP TTProcess

FNSP SS

Drain gatingPower gatingDFPHDHPFCMOS

HS-drain gatingHS-drain gatingHS-power gatingHS-power gatingHS-DFPHHS-DFPHHS-DHPFHS-DHPF

Prop

agat

ion

delay

(s)

100E minus 07

100E minus 08

100E minus 09

100E minus 10

100E minus 11

100E minus 12

Figure 6 Process versus the propagation delay for 8-bit RCA usingthe existing and the proposed techniques

VLSI Design 5

consumption Power consumption savings as observed in 8-bit RCA and 1-bit full adder are 95 and 88 respectivelywhereas propagation delay has been reduced by almost 99in both RCA and full adder circuit

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

References

[1] K Roy SMukhopadhyay andHMahmoodi-Meimand ldquoLeak-age current mechanisms and leakage reduction techniques indeep-submicrometer CMOS circuitsrdquo Proceedings of the IEEEvol 91 no 2 pp 305ndash327 2003

[2] M Powell S Yang B Falsafi K Roy and T N VijaykumarldquoGated-Vdd a circuit technique to reduce leakage in deep-submicron cache memoriesrdquo in Proceedings of the IEEE Sym-posium on Low Power Electronics and Design (ISLPED rsquo00) pp90ndash95 July 2000

[3] M Johnson D Somasekhar L Y Chiou and K Roy ldquoLeakagecontrol with efficient use of transistor stacks in single thresholdCMOSrdquo IEEE Transactions on VLSI Systems vol 10 no 1 pp1ndash5 2002

[4] S Mutoh T Douseki Y Matsuya T Aoki S Shigematsu andJ Yamada ldquo1-V power supply high-speed digital circuit technol-ogy with multithreshold-voltage CMOSrdquo IEEE Journal of Solid-State Circuits vol 30 no 8 pp 847ndash854 1995

[5] L Wei Z Chen M C Johnson K Roy Y Ye and V K DeldquoDesign and optimization of dual-threshold circuits for low-voltage low-power applicationsrdquo IEEE Transactions on VeryLarge Scale Integration (VLSI) Systems vol 7 no 1 pp 16ndash241999

[6] J C Park and V J Mooney III ldquoSleepy stack leakage reductionrdquoIEEE Transactions on Very Large Scale Integration (VLSI)Systems vol 14 no 11 pp 1250ndash1263 2006

[7] S Narendra V De D Antoniadis A Chandrakasan and SBorkar ldquoScaling of stack effect and its application for leakagereductionrdquo in Proceedings of the International Symposium onLow Electronics and Design (ISLPED 01) pp 195ndash200 Hunting-ton Beach Calif USA August 2001

[8] N Hanchate and N Ranganathan ldquoLECTOR a technique forleakage reduction inCMOSdircuitsrdquo IEEETransactions onVeryLarge Scale Integration (VLSI) Systems vol 12 no 2 pp 196ndash205 2004

[9] S Katrue and D Kudithipudi ldquoGALEOR leakage reduction forCMOS circuitsrdquo in Proceedings of the 15th IEEE InternationalConference on Electronics Circuits and Systems (ICECS rsquo08) pp574ndash577 September 2008

[10] J W Chun and C Y R Chen ldquoA novel leakage power reductiontechnique for CMOS circuit designrdquo in Proceedings of theInternational SoC Design Conference (ISOCC rsquo10) pp 119ndash122November 2010

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Navigation and Observation



DistributedSensor Networks


2 VLSI Design

S

Pull-downnetwork

S998400

Pull-upnetwork

(a)

S

Pull-downnetwork

S998400

Pull-upnetwork

(b)

S

Pull-downnetwork

S998400

Pull-upnetwork

(c)

S

Pull-downnetwork

S998400

Pull-upnetwork

(d)

Figure 1 (a) Drain gating (b) power gating (c) drain-header and power-footer gating (DHPF) and (d) drain-footer and power-headergating (DFPH)

transistor is inserted for each input of the gate both in PUNand in PDN resulting in higher delay and area In sleepy stackan additional sleep transistor is connected in parallel with thetransistor stack This reduces the leakage current but at thesame time delay in the circuit is increased

LECTOR [8] and GALEOR [9] are also two leakagetolerant techniques LECTOR makes use of two leakagecontrol transistors (LCTs) that are connected between thePUN and PDN In the same time GALEOR technique makesuse of gated leakage transistors (GLTs) Both LCTs and GLTsreduce leakage by increasing the resistance between supplyvoltage and ground

Another efficient technique to counter the leakage currentproblem is drain gating and its variation [10] explained indetail in Section 2 The modified circuits are proposed inSection 3 Simulation results taking NAND gate 1-bit fulladder and 8-bit RCA (Ripple carry adder) as test benchcircuits are enumerated in Section 4 and Section 5 providesthe final conclusion

2 Drain Gating Technique andIts Variant Circuits

In drain gating technique [10] shown in Figure 1(a) twosleep transistors are added between the PUN and PDNPMOS transistor with sleep input (S) is connected betweenPUN and output node whereas NMOS transistor withsleep input (S1015840) is inserted between the output node andPDN When the circuit is in evaluation mode the NMOSand PMOS sleep transistors are turned on resulting in lowresistance conducting path When the circuit is in standbyboth transistors are switched off to reduce the standby powerOther variant circuits of drain gating are namely powergating drain-header and power-footer gating (DHPF) anddrain-footer and power-header gating (DFPH) In powergating technique PMOS sleep transistor with input (S) is

added between the power supply and the PUN whereasNMOS sleep transistor with input (S1015840) is added betweenthe PDN and ground as shown in Figure 1(b) The twomixed techniques DHPF and DFPH are shown in Figures1(c) and 1(d) respectively As the name suggests in DHPFa PMOS sleep switch is inserted between PUN and outputnode and anNMOS sleep switch is inserted between the PDNand ground rail DFPH consists of an NMOS sleep switchbetween output node and PDN and a PMOS sleep switchbetween the power supply and the PUN Comparative resultsin Section 4 indicate that power gating technique is the bestleakage tolerant technique whereas drain gating techniquehas the least delay among the previously proposed circuits

3 The Proposed High SpeedCircuit Techniques

The proposed circuits are aimed at reducing the propagationdelay incurred by drain gating technique and its variationsFour different circuit techniques namely high speed draingating (HS-drain gating) HS-power gating HS-DHPF andHS-DFPH as shown in Figures 2(a) 2(b) 2(c) and 2(d)respectively are proposed in this section In HS-drain gatingtechnique an additional sleep transistor with sleep input (S)is connected at the output node parallel to the NMOS sleeptransistor (S1015840) and PDN During the active mode when thelogic circuit evaluates the circuits output the added NMOSsleep transistor (S) provides an additional discharging path inthe circuit This added transistor helps in speedy evaluationhence providing higher speed In a similar fashion anadditional NMOS sleep transistor with sleep input (S) isadded to power gating DHPF and DFPH circuits

The proposed cicuits have been verified by taking NANDgate 1-bit full adder and 8-bit RCA as test bench circuitsExperimental results in Section 4 prove that the modifiedHS-drain gating technique has the the least delay among

VLSI Design 3

Pull-upnetwork

Pull-downnetwork

S

SS998400

(a)

Pull-upnetwork

network

S

S

S998400

Pull-down

(b)

S

S

S998400

Pull-upnetwork

networkPull-down

(c)

S

SS998400

Pull-upnetwork

networkPull-down

(d)



Circuittechniques


Delay(ps)

Power(nW)

Delay(ps)

Power(uW)

Delay(ps)

StandardCMOS 2232 451198903 211198903 301198903 522 2371198903

Draingating 1263 251198903 393 151198903 753 8851198903

Powergating 873 2051198903 238 1501198903 239 2051198903

DHPF 1108 801198903 340 251198903 302 121198903

DFPH 871 1751198903 245 1501198903 402 1551198903

HS-draingating 1842 222 250 1508 697 103

HS-powergating 1657 1176 246 499 213 214

HS-DHPF 1670 63 248 3597 415 119

HS-DFPH 1664 1171 247 4487 292 17



a

c

b

a

b

a

b

c

a b

CarrySum

a b cc

a

b

c

a b c

a

b

c





8shown

in Figure 4

4 VLSI Design

FA1FA7 FA0

Sleep

B7

C8

C1

S8 S1 S0

A7 B1 A1B0 A0

Cin

Figure 4 8-bit RCA





5 Conclusions



1 2 3 4 5 6 7

Prop

agat

ion

delay

(s)



Temperature (∘C)

100E minus 12

100E minus 11

100E minus 10

100E minus 09

100E minus 08

100E minus 07


FF SNFP TTProcess

FNSP SS



Prop

agat

ion

delay

(s)

100E minus 07

100E minus 08

100E minus 09

100E minus 10

100E minus 11

100E minus 12


VLSI Design 5




References













RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









VLSI Design 3

Pull-upnetwork

Pull-downnetwork

S

SS998400

(a)

Pull-upnetwork

network

S

S

S998400

Pull-down

(b)

S

S

S998400

Pull-upnetwork

networkPull-down

(c)

S

SS998400

Pull-upnetwork

networkPull-down

(d)



Circuittechniques


Delay(ps)

Power(nW)

Delay(ps)

Power(uW)

Delay(ps)

StandardCMOS 2232 451198903 211198903 301198903 522 2371198903

Draingating 1263 251198903 393 151198903 753 8851198903

Powergating 873 2051198903 238 1501198903 239 2051198903

DHPF 1108 801198903 340 251198903 302 121198903

DFPH 871 1751198903 245 1501198903 402 1551198903

HS-draingating 1842 222 250 1508 697 103

HS-powergating 1657 1176 246 499 213 214

HS-DHPF 1670 63 248 3597 415 119

HS-DFPH 1664 1171 247 4487 292 17



a

c

b

a

b

a

b

c

a b

CarrySum

a b cc

a

b

c

a b c

a

b

c





8shown

in Figure 4

4 VLSI Design

FA1FA7 FA0

Sleep

B7

C8

C1

S8 S1 S0

A7 B1 A1B0 A0

Cin

Figure 4 8-bit RCA





5 Conclusions



1 2 3 4 5 6 7

Prop

agat

ion

delay

(s)



Temperature (∘C)

100E minus 12

100E minus 11

100E minus 10

100E minus 09

100E minus 08

100E minus 07


FF SNFP TTProcess

FNSP SS



Prop

agat

ion

delay

(s)

100E minus 07

100E minus 08

100E minus 09

100E minus 10

100E minus 11

100E minus 12


VLSI Design 5




References













RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









4 VLSI Design

FA1FA7 FA0

Sleep

B7

C8

C1

S8 S1 S0

A7 B1 A1B0 A0

Cin

Figure 4 8-bit RCA





5 Conclusions



1 2 3 4 5 6 7

Prop

agat

ion

delay

(s)



Temperature (∘C)

100E minus 12

100E minus 11

100E minus 10

100E minus 09

100E minus 08

100E minus 07


FF SNFP TTProcess

FNSP SS



Prop

agat

ion

delay

(s)

100E minus 07

100E minus 08

100E minus 09

100E minus 10

100E minus 11

100E minus 12


VLSI Design 5




References













RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









VLSI Design 5




References













RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









Documents

Research Article Performance Analysis of Modified Drain ...downloads.hindawi.com/journals/vlsi/2014/380362.pdfhigher performance. A trade-o is achieved between power and delay so as