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Results of 65nm pixel readout chip demonstrator array. Abderrezak Mekkaoui , Maurice Garcia- Sciveres , Dario Gnani [email protected]. Objectives. To explore the capabilities of advanced CMOS processes to address future HEP needs (Upgrades, High Luminosity LHC) - PowerPoint PPT Presentation
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Results of 65nm pixel readout chip demonstrator array
Abderrezak Mekkaoui, Maurice Garcia-Sciveres, Dario Gnani
2
Objectives
To explore the capabilities of advanced CMOS processes to
address future HEP needs (Upgrades, High Luminosity LHC)
Establish an analog front-end baseline
To have a feel of what is the best way these processes
should be used in order to maximize benefit
To evaluate radiation hardness
3
FE-I4 : Front End chip for the IBL
• The FE-I4B chip is the production version for IBL installation
– Designed in a 130nm CMOS process
– Dimensions : 20 mm x 19 mm
– Active zone : ~ 90 % of the total area
– Respects all the specifications
– IBL Production : 1 Module = 1 Chip
• The FE-I4 pixel array is organized in Double Columns (DC)
– Double Column is divided into 2 × 2 pixel regions
– 1 région : 2×2 pixel
– Pixel size : 50 x 250 µm²
– 26880 pixels
– Radiation tolerance > 200 Mrad
• Phase I or Phase II
– New pixel detector planned
• 2 removable internal layers at radii of 3.3–10
cm
• 2-3 fixed outer layers at radii of about 15–25 cm
– The FE-I4 fits requirements for outer layers in terms
of hit occupancy and radiation hardness
– A new development (FE-I5) is required for the inner
layers
Periphery
IO pads
16
.8
mm
2 m
m
20.2 mm
336×80 pixel array
Main functional core
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Pixel region (2X2) a la FEI4 if implemented in 65nm
Region logic synthesized from FEI4 verilog.Neither 100% complete nor verified.Just to have an idea on what is possible Pixel size=50X100 (?)
~FEI4 AFE equivalent
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“FEI5” 2X2 REGION (100X200)
=> Substantial area reduction=> Ultimately the width of a pixel will limited by practical considerations (power distribution) and not the number of transistors!=> Room to add functionality
FIE4 pixel region Vs Pix65nm region (assuming y=50u)
FEI4 2X2 REGION (100X500)
If area to be kept the same as FEI4, about 4X more logic can be added
6
Snapshot of submitted pixel array
25 mm y cell pitch but 50mm bump y picth. Power distribution will be major factor in the ultimate minimum dimensionsBump mask not part of the submitted layout (same size as FEI4)
Analog FE Config. Logic FutureDigitalRegion
nXm pixels
Analog FEConfig. Logic
Bump opening
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ATPIX65A FEND BLOC DIAGRAM
Inject Bloc Preamp.17fF Feedback cap.Variable “Rff”
Single to differential+Comparator “preamp”
Comparator
TDAC (+/- 4b tuning)
Passive RC: gate leakage limited
Uses only native 65nm Transistors2mA to 25mA @ 1.2V
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ATPIX65A: Atlas Pixel prototype array
Pixels withAddedsensors(row 11:31)
Pixels withAddedmimcaps(31,27,22,18)
16 X 32 array25m X 125m pixels
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Test results: front end waveforms
Preamp out
Single to Diff. out
Chan 15/32 Qin: 2ke
Chip found to work as expected!VDD=1.2VI= 5mA per pixel (can be as low as 2mA)
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Test results: front end waveforms
Qin=10ke-; 5IFF settings
Chan 15/32 Qin: 2ke to 10ke-
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Timewalk @Preamp current of 2mA and 0.2mA
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ATPIX65A: ENC for some columns
. . . .Channels withmimcaps
Channels withDiodes (3 types)
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ATPIX65: ENC Vs Preamp Bias
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ATPIX65A: Noise and Threshold distribution
Channels with caps or diodes
s > than FEI4(as expected!)
15
ATPIX65A: Threshold tuning
Sigma untuned ~350e- rmsSigma Tuned < 60e- rms
---- 565e- p-p tuned ----
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Radiation effects on DC bias voltages0 rad (Chip2)
~70 Mrad (chip2)
>600 Mrad (chip3)
Vbp1 (pmos) 525 474 440 @250 nA
Vbp2 (pmos) 620 609 586 @2 uA
Vbn1 (nmos) 636 623 648 @1uA
Vbn2 (nmos) 238 237 236 @1uA
Vbn3 (nmos) 277 274 276 @0.5uA
VG of diode connected transistors at fixed current (in mV)Different size transistorsSmall/negligible change in threshold voltages of PMOSs/NMOSsPMOS threshold variation more pronounced!Some measurement errors in the low current regime (meter impedance and esd diodes leakage)
17
Radiation effects: Threshold and noise
Green: chipB > 600MradBlue: chipA unirradiated
Different chips. Under same bias conditions except for VthModest ENC increase (but only 2 chips) Preliminary results!
ChipB: ENC=110e- ChipA: ENC=94e-
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Conclusions
Chip works as expected
Good results
SEU evaluation under way (See talk by Mohsine Menouni CPPM)
Promising process. It offers:Very high integration densityInherent very high radiation toleranceA reasonable number of devices types for extra design flexibilityAvailability of high quality passivesA high number of metal levels
19
Backup slides
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Fe55 spectrum as detected by one of the integrated sensors
Chip2 high gain mode. Sensor@-8V
1040e- pulser injection~3.7keV. Assuming Cinjto be nominal.
2154 KeV (2.9KeV? May be partial 5.9KeV charge collection?)
5154 KeV (theory; 5.9KeV?)
For the experiment to agree with theory (for the 5.9KeV), injection cap has to be corrected by 15% . Still being reviewed!
Noi
se a
rtific
ially
Lim
ited
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65nm: Some transistor test result
M. Manghisoni et al. TWEPP 2011
Same gate capacitance No noise degradation at lower nodesNo thermal noise increase with radiation No or little 1/f noise increase with radiation
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65nm: Some radiation tolerance resultsThreshold voltage Leakage current
S. Bonacini et al. TWEPP 2011
65 nm devices seem to outperform their 130nm counterparts in theirtolerance to ionizing radiation !
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ATPIX65: ENC Vs Diode bias
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ATPIX65: Threshold Vs Preamp current
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ATPIX65: Threshold Vs feedback current
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Lower part of the Am241 spectrum as detected by one of the integrated sensors
http:
//sp
ie.o
rg/x
2006
0.xm
l?Ar
ticle
ID=x
2006
0
Chip1 low gain mode(V)
Very preliminary! Work in progress! Low statistics
?
?
27
ATPIX65: ENC Vs IFF (feedback current)