20
5 5 4 4 3 3 2 2 1 1 D D C C B B A A IoT Camera Development Kit Contents Page No Sheet Name 01 03 04 05 06 07 08 09 10 11 12 13 14 02 COVER_PAGE BLOCK_DIAGRAM POWER ON SEQUENCE POWER & RESET SCHEME REV Revision Notes Designer Approver Date SHEKHAR SAINI A0 Initial Draft Release Schematics Drafted in : Allegro Design entry CIS 16.6 DDR2 CONTROLLER & MEMORY 15 16 17 18 19 VINOD KUMAR 03NOV2014 BATTERY_SECTION POWER_SUPPLY SoC_ANALOG_POWER SoC_DIGITAL_POWER Wi-Fi_GS2011MIES EXTERNAL MEMORY INTERFACE AUDIO INTERFACE IMAGE_OUTPUT_OSC USB_AND_UART_INTERFACE IMAGE_INPUT_INTERFACE ETH_PHY_SD_CARD_I/F ETHERNET_PHY BT_NRF51822 PIR & STATUS_LEDS MISCELLANEOUS 20 SHEKHAR SAINI A1 Customer Release1 Arun Kumar PN 09DEC2014 A2 No Design Change, only stackup was changed SHEKHAR SAINI Arun Kumar PN 15DEC2014 B1 I2C Master Selct SW removed & SOT pckg LDO used SHEKHAR SAINI Arun Kumar PN 28MAY2015 Asy No : Title : Rev: Sheet of Fab No : B1 701-1-00237 501-1-00198 20 1 A3 COVER_PAGE <Variant Name> Asy No : Title : Rev: Sheet of Fab No : B1 701-1-00237 501-1-00198 20 1 A3 COVER_PAGE <Variant Name> Asy No : Title : Rev: Sheet of Fab No : B1 701-1-00237 501-1-00198 20 1 A3 COVER_PAGE <Variant Name>

REV Revision Notes Designer Approver Date A0 VINOD KUMAR

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Page 1: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

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D D

C C

B B

A A

IoT Camera Development Kit

Contents

Page No Sheet Name

01

03

04

05

06

07

08

09

10

11

12

13

14

02

COVER_PAGE

BLOCK_DIAGRAM

POWER ON SEQUENCE

POWER & RESET SCHEME

REV Revision Notes Designer Approver Date

SHEKHAR SAINIA0 Initial Draft Release

Schematics Drafted in : Allegro Design entry CIS 16.6

DDR2 CONTROLLER & MEMORY

15

16

17

18

19

VINOD KUMAR 03NOV2014

BATTERY_SECTION

POWER_SUPPLY

SoC_ANALOG_POWER

SoC_DIGITAL_POWER

Wi-Fi_GS2011MIES

EXTERNAL MEMORY INTERFACE

AUDIO INTERFACE

IMAGE_OUTPUT_OSC

USB_AND_UART_INTERFACE

IMAGE_INPUT_INTERFACE

ETH_PHY_SD_CARD_I/F

ETHERNET_PHY

BT_NRF51822

PIR & STATUS_LEDS

MISCELLANEOUS20

SHEKHAR SAINIA1 Customer Release1 Arun Kumar PN 09DEC2014

A2 No Design Change, only stackup was changed SHEKHAR SAINI Arun Kumar PN 15DEC2014

B1 I2C Master Selct SW removed & SOT pckg LDO used SHEKHAR SAINI Arun Kumar PN 28MAY2015

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 201

A3 COVER_PAGE

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 201

A3 COVER_PAGE

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 201

A3 COVER_PAGE

<Variant Name>

Page 2: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

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5

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3

2

2

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1

D D

C C

B B

A A

BLOCK DIAGRAM

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 202

A3 BLOCK_DIAGRAM

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 202

A3 BLOCK_DIAGRAM

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 202

A3 BLOCK_DIAGRAM

<Variant Name>

Page 3: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 203

A3 POWER ON SEQUENCE

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 203

A3 POWER ON SEQUENCE

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 203

A3 POWER ON SEQUENCE

<Variant Name>

Page 4: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

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5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RESET SCHEME

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 204

A3 POWER & RESET SCHEME

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 204

A3 POWER & RESET SCHEME

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 204

A3 POWER & RESET SCHEME

<Variant Name>

Page 5: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

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4

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D D

C C

B B

A A

I2C SLAVE ADDRESS=x16C

BATTERY

Note:Initial Battery Voltage shall be above3.4V(VFET = 3.4V) to put the batteryin charging cycle

Without Battery, DC-DC O/P voltage is3.6V (VBAT =0(<VFET) and SPM = 0(Default) and CHG-EN = 1(Default))

BATTERY CHARGER IC

FUEL GUAGEV_BAT_P

TEMP_OUT

BAT_STAT

BAT_CAP

5V_REF

BC_TRANS

V_BAT_P

BC_FTRY

BC_SPM V_BAT_P

V_BAT_P

V_BAT_P

TEMP_OUTFG_ALARMB

BC_TRANS

VCC_MCU_3V3

VCC_V_BUS

VCC_V_BUS

VCC_VBAT

VCC_VBAT_TEST

VCC_MCU_3V3VCC_MCU_3V3

FG_ALARMB13,17

MCU_I2C_SDA5,17,19

MCU_I2C_SCL5,17,19

MCU_I2C_SCL 5,17,19MCU_I2C_SDA 5,17,19

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 205

A3 BATTERY_SECTION

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 205

A3 BATTERY_SECTION

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 205

A3 BATTERY_SECTION

<Variant Name>

R4 0ENM

R232

100K

Q1 NTLUS3A18PZ

3

4 8

1 2 5 6 7

R10 10KNM

L1 2.2uH

U44

LC709202

VS

S1

VD

D1

3

ALARM#5

TSW9

TSENSE10V

DD

213

SCL12

SDA11

NC16

NC27

NC314

NC415

RES#2

TEST04

TEST18

TEST216

C256

2.2uF

R233 100E

C252

0.01uF

R234 100E

C253

0.1uF

C463

1uF

+_

BT1

3.7V/4.2Ah

3

2

1

BATTERY

CHARGER

U13

NCP1855

IN1A1

IN2A2

OTGB3

ILIM2B4

FLAG#B5

AG

ND

C3

ILIM1C4

FTRYC5

PG

ND

1D

1

PG

ND

2D

2

FETD5

CBOOTE1

TRANSE2

COREE3

WEAKE4

BATE5

SPMA3

SDAA4SCLA5CAP1

B1

CAP2B2

SW1C1

SW2C2

SENSPD3

SENSND4

C251

22uF

R229 100K

FB42 30E

R5 0ENM

R2 0ENM

C250

10uF

FB43 30E

R3 0E

R231

10K

R7 0ENM

R230 0E

D1

R

21

R1 33mE

R9

620E

C462

0.1uFC257

10uF

Page 6: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

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3

2

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1

D D

C C

B B

A A

POWER SUPPLY3V3 REGULATION

AUTOMATICMODE(ADAPTIVESWITCHING TOPWM/PFM MODE

Vih(min) for the VSEL pinis not defined

VCC_2V8_PLL REGULATION

VCC_2V8_VAA REGULATION

VCC_VBAT RANGES FROM 3.0V TO 4.35V

1.35V REGULATION

SoC POWER ON SEQUENCE

Enable ByGS2011

DM368RESET

SYSTEM RESET-SOC PORDM368 VOTLAGE RESET

Vth = +0.85V (Vgs)

SOC 3V3 POWER ENABLE

Vth(max) = -1.0V (VGS)

VCC_VBAT RANGES FROM 3.0V TO 4.35V

1.8V REGULATION

ON Time = 1.4 secOFF Time = 3 sec

After a pushbutton turn-off event isdetected, the LTC2950 interrupts thesystem (µP) by bringing the INT pinlow. Once the system finishes itspower down and housekeeping tasks, itsets KILL low, which in turn releasesthe enable output.

Mount R580 afterpower testing

EN_2V8_VAA

1V35_PG

1V35_PG

1V35_PG

SoC_RESET_SW

V_RESET

V_RESET

PFO#

PFO#

AND_PFO#_SOC_RESET

AND_PFO#_SOC_RESET

EN_1V8_SoC

EN_3V3_SoC

EN_3V3_SoC

1V8_PG

1V8_PG

EN_1V8_SoC

PWRON_MCU_VCC

PWRON_MCU_VCC

2V8_PLL_PG

2V8_PLL_PG

2V8_VAA_PG

2V8_VAA_PG

VCC_MCU_3V3

VCC_VBAT

VCC_MCU_3V3_TEST

VCC_VBAT

VCC_2V8_PLL_TEST

VCC_2V8_VAA_TEST VCC_2V8_VAA

VCC_2V8_PLL

VCC_1V35_TEST

VCC_2V8_PLL

VCC_1V35VCC_1V35_TESTVCC_VBAT

VCC_3V3

VCC_1V8VCC_3V3

VCC_3V3VCC_MCU_3V3

VCC_2V8_VAAVCC_2V8_VAA

VCC_2V8_VAA

VCC_1V8_TEST

VCC_VBAT VCC_1V8_TEST VCC_1V8

VCC_MCU_3V3

VCC_MCU_3V3

VCC_VBAT VCC_VBATVCC_MCU_3V3

VCC_VBAT

VCC_2V8_PLL_TEST

VCC_2V8_VAA_TEST

SOC_POR_nRESET 13

SOC_nRESET17

SYS_PWR_EN17

MCU_OFF_REQ 17

MCU_OFF 17

ON_OFF_SW11

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 206

A2 POWER_SUPPLY

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 206

A2 POWER_SUPPLY

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 206

A2 POWER_SUPPLY

<Variant Name>

R583

10K

R43

100K

FB36 30E

BUCK REGSYNC

U6

NCP6332

PG

ND

1

SW2

AG

ND

3

FB4

EN5

MODE/PG6

AVIN7

PVIN8

AG

ND

_EP

9

R28 0E

C506

0.1uF

POWER

SEQUENCER

U47

LM3881

VC

C1

EN2

GN

D3

INV4

TADJ5

FLAG36

FLAG27

FLAG18

C279

0.1uF

L2 2.2uH

SWITCHER

U15

LM3668SD-2833

VOUT1

SW22

SW14P

VIN

5

EN6 V

DD

7

NC8

MODE/SYNC10

VSEL11

FB12

PG

ND

3

SG

ND

9

SG

ND

_EP

13

R89 10K

Z22

JMPx1

R44

1K

R40

10K

TP3

C89

22uF

R24 220K

R42 0E

U10

NCP752BSN28T1G

IN1

GN

D2

EN3

PG4

OUT5

R250

10K

R618

100K

R616

10K

FB37 30E

R251

10K

FB38 30E

L4

1uH

R624

10K

R587

10K

NM

R582

10K

R249 0E

R30

100K

Q2

NTLUS3A18PZ3

48

12567

R41

10K

Z23

JMPx1

BUCK REGSYNC

U9

NCP6332

PG

ND

1

SW2

AG

ND

3

FB4

EN5

MODE/PG6

AVIN7

PVIN8

AG

ND

_EP

9

FB39 30EC272

0.1uF

R585 0ENM

C267

10uF

R584

10K

C263 27pF

R27

174K

C268

22uF

R37

10K

C265

0.1uF

SW2

KMR231NG143

2

R32 0E

C510

0.1uF

R38

2.4K

R617

10K

R88

10K

C534

10uF

GND

VCC

U11

NL27WZ08

1

2

3

4

5

6

7

8

C278

0.1uFNM

C275

10uF

R588

10K

C467 0.01uF

R580 0E

FB35 30E

C277 0.1uF

C509

0.1uF

C532

10uF

R586

10K

NM

SUPERVISOR

U12

MAX708

MR#1

VC

C2

GN

D3

PFI4

PFO#5

NC6

RESET#7

RESET8

R39

10K

R252

10K C273

10uF

U7

NCP752BSN28T1G

IN1

GN

D2

EN3

PG4

OUT5

C269

10uF

R34

10K

C276 0.1uF

H16

HDR_1X2

12

C271

10uF

R36 0E

C274

22uF

C270 27pF

LTC2950-1

U50

LTC2950-1

VIN1

PB#2

ONT3

GN

D4

INT#5

EN6

OFFT7

KILL#8

R35

100K

C507

0.22uF

R31 220K

H8

HDR_1X212

C466 0.1uF

C86 10uF

R26 0E

R248 0E

C508

0.47uF

L3 1uH

R25

10K

C264

10uF

Q8NTK3134

1

32

Page 7: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

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D D

C C

B B

A A

Layout Notes:Place Differential Pair(_DQSn_P/_DQSn_N)100Ohms Differential Impedance Short andStraight as Possibile with minimum number ofVias.

DDR2 CONTROLLER & MEMORY

PLACE THE CAPS CLOSER TO THE VDD, VDDQ, VDDL PINS OF DDR2

VREF SOURCE

DDR2 CONTROLLER

PLACE CLOSE TODDR2 VREF pin

DDR_A0DDR_A1DDR_A2DDR_A3DDR_A4DDR_A5DDR_A6DDR_A7DDR_A8DDR_A9DDR_A10DDR_A11DDR_A12DDR_A13

DDR_BA0DDR_BA1DDR_BA2

DDR_RAS#DDR_CAS#DDR_WE#

DDR_CS#DDR_CKE

ST_DDR_CLK_PST_DDR_CLK_N

DDR_DQM0DDR_DQM1

DDR_DQS1_PDDR_DQS1_N

DDR_DQ0DDR_DQ1DDR_DQ2DDR_DQ3DDR_DQ4DDR_DQ5DDR_DQ6DDR_DQ7

DDR_DQ9DDR_DQ10DDR_DQ11DDR_DQ12DDR_DQ13DDR_DQ14DDR_DQ15

DDR_DQ8

DDR_A[13:0] DDR_DQ[15:0]

DDR_DQS0_PDDR_DQS0_N

DDR_CLK_PDDR_CLK_N

DDR_A0DDR_A1DDR_A2DDR_A3DDR_A4DDR_A5DDR_A6DDR_A7DDR_A8DDR_A9

DDR_A10DDR_A11DDR_A12DDR_A13

DDR_A[0:13]

DDR_DQ0DDR_DQ1DDR_DQ2DDR_DQ3DDR_DQ4DDR_DQ5DDR_DQ6DDR_DQ7DDR_DQ8DDR_DQ9DDR_DQ10DDR_DQ11DDR_DQ12DDR_DQ13DDR_DQ14DDR_DQ15

DDR_DQ[15:0]

DDR_DQS0_NDDR_DQS0_P

DDR_DQS1_PDDR_DQS1_N

DDR_BA0DDR_BA1DDR_BA2

DDR_RAS#DDR_CAS#DDR_WE#

DDR_CS#DDR_CKE

DDR_CLK_PDDR_CLK_N

DDR_DQM0DDR_DQM1

DDR_DQ0

DDR_DQ15DDR_A0

DDR_A13

VCC_DDR_VREF_0V9

VCC_1V8

VCC_1V8

VCC_1V8

VCC_1V8VCC_DDR_VREF_0V9

VCC_DDR_VREF_0V9

VCC_1V8

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 207

A3 DDR2 CONTROLLER & MEMORY

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 207

A3 DDR2 CONTROLLER & MEMORY

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 207

A3 DDR2 CONTROLLER & MEMORY

<Variant Name>

C282

0.1uF

R47 10E

C10

0.1uF

TP63TP61

C3

10uF

C18

0.1uF

C22

0.1uF

C20

0.1uF

TMS320DM368DDR INTERFACE

U1A

TMS320DM368

DDR_A00U14

DDR_A01V14

DDR_A02W15

DDR_A03T14

DDR_A04U15

DDR_A05V15

DDR_A06W16

DDR_A07T15

DDR_A08W17

DDR_A09U16

DDR_A10V16

DDR_A11W18

DDR_A12V17

DDR_A13T16

DDR_DQ00U11

DDR_DQ01V11

DDR_DQ02R10

DDR_DQ03V10

DDR_DQ04W10

DDR_DQ05V9

DDR_DQ06W9

DDR_DQ07R9

DDR_DQ08W8

DDR_DQ09U8

DDR_DQ10R8

DDR_DQ11V8

DDR_DQ12W7

DDR_DQ13R7

DDR_DQ14V7

DDR_DQ15V6

DDR_DQGATE0T8

DDR_DQGATE1T9

DDR_DQS[0]#U9

DDR_DQS[1]#U6

DDR_DQS[0]T10

DDR_DQS[1]T7

DDR_BA[0]W14

DDR_BA[1]T13

DDR_BA[2]V13

DDR_RAS#U12

DDR_CAS#V12

DDR_WE#W13

DDR_CS#T12

DDR_CKER13

DDR_CLKW11

DDR_CLK#W12

DDR_DQM[0]T11

DDR_DQM[1]W6

DDR_VREFP11

DDR_PADREFPR11

VD

D18

_DD

R_1

N9

VD

D18

_DD

R_2

N11

VD

D18

_DD

R_3

P9

VD

D18

_DD

R_4

P10

VD

D18

_DD

R_5

P12

VD

D18

_DD

R_6

R12

C16

0.1uF

C14

0.1uF

R46 10E

C5

1uF

R49

1K

C9

0.1uF

C12

0.1uFR50

1K

C8

0.1uF

TP64

C4

10uF

TP62

C6

1uF

C283

0.1uF

C19

0.1uF

C21

0.1uF

C17

0.1uF

C281

0.1uF

C15

0.1uF

R45 10E

C13

0.1uF

DDR2 SDRAM

U2

AS4C128M16D2-25BCN

BA0L2

BA1L3

BA2L1

DQ0G8

DQ1G2

DQ2H7

DQ3H3

DQ4H1

DQ5H9

DQ6F1

DQ7F9

DQ8C8

DQ9C2

VD

D1

A1

VD

D2

E1

VD

D3

R1

VD

D4

J9

VD

D5

M9

VD

DL

J1

VD

DQ

1C

1

VD

DQ

2G

1

VD

DQ

3C

3

VD

DQ

4G

3

VD

DQ

5C

7

VD

DQ

6G

7

VD

DQ

7A

9

VD

DQ

8C

9

VD

DQ

9E

9

VD

DQ

10G

9

LDQSF7

LDQS#/NUE8

UDQSB7

UDQS#/NUA8

VS

S1

N1

VS

S2

A3

VS

S3

E3

VS

S4

J3

VS

S5

P9

VS

SQ

1B

2

VS

SQ

2D

2

VS

SQ

3F

2

VS

SQ

4H

2

VS

SQ

5A

7

VS

SQ

6E

7

VS

SQ

7B

8

VS

SQ

8D

8

VS

SQ

9F

8

VS

SQ

10H

8

WE#K3

A0M8

A1M3

A2M7

A3N2

A4N8

A5N3

A6N7

A7P2

A8P8

A9P3

A10/APM2

A11P7

A12R2

CAS#L7

CKJ8

CK#K8

CKEK2 CS#L8

LDMF3

ODTK9

RAS#K7

UDMB3

NC1A2

NC2E2

DQ10D7

DQ11D3

DQ12D1

DQ13D9

DQ14B1

DQ15B9

VS

SD

LJ7

VR

EF

J2

A13R8

RFU_R3R3

RFU_R7R7

C11

0.1uF

R48 49.9E

C280

0.01uF

Page 8: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BOOT MODE SELECTION

EXTERNAL MEMORY INTERFACE

NOTE: BY DEFAULT THE SWITCH SHOULDBE AT OFF POSITION.

BTSEL2 BTSEL1 BTSEL0Boot Mode

NOR Boot

NAND Boot

SD Boot

0

1

0 0

00

0 1 0

AECFG0

8-bit NOR Boot

ADD MUX AECFG1AECFG2

NAND Boot

16-bit NOR Boot

0 1 0

1 10

0 0 0

EM_A8EM_A9EM_A10Address Line

VIL(MAX)=0.8V

No-MountMountAddress Mux

16-bit NOR

8-bit NOR

R30, R31, R33

R32, R34

BOOT MODE SELECTION TABLE :(DEFAULT: NOR 16-BIT)

NAND FLASH INTERFACE

NOR FLASH INTERFACE

R32, R34

R30, R31, R33

BOOT MODES SW1.1SW1.2SW2.1SW2.2SW3.1SW3.2

NAND ON

NOR8-bit ON ON ON

NOR16-bit

SD CARD ON

USB

OFF OFF OFF OFF OFF

OFF OFF OFF

OFF OFF OFF OFF OFF OFF

OFF OFF OFF OFF OFF

IN GENERAL

Address Line EM_A13 EM_A12 EM_A11

USB 1 0 0

ONONOFF OFF OFF OFF

EM_D0

EM_D1

EM_D2

EM_D3

EM_D4

EM_D5

EM_D6

EM_D7

EM_D[15:0]

EM_D0EM_D1EM_D2EM_D3EM_D4EM_D5EM_D6EM_D7

EM_D[15:0]

EM_WAIT

EM_OE#

EM_WE#

EM_A1EM_A2

EM_CE#EM_OE#

EM_WE#NAND_WP

EM_A1EM_A2

EM_A9EM_A8

EM_A10

EM_A13EM_A12EM_A11

EM_D8

EM_D9

EM_D10

EM_D11

EM_D12

EM_D13

EM_D14

EM_D15

EM_A14/EM_BA[0]EM_BA1

EM_A0

EM_A3EM_A4EM_A5EM_A6EM_A7

EM_WAIT

EM_CE1#EM_CE0#

EM_A14/EM_BA[0]

EM_A8 AECFG[0]

EM_D15

EM_A[20:0]

AECFG[1] EM_A9

NAND_WP

EM_A10

EM_A11

AECFG[2]

BTSEL[0]

BTSEL[1]

BTSEL[2]

EM_A12

EM_A13

EM_A7

EM_A12

EM_A9EM_A8

EM_A13EM_A14

EM_CE0#

EM_A11EM_A10

EM_A[20:0]

EM_BA1

EM_A15

EM_A2EM_A1EM_A0

EM_A5EM_A4EM_A3

EM_A6

EM_A17EM_A16

EM_A20EM_A19EM_A18

EM_OE#

NOR_RESETEM_WE#

BYTE#

EM_CE0#

EM_CE1#

EM_CE1#

EM_WAIT

EM_D0

EM_D3EM_D2EM_D1

EM_D6EM_D5EM_D4

EM_D10EM_D9

EM_D11

EM_D7EM_D8

EM_D14EM_D13EM_D12

EM_D[15:0]

EM_D2

EM_A4

VCC_3V3

VCC_3V3

VCC_3V3

VCC_3V3

VCC_3V3

VCC_3V3

VCC_3V3

VCC_3V3

VCC_3V3

VCC_3V3

VCC_3V3

VCC_3V3

VCC_3V3

EM_A14 8

EM_BA0 8

EM_A21 8

EM_A14 8

EM_BA0 8

EM_A21/EM_A1411

EM_A[20:0]10

EM_BA0 8

EM_A218

NOR_RESET13

SoC_REV011

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 208

A3 EXTERNAL MEMORY INTERFACE

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 208

A3 EXTERNAL MEMORY INTERFACE

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 208

A3 EXTERNAL MEMORY INTERFACE

<Variant Name>

C27

0.01uF

R72 1K

R76 0ENM

R54 10K

C29

0.01uF

TP72

R63 1K

R70 1K

NAND FLASH

U4MT29F2G08ABAEAH4-IT:E

DNU_G8G8

WE#C7

WP#C3

ALEC4

CE#C6

CLED5

NC1A1

NC2A2

NC3A9

NC4A10

NC5B1

NC6B9

NC7B10

NC8D6

R/B#C8

RE#D4

NC9D7

VS

S1

C5

VS

S2

F7

VS

S3

K3

VS

S4

K8

VC

C1

D3

VC

C2

G4

VC

C3

H8

VC

C4

J6

NC30L1

NC31L2

NC32L9

NC33L10

NC34M1

NC35M2

NC36M9

NC37M10

I/O0H4

I/O1J4

I/O2K4

I/O3K5

I/O4K6

I/O5J7

I/O6K7

I/O7J8

DNU_G3G3

DNU_G5G5

NC10D8

NC11E3

NC12E4

NC13E5

NC14E6

NC15E7

NC16E8

NC17F3

NC24H3

NC28J3

NC25H5

NC29J5

NC26H6

NC27H7

NC22G6

NC23G7

NC18F4

NC19F5

NC20F6

NC21F8

R75 0E

R57 15K

R62 10K

R73 10K

C25

0.01uF

R53

10K

R58 0E

C26

0.1uF

R59 0ENM

R74 0E

R78 0ENM

C28

0.01uF

External Memory InterfaceTMS320DM368

U1B

TMS320DM368

EM_D01/HD1K16

EM_D02/HD2K19

EM_D03/HD3K15

EM_D04/HD4L15

EM_D05/HD5L19

EM_D06/HD6L18

EM_D07/HD7L16

EM_D08/GIO57/HD8N15

EM_D09/GIO58/HD9N19

EM_D10/GIO59/HD10N18

EM_D11/GIO60/HD11N16

EM_D12/GIO61/HD12P15

EM_D13/GIO62/HD13P19

EM_D14/GIO63/HD14P16

EM_D15/GIO64/HD15P18

EM_WE#/GIO54/HDS2#J15

EM_OE#/GIO53/HDS1#J19

EM_WAIT/GIO52/HRDY#J18

EM_ADV/GIO51/HR_W#M16

EM_CLK/GIO50M15

EM_A00/GIO67/KEYB2/HCNTLBL17

EM_A01/HHWILM19

EM_A02/HCNTLAM18

EM_A03/GIO68/KEYB3R15

EM_A04/GIO69/KEYA0R19

EM_A05/GIO70/KEYA1R16

EM_A06/GIO71/KEYA2R18

EM_A07/GIO72/KEYA3T17

EM_A08/GIO73/AECFG[0]T19

EM_A09/GIO74/AECFG[1]T18

EM_A10/GIO75/AECFG[2]U19

EM_A11/GIO76/BTSEL[0]V19

EM_A12/GIO77/BTSEL[1]U18

EM_A13/GIO78/BTSEL[2]V18

EM_D00/HD0K18

EM_BA0/EM_A14/GIO65/KEYB0P17

EM_BA1/GIO66/KEYB1/HINT#R17

EM_CE0#/GIO56/HCS#M17

EM_CE1#/GIO55/HAS#J17

R61 1K

R69 1K

R56 0E

R60 10K

TP71

R52

10K

R64 10K

ON

SW3

TDA02H0SB1

1

2

4

3

R66 10KON

SW4

TDA02H0SB1

1

2

4

3

ON

SW5

TDA02H0SB1

1

2

4

3

R51 10K C24

0.01uF

R67 1K

R55 0ENM

NORFLASH

U3

PC28F128M29EWL

DQ0E3

DQ1H3

DQ2E4

DQ3H4

DQ4H5

DQ5E5

DQ6H6

DQ7E6

DQ8F3

DQ9G3

DQ10F4

DQ11G4

DQ12F5

DQ13G6

DQ14F6

DQ15/A-1G7

A0E2

A1D2

A2C2

A3A2

A4B2

A5D3

A6C3

A7A3

A8B6

A9A6

A10C6

A11D6

A12B7

A13A7

A14C7

A15D7

A16E7

A17B3

A18C4

A19D5

A20D4

A21C5

A22B8

RY/BY#A4

WE#A5

BYTE#F7

CE#F2

OE#G2

RST#B5

RFU1A1

RFU2A8

RFU3B1

RFU4C1

RFU5C8

RFU6D1

RFU7E1

RFU8F8

RFU9G1

RFU10G8

RFU11H1

RFU12H8

VS

S1

E8

VS

S2

H2

VS

S3

H7

VP

P/W

P#

B4

VC

CG

5

VC

CQ

1D

8

VC

CQ

2F

1

R71 10K

R68 10K

C31

10uF

R65 10K

C30

0.01uF

R77 0E

Page 9: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

IMAGE INPUT INTERFACE

I2C SLAVE ADDRESS=x20(write), X21(read)

Layout Notes:PLACE NEAR VDD PINS OF AR0230

Layout Notes:PLACE NEARVAA_PIX PINSOF AR0230

Layout Notes:PLACE NEAR VAA PINS OF AR0230

Layout Notes:PLACE NEAR C5 PIN OF AR0230

Layout Notes:PLACE NEAR VDD_PLL PINSOF AR0230

Layout Notes:PLACE NEAR VDDIO PINS OF AR0230

IMG_TRIGGER

1V8_IMG_SDA

DOUT[11:0]

DOUT0DOUT1DOUT2DOUT3DOUT4DOUT5DOUT6DOUT7

DOUT[11:0]

DOUT8DOUT9DOUT10DOUT11

IMG_TRIGGERDM368_IMG_RESET

IMG_CLKST_IMG_CLK

1V8_IMG_SCL

1V8_IMG_SDA

HD_SIGNAL

P_CLK

VD_SIGNAL

IMG_FLASH

IMG_SHUTTER

1V8_IMG_SCL

IMG_CLK

RSVD2RSVD1

OE_BAR

DOUT[11:0]

DOUT0DOUT1DOUT2DOUT3DOUT4DOUT5DOUT6DOUT7DOUT8DOUT9DOUT10DOUT11

DM368_IMG_RESET

VD_SIGNAL

HD_SIGNAL

P_CLK

DOUT11

DOUT0

VCC_2V8_VAA

VCC_1V8

VCC_1V8

VCC_1V8

VCC_1V8

VCC_2V8_VAA

AGND

VCC_2V8_VAA

AGND

VCC_1V8

VCC_2V8_PLL

VCC_1V8

AGND

AGND

VCC_2V8_PLL VCC_1V8 VCC_2V8_VAA

VCC_3V3

SOC_I2C_SCL11

SOC_I2C_SDA11

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 209

A3 IMAGE_INPUT_INTERFACE

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 209

A3 IMAGE_INPUT_INTERFACE

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 209

A3 IMAGE_INPUT_INTERFACE

<Variant Name>

C309

10uF

C300

0.01uF

C335

0.01uF

R97

1.5K

C312

0.1uF

R274 10E

C327

10uF

R246

10K

R275 10E

TP6

TP60

C297

0.1uF

C311

0.1uF

TP59

R87 0E

TP7

C301

0.01uF

R220 0E

C296

0.1uF

C310

0.1uF

C305

10uF

C295

0.1uF

DIGITAL

AR0230CS

IMAGE SENSOR

U17

AR0230CS

DOUT0J4

DOUT1J3

DOUT10F4

DOUT11F3

DOUT2J1

DOUT3H6

DOUT4H5

DOUT5H4

DOUT6G6

DOUT7G5

DOUT8G4

DOUT9F5

EXTCLKD3

FLASHE4

FRAME_VALIDE5

LINE_VALIDF6

OE#J8

PIXCLKD4

RESERVED1C9

RESERVED2F7

RESET#H7

SADDRD5

SCLKE6

SDATAE3

SHUTTERB9

SLVS0_NB2 SLVS0_PA2

SLVS1_NB3 SLVS1_PA3

SLVS2_NB5 SLVS2_PA5

SLVS3_NB6 SLVS3_PA6

SLVSC_NB4 SLVSC_PA4

TRIGGERD6

AG

ND

1C

2

AG

ND

2D

8

AG

ND

3E

8

AG

ND

4F

8

AG

ND

5G

2

DG

ND

1B

7

DG

ND

2B

8

DG

ND

3C

3

DG

ND

4C

6

DG

ND

5C

7

DG

ND

6C

8

DG

ND

7D

2

DG

ND

8D

7

DG

ND

9E

2

DG

ND

10E

7

DG

ND

11F

2

DG

ND

12G

3

DG

ND

13G

7

DG

ND

14G

8

DG

ND

15H

2

DG

ND

16H

3

DG

ND

17J6

VD

D1

A7

VD

D2

A9

VD

D3

C5

VD

D4

D1

VD

D5

F1

VD

D6

H9

VD

D7

J5

VD

D_I

O1

A8

VD

D_I

O2

E1

VD

D_I

O3

G9

VD

D_I

O4

H1

VD

D_I

O5

J2

VD

D_I

O6

J7

VD

D_I

O7

J9

TESTH8

VA

A1

C1

VA

A2

D9

VA

A3

F9

VA

A4

G1

VA

A_P

IXE

9

VD

D_S

LVS

C4

VD

D_P

LLB

1

C319

0.01uF

TMS320DM368VIDEO INPUT INTERFACE

U1D

TMS320DM368

YIN0/GIO96D15

YIN1/GIO97D14

YIN2/GIO98B15

YIN3/GIO99A14

YIN4/GIO100/SPI3_SOMI/SPI3_SCS[1]#D12

YIN5/GIO101/SPI3_SCS[0]#B13

YIN6/GIO102/SPI3_SIMOA13

YIN7/GIO103/SPI3_SCLKC12

CIN0B17

CIN1A18

CIN2C16

CIN3A17

CIN4A16

CIN5B16

CIN6C15

CIN7A15

HD/GIO95C14

VD/GIO94B14

C_WE_FIELD/GIO93/CLKOUT0/USBDRVVBUSE13

PCLKD13

C302

10uF

R19 0E

C318

0.01uF

C294

0.1uF

C324 0.1uF

C307

0.1uF

C329

0.1uF

C461

0.01uF

C304

0.01uF

R82 10K

C328

0.1uF

C298

0.01uF C306

0.1uFR93

10K

C308

10uF

C325 0.1uF

C303

0.1uF

C293

10uF

R83 10K

C334

0.01uF

C341

0.1uF

TP9

R80 10K

TP8

C340

10uF

R85 10E

U19

PCA9306

GN

D1

VR

EF

12

SCL13

SDA14

SDA25

SCL26

VR

EF

27

EN8

C326

10uF

C299

0.01uF

R79 10K

TP5

R84 0E

R96

1.5K

R273 10E

Page 10: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SD CARD INTERFACE

Layout Notes:To be placed very close the SD Connector

SD CARD CONN

SoC_SD0_CMDSoC_SD0_CLK

SD0_DATA3

SD0_CLK

SD0_DATA2

SD0_CMD

SD0_DATA0SD0_DATA1

SoC_GIO0

SD0_CLK

SD0_CMD

SD0_DATA0SD0_DATA1SD0_DATA2SD0_DATA3

SoC_SD0_CLK

SoC_SD0_CMD

SoC_SD0_DATA0SoC_SD0_DATA1SoC_SD0_DATA2SoC_SD0_DATA3

SoC_SD0_DATA3SoC_SD0_DATA2SoC_SD0_DATA1SoC_SD0_DATA0

EM_A15EM_A16EM_A17EM_A18

EM_A19EM_A20

VCC_3V3

VCC_3V3

EPHY_RXD316

EPHY_RXD016EPHY_RXD116EPHY_RXD216

EPHY_RXDV16EPHY_RXER16EPHY_RXCLK16

EPHY_TXD016EPHY_TXD116EPHY_TXD216EPHY_TXD316

EPHY_TXEN16EPHY_TXCLK16

EPHY_COL16EPHY_CRS16

EPHY_MDC16

EPHY_MDIO16

EM_A[20:0] 8

MCU_PRGM_SoC_WAKE17

SD0_CD 13

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2010

A3 ETH_PHY_SD_CARD_I/F

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2010

A3 ETH_PHY_SD_CARD_I/F

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2010

A3 ETH_PHY_SD_CARD_I/F

<Variant Name>

R98 10E

R608

10K

C342

0.1uF

C343

10uF

EMI-FILTER

U20

EMI6316

GN

D2

C3

DATA0_INTA1

CLK_INTB1

DATA2_INTD2

DATA3_INTD1

CMD_INTC1

DATA1_INTA2

GN

D1

B3

SDCLK_EXTB4

SDCMD_EXTC4

SDDATA0_EXTA4

SDDATA1_EXTA3

SDDATA2_EXTD3

SDDATA3_EXTD4

VC

C_E

XT

B2

R609

1K

DET_SW-B

DET_SW-A

MIC

RO

-SD

DAT0

DAT2

VDD

VSS

CMD

CD/DAT3

CLK

DAT1

J5

CON_MICROSD

12345678

S1S2S3S4

CD1CD2

Eth Media Access Ctrl & SD Card InterfaceTMS320DM368

U1C

TMS320DM368

GIO4/EMAC_RX_ERA4 GIO5/EMAC_RX_DVB4

GIO6/EMAC_RX_CLKB3

GIO7/EMAC_RXD0A3

GIO8/EMAC_RXD1A2

GIO9/EMAC_RXD2C2

GIO10/EMAC_RXD3B2

GIO11/EMAC_TXD0B1

GIO12/EMAC_TXD1C1

GIO13/EMAC_TXD2D3

GIO14/EMAC_TXD3D1

GIO16/EMAC_TX_CLK/UART1_TXDE1 GIO17/EMAC_TX_EN/UART1_RXDE4

MMCSD0_DATA0H18

MMCSD0_DATA1H19

MMCSD0_DATA2H17

MMCSD0_DATA3H16

MMCSD0_CMDH15

MMCSD0_CLKJ16

GIO38/MMCSD1_DATA0/EM_A15V5

GIO39/MMCSD1_DATA1/EM_A16R5

GIO40/MMCSD1_DATA2/EM_A17U5

GIO41/MMCSD1_DATA3/EM_A18W5

GIO42/MMCSD1_CMD/EM_A19R6

GIO43/MMCSD1_CLK/EM_A20T6

GIO2/MDIOC4 GIO1/MDCLKD6 GIO0B5

GIO15/EMAC_COLD2

GIO3/EMAC_CRSC5

P1

PGB1010603

12

R99 0E

Page 11: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Layout Notes:Differential Pair 90 ohm DifferentialImpedance short and straight aspossible with minimum number of VIAS.

MICRO USB B CONNECTOR

USB TO UART CONVERTER

SPI, UART, USB, ADC ControllersPORT1: UART0

For DM368 Rev Control

SOC_USB_MSOC_USB_P

USB_M_UART0

USB_P_UART0

VCC_V_BUSCON_USB_P_UART

VCOM

CON_USB_M_UART

SOC_UART0_RXSOC_UART0_TX SOC_UART0_RX

SOC_UART0_TX

USB_ID

SPI2_CSSPI2_CLKSPI2_MISOSPI2_MOSI

USB_P_UART0

USB_M_UART0

CON_USB_M_UARTCON_USB_P_UART

SPI1_MOSISPI1_MISO

SPI1_CSSPI1_CLK

SOC_UART1_TX

SoC_REV1

SoC_REV0SoC_REV1

SOC_UART1_RX

SOC_USB_PSOC_USB_M

VCC_V_BUS_UART

FT_VCC_3V3_OUT

VCC_3V3VCC_V_BUS_UART

FT_VCC_3V3_OUT

VCC_V_BUS_UART

FT_VCC_3V3_OUT

VCC_3V3

AVSS_VC

VCC_V_BUS

VCC_V_BUS

VCC_3V3

VCC_MCU_3V3

MIC_IN_P 12MIC_IN_N 12

SOC_I2C_SCL9SOC_I2C_SDA9

SPEAKER_P 12SPEAKER_N 12

BT_SPI_MOSI18BT_SPI_MISO18BT_SPI_CLK18BT_SPI_CS18

EM_A21/EM_A148

MCU_SoC_GPIO117

MCU_SPI_MOSI17MCU_SPI_MISO17

MCU_SPI_CLK17MCU_SPI_CS17

DB_SWDCLK18DB_SWDIO/BLE_RST#18

MCU_SoC_GPIO217

BT_GPIO_1618BT_GPIO_1718

BT_GPIO_2018

SoC_MCU_STDY_WAKE17

SoC_REV0 8

ON_OFF_SW 6FACTORY_RESET 17

USB_WAKEUP_MCU 17

MCU_SoC_GPIO417

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2011

A3 USB_AND_UART_INTERFACE

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2011

A3 USB_AND_UART_INTERFACE

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2011

A3 USB_AND_UART_INTERFACE

<Variant Name>

R101

1.5K

FB22

30E

R611 0E

R116 0E

R605

10K

NM

R108 10ENM

R106 0ENM

R110 10K

R107 0ENM

TP42

C344 10uF

EMI-FILTER

U21

EMI2121

OUT_1+8

VD

D/I

D6

OUT_1-7

IN_1+1

IN_1-2

GN

D1

3

GN

D2

4

GN

D3

5

GN

D_E

P9

C349

0.01uF

R111 10K

TP41

R109 0ENM

R610 0E

R112 10K

SPI, UART, USB & ADCTMS320DM368

U1F

TMS320DM368

GIO22/SPI0_SIMOR2

GIO23/SPI0_SOMI/SPI0_SCS[1]#/PWM0V2

GIO24/SPI0_SCLKT3

GIO25/SPI0_SCS[0]#/PWM1/UART1_TXDT1

GIO26/SPI1_SIMOU1

GIO27/SPI1_SOMI/SPI1_SCS[1]#/B0T2

GIO28/SPI1_SCLK/B1V1

GIO29/SPI1_SCS[0]#/G0U2

GIO30/SPI2_SIMO/G1T4

GIO31/SPI2_SOMI/SPI2_SCS[1]#/CLKOUT2U4

GIO32/SPI2_SCLK/R0W2

GIO33/SPI2_SCS[0]#/USBDRVVBUS/R1V3

GIO34/SPI4_SIMO/SPI4_SOMI/UART1_RXDV4

GIO35/SPI4_SOMI/SPI4_SCS[1]#/CLKOUT1W3

GIO36/SPI4_SCLK/EM_A21/EM_A14W4

GIO37/SPI4_SCS[0]#/MCBSP_CLKS/CLKOUT0T5

GIO45/MCBSP_CLKRB6

GIO46/MCBSP_DRE6

GIO48/MCBSP_CLKXA5

GIO49/MCBSP_DXD5

GIO44/MCBSP_FSRE7

GIO47/MCBSP_FSXC6

GIO21/UART1_RTS/I2C_SDAF3 GIO20/UART1_CTS/I2C_SCLF1

GIO19/UART0_RXDE3

GIO18/UART0_TXDE2

MICIPB8

MICINC8

LINEOC9

SPPB9

SPNA9

VCOMA8

ADC_CH0E8

ADC_CH1B7

ADC_CH2A7

ADC_CH3D8

ADC_CH4D7

ADC_CH5A6

USB_DPN1

USB_DMP1

USB_IDM1USB_VBUSN2

COMPYB12

COMPPBA12

COMPPRC11

VREFD11

IREFA11

VFBB10

IDACOUTB11

TVOUTA10

C346 0.1uF

R606

10K

R104 10E

R113 10KR114 10K

FT230XUSB to UART

Interface

U22

FT230XQ

3V3OUT8

CTS#4

RESET#9

RTS#16

RXD2

TXD15

VC

C10

VC

CIO

1

USBDM7

USBDP6

GN

D_E

P17

GN

D1

3

GN

D2

13

CBUS012

CBUS111

CBUS25

CBUS314

C529 0.1uF

R594 0ENM

R102 0E

R115 10K

J4

CON_B2B_2X10

13

246587

9 1012111413

15 1617 18

2019

C345 0.01uFR595 0ENM

VBUS

D-

D+

ID

GND

J2

CON_USB Micro-B

12345

S1S2

S3

S4

S5S6 R103 0E

R661 47K

R105 0E

R117 10K

R647 25.5K

R604

10K

NM

C347 0.01uF

R119

1.5K

R603

10K

R118

1.5K

Page 12: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AUDIO INTERFACE

SPEAKER INTERFACE

INTEGRATED CABLEASSEMBLY

MicrophoneVCC_2V8_PLL REGULATION

SPK_P

SPK_N

MIC_N

MIC_P

SPEAKER_N

SPEAKER_P

2V8_MIC_EN

2V8_MIC_PG

2V8_MIC_PG

2V8_MIC_EN

VCC_3V3

AVSS_VC

AVSS_VC

VCC_2V8_MIC

AVSS_VC

VCC_2V8_MIC_TEST VCC_2V8_MIC

VCC_2V8_MIC_TEST

VCC_3V3

VCC_3V3

SPEAKER_P11

SPEAKER_N11

SoC_AMP_CNTL13

MIC_IN_P 11

MIC_IN_N 11

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2012

A3 AUDIO INTERFACE

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2012

A3 AUDIO INTERFACE

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2012

A3 AUDIO INTERFACE

<Variant Name>

C361 0.01uF

R613 0E

U52

NCP752BSN28T1G

IN1

GN

D2

EN3

PG4

OUT5

R409

2.2K

R612

2.2K

C515

10uF

C530 100uF

NM

C513

10uF

C478 1uF

R614 0E

R411

0E

NM

+

_

MK2

CMC-5044TF-A

1

2

R412

0E

NM

R619 0E

R620

10K R410 0E

C531 100uFNM

C362 0.01uF

PWR - AMP

AUDIO

U26

NCP2824

INPA1

NCB2

OUTPA3

AG

ND

B1

VD

DA

2

PG

ND

B3

INMC1

CNTLC2

OUTMC3

C360 10uF

C479

1uF

FB40 30E

R133

10K

C516

10uF

+

_

SP1

SP-1605

1

2

C511

0.1uF

C512 1uF

Page 13: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

IMAGE OUTPUT AND OSC SECTION

Please place all together.

IMAGE OUTPUT INTERFACE PRTCSS & OSC

JTAG CONNECTIONS

JTAG controllers from TexasInstruments actively driveTRST high. However, somethird-party JTAG controllersmay not drive TRST high butexpect the use of a pullupresistor on TRST

NOTE:

Place all togther in 0.1inch spacing.

JTAG_TRST#SOC_TCK

SOC_EMU0SOC_EMU1

SOC_TMS

SOC_TDISOC_TDO

SOC_RTCK

PWRCNTON

PWRST

SOC_TMS

SOC_TCK

SOC_RTCK

SOC_TDO

SOC_EMU0

SOC_EMU1

SOC_TDI

OSCCFG

NOR_RESET

VCC_1V35

VCC_3V3

VCC_3V3

SOC_POR_nRESET6

SoC_LED_RED_CTRL 19SoC_LED_GREEN_CTRL 19SoC_MCU_WAKE_UP 17

NOR_RESET 8SoC_PBT_PWR_EN 18

FG_ALARMB 5,17

MCU_SoC_GPIO3 17

SoC_AMP_CNTL 12

SD0_CD 10

EPHY_RSTn 16

PIR_DIG_OUT 17,19MCU_PRGM_GPIO27 17

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2013

A3 IMAGE_OUTPUT_OSC

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2013

A3 IMAGE_OUTPUT_OSC

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2013

A3 IMAGE_OUTPUT_OSC

<Variant Name>

R140 10K

TP18

R100

10K

R144 1K

R141 10K

VIDEO OUPUT INTERFACETMS320DM368

U1E

TMS320DM368

YOUT0[G5]E16

YOUT1[G6]F17

YOUT2[G7]F19

YOUT3[R3]F16

YOUT4[R4]F18

YOUT5[R5]F15

YOUT6[R6]G19

YOUT7[R7]G16

HSYNC/GIO84G15

VSYNC/GIO83G18

LCD_OE/GIO82C19

GIO80/EXTCLK/B2/PWM3B19

VCLK/GIO79B18

GIO81_OSCCFG/LCD_FIELD/R2/PWM3C18

GIO85/COUT0[B3]/PWM3D17

GIO86/COUT1[B4]/PWM3/STTRIGD18

GIO87/COUT2[B5]/PWM2/RTO3D19

GIO88/COUT3[B6]/PWM2/RTO2D16

GIO89/COUT4[B7]/PWM2/RTO1E17

GIO90/COUT5[G2]/PWM2/RTO0E15

GIO91/COUT6[G3]/PWM1E19

GIO92/COUT7[G4]/PWM0E18

R146 1K

TP19

R148 10K

TMS320DM368

U1G

TMS320DM368

PWCTRIO0J3

PWCTRIO1J2

PWCTRIO2J1

PWCTRIO3J5

PWCTRIO4J4

PWCTRIO5K5

PWCTRIO6K4

PWCTRO0K2

PWCTRO1L5

PWCTRO2L4

PWCTRO3L3

RTCXIG1

RTCXOH1

PWRCNTONM2

PWRSTM3

RESET#H3

MXI1L1

MXO1K1

RSV0A1

RSV1R1

RSV2R4

EMU1H4 EMU0G5

RTCKF2

TDIF5

TCKF4

TMSG2 TDOG4

TRST#H5

VSS_MX1L2

VSS_32KH2

R142 0E

TP20

GND

GND

X1

24MHz

12

34

TP21

C365

10uF

R136 0ENM

TP13

C514

1000pF

R150 0ENM

R134 10KR217 0ENM

C363 36pF

R147 1K

R149 1K

TP14

R145 0E

R137 10K

TP15

C364 36pF

R138 10K

R143 10K

TP16

R139 10K

TP17

R615 0E

Page 14: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG POWER

DAC/ADC is not used

AVSS

VCC_1V35

VCC_1V8

VCC_3V3

VCCA_PLL_1V8

VCCA_DAC_1V8

VCCA_VC_1V8

VCCA_USB_1V8

VCCA_ADC_1V8

VCCA_VC_3V3

VCCA_USB_3V3

VCC_1V8

VCC_DAC_1V35

VCC_3V3

VCCA_PLL_1V8

VCC_1V35

VCC_1V8

AVSS

AVSS_VC

VCC_DAC_1V35VCC_1V35

AVSS

VCCA_USB_1V8

AVSS

VCCA_VC_3V3

AVSS_VC

VCC_3V3 VCCA_VC_1V8VCC_1V8

AVSS_VC

AVSS_VC

VCCA_PLL_1V8

AVSS

VCC_1V8

VCCA_DAC_1V8VCC_1V8

VCC_1V8VCCA_USB_3V3VCC_3V3

VCCA_ADC_1V8VCC_1V8

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2014

A3 SoC_ANALOG_POWER

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2014

A3 SoC_ANALOG_POWER

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2014

A3 SoC_ANALOG_POWER

<Variant Name>

C110

0.1uF

C119

0.1uF

C131

0.01uF

C107

1uF

C126

0.1uF

FB10 30E

POWER

TMS320DM368

U1H

TMS320DM368

VDDS18_1G14

VDDS18_2H11

VDDS18_3H14

VDDS18_4J7

VDDS18_5M14

VDDS18_6P7

VDD18_SLDOE5

VDDS33_1F6

VDDS33_2F7

VDDS33_3F10

VDDS33_4H6

VDDS33_5H13

VDDS33_6L12

VDDS33_7N6

VDDS33_8P5

VDDS33_9P6

VDDRAMD4

VPPR3

VDDA18_PLLN4

VDDMXIL6

VDDA33_VCE10

VDDA18_VCE9

VDDA33_USBP4

CVDD1G6

CVDD2G8

CVDD3H7

CVDD4H8

CVDD5H12

CVDD6J8

CVDD7J12

CVDD8J14

CVDD9K8

CVDD10K12

CVDD11L13

CVDD12M6

CVDD13M10

CVDD14M12

CVDD15M13

VDD_ISIF18_33_1F12

VDD_ISIF18_33_2F13

VDD_AEMIF1_18_33_1P14

VDD_AEMIF1_18_33_2R14

VDD_AEMIF2_18_33_1K14

VDD_AEMIF2_18_33_2L14

VDD12_PRTCSS_1J6

VDD12_PRTCSS_2K7

VDD18_PRTCSSK6

VDDA12_DACE12

VDDA12LDO_USBM5

VDDA18_DACD10

VDDA18_ADCG9

VDDA18_USBN5

C127

0.01uF

C130

0.1uF

FB21 30E

C248

0.01uF

C134

0.1uF

C117

1uF

FB13 30E

C249

0.01uF

C132

1uF

C111

1uF

C104

1uF

FB16 30E

C366 0.22uF

FB14 30E

FB9 30E FB11 30E

C120

0.01uF

C367 1uF

C106

0.1uF

C114

1uF

C135

0.01uF

C128

1uF

FB12 30E

C109

0.1uF

FB17 30E

C113

0.1uF

GROUND

TMS320DM368

U1I

TMS320DM368

VSSA33_VCD9

VSSA18_VCF9

VSSAM4

VSSA_ADCF8

VSSA12_DACF11

VSSA18_DACE11

VSSA33_USBP3

VSSA18_USBP2

VSS1A19

VSS2E14

VSS3F14

VSS4G11

VSS5G12

VSS6H9

VSS7H10

VSS8J9

VSS9J10

VSS10J11

VSS11J13

VSS12K9

VSS13K10

VSS14K11

VSS15L7

VSS16L8

VSS17L9

VSS18L10

VSS19L11

VSS20M7

VSS21M8

VSS22M9

VSS23M11

VSS24N8

VSS25N12

VSS26N14

VSS27P8

VSS28P13

VSS29W1

VSS30W19

C124

1uF

FB19 30E

Page 15: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DIGITAL POWER CAPS

Layout Notes:PLACE NEAR CVDD PINS OF DM368

Layout Notes:PLACE NEAR VDDS33 PINS OF DM368

Layout Notes:PLACE NEAR PINS OF 1.8V POWER SECTION

VCC_1V35 VCC_1V35

VCC_3V3 VCC_3V3

VCC_1V8 VCC_1V8

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2015

A3 SoC_DIGITAL_POWER

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2015

A3 SoC_DIGITAL_POWER

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2015

A3 SoC_DIGITAL_POWER

<Variant Name>

C157

0.1uF

C163

560pF

C148

560pF

C158

0.1uF

C165

560pF

C174

0.1uF

C179

0.1uF

C168

560pF

C175

0.1uF

C182

560pF

C170

560pF

C191

10uF

C140

0.1uF

C185

560pF

C192

10uF

C142

0.1uF

C187

560pF

C151

560pF

C161

0.1uF

C145

560pF

C152

10uF

C162

0.1uF

C147

560pF

C155

0.1uF

C177

0.1uF

C167

560pF

C156

0.1uF

C180

0.1uF

C169

560pF

C172

10uF

C138

0.1uF

C184

560pF

C173

10uF

C139

0.1uF

C186

560pF

C189

560pF

C159

0.1uF

C144

560pF

C190

10uF

C160

0.1uF

C146

560pF

C149

560pF

C176

0.1uF

C164

560pF

C150

560pF

C178

0.1uF

C166

560pF

C137

0.1uF

C181

0.1uF

C171

10uF

C136

0.1uF

C183

560pF

C153

10uF

C141

0.1uF

C188

560pF

C154

10uF

C143

0.1uF

Page 16: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Place FBa, Ca, Cb, Cc, Cd as closeto each power pin as possible.

FBa

Cb Cc Cd

FBb

Ce Cf Cg

Ch

Place Ce, Cf,Cg,FBb close toPWFBOUT and place Ch closeto PWFBIN.

set MII/SNIB to '1' for MII modeset ISOLATE to '0' for make MII interface active

set RPTR to '0' for normal modeset SPEED to '1' for 100/AUTO modeset DUPLEX to '1' for full duplexset ANE to '1' for Auto negotiationset LDPS to '1' for Power save mode Enable

PHY Address[:] =1000b

ETHERNET PHY

Ca

RJ45 CONN

NOTE:

AVDD33

EPHY_RXER

EPHY_CRS

PHY_AD0/LINK_LED

PHY_AD3/ACT_LED

PHY_AD1/LED1PHY_AD2/LED2

PHY_AD4/LED4

CRX

RX_N

RX_P

CTX

TX_N

TX_P

PHY_PWFBOUT

PHY_PWFBIN

PHY_TDpPHY_TDn

PHY_RDpPHY_RDn

PHY_PWFBIN

PHY_PWFBOUT

EPHY_COL

EPHY_MDIOEPHY_RSTn

EPHY_CRSEPHY_RXER

EPHY_MDIO

EPHY_RSTn

TX_PTX_NRX_P

RX_NCTXCRX

PHY_AD0/LINK_LED

PHY_AD3/ACT_LED

AGND_PHY

AGND_PHY

AGND_PHY

AGND_PHY AGND_PHY

AGND_PHY

AGND_PHYAGND_PHY

AGND_PHY

AGND_PHY

VCC_3V3 VCC_3V3

VCC_3V3

VCC_3V3

VCC_3V3

VCC_3V3EPHY_TXD310

EPHY_TXD010EPHY_TXD110EPHY_TXD210

EPHY_TXCLK10

EPHY_TXEN10

EPHY_RXD110EPHY_RXD210EPHY_RXD310

EPHY_RXD010

EPHY_RXDV10EPHY_RXER10

EPHY_RXCLK10

EPHY_CRS10

EPHY_COL10

EPHY_MDC 10

EPHY_MDIO 10

EPHY_RSTn 13

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2016

A3 ETHERNET_PHY

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2016

A3 ETHERNET_PHY

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2016

A3 ETHERNET_PHY

<Variant Name>

C376

0.1uF

C373

0.1uF

R152 10K

R160 10K

FB27

30E

X2

25MHz

1 2

43

C374

10uF

R151 10K

R161 10K

R155 10K

C375

0.1uF

R170 510E

C379

24pF

R168 75E

C378

24pF

C383 1000pF

C377

0.1uF

FB29 30E

R162

49.9E

R171 75E

R165

49.9E

C368

10uF

R167 75E

R163

49.9E

DD-

DD+

DB-

DC-

DC+

DB+

DA-

DA+G

Y

J7

CON_RJ45

12345678

L2

L1

L3

L4

S1S2

C369

10uF

INT

ER

FA

CE

NE

TW

OR

KC

ON

FIG

CLOCK

RTL8201CP

ETHERNET PHY

MII-

INT

ER

FAC

E

U27

RTL8201CP-LF

ANE37

AV

DD

3336

DUPLEX38

MDC25

MDIO26

NC27

RESET#42

RPTR40

RTSET28

SPEED39

X146

X247

AG

ND

129

AG

ND

235

DG

ND

111

DG

ND

217

DG

ND

345

DV

DD

33_1

14

DV

DD

33_2

48

RXC16

RXD021

RXD120

RXD219

RXD318

RXDV22

RXER/FXEN24

TXC7

TXD06

TXD15

TXD24

TXD33

TXEN2

COL1

CRS23

LED0/PHYAD09

LED1/PHYAD110

LED2/PHYAD212

LED3/PHYAD313

LED4/PHYAD415

TPRX-30TPRX+31

TPTX-33TPTX+34

ISOLATE43

LDPS41

PWFBIN8

PWFBOUT32MII/SNI#

44

C382

1000pF

R166 510E

R164

49.9E

C381

0.1uF

FB28 30E

R157 10K

C371

0.1uF

C380

0.1uF

1CT:1CT

1CT:1CT

T X

RX

TD

RD

T1

749 013 011

1

2

3

6

7

89

10

16

4 5

11

14

15

12 13

R156

2K

R154 10K

R158 10K

C370

0.1uF

C372

0.1uF

R153 10K

R169 75E

R159 10K

Page 17: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SystemReset

I2C ADDRESS=x1110000

MCU+WI-FI: GS2011MIES

Note that changing an I/O from anoutput to an input may cause afalse interrupt to occur if the stateof the pin does not match thecontents of the Input Port register.

Note:

IO EXPANDER

GS2011 RESET

GS2011 UART

GS2011 PROGRAM

MCU_PRGM_GPIO27

MCU_PRGM_SoC_WAKE

MCU_UART0_RXMCU_UART0_TX

MCU_RESET_SCH

GPIO_IO_EXP_INT

ADC_MCU

SDIO_DATA2

MCU_SPI1_CS0MCU_SPI1_CS1

MCU_SPI1_CLK

MCU_SPI1_DINMCU_SPI1_DOUT

CLK_RTC

MCU_PRGM_GPIO27

MCU_UART0_RXMCU_UART0_TX

MCU_RESET_SCH

MCU_OTP_VPP

MCU_CLK_HS

DC_DC_CNTRL

GPIO_IO_EXP_INT

MCU_I2C_SCLMCU_I2C_SDA

GPIO_IO_EXP_INT

SDIO_DATA1

FACTORY_RESET

VCC_MCU_3V3

VCC_MCU_3V3

VCC_MCU_CT_3V3 VRTCVCC_MCU_3V3 VCC_MCU_CT_3V3

VCC_MCU_CT_3V3VRTC

VCC_MCU_3V3 VCC_MCU_3V3

VCC_MCU_3V3

VCC_MCU_3V3

VCC_MCU_3V3

VCC_MCU_3V3

VCC_MCU_3V3

SoC_MCU_STDY_WAKE11

MCU_I2C_SDA5,19MCU_I2C_SCL5,19

MCU_SPI_MOSI11MCU_SPI_MISO11

MCU_SPI_CLK11

MCU_SPI_CS11

SYS_PWR_EN 6

MCU_SoC_GPIO211

MCU_BT_UART_RX 18MCU_BT_UART_TX 18

SOC_nRESET 6

MCU_SoC_GPIO1 11MCU_PRGM_SoC_WAKE 10

FACTORY_RESET11PIR_DIG_OUT13,19

MCU_OFF_REQ6

MCU_OFF6

MCU_LED_RED_CTRL19MCU_LED_GREEN_CTRL19

BT_MCU_WAKE_UP18SoC_MCU_WAKE_UP13

MCU_SoC_GPIO313

FG_ALARMB5,13

MCU_BT_GPIO18

MCU_SoC_GPIO4 11

MCU_BT_PWR_EN18

USB_WAKEUP_MCU11

MCU_PRGM_GPIO27 13

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2017

A3 Wi-Fi_GS2011MIES

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2017

A3 Wi-Fi_GS2011MIES

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2017

A3 Wi-Fi_GS2011MIES

<Variant Name>

C465 0.1uF

TP58

SW9

KMR231NG143

2

TP55

R269 0E

ON

SW8

TDA02H0SB1

1

2

4

3R662

1K

C477

0.1uF

R262 1K

C475

10uF

C474

0.1uF

C469

0.1uF

R622

1.5K

R271 0E

R235 10K

R237 10K

R597 0E

C468

1uF

C476

0.1uF

H17

HDR_1X4

1234

R264 10K

R598 0E

TP43

R261 10K

R268 0E

R266

10K

WIFI-MODULE

GS2011MXXS

U48

GS2011MIES

ADC_14

EXT_RESET#33

SPI1_CS#_1/GPIO1314

SPI0_CS#_0/SDIO_DAT3/GPIO336

SPI0_DIN/SDIO_CMD/GPIO345

SPI0_CLK/SDIO_CLK/GPIO357

SPI0_DOUT/SDIO_DAT0/GPIO368

SDIO_DAT1_INT/GPIO372

SPI1_CS#_0/GPIO416

SPI1_CLK/GPIO515

SPI1_DIN/GPIO617

SPI1_DOUT/GPIO718

VD

DIO

20

VIN

_3V

335

VO

UT

_1V

834

VR

TC

10

GN

D19

GN

D1

1

GN

D2

36

UART1_TX/SDIO_DAT2/GPIO3228

UART0_RX/GPIO030

UART0_TX/GPIO129

UART0_CTS/GPIO2431

UART0_RTS/GPIO2532

UART1_CTS/GPIO2625

UART1_RTS/GPIO2726

UART1_RX/GPIO327

RTC_IO_19

RTC_IO_211

DC_DC_CNTRL/RTC_IO_412

I2C_CLK/GPIO923

I2C_DATA/GPIO824

CLK_HS_XTAL/GPIO1921

CLK_RTC/GPIO2113

PWM0/GPIO1022

PWM2/GPIO313

VPP37

R253 0E

R270 0E

R267 0E

R621

1.5K

R260 10K

R236 10K

I/O EXPANDER

U46

PCA9538BS

RESET#1INT#11

SCL12

SDA13

VD

D14

VS

S_E

P17

IO02

IO13

IO24

IO35

VS

S6

IO47

IO58

IO69

IO710

A015

A116

R607 10KNM

R272 0E

R263 1K

FB34 30E

TP57

R242 10K

Page 18: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BLE INTERFACE

BLE POWER ENABLEUFL CONNECTOR JTAG HEADER

Vth(max) = -1.0V (VGS)

For Revision control

UFL CONNECTOR

RF Front End

XTAL_2

XTAL_1

VDD_PA

DB_SWDIO/BLE_RST#

BT_UART_RXDB_SWDCLKBT_UART_TX

BT_XL1BT_XL2

BT_UART_TX

BT_UART_RX

BT_REV0BT_REV1

BT_REV1BT_REV0

RF_nRF51822_ANT1

RF_nRF51822_ANT2

VDD_PA

RF_nRF51822_ANT

BT_UFLRF_nRF51822_ANT

VCC_MCU_3V3

VCC_BT_3V3

VCC_BT_3V3

VCC_BT_3V3

VCC_BT_3V3

VCC_MCU_3V3

VCC_BT_3V3

MCU_BT_PWR_EN17

BT_SPI_CLK11

BT_SPI_CS11

BT_SPI_MOSI11BT_SPI_MISO11

DB_SWDCLK11

DB_SWDIO/BLE_RST#11

BT_MCU_WAKE_UP17BT_GPIO_1611BT_GPIO_1711

BT_GPIO_2011

SoC_PBT_PWR_EN13

MCU_BT_UART_RX17

MCU_BT_UART_TX17

MCU_BT_GPIO17

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2018

A3 BT_NRF51822

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2018

A3 BT_NRF51822

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2018

A3 BT_NRF51822

<Variant Name>

C430 0.047uF

Q9

NTK3134NT1G

1

32

R660 0E

C431 18pF

R602

10K

GND

X6

16MHz

1 2

43

L131.8nH

X5 32.768KHz

12

BAND PASS FILTER

FL2

2.45GHz

OUT3

GN

D1

2

GN

D2

4

IN1

R601

10K

NM

C422

1000pF

C434 12pF

R659

0E

NM

C417

10uF

C420

0.1uF

R189

10K

R238 0E

R240 0E

C528

2.7pFNM

C429 0.1uF

C428 2.7pF

R186

10K

NM

J6

CON_COAXIAL

1

23

BALUN + BPF

U58

2450BM14E0003

BAL_PORT13

UNBAL_PORT1

GN

D1

2

DC_FEED5

GN

D2

6

BAL_PORT24

R600

10K

FB31 30ENM

R239 0ENM

R658 0ENM

C433 18pF

C419

0.1uF

H15

HDR_2X3

135

246

NRF51822

U30

NRF51822

ANT131

ANT232

AV

DD

135

DCC2

DEC139

DEC229

P0_0/AREF04

P0_1/AIN25

P0_2/AIN36

P0_3/AIN47

P0_4/AIN58

P0_5/AIN69

P0_6/AIN7/AREF110

P0_711

P0_814

P0_915

P0_1016

P0_1117

P0_1218

P0_1319

P0_1420

P0_1521

P0_1622

P0_1725

P0_1826

P0_1927

P0_2028

P0_2140

P0_2241

P0_2342

P0_2443

P0_2544

P0_26/AIN0/XL245

P0_27/AIN1/XL146

P0_2847

P0_2948

P0_303

AV

VD

236

VS

S1

13

VS

S2

33

VS

S3

34

VS

S_E

P49

VDD_PA30

VD

D1

1

VD

D2

12

SWDCLK24

SWDIO/RESET#23

XC137

XC238

R599

10K

NM

C436

0.1uFNM

Q4

NTLUS3A18PZTCG3

48

12567

R241 0E

C432 12pF

C421

0.1uF

R193

100K

C424 5pF

C418

10uF

R194

1K

Page 19: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

STATUS LEDS

PIR DETECTOR

PIR Sensor

Variable Resistor forSensitivity Control

Layout Notes:PLACE NEAR VDD PIN OF PIR CTLR IC

I2C

ADDRESS=0101110

Note:MODE_SEL = 0 FOR SINGLEPULSE DETECTION

PIR & STATUS_LEDS

PIR_PWRPIR_OUT

PIR_OUT

PIR_ANA_OUT

OP1_N

OP2_N

OP2_N

MODE_SEL

VCC_MCU_3V3

AVSS_PIR AVSS_PIR

VCCA_PIR_3V3

AVSS_PIR

VCCA_PIR_3V3VCC_MCU_3V3

VCCA_PIR_3V3

AVSS_PIR

AVSS_PIR

VCCA_PIR_3V3

AVSS_PIR

VCCA_PIR_3V3

AVSS_PIR

AVSS_PIR

AVSS_PIRSoC_LED_GREEN_CTRL13

SoC_LED_RED_CTRL13

MCU_LED_RED_CTRL17

MCU_LED_GREEN_CTRL17

MCU_I2C_SDA5,17

MCU_I2C_SCL5,17

PIR_DIG_OUT 13,17

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2019

A3 PIR & STATUS_LEDS

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2019

A3 PIR & STATUS_LEDS

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2019

A3 PIR & STATUS_LEDS

<Variant Name>

C441

1000pF

R200 10KNM

FB32 30E

R663 10K

D5

YG

21

R666 10K

R199 10KD4

R

21

C438

1uF

Q7

MBT3904DW1T1G

1

2

3

4

5

6

+ C443

33uFPIR

CTLR

U32

NCS36000D

OP2_O1

OP2_N2

OP1_O3

OP1_N4

OP1_P5

VS

S7

OUT8

LED9

NC11

OSC13

VD

D14

MODE12

LED_EN#10

VREF6R208

220E

C440

0.1uF

R204

100K

R667 47K

R202 3.3K

C442

0.1uF

R664 10K

C439

0.01uF

TP25 TP26

R195 10KNM

R669 47K

R201

12K

C446 0.22uF

R205

220E

C448 0.1uF

R665 10K

R206

220E

DIG-POT

U33

CAT5137

GN

D2

RH6

RW5

VD

D1

SCL3

SDA4

C447 0.47uF

R198 620K

R670 47K

R668 47K

C445 100uF

R207

220E

Q6

MBT3904DW1T1G

1

2

3

4

5

6

D

S

GND

XDCR1

IRA-S210ST01

12

3

R203 220K

D3

YG

21

C444 0.015uF

FB33 30E

D2

R

21

R197

47K

R196 10K

Page 20: REV Revision Notes Designer Approver Date A0 VINOD KUMAR

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MISCELLANEOUS

LOCAL FUDICIALSFor DM368 For AR0230 For DDR2

MOUNTING HOLES

GLOBAL FUDICIALS

GROUND POST

For NOR FLASH

OFF BOARD COMPONENTS

For BT For GS2011M

PATCH ANTENNA-WIFI PATCH ANTENNA-BT

ON SEMI LOGO ON PCB

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2020

A2 MISCELLANEOUS

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2020

A2 MISCELLANEOUS

<Variant Name>

Asy No :

Title :

Rev:

Sheet ofFab No :

B1701-1-00237

501-1-00198 2020

A2 MISCELLANEOUS

<Variant Name>

MH3

98MILS

FD16

Local

TP31

MIS2

M127B02820WR2

C455 1000pF

DAT2

CD/DAT3

CMD

VDD

CLK

DAT0

VSS

DAT1

uS

D

CA

RD

Z12

SD-C04G2R7Y(66CGP)

FD6

Global

FD13

Local

Z14

FXP73.07.0100A

FD2

Global

BPCB1

BPCB

MH1

118MILS

FD10

Local

FD7

Local

TP29

PIR

LENS

MIS3

PD55-14006

Z13

FXP73.07.0100A

FD1

Global

FD17

Local

LENS HOLDER

MIS1

A02-002

FD12

Local

MH2

98MILS

TP30

FD15

Local

FD4

Global

FD9

Local

FD5

Global

FD3

Global

FD18

Local

FD14

Local

FD11

Local

TP32

FD8

Local

R215 10M