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RF Basics(Block Diagram)
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1
RF circuit design: Basics
Akira Matsuzawa
Tokyo Institute of Technology
2
Contents
• Building blocks in RF system and basic performances
• Device characteristics in RF application• Low noise amplifier design• Mixer design• Oscillator design
3
Basic RF circuit block
Receiver
Transmitter
ImpedanceMatching
1)LowNoiseAmp. 2) Mixer
3) Oscillator
PowerAmp.
Filter
RF systems are composed of limited circuits blocks.LNA, Mixer, and Oscillator will be discussed in my talk.
4
Basic functions of RF building blocks
Log (f) Log (f)
dB dB1) Amplifier3) Filter
Down conversion
Up conversion
2) Mixer+ Oscillator
Desired
Undesired
Amplifier, frequency converter (mixer +oscillator), and filerare basic function blocks in RF system.
Frequency conversion
5
RF Amplifier
• Gain: Amplify small signal or generate large signal.• Noise: Smaller noise and larger SNR.• Linearity: Smaller non-linearity.
Non-linearity generates undesired frequency components.
.....)()()()( 33
221 +++= tvtvtvtv inininout ααα
( ) ( )( ) ( ) ( ) ( )( ) ( )( )tttttt 2121212
21 coscos2cos2cos2coscos ωωωωωωωω ++−+++=+
( ) ( )( ) ( )( ) ( )( ) ....2cos212cos
21coscos 1221
321 +−+−=+ tttt ωωωωωω
6
Input and output characteristics
Pout
Pin
OIP3
IIP3
IP3
1dBPout(1dB)
Fundamental IMD3
Slope=1Slope=3
SNR minSNR min
SFDRBDR
NoiseFloor
NoiseFloor
SFDR
MDSCP1dB
Distortion and noise are important factors in RF amplifier, as well as power and gain.
7
Dynamic range
BWNFdBmFloorNoise log10174 ++−=
( ) min332 SNRFloorNoiseIIPSFDR −−=
SFDR: Spurious free dynamic rangeThe input power range over which third order inter-modulation productsare below the minimum detectable signal level.
BDR: Blocking dynamic range
kT limitation Bandwidth
MDS: Minimum detectable signal level= Noise Floor +SNRmin
min1 SNRFloorNoisePBDR dB −−=
8
Non-linearity
3
11 145.0
αα
=dBCP
CP1dB: The input level at which the small signal gain has dropped by 1dB.
IMD3: The third order inter modulation term
IP3: The metric third order intercept point. It is the point where the amplitude ofthird order inter modulation is equal to the that of fundamental.
3
13
34αα
=IPA IIP3: Input referred intercept pointOIP3: Output referred intercept point
( )inout PIIPIMDP −⋅=− 33 2
9
MOS transistor
Gate
Drain
Source
G D
S, B
rg
Cgs
Cgd
gmvg’
vg’ rds
Cds
MOS Transistor Equivalent Circuit
Body
Intrinsic gate voltage and gm are the most important factors in RF CMOS.
10
Cutoff frequency: fT
CingmViVi
CingmfT π2
=∴
Ii
Ii Io
)cos(
)sin(
tCIioVi
tIioIi
in
ωω
ω
=
=
inCtgmIiogmViIo
ωω )cos(
==
fT: Frequency at which the current gain is unity.
Input current
Gate voltageS
GD
Output current
Proportional to gmInversely proportional to Cin
For higher fT, increase gm and decrease Cin.
11
Amplifier gain
insg
Cr1
=ω
s
T
rrG 0⋅≈
ωω
inT
Cgm
=ωCin gmVg
Vgrs
Vs ro
Ig Id Log (G)
Log (f)
G=gmr0
1
rsr
Crgmr
Tins
o 00 ωω ==
For the larger gain
Fundamentally larger gmr0 oeff
dso r
VIgmrG ⋅
⎟⎠⎞
⎜⎝⎛
≈≈
2
Larger Ids or ro
Larger Q
CQLQro0
0ω
ω ==Q
Distortion and Cin increase
Veff is difficult to reduce
Higher fT and lower rs
For higher voltage gain, increase gm, fT, ro (Q), and decrease input and gate resistance
12
Characteristics of gm (Basic)
⎟⎠⎞
⎜⎝⎛
=⎟⎠⎞
⎜⎝⎛
=
2
1,
2effeff VIds
gmVIdsgm
dsox
eff IWL
CnV ⋅⋅⋅=
12μ
( )
dsOX
effOX
gs
ds
effOX
TgsOXds
ILW
nCgm
VLW
nC
dVdIgm
VLW
nCVV
LW
nCI
⎟⎠⎞
⎜⎝⎛=
⎟⎠⎞
⎜⎝⎛=≡
⎟⎠⎞
⎜⎝⎛=−⎟
⎠⎞
⎜⎝⎛=
μ
μ
μμ
2
2222
Scaling W/L ratio
Square law region
Gm is proportional to the Ids and inversely proportional to the Veff.
Veff is proportional to square root of Ids and inversely proportional to square root of (W/L) ratio.
dseff JLWIdsLV ⋅=∝
Veff is proportional to square root of drain current density.
13
Non-ideal effects to square low region
TdT
ds
T
gssods
nUsIgm
nUIgm
nUVII
1
exp
==
⎟⎟⎠
⎞⎜⎜⎝
⎛=
Sub-threshold regionLow Veff
0.2 0 0.2 0.4 0.6 0.80
5
10
15
20
25
3025.083
1.302
eff 0.4 10, Veff,( )
eff 0.2 5, Veff,( )
10.2 VeffVeff (V)
constnUIds
gmT==
1
VeffIdsgm 2
=
Gm
/Ids (
S/A
)Mobility degradationHigh Veff
LvV ceff
00
0 ,1
μθθθμμ +≈+
≈
( Weak inversion)
This effect becomes larger at large Veff and short channel length.
At larger Veff and lower Veff, two non-ideal effects are not negligible .
14
Distortion
IIP3
Veff (V)
L=0.1umL=0.2um
L=0.4um
⋅⋅⋅⋅+++= 33
221 effeffeff VaVaVaIds
3
133
3
334
61
aaI
dVIda IPeff
ds=≡
1
10
100
0.1
1
10
-0.1 0 0.1 0.2 0.3 0.4 0.5
Veff (V)
gm/Id
s (S
/A)
IIP3
(V)
Lower Veff gives higher gm, bur results in higher distortion.To obtain lower distortion ( higher IIP3), we must increase Veff.
Higher gm and lower distortion means higher Ids.
15
LC resonator
CQLQro0
0ω
ω ==Substrate
LC
r0
Q
LC1
0 =ω
LC resonator can be regarded as resistance at the resonance frequency.
16
Substrate effect
SDSDSPAD
Gate
SDSDSPAD
GateShield layer
RF power loss and noise generation
Substrate should be treated as resistive network.
This substrate resistance causes RF power loss and noise generation.
Shielding can reduce this effect.
17
Power loss in substrate
Rp(Ω)
1 101K 10K
Cp(pF)
0.1
1Gp(mS)
100
C
RpGp Cp
Equivalent
MOS: 10ΩcmGaAs: 1GΩcmCR
CC
RG
pp
p
p
p
p
pp
1
1
1
1
1
2
2
2
=
⎟⎟⎠
⎞⎜⎜⎝
⎛+
=
⎟⎟⎠
⎞⎜⎜⎝
⎛+
⎟⎟⎠
⎞⎜⎜⎝
⎛
⋅=
ϖ
ϖω
ϖω
ϖω
Very low resistance or high resistance realizes low power loss.
Higher C and moderate Rsubresults in higher power loss.
18
GHz operation by CMOS
inT
Cgmfπ2
≡
The cutoff frequency of MOS becomes higher than that of Bipolar.Over several GHz operations have attained in CMOS technology
1995 2000 2005
1G
10G
100G
100M
Freq
uenc
y (H
z)
200M
500M
2G
5G
20G
50G
fT : CMOS
fT : Bipolar (w/o SiGe)
D R/C for HDDIEEE 1394
CellularPhone
fT /10 (CMOS )
CDMA fT /60 (CMOS )
0.35um0.25um
0.18um
0.13um
Year
Digital circuits
RF circuits
eff
satTpeak
Lvfπ2
≈5GHz W-LAN
19
Effect of parasitic capacitance to fT
0 200 400 600 800 10000
2 .1010
4 .1010
6 .1010
5.786 1010.
1.576 109.
fti 0.2 W, 5 10 3., 0,
fti 0.2 W, 5 10 3., 0.1 10 12.,
fti 0.2 W, 5 10 3., 0.5 10 12.,
1 103.10 W
0
20
40
60
f T(G
Hz)
W(um)
Cp=0
Cp=0.1pF
Cp=0.5pF
Ids=5mAL=0.2um
(1)
(2)
)(2 pgdgsT
CCCgmf
++≡
π
fT of actual circuit is reduced by a parasitic capacitance.There is an optimum gate width to obtain highest fT.
CingmVi
ViCp
Cin=Cgs+Cgd
Region(1); Increased by increasing gmRegion(2); Decreased by increasing Cin
20
fT: MOS vs. Bipolar
⎟⎠⎞
⎜⎝⎛
≡
2effV
IdsgmTU
Icgm ≡
Teff nUV 2min = n: 1.4
BipCMOS gmgm41,
21
<
mVq
kTUT 26≈≡
(Same operating current)
CingmfT π2
≡
BipCMOS CinCin41,
21
< (Same fT)
Veff/2: 50-100mV(actual ckt.)
Even if fT of MOS is the same as that of Bipolar, fT of MOS is easily lowered by a parasitic capacitance.Because, gm of MOS is ½ to ¼ of that of Bipolar at the same current.
MOS Bipolar
Small parasitic capacitance is a key for RF CMOS design.
21
VT mismatch
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
5
0
10
15
)(1 1−mLW
μ
ΔV
T(σ
:mV
)
0.4um Nch
0.4um Pch
0.13um Nch In w/o Halo*
0.13um Nch Boron w. Halo*
* Morifuji, et al., IEDM 2000.
VT mismatch degrades accuracy; ADC, OP amp, and Mixer.Larger gate area is needed for small VT mismatch.Scaling and proper channel structure improves mismatch.
LWTV ox
T ∝Δ
Larger gate area
Tox Scaling
Channel engineering
22
VT mismatch: Fluctuation of doping
基板
- --- - - - - - -
- - - -
-
-- -
- - -ddepl
VAVT 1=Adepl
oxVT
Aox
Adeplox
ox
deplT
Nd
LWtA
LWN
tALW
NLWdAt
CQ
V
1
4
∝
≈′==Δ
=Δ
Q
mVVnmtmWL
T
ox
205,25.0
=ΔT.Mizuno, J.Okamura and A.Toriumi, ”Experimental study o f threshold voltage
fluctuation due to statistical variation of channel dopant number in MOSFETs,”IEEE Trans. On Electron Devices, ED-41, 2216 (1994)
=== μ
Courtesy of Prof. Taniguchi, Osaka Univ.
23
1/f noise
1E-19
1E-18
1E-17
1E-16
1E-15
1E-14
1E-13
1E+02 1E+03 1E+04 1E+05 1E+06 1E+07
L=0.4um
L=1.0um
Bipolar
nMOSVdd=3VId=1mA
1E-19
1E-18
1E-17
1E-16
1E-15
1E-14
1E-13
1E+02 1E+03 1E+04 1E+05 1E+06 1E+07
nMOS
pMOS
W/L=800/0.4Vdd=3VId=1mA
Bipolar
2
Inpu
t ref
erre
d no
ise
volta
ge (V
2 /Hz)
Frequency (Hz) Frequency (Hz)
Inpu
t ref
erre
d no
ise
volta
ge (V
2 /Hz)
Nch/Pch 0.4um Nch 0.4um/1.0um
1/f noise of MOS is larger than that of bipolar.
22 , oxvfvf
nf TSff
LWSV ∝
Δ=
For the lower 1/f noise, the larger gate area is needed.
24
Noise figure: General
sss jXRZ +=
( )nis
s
nv
s
nis
s
nv
rsn
ngsngrsn GRRR
RGZ
RR
V
IZVVF ++≈++=
++= 11
2
2,
22,
ningnvng kTGIkTRV 44 2,
2 ==
NoiselessCircuit
Vs
ZsVn,rs Vng
Ing
The lower Rnv and Gni realizes the better for a lower noise figure.
ni
nv
ng
ngsopt
GR
IVR == ninvGRF 21min +≈
25
Noise figure: MOS transistor
niss
nv GRRRF ++≈1
gmRgs
51
≈231NL
WRR totsrg =gsgnv RRR +=
20
5⎟⎠⎞
⎜⎝⎛≈
Tni
gmGωω
20
5511 ⎟
⎠⎞
⎜⎝⎛++≈
T
gmRsgmRs
Fωω
00
11ωω
ωgs
Tsopt
CgmR =⎟
⎠⎞
⎜⎝⎛≈
TF
ωω0
min 21+≈
26
Lg
Ls
Cpi
Rsub
M1
M2
Z0 rg
Cgs rgs
( ) sTsgsg
gsin LLCgm
ssCLLsZ ω≈⎟
⎠⎞
⎜⎝⎛+++≈
1
( )gsgs LLC +=
10ω
Impedance matching
Low noise amplifier design
Narrowband LNA uses inductor degeneration for impedance matching.
27
Low NF design
0
20
00
141Z
rrgmZZ
rrF ggs
T
ggs ++≈⎟
⎠⎞
⎜⎝⎛+
++≈
ωωγ
gmrgs
51
≈
S
D
S
D
S
S
D
Divide the gate
LWRr tot
srg =
231NL
WRr totsrg =
Rsr: Sheet resistanceN:The # of division
Low noise figure
1) Lower the gate resistance
Dived the gate or lower the gate sheet resistance
2) Reduce substrate loss
Use shield technique to the input bonding PAD.
Use high resistive substrate, if possible.
3) Increase drain current ( )ds
effgs
IV
gmr
1051
≈≈4) Increase Z0, if possible.
Reduce parasitic capacitance
28
Ids and Veff optimization
WIV ds
eff ∝
001
3 ZIVgmZF
IIPDR dseffLNA
LNA ≈∝−
∝
Veff
NF
Gain
3rd distortion
dB
Adjust the Ids and Veff for optimization of gain, noise and distortion.
Lower Ids
Higher Ids
effVIIP ∝3
Dynamic range of LNA is proportional to Ids.
29
NF progress in MOS LNA
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
0.11
Gate length (μm)
0.35 0.250.5
NF
(dB
)NF of MOS LNA is reaching 1dB.
30
Mixer
( )( )tAV LOsso ωωπ
±= cos2Vs
VLO
Vo( )tAV sss ωcos=
( )tAV LOLOLO ωcos=
If VLO>>4Veff (Full swing)
FIF FIF
Freq
dB
FIF
Freq
dB
FLO
Fdes
Fimage
RF spectrum IF spectrum
Mixer converts frequency, but image signal is converted to the same frequency.
31
Image-reject mixers
( )tLOωcos
LPF
+
LPF °− 45
Vin (t) Vout(t)
( )tLOωsin
°45
( ) ( )tAtAtV imimdesdesin ωω coscos)( +=
( ) ( )tIAAtAAtV IFRcimIFcdesout ωω coscos)( +=
Ac: Conversion gain, IR: Image rejection
IR=0 if I/Q phase difference is 90° and Channel conversion gains are equal.
The quadrature mixing realizes image-suppression.Gain and phase matching is needed.
32
Gain mismatch and phase error
φγγφγγ
cos21cos21
2
2
++−+
=desired
spur
PP γ
φ: Gain ratio
:Phase error
A. Rofougaran, et al., IEEE J.S.C. Vol.33, No.4, April 1998. PP. 515-534.
33
Passive FET mixer
Lo Lo
LoLo
Vin
Vin
Vo Vo
Low powerHigh linearityNo 1/F noise
No conversion gainNo isolation, Bi-directional
Passive FET mixer
MOS can realize a passive mixer easily.
Ultimately low power, but take care of isolation.
34
Active mixers
Zs
ZL
Lo Lo
Vo Vo
Vin
ZL
Single balanced mixer
Zs
Lo Lo
Vo
Vin
ZL
Zs
ZL
Lo
Vin
Vo
Double balanced mixer
M1
M2 M3
M1 M1’
M2 M3 M2’ M3’
Very small direct feed through and even order distortion
35
Active mixer design
s
LLmix
ZZorZgmG
ππ22
,1 ==
eff
ds
eff
L
onin
LLLO
LLon
VIIP
IVkT
gmkT
Rgm
vSSBv
gmkTRRgmAIRkTRv
≈
≅≈
⎟⎠⎞
⎜⎝⎛
=
≈⎟⎠⎞
⎜⎝⎛ ++=
3
22
8218
2
1
22
1
22
12
12
γπγπ
π
γγπγ
Mixer gain
Thermal noise
A larger dynamic range needs larger current
RL: Resistive component in ZL
when Zs is used
Ts TLO
1/F noise
1) Switch transistor (M2, M3)
CgsWLswn
swnLO
on
v
vTTsv
11,
2
,,4
∝≈
=
2) Load transistors Directly produces
Phase modulation
Shorter switching time or larger Ts/TLo ratio
The larger Ids is needed for high dynamic rangeand shorter switching time for low 1/f noise.
36
Oscillator
πo
oscIrV 4
=
QCV
rVI odd
o
ddopt
ωππ==
2
CQLQro0
0ω
ω ==
L CQr0-1/gm
1) Amplitude condition
Oscillationamplitude
Vdd
2) Oscillation condition
-1/gm
Headroomlimit
2Vdd
QCVI
rgm effo
o
3,2,3,2 ,2 ω
>>
L
C
L
C
Vb
Vc
Vo Vo
(a)
M1
M2 M3
I
There is an optimum Ids for low phase noise.
37
Phase noise of oscillator
( )ωjZ
0
21ω
LQBw
=
Bw
ω
R
0.7R
[ ])(cos)( 0 ttAtv φω +=
ωφφω jdtd
m ==mω : Offset angular frequency
( )mmm SS ωωω φω2)( = )( mS ωω
( )mS ωφ
:Noise spectrum densityon offset angular frequency
:Noise spectrum densityon phase
mLm Q
Bwω
ωωθ
0
2==Δ
ω
0ω
ωω
φ dQd L
0
2=φ
θΔ Phase error between in and out
( )mL
m SQ
S ωωω θω Δ⎟⎟⎠
⎞⎜⎜⎝
⎛=
20
2)(
( ) ( )mmL
m
mLm S
QS
QS ω
ωωω
ωωω θθφ ΔΔ ⎟⎟
⎠
⎞⎜⎜⎝
⎛=⎟⎟
⎠
⎞⎜⎜⎝
⎛=
20
2
20
21
2)(
( )mS ωθΔ
Bwm
:Noise spectrum densityon phase error
<ω
Phase-frequency relation and resonator characteristics determine phase noise.
38
Phase noise of oscillator
202
22
24 ⎟⎟
⎠
⎞⎜⎜⎝
⎛=⋅
Δ=
Δ monn
QkTrZ
fi
fv
ωω
( )
0
00
2ωω
ωωωm
mLjZ ≈+
LrQ0
0
ω=
( )ωjZ
0
21ωQ
Bw=
Bw
ω
R
0.7R
L CQ
-1/gm -1/gmr0
( )m
mQrZωωωω
200
0 ≈+
{ }⎥⎥⎦
⎤
⎢⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛⋅=
20
22log10
msigm
QPkTL
ωωω
0ωω <<m
Noise spectrum density
Phase noise
(Filter action)
39
Frequency characteristics of Phase noise in oscillator
0
2ω
LQBw =
3
20 1
2 mLa
Q ωω
⎟⎟⎠
⎞⎜⎜⎝
⎛( )mS ωφ
2
20 12
2 mL PsFkT
Q ωω
⎟⎟⎠
⎞⎜⎜⎝
⎛
PsFkT2
coω
-9dB/oct(Slope =-3)
-6dB/oct(Slope=-2)
m
Phas
e no
ise
spec
trum
ω
1/f noise Thermal
( )
Thermal
mm
aSω
ωθ =Δ
( )PsFkTS m
2=Δ ωθ
( )mmL
m SQ
S ωωωω θφ Δ⎟⎟
⎠
⎞⎜⎜⎝
⎛=
20
21)(
1/f noise and thermal noise is converted to 1/f3 and1/f2, respectively.
40
Up and down converted noise
)/( HzVVnoise
ωo 2ωo 3ωo
P (dBm)
ω
ω
Noiseshaping
Down-conv.Up-conv.
Noises around N*fo are up and down converted to fo.
41
FoM and minimum phase noise
IVfLffFoM
ddmm )(1
20
⎟⎟⎠
⎞⎜⎜⎝
⎛=
⎟⎟⎠
⎞⎜⎜⎝
⎛⋅⎟⎟
⎠
⎞⎜⎜⎝
⎛⋅⋅=⋅⎟⎟
⎠
⎞⎜⎜⎝
⎛⋅⋅=
roVFkT
ff
QPFkT
ff
QfL
om
o
RFm
om
2
1211
21)(
2
2
2
2
2
19882 mo
o
o grV
IrF ⋅++= γπγ
Fm: Offset frequencyL(fm): Phase noise at offset freq.
F: Noise factor
indo
ddodd
o
ddopt
LQV
QCV
rVI
ωπωππ
22===
2
1,
2
93242
14 Q
VVkT
QFoM
eff
dd∝
++=
γπγπ
FoM is basically proportional to Q2.
at Iopt
42
Oscillator design
Bias currentIopt
Phase noise Oscillationamplitude
2Vdd
C
L L
C
Vb
Vc
Vo Vo
M1
M2 M3
I
Larger VddLarge Veff1, but take care of Vo reductionLarge L1, W1 to reduce 1/f noiseEnough W/L for M2, M3Higher QLarger QLind for Lower Iopt
2
1,min
212
)( ⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎠⎞
⎜⎝⎛ +⋅⋅⋅=
m
o
effdd
indo
ddm
ff
VVQL
VkTfL ωγ
2
1,2min
212
12
)( ⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎠⎞
⎜⎝⎛ +⋅⋅⋅=
m
o
effddoptm
ff
VVQIkTfL γ
indo
ddodd
o
ddopt
LQV
QCV
rVI
ωπωππ
22===
Careful optimization reduces the oscillator phase noise.
43
L
C
L
CVc
Vb
Vo VoL
C
L
C
Vb
Vc
Vo Vo
L
C
L
C
Vb
Vc
Vo Vo
Cx
LxCsHi-Z at 2fo
(a) (b)(c)
CMOS oscillator circuits
Basic Low power (gm is higher) Low noise by filtering
E. Hegazi, ISSCC 2001
44
Filtering of 2fo component in OSC.
Noise filtering of 2fo component reduces the OSC phase noise to -10dB.
E. Hegazi, ISSCC 2001
45
-150.0
-140.0
-130.0
-120.0
-110.0
-100.0
-90.0
1994 1995 1996 1997 1998 1999 2000 2001 2002
SSB
Pha
se N
oise
[d
Bc/
Hz]
(@1
GH
z,10
mW
,600
kHz)
◆CMOS
■Si-bipolar/BiCMOS
▲SiGe-BiCMOS
Year
Oscillator phase noise progress
Phase noise in CMOS oscillator becomes lower than that of bipolar.
46
Acknowledgment and references
• AcknowledgmentI would like to thank Prof. Asad Abidi in UCLA for his advices.
• References– Asad A. Abidi, “Power-Conscious design of Wireless circuits and
systems,” pp.665-695, “Trade-offs in Analog Circuit Design,” KluwerAcademic Publishers, 2002. (Edited by Chris Toumanzou, George Moschytz, and Barrie Gilbert)
– Thomas. H. Lee, “The design of CMOS RF ICs,” Cambridge University Press, Jan. 1998.
– Bezad, Razavi, “RF micro-electronics,” Prentice Hall, Nov. 1999.– Domine Leenaerts, Johan van der Tang, and Ciero Vaucher, “Circuit
Design for RF Transceivers,” Kluwer Academic Publishers, 2001.– Charles Chien, “Digital Radio Systems on A chip,” Kluwer Academic
Publishers, 2001.– E. Hegazi, et. Al., ”A Filtering Technique to Lower Oscillator Phase
Noise,” ISSCC 2001, 23.4, Feb. 2001.