we innovatively characterize

RF SOI: A Deeper Insight for a Faster Time-to-Market

Mostafa Emam mostafa.emam@incize.com

Beyond Computing' Innovative Technologies Symposium

Tuesday 17 March 2015

Since 2011

Technology Enablement

Radiation Hardness

Self-Heating Thermal Noise

C L I E N T S

Wafer producers

Foundries

MEMS fabless

Imaging Industry

RadioFrequency

RF as a tool for the enhancement of many technologies

22.000.000 /mm2

1948

Bell Labs

[wikipedia]

Frank Schwierz Nature Nanotechnology 5, 487–496 (2010)

High Resistivity Substrate

SiO2

System-on-Chip

Mixed Signal

RF

DSP

Processor

Memory

Base Band MEMS

WLAN

PMU

Si

Logic CPU/DDR SRAM GPU/Interface

RF WiFi/Bluettoth/FM tuner GSM/3G Baseband Processor

Power Amp/Power Management Accelerometer/Gyroscope

Mixed Signal

High Resistivity SOI substrates: how high should we go?

-  STD SOI: 20 Ω.cm ⇒ high losses

-  HR SOI of 10 kΩ.cm would correspond to a lossless Si substrate

Si substrate

signal

Conductor losses (αcond) Substrate losses (αsub)

q  Compatible with CMOS technology

Substrate technology

q  Low parasitic conductance/capacitance q  Low RF losses (ρ > 3 kΩ-cm) q  Low crosstalk q  Linearity ( 1 kΩ-cm) q  Availability (mainstream production, size) q  Low cost

q  Compatible with CMOS technology q  Low parasitic conductance/capacitance q  Low RF losses (ρ > 3 kΩ-cm) q  Low crosstalk q  Linearity ( 1 kΩ-cm) q  Availability (mainstream production, size) q  Low cost

Substrate technology Substrate technology Substrate technology

[D. Lederer et al., SOI 2003], [C. Roda Neve et al., TED’12]

q  Compatible with CMOS technology q  Low parasitic conductance/capacitance q  Low RF losses (ρ > 3 kΩ-cm) q  Low crosstalk q  Linearity ( 1 kΩ-cm) q  Availability (mainstream production, size) q  Low cost

HR-SOI (as HR-Si) suffers from parasitic substrate effects

Substrate technology

[D. Lederer et al., SOI 2003], [C. Roda Neve et al., TED’12]

HR-SOI suffers from Parasitic Surface Conduction (PSC) effect at the SiO2/Si interface.

Parasitic Surface Conduction (PSC)

n-type

Mobile & Interface trapped

charges

Accumulation layer

Fixed charges

Highly conductive layer

10 kΩ.cm [C. Roda Neve et al., TED’12]

SiO2

HR-Si

System-on-Chip RF

DSP

Processor

Memory Mixed Signal

Base Band MEMS

WLAN

PMU Si

+ PSC ≅ 200 Ω.cm

 

Trap  rich  layer  

n-type

Mobile & Interface trapped

charges

Accumulation layer

Fixed charges

Highly conductive layer

High  Resis0vity  SI  Base  

SiO2  (BOX)  Trap rich layer

 

SiO2  (BOX)  

Mono-‐crystal  Top  Silicon  

Trap Rich layer freezes the highly conductive layer at BOX – Handle interface

 

Trap  rich  layer  

High  Resis0vity  SI  Base  

SiO2  (BOX)    

SiO2  (BOX)  

Mono-‐crystal  Top  Silicon  

Trap-rich Fabrication •  Proton implantation

[Wu et al., EDL’00] •  Silicon etching

[Roda Neve et al., EUMC’07] •  Ar implantation

[Posada et al., EuMIC’06] •  Oxygen-doped polycrystalline Si

[Rong et al., EDL’04] •  Amorphous Si

[Lederer et al., EDL’95] •  Polycrystalline Si

[Gamble et al., MGWL’99] •  RTA-crystallized Polysilicon

[Lederer et al., EDL’05] •  Nanocrystalline Si

[Chen et al., EDL’11]

q  Compatible with CMOS technology q  Low parasitic conductance/capacitance q  Low RF losses (ρ > 3 kΩ-cm) q  Low crosstalk q  Linearity ( 1 kΩ-cm) q  Availability (mainstream production, size) q  Low cost

Substrate technology

trap-rich HR-SOI

Substrate technology

Spreading Resistance Profiling (SRP)

RF Non-Destructive Characterization

Destructive. Difficult to get detailed wafer

mapping.

Does not capture interface

conduction.

Difficult to relate to final processed RF

and Non-linear wafer behavior.

Expensive

DUT

Port 1 Port 4 Port 2

Calibratedpower

HarmonicMeas.

Fund. ToneMeas.

Harmonicgeneration

Fund. Tone

Aprobe Aprobe Aharm

Afund

DUT

Port 1 Port 4 Port 2

Calibratedpower

HarmonicMeas.

Fund. ToneMeas.

Harmonicgeneration

Fund. Tone

Aprobe Aprobe Aharm

Afund

DUT

Port 1 Port 4 Port 2

Calibratedpower

HarmonicMeas.

Fund. ToneMeas.

Harmonicgeneration

Fund. Tone

Aprobe Aprobe Aharm

Afund

DUT

Port 1 Port 4 Port 2

Calibratedpower

HarmonicMeas.

Fund. ToneMeas.

Harmonicgeneration

Fund. Tone

Aprobe Aprobe Aharm

Afund

DUT

Port 1 Port 4 Port 2

Calibratedpower

HarmonicMeas.

Fund. ToneMeas.

Harmonicgeneration

Fund. Tone

Aprobe Aprobe Aharm

Afund

DUT

Port 1 Port 4 Port 2

Calibratedpower

HarmonicMeas.

Fund. ToneMeas.

Harmonicgeneration

Fund. Tone

Aprobe Aprobe Aharm

Afund

Harmonic Distortion

S-Parameters

Cross Talk

Digital Noise

Measurement Setup

è S-parameters & cross-talk from 5 Hz to 26 GHz è THD (H2 & H3) from -25 to 40 dBm

(900 MHz, 1.8 GHz, 3.6 GHz -> 5 GHz) HD > -145 dBm (noisefloor) Dynamic range of 165 dBc (140 dBc at 40 dBm of input power)

Harmonic Distortions (Large Signal)

Effective Resistivity, Substrate Losses

(Small Signal)

Line

Through Open

LRF Pad

RF Pad RF Pad

RF Pad

RF PadRF Pad

WS

Wg

S

L

W

Cross Talk through the substrate (Small Signal)

Incize provides its customers with tailored libraries of test structures adapted to their technology for optimized characterization results.

SiO2

Si

(b)

SiO2

Si

(a)

trap-rich layer

(BOX) (BOX)toxtp

tSi

Wg S W

Harmonic Distortions (Large Signal)

Effective Resistivity, Substrate Losses

(Small Signal)

Line

Through Open

LRF Pad

RF Pad RF Pad

RF Pad

RF PadRF Pad

WS

Wg

S

L

W

Cross Talk through the substrate (Small Signal)

Incize is developing the first defacto Standard for substrate characterization.

Harmonized FoM Optimized Geometries Enhanced Efficiency

SiO2

Si

(b)

SiO2

Si

(a)

trap-rich layer

(BOX) (BOX)toxtp

tSi

Wg S W

SiO2

Si

(b)

SiO2

Si

(a)

trap-rich layer

(BOX) (BOX)toxtp

tSi

Wg S W

ρSi à from 10 Ω to 10 kΩ-cm

tox à from 50 to 1000 nm

HR-Si trap-rich HR-Si

Lossless linear reference

Quartz

48 substrates

5 10 15 20 25101

102

103

104

105

Freq. [GHz]

α [d

B/m

m]

std-SiHR-Sitrap-rich HR-SiQuartz

3 kΩ-cm

ρ eff [Ω

-cm

]

5 10 15 20 250

0.5

1

1.5

2

Freq. [GHz]

α [d

B/m

m]

std-SiHR-Sitrap-rich HR-SiQuartz

Error in ρeff extraction due to VNA accuracy (freq. dependent)

std-Si HR-Si Quartz trap-rich HR-Si

10 > 5 k

- > 5 k

33 64

> 5 k > 5 k

ρnom [Ω-cm]

ρeff [Ω-cm] Qf ~ 3x1011

Small Signal Characterization

[Roda Neve et al., EUMIC’08]

TR HR-SOI substrate meets harmonic distortion switches specifications.

.

900 MHz

CPW 2146 µm-long

[K. Ben Ali, SiRF 2014]

Large Signal Characterization

-25 -20 -15 -10 -5 0 5 10 15 20 25-120

-100

-80

-60

-40

-20

0

Pin [dBm]

P out

2nd

Har

m. [

dBm

]

Std-SOIHR-SOITR-SOIQuartz

-30 dB

Specs -35 dB

.

900 MHz

CPW 2146 µm-long

Large Signal Characterization

-100 -50 0 50 100

-120

-100

-80

-60

-40

-20

0

Vbias

(V)

HD2,

(dB

m)

-100 -50 0 50 100

-120

-100

-80

-60

-40

-20

Vbias

(V)

HD3

(dB

m)

StdSOIHR-SOITR-SOIQuartz

StdSOIHR-SOITR-SOIQuartz

1k 10 k 100k 1 M 10M 100 M 1 G 10G-160

-140

-120

-100

-80

-60

-40

-20

Frequency [Hz]

S21

[dB]

d= 50 µm

Low Frequency

HR-SOITR-SOISOS

Test structure

d = 50µm 150 x 50 µm

PAD PAD

CROSSTALK

SiO2

Si

[K. Ben Ali et al., TED’11]

d

Crosstalk on HR and TR-SOI

CROSSTALK HR-Si

Trap-rich layer

PAD PAD

SiO2

1k 10 k 100k 1 M 10M 100 M 1 G 10G-160

-140

-120

-100

-80

-60

-40

-20

Frequency [Hz]

S21

[dB]

d= 50 µm

Low Frequency

HR-SOITR-SOISOS

Test structure

d = 50µm 150 x 50 µm

-35 dB 20 dB/dec

[K. Ben Ali et al., TED’11]

Crosstalk on HR and TR-SOI

NOISE SOURCE (digital) VICTIM (analog)

SUBSTRATE COUPLING

Bulk Si / SOI HR-Si

Digital Substrate Noise

BULK HRSOI

Limited DSN reduction due to PSC

[D. Bol et al., SOI’07]

UCL’s SOI FD MOSFET NP2N L = 2 µm W = 20 µm Nf = 20

RF in

900 MHz

Mixed

Output

900 MHz

Noise

HR -‐ Si  (n -‐ type)

Trap -‐ rich layer BOX Source

N + N + Drain Gate Si

Noise: square signal @ 500 kHz

HR SOI

TR SOI

Almost 25 dB reduction of the coupled noise.

Digital Substrate Noise

Without Noise

[K. Ben Ali, SOI Conf. 2012] TR-SOI reduces Digital Substrate Noise

0 2 4 6 80

20

40

60

80

100  

 

Quality  Fac

tor

F requenc y  (G Hz )

 IND2  on  HR -‐4k  IND2  on  HR -‐10k  IND2  on  TR -‐4k  IND2  on  TR -‐10k

-20 -10 0 10-120

-110

-100

-90

-80

-70

-60

Pin [dBm]

P out

2nd

Har

m. [

dBm

]

HR 4 kΩ.cmHR 10 kΩ.cmTR 4 kΩ.cmTR 10 kΩ.cm

HD2 @ 900 MHz

-20 -10 0 10-120

-110

-100

-90

-80

-70

-60

Pin [dBm]

P out

2nd

Har

m. [

dBm

]

HR 4 kΩ.cmHR 10 kΩ.cmTR 4 kΩ.cmTR 10 kΩ.cm

HD2 @ 2 GHz

-20 -10 0 10-120

-110

-100

-90

-80

-70

-60

Pin [dBm]

P out

2nd

Har

m. [

dBm

]

HR 4 kΩ.cmHR 10 kΩ.cmTR 4 kΩ.cmTR 10 kΩ.cm

HD2 @ 4 GHz

Inductors on TR HR-SOI wafer show •  Improved Q •  Reduced substrate harmonic distortions

[K. Ben Ali, SiRF 2014]

Integrated Inductors on TR-SOI Measured results of 35 µm-thick 2 nH spiral

inductors on HR-Si and Trap-Rich HR-Si

q  Displacement Damage + secondary ionizing effects (h+-e- pairs)

SiO2

HR-Si

Induced interface traps

depleted region

Induced fixed charges

p-type

HIGH-ENERGY NEUTRONS

Doping variation &

Carrier mobility degradation

Impact of neutron irradiation

[C. Roda Neve, RADECS 2009]

2 4 6 8 10 12 140

0.2

0.4

0.6

0.8

1

Frequency [GHz]

α [d

B/m

m]

beforeafter50 nm SiO2

500 nm SiO2

500 nm SiO2 + PSi

50 nm SiO2 + PSi

ü  Fast neutron beam ü  High neutron flux and mean energy of 20 MeV ü  Ambient temperature ü  Neutron fluence up to 2.2x1014 neutrons/cm2 ü  Passive regime à devices are not biased

Loss reduction after irradiation (no PSi)

0.4 dB/mm à 50 nm 0.5 dB/mm à 500 nm

Final attenuation after irradiation (no Psi)

α500 nm > α50 nm

Almost no variation for substrates with PSi

Impact of neutron irradiation

[C. Roda Neve, RADECS 2009]

FD SOI MOSFETs 400 nm BOX 80 nm SOI 25 nm gate oxide

Gate Length (L): 2 µm # fingers: 20 Finger width (W): 20 µm Chanel doping: NP2N - Boron implantation

(4 x 1016 at/cm3)

Academic process UCL SOI CMOS technology

[K. Ben Ali, SOI Conf. 2012]

Impact of TR-SOI on Active Devices

Commercial PD SOI MOSFET Foundry technology 5-metal layers, Lg< 0.3 µm

50 100 150 200 250 300 350

2

4

6

8

10

12

14

16

18

ID (mA/mm)

f t (G

Hz)

TR-SOIHR-SOI

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 10

50

100

150

200

250

300

350

VGT (V)

g m (m

S/m

m)

TR-SOIHR-SOI

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 10

50

100

150

200

250

300

350

VGT (V)

I D (m

A/m

m)

TR-SOIHR-SOI

[K. Ben Ali, SOI Conf. 2014]

Impact of TR-SOI on Active Devices

TR HR-SOI shows no impact on Active Devices performance

Compatibility with CMOS technology

Low RF losses (ρ > 3 kΩ-cm)

Low crosstalk (f < 10 GHz)

Linearity ( 1 kΩ-cm)

Availability (mainstream production, wafer size)

Low cost

HR-SOI SOS SOQ

trap-rich HR-SOI SOI

So …

TR-SOI substrate is the most promising solution for RF SoC, and future LTE, 5 G generations.

Take AwayRF is not only for high frequency operation, it is

a powerful tool to enable many technologies.

Incize is developing the first standard to optimize the substrate characterization

Trap-Rich HR SOI is THE technology for next generations of HF applications

Acknowledgments

Incize Team: Dr. Khaled Ben Ali and Dr. Sergej Makovejev

Dr. Cesar Roda Neve from IMEC (ex-UCL).

UCL: Prof. Jean-Pierre Raskin and his group. Winfab and WELCOME teams.

thank you!