RFIC – Atlanta June 15-17, 2008 RMO1C-3 An ultra low power LNA with 15dB gain and 4.4db NF in 90nm CMOS process for 60 GHz phase array radio Emanuel Cohen

RFIC – Atlanta June 15-17, 2008

RMO1C-3

An ultra low power LNA with 15dB gain and 4.4db NF in 90nm CMOS process

for 60 GHz phase array radio

Emanuel Cohen(12), Shmuel Ravid(1), and Dan Ritter(2)

(1) Mobile Wireless Group, Intel Haifa, Israel (2) Department of Electrical Engineering, Technion, Haifa, Israel


Outline

• Design methodology flow and passives

• Circuit implementation options

• LNA measurements

• Conclusions


Motivation

• How low can we get power consumption in a mm-wave LNA without compromising gain NF and size?

• Typical LNA designed for 60GHz showed a power of 20mW (@15dB gain). For a phase array with 30-60 elements we end up with ~1Watt !

• Power and size must go down for a full phase array system in commercial application


LNA Design Methodology

1. Choose the passive circuits and models

2. Choose the transistor width for optimized target

3. Choose best topology with optimized transistor

width


Passive inductor design

0 10 20 30 40 50 60 70 80 90 100110120

-60

-50

-40

-30

-20

Frequency [GHz]

Co

up

lin

g [

dB

]

Coupling no ring

Coupling with ring

19dB

• Ground ring on inductor

improves isolation by 19dB

• No real impact on Q


Creating inductor simple model

• Build a model based on a library of inductors

with EM simulation

• Then the design can be optimized without EM

iterations

Simple pi model


Full EM simulation

• Full EM possible in momentum - 8 hour run

• Excellent fit to stand alone inductor proves

good inductor isolation with ground ring


Capacitors MIM cap Finger CapParasitic capacitance

[pf]

Parasitic capacitance[pf]

Q

Q

[pf]

200pf

• MIM cap Q~9 and finger cap Q >>10

• Finger cap has ~8% parasitic (after optimizing

and using 2-4 layers only)

• Finger cap was chosen for the design


Transistor size and circuit topology

• Transistor size is the key issue for low power design

50110_ 10

indRLoglossInd

)4.2(2.0_80pHy L 40

)6(5.0_320pHy L 10

ind

ind

RdBlossInduW

RdBlossInduW

For Q~20

• 0.3dB max penalty , with full simulation even less • ¼ of power consumption

dsJkGain

WkIdc


LNA behavior with W change

0

2

4

6

8

10

12

14

16

18

20

Frequency [GHz]

Ga

in [

dB

]

55 60 65 704

5

6

7

8

9

No

ise

Fig

ure

[d

B]

NF 30x1 umNF 3x(10x1) umNF 10x1 um

Gain 30x1 um

Gain 3x(10x1) um

Gain 10x1 um

• 3 stage CS design with different transistor sizes

• and same current density.

• Similar performance is achieved with W=10um

and 3x10um

No real BW degradation

Different TransistorsHave similar Q impedance


LNA with different topologies

40 50 60 70 80-30

-25

-20

-15

-10

-5

0

5

10

15

20

25

30

35

Ga

in /

S2

2 [

dB

]

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

Frequency [GHz]

No

ise

Fig

ure

[d

B]

Gain 2Casc par ind(2)Gain 2Casc ser ind(1)S22 2Casc par ind(2)S22 2Casc ser ind(1)S22 3CSGain 3CS

Nf 2Casc par ind(2)Nf 2Casc ser ind(1)Nf 3CS

NF

S21

S22

• Using optimized flow to check different topologies without

iterations

• All topologies designed for ~4mW W=1x10um


Low Noise Amplifier schematic

0 20 40 60 80 100 120300

350

400

450

500

Ind

ucta

nce

[p

Hy]

-10

0

10

20

30

Frequncy [GHz]Q

in

du

cto

r

Lind Qind

• Big inductors still maintain high SRF

• Have better Q


LNA Layout

• die 440 um x 320 um

• Size limited by pads- inner core (0.04mm2)


Measured and Simulated Performance

45 50 55 60 65 70 75-25

-20

-15

-10

-5

0

5

Frequency [GHz]

Sp

ara

m [d

B]

S11 measuredS22 measuredS11 simulatedS22 Simulated

50 55 60 65 70-5

0

5

10

15

20

Ga

in [d

B]

50 55 60 65 704

6

8

10

12

14

Frequency [GHz]

No

ise

Fig

ure

Gain measuredGain simulated

NF measuredNF simulated

• Gmax=15dB NF=4.4dB

• Power consumption 4mW


NF set-up at 60Ghz

[ S. Pellerano, Y. Palaskas , K. Soumyanath “A 64GHz 6.5dB NF

15.5dB Gain LNA in 90nm CMOS” in IEEE ESSCIRC 2007 ]

Down converter

NFA


Comparison with State of the Art LNAs

• Lowest power with smallest size at same Gain


Additional bias point characterization

• Bias point compromise – 0.2dB in NF– 3dB in Gain

1 2 3 4 5 6 7 8 98

10

12

14

16

18

20

Icc [mA]

Gai

n [d

B]

max gain (58Ghz) versus bias current at different Vcc

0.707

0.907

1.1071.307

1.506

1 2 3 4 5 6 7 8 94

4.2

4.4

4.6

4.8

5

5.2

5.4

5.6

Icc [mA]

NF

[dB

]

min NF (58Ghz) versus bias current at different Vcc

0.707

0.907

1.1071.307

1.506

mAJ opt /140 mAJopt /200

mAJ /100


NF , Gain vs. total power dissipation

• Maximum points align on the same line

• There is no difference between changing Vds or Ids

• Consumption can drop to 2mW for 12dB of gain

0 2 4 6 8 10 12 140

2

4

6

8

10

12

14

16

18

20

Power consumption [mW]

Ga

in

[dB

]

4

4.5

5

5.5

6

No

ise

fig

ure

[d

B]

Vdd 0.7 VVdd 0.9 VVdd 1.1 VVdd 1.3 VVdd 1.5 V

NF

Gain


Compression point measure

• Max input signal ~ -25dBm for high data rates

• This is enough for a 60Ghz link budget

-35 -30 -25 -20 -15 -10

10

11

12

13

14

15

16

Pin [dBm]

Ga

in [

dB

]

Pin-Pout simulated

Pin-Pout measured

IP1dB=-18dBm


Conclusions

• Fast design flow with lumped inductor and ground ring was created

• The flow enabled a check of full circuits topology for a fair comparison on optimized results

• The CS and small transistor size 1x10um is the best tradeoff between power consumption Gain and NF.

• A record power consumption of 4mW achieved with best NF of 4.4dB 15dB gain and similar to smallest footprint published

• Lumped inductor enabled smallest size and no additional design complexity


Thank You


Input impedance with W

• Q is very similar

10um

40um

Documents

RFIC – Atlanta June 15-17, 2008 RMO1C-3 An ultra low power LNA with 15dB gain and 4.4db NF in 90nm CMOS process for 60 GHz phase array radio Emanuel Cohen