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Andrea CastoldiPolitecnico di Milano & INFN
Rivelatori di immagini ad alta velocita’ per il European X-ray Free Electron Laser
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 2/27
MoU signed by: Germany, Italy, France, Greece , Spain, Sweden, Switzerland, UK, Poland, Hungary, Denmark, Russia and China
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 3/27
SASE (Self-Amplified Spontaneous Emission)
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 4/27
XFEL projects: time schedule comparison
2004-2006 2012-2013EXFEL
2014-2015SASE1
2009 – LCLSstarts operation
15 july 2006The European Project Team for the XFEL delivered the TDR
R&D until ~2011
Preparation Construction Operation
2010 – SCSSstarts operation
EXFEL
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 5/27
Time structure of EXFEL: difference with “others”
600 µs99.4 ms
100 ms 100 ms
200 ns
FELprocess
X-ray photons100 fs
Electron bunch trains; up to 3000 bunches in 600 µsec, repeated 10 times per second.Producing 100 fsec X-ray pulses (up to 30 000 bunches per second).
30 000 bunches/sbut
99.4 % emptiness
What are the challenges for 2D detectors?
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 6/27
Consequences of time structure
• Either: < 10Hz or > 1.5 kHz; best 5 MHz
• All photons arrive in 100 fsec è integrating detectors.
• Experiments should profit from high luminosity (30 000 shots/sec) and time structure (200 ns).
• Every shot is a new experiment but poses technological challenges (jitter, sample destruction, detector charge handling and position resolution) à 103-105 photons per pixel per pulse
(i.e. 3×106-108 e-h pairs per pixel !)
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 7/27
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 8/27
17th July 2006:46 pages; covering 5 areas
6 EoIs received;different consortiaand technologies
3 EoIs selected to develop full proposal
Call for EOI
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 9/27
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 10/27
Large Pixel Detector (LPD)• Rutherford Appleton Laboratory(c/o Markus French)
• Science and Technology Facilities Council
• involvement of UK universities
Principle: tiled hybrid with 500µm pixels
500 µm pixels5 MHz framing speedSingle photon sensitivity105 dynamic range (3 gains in parallel)512 image storage depth 128 x 32 pixels monolithic tilesRoof tile structure courtesy of H.Graasfma for the European XFEL
Heinz Graafsma, DESY
XFELThe EuropeanX-Ray Laser Project
11
Analog pipeline Hybrid Pixel Detector (HPAD)
DESYPSI/SLSUniversity BonnUniversity Hamburg
Principle: bump-bonded hybrid pixels
100 to 200 µm pixels5 MHz framing speedSingle photon sensitivity5 x 104 dynamic range, using 3 switched gains 400 to 1000 image storage depth256 x 512 monolithic tilesFlat detector
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 12/27
The Linear Silicon Drift Detector (LSDD)
1. MPI-HLL (MPI and MPP)2. Politecnico di Milano & INFN 3. DESY4. Un. Mannheim5. Un. Bergamo/Pavia6. Un. Siegen
The Consortium:
PoliMi & INFN PoliMi & INFN
MPI-HLL DESY
UniBG
DESY
MPI-HLL
MPI-HLL
Un. Siegen
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 13/27
Who we are…and what we do (Detector/On-Chip/Analog)
• Politecnico di Milano and INFN, Sez. di Milano, Italy
• MPI Halbleiterlabor, München, GermanyLSD Detector
chip
Detector
On-chip Electronics
Front-end ASICs
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 14/27
Detector Structure: multi-column SDDs
• fast and noiseless electron drift
• control of lateral broadening of charge cloud
• limited no. of channels (simplified interconnection issue)
• collecting anode and on-chip electronics:
-high energy/position res.
-speedxyz
N-side
P-side
QTd
Bias /Control Logic
anodes
Applicazione in ambito internazionale di R&D nata in INFN-gr.5 (esp. RIMAX, CODERA, COMPTON) con ruolo di leadership a Milano
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 15/27
Working principle in the XFEL facility
600
700800
9001000
1100700
800900
10001100
1200
50
55
60
65
lateral coordinate [ µ m]drift coordinate [ µ m]
-pot
entia
l [V
]
Tdrift~ Ldrift/vdrift
time
current
Td
trigger byXFEL (~1ns)
Anode
hv
The current shape at the anode “mirrors” the photon imageimpinging on the detector
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 16/27
Detector topology
Vdrift ˜ 13 µm/ns (i.e. ~3.5V/30µm bias) Tdrift, max = 1000 ns
1.28 cm(64 pixels)
on-chip electr.
on-chip electr.
128 channels
128 channels
1.28 cm(64 pixels)
1 MHz frame
200µm pixel
E=2-20 keV
103 X-rays/pixel
QE>80%@10keV
ENC~50 el.
Expandable to:
512x512 (monolithic)
1000 ns
1000 ns(?x=200µm,?t=15.6ns)
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 17/27
Analog frontend electronics
0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 8 0 2 0 00
0 . 2
0 . 4
0 . 6
0 . 8
1
1 . 2
1 . 4
i(t)
single SDD line i(t) V(t)200µm
On-chipelectronics
Ampl.+buf.stages
SDD chip ASIC
Analog FE electronics
• purpose of the analog FE electronics is to provide an amplificationand fast shaping of the SDD current signals
• the FE electronics is based on the SDD on-chip electronics + custom ASIC
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 18/27
On-chip electronics: input devicesØOn-chip DEPMOS ØOn-chip JFETs
•minimization of stray capacitances, low noise •Speed issues may require a feedback preamplifier configuration à 2 bonding/channel & integrated reset mechanism
CFET Cstray gmInput device
ext. FET
on-chip JFET
DEPMOS
1pF
70fF
40fF
0.5pF
∼ 0
0
3mS
350µS
100µS
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 19/27
On-chip JFETs: esp. INFN-gr.5 COMPTON (2004-2006)
0 1 2 3 4 5Vds [V]
200
400
600
Ids
[µA
]
Vgs=0 V
-0.5 V
-1 V
-1.5 V
-2 V
-2.5 V
0 100 200anode #
0
200
400
600
800
I dss
[µA
]
2
3
4V
p [V
] (@
I dss
/100
0)Idss=620 µS ± 15 µS
VP=2.75 V ± 0.04 V
0 100 200anode #
0
100
200
300
400
g m [µ
S]
20
30
40
r 0 [k
Ω]gm=350 µS ± 8 µS
r0=25.6 kΩ ± 0.8 kΩ
240 channels
1 cm
The measured spread of DC parameters on 240 ch. is less than 3%
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 20/27
Analog frontend: readout strategiesA. Direct reading of the on-chip FET current with external I/V conversion
i(t)
SDD chip FE chipNon-linearreset path
• a VLSI transimpedance amplifieroperates the I/V conversion of theFET current induced by the SDDcurrent pulse
• non-linear signal compressionimplemented directly by an on-chipdevice in the anode region
iFET(t)
B. Full transimp. amplifier based on the on-chip FET as input transistor
V(t)i(t)
Reset FET
SDD chip FE chip
First FET
1/α
• closed-loop configuration based on the on-chip FET as input transistor and on a Reset on-chip device to implementthe dynamic feedback resistance of a transimpedance amplifier
• non-linearity for signal compression inthe feedback path (e.g. Idrain/VGS reset FET)
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 21/27
Data Acquisition: Burst write/Gap read
ADCTX
CWDMMCC FPGA
MEM
from ROIC to Preprocessor
Strategy Straightforward Solution
• Digitizer per Drift Path
• ROIC near
Short-distance High-speed Data Transfer
• Temporary Data Storage
• ADC near
Flexible & Standardized Readout
• Field-programmable Devices
• Data-link Layer ?Physical Layer Devices
Insensitive & Large Throughput Capacity
• Digital Optical Transfer Mode
• Wavelength-Division Multiplexing
Challenge 1-M Pixel ? 16 k digitizers
• High Speed & Resolution
• Low Area & Power
1.4-Mb/digitizer ? 3 GByte
• Bursty Write Access
• Low Area & Power
Complexity
• Low-jitter Clock Management
• Dynamic Power Management
• Small Form Factor
Burst write Gap read
Conclusion
• use high integration density BUT only as high as mandatory (space requirement)
• use commercial products whenever possible (3 years to prototype)
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 22/27
Focal plane layout: 256 x 256 and 1k x 1k
Focal plane sub-module (2011): 256 x 256 pixel of 200 microns
LSDD detector
analog FE ASIC
connector 256 chPCB
21 c
m
detector sub-module(256 x 256) detector module
(512 x 512)
Focal plane 1k x 1k (2013)
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 23/27
Detector R&D keypoints
• confining mechanism of charge lateral broadening
• electron injectors
• optimization of p+ strips for high drift field
• back-side junction segmentation and structure
• guard ring topology (HV ~ 1000 V)
• timing properties (i.e. position resolution) vs. material properties/stripgeometry/operating parameters
• device integration of detector and on-chip electronics
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 24/27
High charge confining techniques
lat. coordinate
1. Proper combination of deep n- and p-implants
deepp-impl.
-400 -200 0 200 400lateral coordinate [um]
0.0
0.5
1.0
colle
cted
cha
rge
/ Q
t =3 sd µ
T=300 KQ=16000 el
(only p-type implants)exp. measurements – 60µm channels
deepn-impl.
deepp-impl.
deepn-impl.
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 25/27
Timing calibration by electron injectors
à test structures to be designed and studied to decide topology
• number of injectors per column to be defined (at least 2, bettermore)
• amount of charge injection depends on detector „pixel“ size
• interconnection: one bonding pad per row of injectors
• acquisition of additional „calibration images“ before/after bunchtrain (in the time gap) with very slow repetition rate
• intensity calibration ?
?x=200µm
?t=15.6ns
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 26/27
Detector, OCE & Analog ASIC - Time Scale
time
S+18m S+48m
Bread- board Module tested
End of Phase I 256x256 module
delivery
S+0m
LS
DD
-D
etec
tor
On
-ch
ipel
ectr
onic
sA
nal
og
AS
IC First prototypeof FE chip Second prototype of FE
chip - 64 channels
Final prototypes of FE chip 64 channels/chip
First prototype of LSDD-Detectorwith 8 channelsfully equipped
1.1 cm drift
length
1.28 cm drift length
(64 equivalent
pixels)
at least 32 channels
at least 32 channels
Final detector production: 256 x 256 pixels monolithic
64 equivalent
pixels
256 channels
1st detector production:
(64 + 64) equiv. pixels,
at least 32 channels
A.Castoldi - Rivelatori per EXFEL – CSN5 22/5/2007 Slide 27/27
Next steps
ü Valutazione delle proposte (XDAC 8/9 Maggio)• intensificare attivita’ R&D sul rivelatore/keypoints
(tempi di progetto e supporto da EXFEL limitati)
• Link the proposals to the science fields• Assign potential users to the detector projects• Start projects and • Develop real requirements
Grazie per la vostra attenzione