Rome Laboratory Reliability Engineers Toolkit

The Rome Laboratory

Reliability Engineer's

Toolkit

April 1993

ROME LABORATORY RELIABILITY

ENGINEER'S TOOLKIT

April 1993

An Application Oriented Guide for the

Practicing Reliability Engineer

Systems Reliability Division Rome Laboratory

Air Force Materiel Command (AFMC) 525 Brooks Rd.

Griffiss AFB, NY 13441-4505

QUICK REFERENCE

Qu ick R o t o r m e * AppBleatllora Entfox How Do I . . . ? • Understand the Principles of TQM 2

Understand Basic DoD R&M Policy and Procedures 7 Develop Quantitative Requirements

Reliability (R) 11 Maintainability (M) .................................. 17 Testability (T) 20

• Tailor R&M Task Requirements. 23 R&M Task Application/Priorities 25 Develop a Contract Data Requirements List 26

• Specify Information To Be Included in Proposals 28 Evaluate Contractor Proposals 31

• Specify Part Stress Derating 37 Determine the Limitations of Common Cooling Techniques 44 Understand Basic Parts Control 46

• Identify Key R&M&T Topics for Evaluation at Design Reviews 55 Evaluate Contactor's Method of Managing Critical Items 62 Understand Design Concerns Associated with Dormant Conditions......... 63 Understand Basic SMT Design Issues 66 Evaluate Power Supply Reliability 67 Determine Part Failure Modes and Mechanisms 69 Evaluate Fiber Optic Reliability 73

• Understand R&M&T Analysis Types and Purposes 77 Understand Reliability Prediction Methods 80 Understand Maintainability Prediction Methods.. 81 Understand Testability Analysis Methods 84 Evaluate a Reliability Prediction Report.. 85 Evaluate Existing Reliability Data 86 Evaluate a Maintainability/Testability Analysis Report 87 Evaluate a Failure Modes, Effects and Criticality Analyses Report 88

• Approximate the Reliability of Redundant Configurations 89 Perform a Quick (Parts Count) Reliability Prediction 92

• Adjust Reliability Data for Different Conditions 105 • Predict the Reliability of SMT Designs... 108

Understand Finite Element Analysis Application 113 Estimate IC Junction Temperatures for Common Cooling Techniques 115 Understand Sneak Circuit Analysis Application... 119

ROME LABORATORY RELIABILITY ENGINEER'S TOOLKIT

QUICK REFERENCE

• Estimate Reliability for Dormant Conditions 122 Estimate Software Reliability 124

• Develop an Environmental Stress Screening (ESS) Program 129 Select a Reliability Qualification Test 134

• Select a Maintainability Qualification Test 136 Select a Testability Demonstration Test 137 Evaluate a Failure Reporting and Corrective Action System 138 Evaluate a Reliability Demonstration Test Plan 140 Evaluate a Reliability Demonstration Test Procedure 144

• Evaluate a Maintainability Test Plan and Procedure 145 Participate in R&M Testing 146 Evaluate R&M Demonstration Test Reports 147 Understand Basic Design of Experiments Concepts 148 Understand Basic Accelerated Life Testing Concepts 153 Become Aware of Time Stress Measure Devices 159

For More Help Appendices How Do I . . . ? • Translate User Needs to R&M Requirements A-1

Develop SOW and Specification Requirements (Example) A-7 Become Aware of Available R&M Software Tools... A-17 Develop Design Guidelines (Example) A-23

• Select a MIL-HDBK-781 Test Plan A-37 • Calculate Confidence Intervals A 43 • Calculate the Probability of Failure Occurrence A 46

Understand Reliability Growth Testing A-51 • Select a MIL-STD-471 Test Plan A 61 • Find More R&M Data A-67

Find R&M Related Electronic Bulletin Boards A 72 • Obtain R&M Training A 75 • Obtain R&M Periodicals A 76

Become Aware of R&M Symposia and Workshops A-76 • Become Aware of R&M Specifications, Standards, Handbooks and

Rome Laboratory Technical Reports A-81 Understand Common Acronyms A-95


FOREWORD

FOREWORD

The original RADC (now Rome Laboratory) Reliability Engineers Toolkit. July 19s8, proved to be a best seller among military, industry ana academic reliability practitioners. Over 10.000 copies were distributed and the Toolkit and its authors received the 1989 Federal Laboratory Consortium Special Award for Excellence in Technology Transfer.

This updated version, completed in-house at the Systems Reliability Division, contains new topics on accelerated testing, thermal analysis, surface mount technology, design of experiments, hardware/software reliability, component failure modes/mechanisms, dormancy, and sneak analysis. Revisions and updates in most other areas were also made.

Tnis revision was led by a project team consisting of Bruce Dudley. Seymour Morris, Dan Richard and myself. We acknowledge the fine support we received from technical contributors Frank Born, Tim Donovan. Barry McKinney, George Lyne. Bill Bocchi. Gretcnen Bivens, Doug Holzhauer. Ed DePalma. Joe Caroli. Rich Hyle, Tom Fennell. Duane Gilmour, Joyce Jecen, JIM Ryan. Dr. Roy Stratton. Dr. Warren Debany, Dan Fayette, and Chuck Messenger. We also tnank typists Elaine Baker and Wendy Stoquert and the Reliability Analysis Center's Macintosh Wniz, Jeanne Croweii.

Your comments are always welcome. If you wish to throw bouquets, these people should receive them. If it s bricks you're heaving, aim them at Bruce, Seymour, or me at the address below.

^ Anthony J. Feduccia Rome Laboratory/ERS

525 Brooks Road Griffiss AFB, NY 13441-4505

ROME LABORATORY RELIABILITY ENGINEER'S TOOLKIT iii

TABLE OF CONTENTS

Table of Contents Introduction . 1

Requirements R1 Quantitative Reliability Requirements......... ....................... 11 R2 Quantitative Maintainability Requirements................. 17 R3 Quantitative Testability/Diagnostic Requirements 20 R4 Program Phase Terminology 23 R5 Reliability and Maintainability Task Application/Priorities 25 R6 Contract Data Requirements .............. 26 R7 R&M Information for Proposals........................................... 28

Source Selection S1 Proposal Evaluation for Reliability and Maintainability... 31

Design D1 Part Stress Derating 37 D2 Thermal Design 44 D3 Parts Control 46 D4 Review Questions 55 D5 Critical Item Checklist 62 D6 Dormancy Design Control 63 D7 Surface Mount Technology (SMT) Design 66 D8 Power Supply Design Checklist 67 D9 Part Failure Modes and Mechanisms 69

D10 Fiber Optic Design Criteria 73

Analysis A1 Reliability and Maintainability Analyses 77 A2 Reliability Prediction Methods 80 A3 Maintainability Prediction Methods 81 A4 Testability Analysis Methods 84 A5 Reliability Analysis Checklist 85 A6 Use of Existing Reliability Data 86 A7 Maintainability/Testability Analysis Checklist 87 A8 FMECA Analysis Checklist 88 A9 Redundancy Equations 89

A10 Parts Count Reliability Prediction 92 A11 Reliability Adjustment Factors 105 A12 SMT Assessment Model 108 A13 Finite Element Analysis 113 A14 Common Thermal Analysis Procedures 115 A15 Sneak Circuit Analysis 119 A16 Dormant Analysis 122 A17 Software Reliability Prediction and Growth 124

ROME LABORATORY RELIABILITY ENGINEER'S TOOLKIT v

TABLE OF CONTENTS

Testing T1 ESS Process 129 12 ESS Placement 130 T3 Typical ESS Profile 131 14 RGT and RQT Application 133 T5 Reliability Demonstration Plan Selection 134 16 Maintainability Demonstration Plan Selection 136 T7 Testability Demonstration Plan Selection 137 18 FRACAS (Failure Reporting and Corrective Action System)........ 138 19 Reliability Demonstration Test Plan Checklist 140

T10 Reliability Test Procedure Checklist 144 T11 Maintainability Demonstration Plan and Procedure Checklist 145 T12 Reliability and Maintainability Test Participation Criteria 146 T13 Reliability and Maintainability Demonstration Reports Checklist.. 147 T14 Design of Experiments.... 148 T15 Accelerated Life Testing 153 T16 Time Stress Measurement 159

Appendices 1 Operational Parameter Translation A 1 2 Example R&M Requirement Paragraphs A 7 3 R&M Software Tools... A-17 4 Example Design Guidelines A 23 5 Reliability Demonstration Testing A 37 6 Reliability Growth Testing A-51 7 Maintainability/Testability Demonstration Testing. A-59 8 Reliability and Maintainability Data Sources A-65 9 Reliability and Maintainability Education Sources A-73

10 R&M Specifications. Standards. Handbooks and Rome Laboratory Technical Reports A-79

11 Acronyms A-95


INTRODUCTION

Introduction Purpose This Toolkit is intended for use by a practicing reliability and maintainability (R&M) engineer. Emphasis is placed on his or her role in the various R&M activities of an electronic systems development program. The Toolkit is not intended to be a complete tutorial or technical treatment of the R&M discipline but rather a compendium of useful R&M reference information to be used in everyday practice.

Format The format of the Toolkit has been designed for easy reference. Five main sections are laid out to follow the normal time sequence of a military development program.

Descriptions of the "how to" of the R&M engineer's activities have been designed to take the form of figures, tables, and step-by-step procedures as opposed to paragraphs of text. Appendices are included to give a greater depth of technical coverage to some of the topics as well as to present additional useful reference information.

The Toolkit also includes a "Quick Reference Application Index" which can be used to quickly refer the R&M engineer to the portion of a section that answers specific questions. A quick reference "For More Help Appendices" index is also included for the more in-depth topics of the appendices.

Ordering information for the military documents and reports listed in the Toolkit is located in Appendix 10.

Terminology The term Reliability used in the title of this document is used m the broad sense to include the field of maintainability. The content of the report addresses reliability and mamtamab lity (R&M) because they are usually trie responsibility of one government individual in a military electronics development program. In this context testability is considered as a part of maintainability and is, therefore, inherently part of the M of R&M Where testability issues, such as development of quantitative requirements, are appropriate for separation from "M" discussion, they are and haê been labeled accordingly

Underlying Philosophy The development and application of a successful reliability program requires a number of tasks and coordination steps. Key ingredients include:

Aggressive Program Manager Support • Thorough Technical Reviews • Firm and Realistic Requirements • Complete Verification • Effective Built-in-Test • Parts Control • Failure Reporting & Corrective Action

ROME LABORATORY RELIABILITY ENGINEER'S TOOLKIT 1

INTRODUCTION

Total Quality Management Total Quality Management (TQM) is an approach which puts quality first as the means to long-term survival and growth. It employs teamwork to improve the processes used by an organization in providing products and services. One could argue that TQM encompasses Reliability Engineering or that Reliability Engineering encompasses many TQM activities. Either way, the reliability engineer may well get involved in TQM. For example, he/she may be asked to evaluate a contractor's TQM approach, assist process improvement teams with statistical analyses, or serve as a member of a process improvement team looking at his/her own agency's processes. It, therefore, behooves the reliability professional to have some knowledge of TQM.

Principles of TQM Management Leadership: For successful TQM, the company management must create a cultural change from authoritarian management focused on short-term goals to using the full potential of all employees for long-term benefit. This means the agency executives must be consistent, persistent and personally involved in the pursuit of quality.

Focus on Customer: It is easy to appreciate the need to focus on the external customer. Less obvious is the concept of internal customer satisfaction. Reliability engineering, for example, may be asked by Design Engineering (the customer) to review a proposed design for reliability. If an incomplete or shoddy evaluation is done, the ultimate design may not meet specifications. Output suffers and so does the efficiency of the project team. A TQM oriented organization seeks to understand and delight its customers, both external and internal.

• Constant Improvement: It is estimated that about 25% of operating costs of a typical manufacturing agency go for rework and scrap. Service organizations pay an even higher penalty for not doing things right the first time. Reducing these costs is a potential source of vast profit. Hence, TQM agencies seek to constantly improve their processes. The usual change agent is a team with members from all offices involved in the process, and including those who actually perform the work. Besides the measurable benefits, process improvements mean fewer defects going to customers, with an unmeasurable but significant effect on the bottom line.

Use of Measurements and Data: TQM agencies seek to measure quality so that improvements can be tracked. Every process will have some operational definition of quality. The overall agency progress can be measured by calculating the "cost of quality" (money spent for preventing defects, appraising quality, rework and scrap). Typically, as more money is spent on preventing defects, savings made in scrap and rework reduce the overall cost of quality. Another common approach is to score the agency using the criteria for the Malcolm Baldrige National Quality Award as a measure. For Government agencies, the scoring criteria for the Office of

2 ROME LABORATORY RELIABILITY ENGINEER'S TOOLKIT

INTRODUCTION

Management and Budget (OMB) Quality improvement Prototype Award is used in lieu of the Malcolm Baldrige criteria. R&M engineers should use Statistical Process Control, Statistical Design of Experiments, Quality Function Deployment, Taguchi Methods, and other available quality tools. Design of Experiments is explained in Topic T14. Statistical Process Control techniques are described in this topic.

Employee Involvement: A TQM agency recognizes the value of a skilled work force cooperating to satisfy the customer. Extensive education and training programs exist. Training in job skills, quality methods, and team building techniques is widely available. Cooperation between offices is the norm (e.g. concurrent engineering). Employees on all levels are widely involved In process Improvement teams. Management looks for ways of reducing the hassle created by bureaucratic rules and regulations. Employees are trusted and empowered to do their jobs.

Results: In a TQM agency, Improvement is continuous and measured. Image building measurements like the number of Improvement teams formed, are of less value than measures of cost of quality or increase in production which show real results. Management is not concerned with filling squares, but with making worthwhile changes.

TQM Tools

Process Flow Chart: A diagram showing all the major steps of a process. The diagram also shows how the various steps in the process relate to each other.

Input ^ Process Output _

i i Process

Feedback

Process Flow Chart


INTRODUCTION

Pareto Chart: A bar graph of identified causes shown in descending order of frequency used to prioritize problems and/or data. The Pareto Principle states that a few causes typically account for most problems (20% of the serial numbered units account for 80% of the failures: 20% of the people do 80% of the work: etc.) Pareto diagrams help analyze operational data and determine modes of failure. They are especially useful when plotted before and after an improvement project or redesign to show what progress has been made.

100%

& c 0) = 50% Q>

0

Fishbone Chart: A cause and effect diagram for analyzing problems and the factors that contribute to them, or, for analyzing the factors that result in a desired goal. Also called an Ishikawa Chart. This tool requires the listing of all possible factors contributing to a result and the subsequent detailed investigation of each factor. It is usually developed in brainstorming sessions with those that are familiar with the process in question.

Factors Temperature Redundancy

Open Short Stuck-At Failure Mode

Drift

Pareto Chart


INTRODUCTION

• Control Chart: A method of monitoring the output of a process or system through the sample measurement of a selected characteristic and the analysis of its performance over time. There are two main types: control charts for attributes (to plot percentages of "go/no go' attribute data) and control charts for variables (to plot measurements of a variable characteristic such as size or weight). Control charts identify changes in a process as indicated by drift, a shift in the average value, or. increased variability. The upper and lower control limits are based on the sample mean (x), sample standard deviation (s) and the sample size (n)

Shewhart Cycle A method created Dy Walter A Shewhart, for attacking problems.

The cycle starts with the planning phase: defining the particular problem, deciding what data are needed and determining how to obtain the data; that is via test, previous history, external sources, etc. The process flow charts and Ishikawa diagrams are very useful at this point.


INTRODUCTION

After planning It Is necessary to do something (D on the chart); Getting the data needed, running a test, making a change, or, whatever the plan calls for.

The next step, C on the chart, is to check the results. In some Instances, this would be done by a control chart. In any event the results are evaluated and causes of variation Investigated. Histograms, Pareto Charts and Scattergrams can be helpful.

The last step, A, stands for Analyze and Act. What did the data in step C Indicate? Based on the analysis, appropriate action Is taken. This could be a process change or a decision that a new plan Is needed. In any event, after you act, you go back to P and start another cycle. Even If the first trip around worked wonders, there are always more opportunities waiting to be discovered. The cycle Is really a spiral going upward to better and better quality.

Reliability TQM Tasks Many corporations have considered or utilized TQM principles. The reliability tasks most frequently used In producing a quality product are assembled in the following Pareto chart:

100%'

% of Corporations

Using

90%

Failure Reporting &

Corrective Action

(FRACAS)

75%

Test Analyze &

Fix

(TAAFJ

65%

Program. Reviews

50%

Parts Control

40%

Part Derating

30%

Failure Mode &

Effects (FMECA)

Tasks

Pareto Chart


INTRODUCTION

Department of Defense R&M Policy and Procedures Department of Defense (DoD) Directive 5000.1, Defense Acquisition (23 Feb 91), establishes management policies and procedures for acquiring systems which satisfy all aspects of user operational needs. It Is based on the principles contained In the Defense Management Report to the President (prepared by the Secretary of Defense, Jul 89). DoD Directive 5000.1 cancels 63 other DoD directives and policy memorandum, and replaces them with a single reference; DoD Instruction 5000.2, Defense Acquisition Policies and Procedures (23 Feb 91). The following R&M related documents are Included In these cancellations: (1) DoD Instruction 3235.1, "Test and Evaluation of System Reliability, Availability and Maintainability", 1 Feb 82, (2) DoD Instruction 4120.19, "DoD Parts Control Program", 6 Jul 89. and (3) DoD Directive 5000.40, "Reliability and Maintainability", 8 Jul 80.

DoD Instruction 5000.2 establishes an Integrated framework for translating broadly stated mission needs into an affordable acquisition program that meets those needs. It defines an event oriented management process that emphasizes acquisition planning, understanding of user needs and risk management. St Is several hundred pages Song and has 16 separate parts covering everything from Requirements Evolution and Affordability to the Defense Acquisition Board Process. Part 6, Engineering and Manufacturing, Subsection C, Reliability and Maintainability, establishes DoD R&M policy. The basic R&M policies and procedures described in this seven page section can be summarized as follows:

Policies Understand user needs and requirements.

Actively manage all contributors to system unreliability.

Prevent design deficiencies and the use of unsuitable parts.

Develop robust systems insensitive to use environments.

Procedures

Define both mission and logistics R&M objectives based on operational requirements and translate them into quantitative contractual requirements.

Perform R&M allocations, predictions, and design analysis as part of an iterative process to continually improve the design.

Establish parts selection and component derating guidelines.

Preserve reliability during manufacturing through an aggressive environmental stress screening program.

Establish a failure reporting and corrective action system.


INTRODUCTION

8 ROME LABORATORY RELIABILITY TOOLKIT

Section R R e q u i r e m e n t s

Contents

R1 Quantitative Reliability Requirements 11

R2 Quantitative Maintainability Requirements 17

R3 Quantitative Testability/Diagnostic

Requirements 20

R4 Program Phase Terminology 23

R5 R&M Task Application/Priorities 25

R6 Contract Data Requirements 26

R7 R&M Information for Proposals 28

R e l a t e d T o p i c s

Appendix 2 Example R&M Requirements Paragraphs A-7


Requir^rnem development is c\Mosi to program succcss, Miift&y sranr'arcis (:Vs5L-STDs) cannot be bBncJIy applied. Requirements be faîred to f.Sie [ndsvlfiiiat program situation considering She following:

° Opersibna! Environment

Other Contract Provisions (Incerrtivee, warranties, mo.) Off-The-Sheff Versus I D s s f g n - e d Hardware-

For More Information MIL-STD-470 "Maintainability Program for Systems and Equipment"

"Definition of Terms for Reliability and Maintainability" MIL-STD-721

MIL-STD-785

MIL-STD-2165

DODD 5000.1

DODI 5000.2

RADC-TR-89-45

"Reliability Program for Systems and Equipment Development and Production"

"Testability Programs for Electronic Systems and Equipment"

"Defense Acquistion"

"Defense Acquisition Management Policies and Procedures"

"A Government Program Manager's Testability/Diagnostic Guide"

RADC-TR-90-31 "A Contractor Program Manager's Testability Diagnostic Guide"

RADC-TR-90-239 "Testability/Diagnostics Design Encyclopedia"

RL-TR-91 -200 "Automated Testability Decision Tool"


REQUIREMENTS - TOPIC Ftf

I @ p i © Ri l * Q y a i r e S M w ® Migi tooBof^

Scope of Requirements Reliability parameters expressed by operational users and ones specified In contractual documents take many forms. Tables R1-1 and R1-2 Identify the characteristics of reliability parameters.

Table R1-1: Logistics (Basic) and Mission Reliability Characteristics Logistics (Basic) Reliability Mission Reliability

Measure of system's ability to Measure of system's ability to operate without logistics support complete mission

Recognize effects of all Consider only failures that occurrences that demand support cause mission abort without regard to effect on mission

Degraded by redundancy Improved by redundancy

Usually equal to or lower than Usually higher than logistics mission reliability reliability

Table R1-2: Operational and Contractual Reliability Characteristics Contractual Reliability Operational Reliability

Used to define, measure and Used to describe reliability evaluate contractor's program performance when operated

in planned environment Derived from operational needs

in planned environment

Not used for contract reliability • Selected such that achieving them requirements (requires

allows projected satisfaction of translation) operational reliability

translation)

Used to describe needed level Expressed in inherent values of reliability performance

Account only for failure events Include combined effects of subject to contractor control item design, quality,

installation environment, Include only design and maintenance policy, repair, manufacturing characteristics etc.



Contractual Reliability Operational Reliability • Typical terms

MTBF(mean-time-between-failures) • Typical terms

MTBM (mean-time-between-mainte nance)

Mission MTBF (sometimes also ualled MTBCF, MTBD (mean-time-between

demand)

MTBR (mean-time-between removal)

MTBCF (mean-time-between-critical-failure)

Operational Constraints Mission Criticality Availability Constraints Self-Sufficiency Constraints Attended/Unattended Operation Operational Environment

Use of Off-the-shelf or Newly Designed Equipment

How to Develop Requirements Figure R1-1 defines the general reliability requirement development process. Key points to recognize from this process are:

1. User requirements can be expressed in a variety of forms that include combinations of mission and logistics reliability, or they may combine reliability with maintainability in the form of availability Conversion to commonly used operational terms such as mean-time-between maintenance (MTBM) and mean-time-between-critical-failure (MTBCF) must be made from terms such as operational availability (Aq) and break-rate, etc to enable translation to parameters which can be specified in contracts.

An example is:

A MTBM 0 - MTBM + MDT

(Solve for MTBM using mean downtime (MDT) which includes the actual repair time plus logistics delay time.)



2. Since operational reliability measures take into account factors beyond the control of development contractors, they must be translated to contractual reliability terms for which contractors can be held accountable. (Appendix 1 provides one means of accomplishing this translation.)

3. The process cannot end with tne translation to a contractual value. Evaluation of the realism of the translated requirements is a necessary step. Questions that have to be answered are: are the requirements compatible with the available technology and do the requirements unnecessarily drive the design (conflict with system constraints such as weight and power). Addressing these issues requires reviewing previous studies and data for similar systems. Adjustment factors may be appropriate for improvement of technology and for different operating environments, duty cycles, etc. See Topic A11 for Reliability Adjustment Factors.

4. Systems with mission critical requirements expressed by the user present difficulties in the requirement development process. Translation models don't account for the nonexponential situations that exist with redundant systems. Because the reliabilities oi redundant paths are high compared to serial ones, an approximation can DO made that these paths have an equivalent failure rate ot zero so that only the remaining serial elements need to be translated.

5. The requirement process involves allocation of values to lower levels. In some cases, this is an iterative process requiring several tries to satisfy all requirements. For otner cases, the requirements cam be satisfied and dialogue and tradeoffs with the user are required.

6. For cases where user needs are not specified it still makes sense to invoke at least a logistics (basic) reliability requirement. In so doing, the contractor has a degree of accountability and is likely to put more effort into designing a reliable system.

7. Table R1-3 indicates typical ranges of MTBF for different types of electronic systems.



Table R1-3: Typical MTBF Values

Radar Systems MTBF (Hours) Ground Rotating Search Radar 100-200 Large Fixed Phase Array Radar 5-10 Tactical Ground Mobile Radar 50-100 Airborne Fighter Fire Control Radar 50-200 Airborne Search Radar 300-500 Airborne Identification Radar 200-2,000 Airborne Navigation Radar.. 300-4,500

Communications Equipment MTBF (Hours) Ground Radio 5,000-20,000 Portable Ground Radio 1,000-3,000 Airborne Radio 500-10,000 Ground Jammer 500-2,000

Ground Computer Equipment MTBF (Hours) Workstation 2,000-4,500 Personal Computer (CPU) 286/386/486 1,000-5,000 Monochrome Display 10,000-15,000 Color Display 5,000-10,000 40-100 Megabyte Hard Disk Drive 10,000-20,000 Floppy Disk/Drive 12,000-30,000 Tape Drive 7,500-12,000 CD/ROM 10,000-20,000 Keyboard 30,000-60,000 Dot Matrix, Low Speed, Printer 2,000-4,000 Impact, High Speed, Printer 3,000-12,000 Thermal Printer 10,000-20,000 Plotter 30,000-40,000 Modem 20,000-30,000 Mouse 50,000-200,000 Clock 150,000-200,000

Miscellaneous Equipment MTBF (Hours) Airborne Countermeasures System 50-300 Airborne Power Supply 2,000-20,000 Ground Power Supply 10,000-50,000 IEEE Bus 50,000-100,000 Ethernet 35,000-50,000



Figure R1-1: Quantitative Reliability Requirement Development Process



Figure R1-1 Notes: 1. User Needs Cases

Case Logistics Reliability Mission Reliability Comments

1 Specified Specified

2 Specified Not specified Delete steps D, H, I

3 Not specified Specified

4 Not specified Not specified Delete steps D, H, I

2. A 10-20% reliability improvement factor is reasonable for advancement of technology.

3. Adjustment of data to use environment may be required (see Topic A11) See Appendix 8 for R&M data sources

4. Reliability requirements necessitating redundancy ddd weight uost and power

5. Alternate forms of user requirements should be converted to MTBM's to u liable translation



Topic R2; Quantitative Maintainability Requirements Scope of Requirements Unique maintainability parameters need to be specified for three basic levels of repair:

• Organizational Level: Repair at the system location. Usually involves replacing plug-in modules and other items with relatively short isolation and replacement times.

Intermediate Level: Repair at an intermediate shop facility which has more extensive capabilities to repair lower hardware indenture levels.

• Depot Level: Highly specialized repair facility capable of making repairs at all hardware indenture levels. Sometimes the original equipment manufacturer.

Recent Air Force policy has promoted the concept of two level maintenance in place of the traditional three level system. Under this concept the classification is:

On-equipment: Maintenance actions accomplished on complete end items.

Off-equipment: In-shop maintenance actions performed on removed components.

Parameters which need to be specified vary with the level of repair being considered. Key maintainability parameters include:

Mean time to repair (MTTR): Average time required to bring system from a failed state to an operational state. Strictly design dependent. Assumes maintenance personnel and spares are on hand (i.e.. does not include logistics delay time). MTTR is used interchangeably with mean corrective maintenance time (Met).

Mean maintenance manhours (M-MMH): Total manpower per year (expressed in manhours) required to keep the system operating (not including logistics delay time).

• Mean time to restore system (MTTRS): The average time it takes to restore a system from a failed state to an operable state, including logistics delay time MTTRS = logistics delay time + MTTR). Logistics delay time includes all time to obtain spares and personnel to start the repair.

Preventive maintenance (PM): Time associated with the performance of all required preventive maintenance. Usually expressed in terms of hours per year.



Operational Constraints Basic maintainability requirements are determined through an analysis of user operational constraints. Operational constraints include:

Operating hours per unit calendar time and/or per mission

Downtime, maintenance time, or availability constraints

Mobility requirements

Atte nded/u natte nded operation

Self-sufficiency constraints

Reaction time

Operational environment (e.g., chemical, biological and nuclear)

Skill levels of maintenance personnel

Manning

• Types of diagnostics and maintenance support equipment which can be made available or implemented (built-in test, manual test equipment, external automatic test equipment, etc.).

Levels at which repair takes place

Use of off-the-shelf equipment versus newly designed equipment

How to Develop Requirements The best guidance available is to provide a range of typical values usually applied for each parameter.



Table R2-1: Typical Maintainability Values

Organizational intermediate Depot MTTR M-MMH MTTRS PM

.5-1.5 hr Note 1 1 - 8 Hrs (Note 2) 2 -15 hr/yr

.5 - 8 hr Note 1 NA NA

1 -4 hr Note 1 NA NA

Notes:

1. M-MMH depends on the number of repair visits to be made, the MTTR for each repair visit and the number of maintenance personnel required for each visit. Typical calculations of the mean maintenance manhours per year include:

a. Immediate maintenance of a continuously operated system: M-MMH = (8760 hr/yr)/(MTBF) x (MTTR) x (maintenance personnel per repair) + (PM hours per year) x (Maintenance personnel).

b. Delayed maintenance of a fault tolerant system: M-MMH = (number of expected repair visits) x (time for each visit) x (maintenance personnel per visit) + (PM hours per year) x (Maintenance personnel).

c. Maintenance of a continuously operated redundant system allowed to operate until failure. M-MMH = (8760 hr/yr)/(MTBCF) x (time for each visit) x (maintenance personnel per visit) + (PM hours per year) x (Maintenance personnel).

Time for each visit is the number of repairs to be made times the MTTR for each repair if repairs are made in series.

2. For unique systems that are highly redundant, MTTRS may be specified as the switch time.



Topic R3: Quantitative Testability/Diagnostic Requirements Scope of Requirements Testability/Diagnostics functions and parameters that apply to each repair level:

Fault Detection: A process which discovers the existence of faults.

Fault Isolation: Where a fault is known to exist, a process which identifies one or more replaceable units where the fault(s) may be located.

False Alarms: An indication of a fault where no fault exists such as operator error or Built-in Test (BIT) design deficiency.

Testability/Diagnostic requirements are sometimes expressed in the form of rates or fractions such as:

Fraction of Faults Detected (FFD): The quantity of faults detected by BIT or External Test Equipment (ETE) divided by the quantity of faults detected by all fault detection means (including manual).

System and Equipment Level - FFD is usually weighted by the measured or predicted failure rates of the faults or replaceable units.

Microcircuit Level - FFD is called fault coverage or fault detection coverage, and ail faults are weighted equally. In the fault-tolerant design community, "fault coverage" almost invariably refers to fault recovery coverage. This is usually expressed as the conditional probability that, given a fault has occurred and has been detected, the system will recover.

Fault Isolation Resolution (FIR): The probability that any detected fault can be isolated by BIT or ETE to an ambiguity group of size *x* or less. (Typically specified for several values of "x").

False Alarm Rate (FAR): The frequency of occurrence of false alarms.

Scope of Diagnostics Embedded: Defined as any portion of the weapon systems diagnostic capability that is an integral part of the prime system.

External: Any portion of the diagnostic capability that is not embedded.

Manual: Testing that requires the use of technical manuals, troubleshooting procedures, and general-purpose test equipment (e.g., voltmeter) by a maintenance technician.



• Test Program Set (TPS): The complete collection of data and hardware necessary to test a specmc Unit Under Test (UUT) on a specific Automatic Test Equipment (ATE). As a minimum, a TPS consists of:

- Test vector sets (for a digital UUT)

- Test application programs (software that executes on the ATE and applies the vectors under the necessary conditions)

Test fixtures and ATE configuration files

Documentation

A major element of external diagnostics involves the following:

• Automatic Test Equipment (ATE): The apparatus with which the actual UUT will be tested. ATE for digital UUTs has the capability to apply sequences of test vectors under specified timing, loading, and forcing conditions.

How to Develop Requirements In theory weapon system diagnostic requirements should be developed as an out-growth of the user developed mission and performance requirements contained in a Mission Need Statement (MNS) Operational Requirements Document (ORD) or similar type document.

The following should also be considered:

Diagnostic capability realistically achievable with the selected hardware technology and software complexity.

• Tradeoffs involving reliability, maintainability, logistics, weight, power requirements, and system interruption.



Table R3-1: Typical Testability Values

% Capability Repair Level Fault Detection (All Means) 90-100

100 100

Organizational Intermediate Depot

Fault Detection: BIT & ETE BIT & ETE BIT & ETE

90 98 95 98

95-100

Organizational Intermediate Depot

Fault Isolation Resolution Three or fewer LRUs One LRU Four or fewer SRUs One SRU

100 90-95

100 75-85

Organizational Organizational Intermediate Intermediate

Notes:

LRU - Line-Replaceable Unit (e.g., Box, Power Supply, etc.) SRU - Shop-Replaceable Unit (e.g., Circuit Card) BIT - Built-in-Test ETE - External Test Equipment



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Topic R8; Contract Data Requirements In order for the government to receive outputs from the required contractor performed tasks, the appropriate deliverables must be specified in the Contract Data Requirements List (CDRL). The content of these CDRL items is specified by reference to standard Data Item Descriptions. The timing and frequency of the required reports must be specified in the CDRL.

Table R6-1: Data Items & Delivery Dates

Title Recommended Delivery Date

Reliability DI-R-7079

DI-R-7080

DI-R-7083

DI-R-7085A

DI-R-7086

DI-R-7094

DI-R-7095

DI-R-7100

DI-RELI-80247

DI-RELI-80248

DI-RELI-80249

DI-RELI-80250

DI-RELI-80251

DI-RELI-80252

DI-RELI-80253

DI-RELI-80254

Reliability Program Plan

Reliability Status Report

Sneak Circuit Analysis Report

FMECA Report

FMECA Plan

Reliability Block Diagram & Math Model Report

Reliability Prediction & Documentation of Supporting Data

Reliability Report for Exploratory Development Models

Thermal Survey Report

Vibration Survey Report

Burn-in Test Report

Reliability Test Plan

Reliability Test Procedures

Reliability Test Report

Failed Item Analysis Report

Corrective Action Plan

90 days prior to PDR

90 days prior to PDR & bimonthly

30 days prior to PDR & CDR

30 days prior to CDR




30 days prior to end of contract

30 days prior to PDR & after testing

90 days prior to start of testing

60 days after end of testing




As required




DI-RELI-80255

DI-RELI-80685

DI-MISC-80071

Maintainability DI-MNTY-80822

DI-MNTY-80823

DI-MNTY-80824

DI-MNTY-80825

DI-MNTY-80826

DI-MNTY-80827

DI-MNTY-80828

DI-MNTY-80829

DI-MNTY-80830

DI-MNTY-80831

DI-MNTY-80832

Testability DI-R-7080 & DI-RELI-80255

DI-MNTY-80831 & 80832

DI-T-7198

DI-T-7199

Title Failure Summary & Analysis Report

Critical Item Control Plan

Part Approval Request

Maintainability Program Plan

Maintainability Status Report

Data Collection, Analysis & Corrective Action System Reports

Maintainability Modeling Report

Maintainability Allocations Report

Maintainability Predictions Report

Maintainability Analysis Report

Maintainability Design Criteria Plan

Inputs to the Detailed Maintenance Plan & Logistics Support

Maintainability Demonstration Test Plan

Maintainability Demonstration Report

Recommended Delivery Date

Start of testing, monthly


As Required


90 days prior to PDR & bimonthly As Required






As required



(See Reliability & Maintainability Data Item List)

(See Maintainability Data Item List)

Testability Program Plan 90 Days prior to PDR

Testability Analysis Report 30 days prior to PDR & CDR



Topic R7; R&M Information for Proposals PrgDosal preparation guidance should be provided in the request for proposal (RFP) package to guide the contractor in providing the information most needed to properly evaluate the R&M area during source selection. This is part of the requirements definition process.

Depending on the scope of the R&M requirements specified, information such as the following should be requested for inclusion in the proposal:

Preliminary R&M analysis/models and estimates of values to be achieved (to at least the line replaceable unit (LRU) level)

Design approach (including thermal design, parts derating, and parts control)

R&M organization and its role in the overall program

Key R&M personnel experience

Schedules for all R&M tasks

Description of R&M design guidelines/criteria to be used and trade studies and testing to be performed

Note:

It is critical that qualified R&M personnel take part in the actual evaluation of technical proposals. The R&M engineer should make sure this happens by agreement with program management.

28 ROME LABORATORY RELIABILITY E N G I N E E R ' S TOOLKIT

Contents

Proposal Evaluation for Reliability 31 and Maintainability


The criteria lor evaluation of contractor proposals has to match the requirements: specified In the Request lor Proposal (RFP). Contractors must be scored by: comparing their proposals to the criteria, not to each other. R&M are generally: evaluated as parts of the technical area. The total source selection process Includes other nontechnical areas, Air Force policy has emphasized the importance o? R8M Sn Vrte sovroe z&leafcn process.

For More Information

AFR 70-15 "Source Selection Policy and Procedures"

AFR 70-30 "Streamlined Source Selection Procedures"


SOURCE SELECTION - TOPIC S1

Topic SI: Proposal Evaluation for Reliability and Maintainability Understanding

Does the contractor show understanding of the importance of designing in R&M&T in the effort?

Does the contractor show a firm understanding of R&M&T techniques, methodology, and concepts?

Does the contractor indicate understanding of the role of testability/diagnostics on maintainability and maintenance?

Does the contractor understand integrated diagnostics design principles?

Does the contractor note similar successful R&M&T efforts?

Approach

Management Is an R&M&T manager identified, and are his/her experience and qualifications adequate in light of the scope of the overall program?

- Are the number and experience of R&M&T personnel assigned to the program, and the number of manhours adequate, judged in accordance with the scope of the overall program?

Does the R&M&T group have adequate stature and authority in the organizational framework of the program (e.g., they should not fall under direct control of the design group)?

Does the R&M&T group have an effective means of crosstalk and feedback of information between design engineers and higher management?

- Does the R&M&T manager have adequate control over R&M&T for subcontractors and vendors?

Is the testability diagnostics function integrated into the R&M program?

Does the contractor utilize concurrent engineering practices and is the R&M&T group represented on the team?

Design Are design standards, guidelines and criteria such as part derating, thermal design, modular construction, Environmental Stress Screening (ESS), and testability cited?



Is the contractor's failure reporting and corrective action system (FRACAS) a closed loop controlled process?

Is there a commitment to the required parts control program (e.g., MIL-M-38510, MIL-STD-883, etc.)? Are approval procedures described/ proposed for nonstandard parts?

Are system design reviews (internal and external) required regularly?

- Are tradeoff studies proposed for critical design areas?

- Is a time-phasing of R&M&T tasks provided along with key program milestones?

Are areas of R&M&T risk identified and discussed?

Does the contractor include consideration of software reliability?

Does the contractor describe his plan for testability/diagnostics design and the potential impacts on reliability and maintainability?

Does the contractor identify tools to be used to generate test vectors and other diagnostic procedures for BIT and ATE (automatic test equipment)?

Analysis/Test Are methods of analysis and math models presented?

Are the R&M&T prediction and allocation procedures described?

- Has the time phasing of the R&M&T testing been discussed, and is it consistent with the overall program schedule?

Is adequate time available for the test type required (such as maximum time for sequential test)?

Is the ESS program consistent with the requirements in terms of methodology and scheduling?

Does the contractor make a commitment to predict the design requirement MTBF prior to the start of testing?

Are the resources (test chambers, special equipment, etc.) needed to perform all required testing identified and, is a commitment made to their availability?



Compliance

• Design Does the contractor indicate compliance with all required military specifications for reliability, maintainability and testability?

Is adequate justification (models, preliminary estimates, data sources, etc.) provided to backup the claims of meeting R&M&T requirements?

Is there an explicit commitment to meet any ease of maintenance and preventive maintenance requirements?

Is there an explicit commitment to meet the Built-in-Test (BIT)/Fault-isolation Test (FIT) requirements (Fraction of Faults Detected (FFD), Fault Isolation Resolution (FIR) and False Alarm Rate (FAR))?

Is each equipment environmental limitation specified and do these conditions satisfy the system requirements?

Are all removable modules keyed?

Will derating requirements be adhered to and are methods of verifying derating requirements discussed?

• Analysis/Test Is a commitment made to perform a detailed thermal analysis?

Will the contractor comply with all R&M&T required analyses?

Is there an explicit commitment to perform all required environmental stress screening?

Does the contractor comply with all system level R&M&T test requirements? Will the contractor demonstrate the R&M&T figures of merit (MTBF, MTTR, FFD, FIR and FAR) using the specified accept/reject criteria?

Does the contractor comply with the specification (or other commonly specified) failure definitions?

Does the contractor agree to perform thermal verification tests and derating verification tests?

• Data Is there an explicit commitment to deliver and comply with all of the required R&M&T data items?


Section D Design

Contents

D1 Part Stress Derating 37

D2 Thermal Design 44

D3 Parts Control 46

D4 Review Questions 55

D5 Critical Item Checklist 62

D6 Dormancy Design Control 63

D7 Surface Mount Technology (SMT) Design 66

D8 Power Supply Design Checklist 67

D9 Part Failure Modes and Mechanisms 69

D10 Fiber Optic Design Criteria 73


• P H H H H i l i ^ H H H I I H H H I H H H H H l Proven design approaches critics! to system R&U success. For rnartyi programs the government requires that certain approaches be usee5 (sycli as &i larthuiiar tevcsfov part stress oerstinQ). Other prog^tr-G allow the contractor toi CQvekm arso uso his a-m design cntarfe as long ss his enc product design nrre te •ihe> government requirements "or is oubjea to provisions of product performance! agreements (guarsrtees, warranties, etc^ Regard^ss of >:!*«© sKusy/sot, the R&Mi engineer must acthmt/ evaSuate the* ooFnractcr cSsslgr? progress.


MIL-STD-883

MIL-STD-965

MIL-STD-1521

MIL-HDBK-251

MIL-HDBK-338

MIL-HDBK-97S

M I L - M - 3 8 5 1 0

MIL-S-19500

RADC-TR-82-172

RADC-TR-88-69

RADC-TR-88-110

RADC-TR-88-124

RL-TR-91-39

RL-TR-92-11

"Test Methods and Procedures for Microelectronics"

"Parts Control Program"

"Technical Reviews and Audits for Systems, Equipments, and Computer Software"

"Reliability/Design Thermal Applications"

"Electronic Reliability Design Handbook51

"NASA Parts Application Handbook"

"Microcircuits, General Specification for

"Semiconductor Devices, General Specification for"

"RADC Thermal Guide for Reliability Engineers"

"R/M/T Design for Fault Tolerance, Program Manager's

Guide"

"Reliability/Maintainability/Testability Design for Dormancy"

"Impact of Fiber Optics on System Reliability/Maintainability"

"Reliability Design for Fault Tolerant Power Supplies"

"Advanced Technology Component Derating" 36 ROME LABORATORY RELIABILITY ENGINEER'S TOOLKIT

DESIGN: - TOPIC P3

Topic D1: Part Stress Derating The practice of limiting electrical, thermal and mechanical stresses on parts to levels below their specified ratings is called derating. Sf a system is expected to be reliable, one of the major contributing factors must be a conservative design approach incorporating realistic derating of parts. Table D1-1 defines the key factors for determining the appropriate level of derating for the given system constraints. Table D1-2 indicates the specific derating factors for each part type.

Table D1-1: Part Derating Level Determination

Factors Score Reliability Challenge

• For proven design, achievable with standard parts/circuits

1

• For high reliability requirements, special design features needed

2

• For new design challenging the state-of-the-art, new concept

3

System Repair For easily accessible, quickly and economically repaired systems

1

For high repair cost, limited access, high skill levels required, very low downtimes allowable

2

For nonaccessible repair, or economically unjustifiable repairs

3

Safety For routine safety program, no expected problems 1 For potential system or equipment high cost damage 2 For potential jeopardization of life of personnel 3

Size, Weight For no significant design limitation, standard practices 1 For special design features needed, difficult requirements

2

For new concepts needed, severe design limitation 3

Life Cycle For economical repairs, no unusual spare part costs expected

1

For potentially high repair cost or unique cost spares 2 For systems that may require complete substitution 3

Instructions: Select score for each factor, sum and determine derating level or parameter

Derating Level Total Score I 11 - 15 II 7-10 III 6 or less


DESIGN: - TOPIC P3

Table D1-2: Part Derating Levels All of the percentages provided are of the rated value for the derating parameter, unless otherwise labeled. Temperature derating is from the maximum rated.

Derating Level Part Type Derating Parameter I II III Capacitors

Film, Mica, Glass DC Voltage 50% 60% 60% Film, Mica, Glass Temp from Max Limit 10°C 10°C 10°C

Ceramic DC Voltage 50% 60% 60% Temp from Max Limit 10°C 10°C 10°C

Electrolytic Aluminum DC Voltage 80% Temp from Max Limit - 20° C

Electrolytic Tantalum DC Voltage 50% 60% 60% Temp from Max Limit 20° C 20°C 20°C

Solid Tantalum DC Voltage 50% 60% 60% Max Operating Temp 85° C 85°C 85° C

Variable Piston DC Voltage 40% 50% 50% Temp from Max Limit 10°C 10 C 10°C

Variable Ceramic DC Voltage 30% 50% 50% Temp from Max Limit 10°C 10°C 10°C

Connectors

Voltage 50% 70% 70% . Current 50% 70% 70% Insert Temp from Max Limit 50°c 25°C 25°C

Diodes

• Signal/Switch Forward Current 50% 65% 75% (Axial Lead) Reverse Voltage 70% 70% 70%

Max Junction Temp 95° C 105°C 125°C

• Voltage Regulator Power Dissipation 50% 60% 70% Max Junction Temp 95° C 105°C 125°C

• Voltage Reference Max Junction Temp 95° C 105°C 125°C


DESIGN: - TOPIC P3

• Transient Suppressor Power Dissipation 50% 60% 70% Average Current 50% 65% 75% Max Junction Temp 95° C 105°C 125°C

• Microwave Power Dissipation 50% 60% 70% Reverse Voltage 70% 70% 70% Max Junction Temp 95° C 105°C " 125°C

• Light Emitting Diode Average Forward Current 50% 65% 75% (LED) Max Junction Temp 95°C 105°C 125°C

• Schottky/Positive Power Dissipation 50% 60% 70% Intrinsic Negative Reverse Voltage 70% 70% 70% (PIN) (Axial Lead) Max Junction Temp 95° C 105°C 125°C

• Power Rectifier Forward Current 50% 65% 75% Reverse Voltage 70% 70% 70% Max Junction Temp 95° C 105°C 125°C

Fiber Optics

• Cable Bend Radius 200% 200% 200% (% of Minimum Rated) Cable Tension 50% 50% 50% (% Rated Tensile Strength) Fiber Tension 20% 20% 20% (% Proof Test)

Inductors

• Pulse Transformers Operating Current 60% 60% 60% Dieiearic vonage 50% 50% 50% Temp from Max Hot Spot 40° C 25°C 15°C

• Coils Operating Current 60% 60% 60% Dielectric Voltage 50% 50% 50% Temp from Max Hot Spot 40° C 25°C 15°C

Lamps

• Incandescent Voltage 94% 94% 94%

• Neon Current 94% 94% 94%

Derating Parameter Derating Level

I 11 III

Max Junction Temp

50% 50% 95° C

50% 70% 95° C

50% 95°C

50% 70% 95° C

50% 70% 95° C

60% 65%

105°C

60% 70%

105°C

65% 105°C

60% 70%

105°C

65% 70%

105°C

70% 75%

125°C

70% 70%

125°C

75% 125°C

70% 70%

125°C

75% 70%

125°C

Fiber Optics

• Cable Bend Radius 200% 200% 200% (% of Minimum Rated) Cable Tension 50% 50% 50% (% Rated Tensile Strength) Fiber Tension 20% 20% 20% (% Proof Test)

Inductors

• Pulse Transformers

• Coils

Operating Current Dieiearic vonage Temp from Max Hot Spot

Operating Current Dielectric Voltage Temp from Max Hot Spot

60% 50% 40° C

60% 50% 40° C

60% 50% 25°C

60% 50% 25°C

60% 50% 15°C

60% 50% 15°C

Lamps

• Incandescent

• Neon

Voltage

Current

94%

94%

94%

94%

94%

94%


DESIGN: - TOPIC P3

Microcircuits: This derating criteria is based on available data and is limited to: 60,000 gates for digital devices, 10,000 transistors for linear devices, and 1 Mbit for memory devices. Microcircuits should not exceed supplier minimum or maximum rating for supply voltage, 125°C junction temperature (except GaAs), or supplier maximum.

Derating Levei Part Type Derating Parameter 1 11 111 Microcircuits • MOS Digital Supply Voltage +/-3% +/-5% +/-5%

Frequency (% of Max Spec) 80% 80% 80% Output Current 70% 75% 80% Fan Out 80% 80% 90% Max Junction Temp 80°C 110°C 125°C

• MOS Linear Supply Voltage +/-3% +/-5% +/-5% Input Voltage 60% 70% 70% Frequency (% of Max Spec) 80% 80% 80% Output Current 70% 75% 80% Fan Out 80% 80% 90% Max Junction Temp 85° C 110°C 125°C

• Bipolar Digital Supply Voltage +/-3% +/-5% +/-5% Frequency (% of Max Spec) 75% 80% 90% Output Current 70% 75% 80% Fan Out 70% 75% 80% Max Junction Temp 80° C 110°C 125°C

• Bipolar Linear Supply Voltage +/-3% +/-5% +/-5% Input Voltage 60% 70% 70% Frequency (% of Max Spec) 75% 80% 90% Output Current 70% 75% 80% Fan Out 70% 75% 80% Max Junction Temp 85° C 110°C 125°C

Microprocessors

Supply Voltage +/-3% +/-5% +/-5% Frequency (% of Max Spec) 80% 80% 80% Output Current 70% 75% 80% Fan Out 80% 80% 90% Max Junction Temp, 8-BIT 120°C 125°C 125°C Max Junction Temp, 16-BIT 90°C 125°C 125°C Max Junction Temp, 32-BIT 60°C 100°C 125°C


DESIGN: - TOPIC P3

• Bipolar Supply Voltage +/-3% +/- 5% +/-5% Frequency (% of Max Spec) 75% 80% 90% Output Current 70% 75% 80% Fan Out 70% 75% 80% Max Junction Temp, 8-BIT 80°C 110°C 125°C Max Junction Temp, 16-BIT 70°C 110°C 125°C Max Junction Temp, 32-BIT 60°C 100°C 125°C

Memory/PROM

• MOS Supply Voltage +/-3% +/-5% +/-5% Frequency (% of Max Spec) 80% 80% 90% Output Current 70% 75% 80% Max Junction Temp 125°C 125°C 125°C Max Write Cycles (EEPROM) 13,000 105,000 300,000

• Bipolar Fixed Supply Voltage +/-3% +/- 5% +/-5% Frequency (% of Max Spec) 80% 90% 95% Output Current 70% 75% 80% Max Junction Temp 125°C 125°C 125°C

Microcircuits, GaAs

• MMIC/Digital Max Channel Temp 90°C 125°C 150°C

Miscellaneous

• Circuit Breakers Current 75% 80% 80%

• Fuses Current 50% 50% 50%

Derating Parameter

MOS

Bipolar

Derating Level 1 11 11

+/-3% 75% 70% 70% 80°C 70°C 60°C

+/-5% 80% 75% 75%

110°C 110°C 100°C

Supply Voltage Frequency (% of Max Spec) Output Current Max Junction Temp Max Write Cycles (EEPROM)

Fixed Supply Voltage Frequency (% of Max Spec) Output Current Max Junction Temp

+/-3% 80% 70% 125°C 13,000

+/-5% 90% 80% 80%

125°C 125°C 125°C

+/-5% 80% 75%

125°C 105,000

+/-3% +/- 5% 80% 90% 70% 75% 125°C 125°C

+/-5% 90% 80%

125°C 300,000

+/-5% 95% 80%

125°C

Microcircuits, GaAs

• MMIC/Digital Max Channel Temp 90°C 125°C 150°C

Miscellaneous

• Circuit Breakers Current

• Fuses Current

75%

50%

80%

50%

80%

50%

Optoelectronic Devices

• Photo Transistor Max Junction Temp

Avalanche Photo Diode (APD)

Photo Diode, PIN (Positive Intrinsic Negative)

Max Junction Temp

Reverse Voltage Max Junction Temp

Injection Laser Diode Power Output Max Junction Temp

95°C 105°C 125°C

95°C 105°C 125°C

70% 70% 70% 95°C 105°C 125°C

50% 60% 70% 95°C 105°C 110°C


DESIGN: - TOPIC P3

Derating Level Part Type Derating Parameter I II 111 Relays

Resistive Load Current 50% 75% 75% Capacitive Load Current 50% 75% 75% Inductive Load Current 35% 40% 40% Contact Power 40% 50% 50% Temp from Max Limit 20° C 20°C 20° C

Resistors

• Composition Power Dissipation 50% 50% 50% Temp from Max Limit 30°C 30°C 30°C

• Film Power Dissipation 50% 50% 50% Temp from Max Limit 40°C 40°C 40°C

• Variable Power Dissipation 50% 50% 50% Temp from Max Limit 45°C 35°C 35°C

• Thermistor Power Dissipation 50% 50% 50% Temp from Max Limit 20°C 20°C 20°C

• Wirewound Accurate Power Dissipation 50% 50% 50% Temp from Max Limit 10°C 10°C 10°C

• Wirewound Power Power Dissipation 50% 50% 50% Temp from Max Limit 125°C 125°C 12MC

• Thick/Thin Film Power 50% 50% 50% Voltage 75% 75% 75% Max Operating Temp 80°C 80°C 80°C

Transistors (Power)

• Silicon Bipolar Power Dissipation 50% 60% 70% Vce, Collector-Emitter 70% 75% 80% Voltage lc, Collector Current 60% 65% 70% Breakdown Voltage 65% 85% 90% Max Junction Temp 95°C 125°C 135°C

• GaAs MESFET Power Dissipation 50% 60% 70% Breakdown Voltage 60% 70% 70% Max Channel Temp 85°C 100°C 125°C

• Silicon MOSFET Power Dissipation 50% 65% 75% Breakdown Voltage 60% 70% 75% Max Junction Temp 95°C 120°C 140°C


DESIGN: - TOPIC P3

Derating Level Part Type Derating Parameter I II III Transistors (RF Pulse)

• Silicon Bipolar Power Dissipation 50% 60% 70% • Silicon Bipolar Vce, Collector-Emitter 70% 70% 70% Voltage lc, Collector Current 60% 60% 60% Breakdown Voltage 65% 85% 90% Max Junction Temp 95° C 125°C 135°C

• GaAs MESFET Power Dissipation 50% 60% 70% Breakdown Voltage 60% 70% 70% Max Channel Temp 85° C 100°C 125°C

Transistors (Thyristors)

• SCR & TRIAC On-State Current 50% 70% 70% Off-State Voltage 70% 70% 70% Max Junction Temp 95° C 105°C 125°C

Tubes

Power Output 80% 80% 80% Power Reflected 50% 50% 50% Duty Cycle 75% 75% 75%

Rotating Devices

Bearing Load 75% 90% 90% Temp from Max Limit 40° C 25° C 15°C

Surface Acoustic Wave Device (SAW)

Input Power from Max Limit 13dBm 13dBm 13dBm (Freq > 500 MHz) Input Power from Max Limit 18dBm 18dBm 18dBm (Freq < 500 MHz) Operating Temperature 125°C 125°C 125°C

Switches

Resistive Load Current 50% 75% 75% Capacitive Load Current 50% 75% 75% Inductive Load Current 35% 40% 40% Contact Power 40% 50% 50%


DESIGN: - TOPIC P3

Topic D2: Thermal Design One of the Important variables In system reliability Is temperature. Therefore, the thermal design of a system must be planned and evaluated. Full discussion of this topic Is beyond the scope of this document but it Is Important to point out to a reliability engineer what limitations there are for common thermal design approaches. Table D2-1 summarizes fundamental thermal design Issues which should be addressed during system development. Table D2-2 summarizes the most common cooling techniques for electronics and their limitations. Analysis Topic A14 provides a basic method of estimating microcircuit junction temperatures for these cooling techniques.

Table D2-1: Thermal Design Issues

Issue Concern

• Thermal Requirements: Has a thermal analysis requirement been incorporated into the system specification?

• Cooling Allocation: Has cooling been allocated down to each subsystem, box and LRU.

• Preliminary Thermal Analysis: Has a preliminary analysis been performed using the manufacturer's specifications for power outputs?

• Detailed Thermal Analysis: Has a detailed analysis been performed using actual power dissipations?

• Thermal Analysis Assumptions: Have junction-to-case thermal resistance values been fully justified?

Does the thermal analysis make use of junction-to-ambient thermal resistances?

Are all modes and paths of heat transfer considered in the analysis?

If not specified, a formal analysis probably will not be performed and there will be no possibility of independent review.

Cooling allocations should be made to the box level (or below) and refined as the thermal design matures.

This usually represents the worst case because manufacturers specify maximum power dissipations.

The preliminary analysis needs to be refined using actual power dissipations. Results need to feed into reliability predictions and derating analysis.

Optimistic values can have a significant effect on results. Thermal resistances from MIL-M-38510 should be used unless other values are justified.

Junction-to-ambient values should not be used since they are highly dependent on coolant flow conditions.

The three modes are convection, conduction, and radiation. Rationale should be provided for omitting any heat transfer modes or paths.


DESIGN: - TOPIC P3

Table D2-2: Cooling Technique Limitations Cooling Technique Maximum Cooling

Capacity Description

Impingement

Free Convection Circuit Cards

Well Ventilated Box

Poorly Ventilated Box

Forced Air Circuit Cards

Box

Coldwall

.5 W/in2

300 W/ft3

100W/ft3

2 W/in2

1000 W/ft3

1 W/in2

Flow-Through 2 W/in2

HEAT EXCHANGE

Example: A 9" x 5" printed circuit board using free convection cooling would be limited to about 22.5 watts.


DESIGN: - TOPIC P3

Topic D3; Parts Control Managing a parts control program Is a highly specialized activity and does not typically fall under the system's R&M engineer's responsibility. However, because of the Interrelationship of parts control and good system reliability, It Is Important that R&M engineers and program managers have a general understanding of the parts control discipline. Parts control questions which are often asked include:

• Why do parts control?

• What are the various "tools" to accomplish parts control?

- What is a military specification "Mil-Spec" qualified part, a M1L-SID-883 part, a Standard Military Drawing (SMD) part, and a vendor equivalent part?

Why do parts control? Since the invention of semiconductors, users could never be sure that a device purchased from one manufacturer would be an exact replacement for the same device obtained from another supplier. Major differences in device processing and electrical testing existed among suppliers. Because of the importance of semiconductors to military programs, the government introduced standard methods of testing and screening devices in 1968. Devices which were tested and screened to these methods were then placed on a government approval list called the qualified parts list (QPL). Through this screening and testing process, a part with known quality and performance characteristics is produced. The philosophy for assuring quality product has evolved since 1968 and now there are two methodologies in place, the original QPL program and the new Qualified Manufacturer's List (QML) program (established 1985). The QML approach defines a procedure that certifies and qualifies the manufacturing processes and materials of potential vendors as opposed to the individual qualification of devices (QPL). Hence, all devices produced and tested using the QML certified/qualified technology flow are qualified products. Part's technology flows qualified to this system are listed on the Qualified Manufacturer's List. Both Hybrids as well as monolithic microcircuits are covered under this system.

What are the various "tools" to accomplish parts control? The government has subdivided parts into three basic classifications: (1) microelectronics, (2) semiconductors (e.g. transistors, diodes, etc.) and (3) electrical parts (e.g. switches, connectors, capacitors, resistors, etc.). For each class, part specification and test method documents have been developed. Table D3-1 summarizes key documents and their content.

What is a military specification "Mil-Spec" qualified part, a MIL-STD-883 part, a Standard Military Drawing (SMD) part, and a vendor equivalent part? The primary difference in these descriptions is that each of these part classes has undergone different levels of screening and certification. Certification involves specifying and documenting the part manufacturing process. If also involves government and manufacturer agreement on a detailed part specification. This ensures consistent part quality and known performance. Table D3-2 summarizes


DESIGN: - TOPIC P3

common classes of parts and what these classifications signify. Table D3-3 summarizes MIL-STD-883D screening procedures and is included to give the reader a feel for the wide range of tests required. These screening requirements are similar for the respective systems defined in Table D3-2. Topic A11, Table A11-1 shows the impact of the various part designations on system reliability.

Table D3-1: Key Parts Control Documents and Their Content

Document Title Content

MIL-M-38510 General Specification for Microcircuits

MIL-l-38535 General Specification for Integrated Circuits (Microcircuits) Manufacturing

Provides detailed specification requirements in the form of "slash sheets" for several hundred of the most commonly used microcircuits. Covers screening requirements (referenced to MIL-STD-883), electrical testing, quality conformance, physical dimensions, configuration control for critical manufacturing processing steps and production line certification.

Provides detailed specification requirements in the form of standard military drawings (SMDs). Quality assurance requirements are defined for all microcircuits built on a manufacturing line which is controlled through a manufacturer's quality manage-ment program and has been certified and qualified in accordance with the require-ments specified. The manufacturing line must be a stable process flow for all microcircuits. Two levels of product assurance (including radiation hardness assurance) are provided for in this specification, avionics and space. The certification and qualification sections specified outline the requirements to be met by a manufacturer to be listed on a Qualified Manufacturer's List (QML). After listing of a technology flow on a QML, the manufacturer must continually meet or improve the established baseline of certified and qualified procedures through his quality management program and the technology review board.


DESIGN: - TOPIC P3

Document Title Content

MIL-H-38534 General Specification for Hybrid Microcircuits

MIL-STD-883 Test Methods and Procedures for Microelectronics

MIL-S-19500 General Specification for Semiconductors

Provides detailed specification requirements in the form of Standard Military Drawings (SMDs) for standard hybrid products, and Source Control Drawings (SCDs) using the SMD boilerplate for custom hybrids. Covers requirements for screening (referenced to MIL-STD-883) quality conformance inspections, configuration control, rework limitations and manufacturing line certification procedures.

Provides uniform methods and procedures for testing microelectronic devices. Structured into five classes of test methods: 1000 class addresses environmental tests, 2000 class addresses mechanical tests, 3000 class addresses electrical tests for digital circuits, 4000 class addresses electrical tests for linear circuits, and 5000 class addresses test procedures. The tests covered include moisture resistance, seal test, neutron irradiation, shock and acceleration tests, dimensional tests, input/output current tests, and screening test procedures to name a few. Two test levels are described: Class B (Class H, MIL-H-38534/Class Q, MIL-l-38535) and Class S (Class K, MIL-H-38534/Class V, MIL-l-38535). Class S is geared toward space qualified parts and requires a host of tests not performed on Class B parts (e.g. wafer lot acceptance, 100% nondestructive bond pull, particle impact noise detection, serialization, etc.).

Provides detailed specification sheets establishing general and specific requirements including electrical characteristics, mechanical characteristics, qualification requirements, inspection procedures and test methods.


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DESIGN: - TOPIC P3

Table D3-2: Microelectronics Classifications and Descriptions

Part Classification Part Classification Description

JAN or MIL-M-38510 Parts These parts have a detailed specification (slash sheet) in MIL-M-38510 which controls all mechanical, electrical, and functional parameters of the part. Additionally, the manufacturing process flow is certified by DoD's Defense Electronics Supply Center (DESC), the devices are screened to MIL-STD-883 test method requirements, and are subjected to rigorous quality conformance testing. A manufacturer, once certified by DESC, can then qualify products to the specification and have these products listed on the qualified products list. The product specification (performance and mechanical) is contained in a M38510/0000 "slash sheet" or one part number SMD. Standardization is achieved through many manufacturers building product to the same "one part SMD" or "slash sheet" and testing them using the standard test methods found in MIL-STD-883.

QML (Qualified Manufacturers Listing) Device performance requirements (electrical, or MIL-l-38535 Parts thermal, and mechanical) are detailed in the

Standard Military Drawing (SMD). The qualifying activity or its agent certifies and qualifies the manufacturers process flows. Once certified and qualified, the manufacturer may produce multiple device types on that flow as MIL-l-38535 compliant parts. Since the process is considered qualified, individual products do not have to be qualified individually for selected quality conformance inspections, except Class V (Space) product. Where standard tests are used by the manufacturer to qualify the process, the use of American Society for Testing and Materials (ASTM). MIL-STD-883 or Joint Electron Device Engineering Council (JEDEC) specitications are suggested. The manufacturer may also document and use new tests developed to improve quality and reliability. Manufacturers are required to identify a Technical Review Board (TRB) within their company. It is the duty of the TRB to approve all changes in the process and report to DESC on a regular basis. Changes in the process and products are reviewed annually by a team of users, the qualifying activity and the preparing activity. Progress in meeting company established yield. Statistical Process Control (SPC). and reliability goals are reported at this meeting. Parts produced under MlL-l-38535 are listed on the QML.


DESIGN: - TOPIC P3

Part Classification Part Classification Description

QML (Hybrids) /CH or MIL-H-38534 Parts

The requirements for a hybrid microcircuit are set forth in Standard Military Drawings (SMDs) or Source Control Drawings (SCDs). The qualifying activity qualifies the manufacturer's process flows and once certified and qualified may produce multiple device types on that flow as MIL-H-38534 compliant parts. Test methods are defined in MIL-STD-883. All major changes to the process flows require qualifying activity approval. Parts produced under this system are listed in the Qualified Manufacturer's List.

Standard Military Drawing (Class M) and MIL-STD-883 Compliant Devices

This system evolved from various manufacturer's in-house versions of Test Methods 5004 and 5005 of MIL-STD-883. It was an informal and inconsistent system in the late 70's and early 80's known as MIL equivalent, or look aiikes. Manufacturers were falsely advertising these parts as equivalent to JAN parts, without basis, because most critical JAN requirements (e.g. audits, qualification, quality conformance inspection tests) were not followed. In some cases, not all the required JAN testing was being performed by the manufacturer. This resulted in the government incorporating a truth in advertising paragraph in MIL-STD-883 (i.e. Paragraph 1.2.1). This required the manufacturer to self-certify that all 1.2.1 requirements, a subset of the MIL-M-38510 requirements, were being met if advertised as meeting MIL-STD-883 requirements. DESC has begun an audit program to verify the manufacturers self compliance to MIL-STD-883, Paragraph 1.2.1 compliant product. The primary difference between Standardized Military Drawing (SMD) product and MIL-STD-883 compliant product is that SMD (Class M) sources are approved by the Defense Electronics Supply Center (DESC). DESC manages the procurement document (SMD) and approves the sources by accepting their certificate of compliance to the Paragraph 1.2.1 requirements. The MIL-STD-883 compliant product is produced to uncontrolled vendor data books and the government has no control over compliancy claims. Certification and qualification by DESC is not required for either system.


DESIGN: - TOPIC P3


DESIGN: - TOPIC P3

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DESIGN: - TOPIC P3

Topic D4: Review Questions Program and design reviews are key vehicles for measuring development progress and preventing costly redesigns. Participation by government individuals knowledgeable in R&M is critical to provoking discussions that bring out the issues important to R&M success. Of course, the questions to be posed to the development contractor depend on the timing of the review as indicated below. Action Items should be assigned at the reviews based on open R&M issues and the reliability engineer must follow-up to ensure that they're resolved satisfactorily.

Table D4-1: Major Program Reviews

Review Purpose R&M Engineers Role System To ensure a complete Requirements understanding of system Review (SRR) specification and statement of work

requirements. This is usually done by means of a detailed expansion and review of the contractor's technical proposal.

Discuss the performance of all required R&M tasks and requirements with contractor R&M personnel. Topics such as the contractor's overall reliability program plan, data items and delivery schedule are usually discussed.

Preliminary To evaluate progress and technical Design adequacy of the selected design Review (PDR) approach prior to the detailed

design process.

Critical Design To ensure that the detailed design Review (CDR) satisfies the requirements of the

system specification before freezing the design for production or field testing.

Test Readiness To ensure that all CDR problems Review (TRR) have been satisfactorily resolved

and to determine if the design is mature enough to start formal testing.

Review preliminary R&M modeling, allocations and predictions to ensure adequacy in meeting R&M requirements. Discuss status of other R&M tasks such as parts control, derating, thermal design and reliability critical items.

Review the final reliability analysis and modeling to ensure R&M requirements are met. Discuss parts control program status and military part procurement lead time requirements. Review adequacy of the final thermal analysis and derating. Discuss R&M testing.

Review R&M test plans and procedures to ensure acceptable ground rules and compliance with requirements.

Production To review test results and Readiness determine whether or not the Review (PRR) design is satisfactory for

production.

Discuss R&M testing results and ensure any design deficiencies found during testing have been corrected. Discuss production quality assurance measures.

ROME LABORATORY'S RELIABILITY ENGINEER'S TOOLKIT 55

DESIGN: - TOPIC P3

Table D4-2: Design Review Checklist

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What techni betwe other (e.g.. E n g i n e e r i n g , Procurement, and Te Evaluation)?

gineering should i at all engineering

,etings where R&M .. . .. d. Easy avenues of technical interchange

i the electrical design nd other groups such nal engineering must

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iip or an option to opinion is essential iilure tracking and action loop is to be

Is tt sub the Data (GIDEP)? proce parts on the ALERT list to parts used in 1

Are given form of testing laboratory

Do thi require sped based level

part types should ked against the

ALERT data base and incoming ALERTS should be checked against the system parts list. (GIDEP ALERTS are notices of

parts, materials or

arts are usually contract or by

MIL-STD-785. Methods of I critical parts must be

by the contractor. Topic D5 for a critical

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ints should include by analysis or


DESIGN: - TOPIC P3

Question

Review Where Usually Most Applicable SRR PDR CDR TRR PRR Remarks

Does the reliability group X have access to component and failure analysis experts and how are they integrated into the program?

Is there adequate X communication between testability design engineers and the electrical design group to ensure that testability considerations are worked into the upfront design?

Are JAN microcircuits (MIL-M-38510 or MIL-l-38535) and semiconductors (MIL-S-19500) being used wherever possib le and are procurement lead times for these devices adequate?

Where nonstandard parts are used, are they procured via a specification control drawing (SCD) and do they have at least two suppliers? Are methods for nonstandard part approval clearly established and is there a clear understanding of what constitutes a standard and nonstandard part?

Has an up-to-date preferred parts selection list (PPSL) been established for use by designers?

Failure analysis is essential to determine the cause and effect of failed components.

Part quality in order of preference: MIL-M-38510, or MIL-l-38535 devices; MIL-STD-883 Class B; MIL-STD-883 vendor equivalent; commercial hermetically sealed. JAN parts usually require longer procurement times (3 to 6 months) which somet imes causes commercial parts to be forced into the design.

Specif icat ion control drawings should specify reliability, environment and testing requirements.

DESC and DISC establish baseline PPSLs which should be the basis of the contractor's list.


DESIGN: - TOPIC P3

Question


R&M Design Do the R&M&T models accurately reflect the system configuration, its modes of operation, duty cycles, and implementation of fault tolerance?

Do predictions meet numerical R&M specification requirements? Are prediction procedures in accordance with requirements?

If not, better cooling, part quality and/ or redundancy should be considered.

Have R&M allocations been made to the LRU level or below? Do reliability pre-dictions compare favorably to the allocation?

Weighted reliability allo-cations should be made to lower levels based on the upper test MTBF (Go), or similar measure.

Does the testability analysis show that numerical testability requirements will be met for the organizational, intermediate and depot repair levels?

If not, alternate design concepts must consider including more automated features.

Have tradeoff studies been performed in the areas of R&M&T?

Has a thermal analysis been performed to ensure an adequate cooling technique is used and have the temperature results been factored into the reliability analysis?

Has piece part placement been analyzed to ensure that high dissipating parts are placed away from heat sensitive parts?

Typical tradeoffs might include redundancy levels, weight, power, volume, complexity, acquisition cost, life cycle cost.

Thermal analysis is essential to a complete program.

For example, high power dissipation components such as large power resistors, diodes and transformers should be investigated.


DESIGN: - TOPIC P3

Question


Have methods been X established to ensure that operating temperatures of off-the-shelf equipment will be within specified limits?

Do parts used in the design meet system environmental requirements?

Is there a clearly established derating criteria for all part types used in the design and is there a clear procedure for monitoring and enforcing this criteria?

X X

Reference environmental requirements in the system specification.

Temperature range for most military parts is - 55°C to + 125°C. Temperature range for most commercial parts (plastic) is 0°C to 70°C,

The part derating levels are a function of program type but should be at least Level III in Topic D1.

Are temperature overheat sensors included in the system design?

Is there a clear procedure for the identification of parts not meeting the derating criteria?

Will part derating verification tests be performed?

Have limited life parts and preventive maintenance tasks been identified, and inspection and replacement requirements specified?

X X

X X A tradeoff analysis should be performed on parts not meeting derating criteria to determine if a redesign to lower stress is appropriate.

Depending on system criticality, 3 to 7 percent of the system's parts should undergo stress verification. No more than 30 percent of the tested parts should be passive parts (resistors, capacitors, etc.).

For example, inspection items may include waveguide couplers, rotary joints, switches, bearings, tubes and connectors. Typical Preventive Maintenance (PM) items include air filters, lubrication, oil changes, batteries, belts, etc.


DESIGN: - TOPIC P3

Question


Have single points of failure been identified, and their effects determined?

Important for identifying areas where redundancy should be implemented and to assist in ranking the most serious failure modes for establishing a critical items list.

Have compensating features X X been identified for those single points of failure where complete elimination of the failure mode is impractical?

Have areas where fault x X ambiguity may exist been identified? Have alternative methods of isolation and checkout (e.g., semi-automatic, manual, repetitive replacement, etc.) been identified for these areas?

Compensating features could include increased part quality, increased testability, additional screening, fail safe design provisions, etc.

Additional test nodes must be considered to break ambiguity groups.

For each maintenance level, has a decision been made for each item on how built-in-test, automatic test equipment, and general purpose electronic test equipment will support fault detection and isolation?

X X

Are features being incorporated into the testability design to control false alarms?

X X Typical features might include definition of test tolerances, transient monitor-ing and control, multiple run decision logic, environmental effects fi l tering and identification, etc.

R&M Testing Is there a failure reporting and corrective action system (FRACAS) in place, and does it account for failures occurring during all phases of testing?

X X X FRACAS should include data from incoming inspection, development testing, equip-ment integration testing and R&M testing. FRACAS should be "closed loop" emphasizing corrective action


DESIGN: - TOPIC P3

Question


Is there a failure analysis capability and will failures be subjected to a detailed analysis?

Contractor should identify criteria used to determine which failures will be analyzed.

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LABORATORY'S RELIABILITY ENGINEER'S TOOLKIT 61

DESIGN: - TOPIC P3

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Major Concerns

• Has the contractor developed formal policies and procedures for identification and control?

• Are the procedures implemented at the initial design stage and do they continue through final acceptance period?

• Are periodic reviews planned to update the list and controls?

• Has an FMEA been performed on each critical item?

• Are compensating features included in the design?

• Does the contractor's control plan eliminate or minimize the reliability risk?

• As a minimum, are the following criticality factors considered:

- Failures jeopardizing safety

- Restrictions on limited useful life

- Design exceeding derating limits

- Single sources for parts

- Historically failure prone items

- Stringent tolerances for manufacturing or performance

- Single failure points that disrupt mission performance

Comments • Policies should be distributed to

design, manufacturing, inspection and test personnel.

• The program has to start early so that safety related items can be minimized.

• Reviews at SRR, PDR, and CDR must be considered.

• Failure modes need to be identified so that control procedures can be developed.

• Features such as safety margins, overstress testing, special checkouts should be considered.

• Development of a list of critical items is only half the solution; controls such as stress tests, design margins, duty cycles, and others must be considered.

• A list of critical items, personnel responsible for monitoring and controlling, and review procedures must be established. Other application unique critical items should be identified by the procuring activity.


DESIGN: - TOPIC P3

Topic Di; Dormancy Design Control Dormancy design control is important in the life cycle of a weapon system because, after an equipment has been installed or stored in an arsenal, the predominant portion of its life cycle is in the dormant mode. The main problems are the lack of dormancy related design guides and control methods to maintain or assure system reliability in storage. Questions often asked and seldom answered are:

Most important stresses? Mechanical, chemical, and low thermal; the synergism of these three stresses is critical.

Most significant failure mechanisms? Failures related to latent manufacturing defects, corrosion , and mechanical fracture, with most failures being the result of latent manufacturing defects rather than specific aging mechanisms.

Types of failure? Most failures that occur during nonoperating periods are of the same basic kind as those found in the operating mode, though precipitated at a slower rate.

Most important factor? Moisture is the single most important facior affecting long term nonoperating reliability. . All possible steps snould be taken to eliminate it from electronic devices. Hygroscopic materials should be avoided or protected against accumulation of excess moisture.

Materials to avoid? Avoid materials sensitive to cold flow and creep as well as metalized and non-metallic finishes which have flaking characteristics. Avoid the use of lubricants: if required, use dry lubricants such as graphite. Do not use teflon gaskets in lieu of conventional rubber gaskets or better yet, use silicone based rubber gaskets.

Storage Guidelines

• Do not test the equipment: Periodic testing results in failures rather than higher states of readiness. Historical data on missile systems that were stored and tested periodically shows that failures were introduced into the equipment as a result of the testing process. Causes of the failures were test procedures, test equipment and operator errors. Main guidelines are:

- Disconnect all power

- Ground all units and components

- Pressurize all coax waveguides: Use nitrogen to prevent moisture and corrosion.

- Maintain temperature at 50°F +/«§°F: At least drain all equipment of water to prevent freezing or broken pipes.


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DESIGN: - TOPIC P3

TOOLKIT 65

SMT involves placing a component directly onto the surface of a printed circuit board (PCB) and soldering its connections in place. SMT components can be active (integrated circuits) or passive devices (resistors), and can have different lead designs as presented below. In either case, the solder connection is both an electrical and mechanical connection, thus replacing the mechanical connection associated with plated through holes (PTH). Maximizing the integrity of SMT designs centers around minimizing the thermal and mechanical fatigue of both the components solder connection and the board's PTHs.

Common Lead Designs

Leadless Gull-wing J-lead S-lead

Leadless Chip Carriers (LCCs): Attaching component to board directly with solder alone.

Leaded Chip Carrier: Attaching a leaded component to board with solder.

CTE: Coefficient of Thermal Expansion is the change in length per unit length when heated through one degree. It directly effects the thermal strain and thus the stress in the solder joint.

Design Guidelines

Use the largest allowable standard size for passive components to minimize manufacturing flaws.

Carefully consider the application for active devices when electing to use leadless versus leaded components.

Use special CTE matching to preclude stress cracking in LCC solder joints.

Minimize PCB to 13" x 13" size to avoid warp and twist problems.

Provide an adequate clearance at the board's edge in order to provide space for the board mounting and wave solder conveyor fingers.

Locate components on a grid to ease programming of automatic dispensing or placement equipment.

Allow proper spacing between components to account tor visual inspection, rework, and engineering changes to assembly.


DESIGN: - TOPIC P3

Topic D8; Power Supply Design Checklist For many years power supply reliability has fallen short of expectations especially when used in adverse environments. Today the situation is even worse as power supplies are being designed to exceed three watts per cubic inch - a challenge to construction and packaging techniques and part technology. And, since high density means more concentrated heat - the enemy of all components - power supply reliability problems will prevail. Following are design considerations and possible solutions to review:

Table D8-1: Design Checklist (New Designs)

Items to be Addressed Solutions/Recommendations

• Transient effects - In-rush current Apply resistor-triac technique, thermistor

technique

- High-voltage spikes Apply metal oxide varistor (MOV) transient voltage suppressor

- Short circuits Apply constant current and current foldback protection

- Switching voltage transients Apply snubber circuits

• Effects of AC ripple current Consider use of MIL-C-39006/22 capacitors

• Corrosion due to leakage Avoid wet slug tantalum capacitors and use plating and protective finishes

• Aluminum electrolytic capacitors Epoxy end-seals minimize external contamination

• Temperature stability Use low temperature coefficient capacitors (mica or ceramic)

• Packaging techniques Enhance heat transfer, control electromagnetic interference, decrease parasitic capacitance

• Saturation Use antisaturation diodes (Baker Clamps) in conjunction with a switching transistor

• Potentiometers Replace with precision fixed resistor

• Short mounting leads Derate the operating voltage below 50% to prevent hot spots


DESIGN: - TOPIC P3


DESIGN: - TOPIC P3

Topic PS: Part Failure Modes and Mechanisms To properly apply electronic parts In complex and high density equipment designs, the engineer needs to know what factors are significant. With knowledge about the failure modes, mechanisms, and frequency of occurrence design changes can be instituted to eliminate or degrade the accelerating factors thereby increasing the equipment reliability. Table D9-1 presents these factors for a representative group of electronic components. For further information on part construction and operation, consult MIL-HDBK-978B, "NASA Parts Application Handbook," or MSI-HDBK-338, "Electronic Reliability Design Handbook."

Table D9-1: Part Failure Modes and Mechanisms

Type Failure Mechanisms % Failure Modes Accelerating Factors

Microcircuits Digital Oxide Defect 9

Electromigration 6 Overstress 18 Contamination 16

Mechanical 17 Elec. Parameters 33

Memory Oxide Defect 17 Overstress 22

Contamination 25

Mechanical 9 Elec. Parameters 26

Linear Overstress 21

Contamination 12 Mechanical 2 Elec. Parameters 48 Unknown 16

Hybrid Overstress 17 Contamination 8 Mechanical 13 Elec. Parameters 20 Metallization 10 Substrate Fracture 8 Miscellaneous 23

Short/Stuck High Electric Field, Temp. Open/Stuck Low Power, Temp. Short then Open Power Short/Stuck High Vibration, Shock, Short/Stuck High

Moisture, Temp. Stuck Low Shock, Vibration Degraded Temp., Power

Short/Stuck High Electric Field, Temp. Short then Open or Power, Temp. Stuck Low Short/Stuck High Vibration, Shock Short/Stuck High

Moisture, Temp. Stuck Low Shock, Vibration Degraded Temp., Power

Short then Open or Power, Temp. Stuck Low Short/Stuck High Vibration, Shock Stuck Low Shock, Vibration Degraded Temp., Power Stuck High or Low

Short then Open Power, Temp Short Vibration, Shock Open Shock, Vibration Degraded Temp., Power Open Temp., Power Open Vibration Open


DESIGN: - TOPIC P3


Diodes Signal Elec. Parameter 48 Degraded Temp., Power Signal

Die Fracture 10 Open Vibration Seal Leak 3 Open Moisture, Temp. Overstress 17 Short then Open Power, Temp. Unknown 21 Open

Power, Temp.

Zener Elec. Parameter 32 Degraded Temp., Power Leakage Current 7 Degraded Power Mechanical 1 Open Shock, Vibration Overstress 33 Short then Open Voltage, Temp. Unknown 26 Open

Transistors Bipolar Overstress 54 Short then Open Power, Temp.

Elec. Parameters 25 Degraded Temp., Power Leakage Current 10 Degraded Power Miscellaneous 10 Open

Field Effect Overstress 51 Short then Open Power, Temp. Elec. Parameters 17 Degraded Temp., Power Contamination 15 Short Vibration, Shock Miscellaneous 16 Open

Resistors Composition Moisture Intrusion 45 Resistance (R) Moisture, Temp.

Change Non-uniform Material 15 R Change, Open Voltage/Current, Contamination Temp.

14 R Change Voltage/Current, Lead Defects Temp.

25 Open Moisture, Temp., Voltage/Current

Film Moisture Intrusion 31 R Change Moisture, Temp., Contamination

Substrate Defects 25 R Change Temp., Voltage/

% Failure Modes Accelerating Factors

Bipolar

Field Effect

Overstress Elec. Parameters Leakage Current Miscellaneous

Overstress Elec. Parameters Contamination Miscellaneous

48 10 3

17 21

32 7 1

33 26

54 25 10 10

51 17 15 16

Degraded Open Open Short then Open Open

Degraded Degraded Open Short then Open Open

Short then Open Degraded Degraded Open

Short then Open Degraded Short Open

Temp., Power Vibration Moisture, Temp. Power, Temp.

Temp., Power Power Shock, Vibration Voltage, Temp.

Power, Temp. Temp., Power Power

Power, Temp. Temp., Power Vibration, Shock

Resistors Composition

Film

Moisture Intrusion

Non-uniform Material Contamination

Lead Defects

Moisture Intrusion

Substrate Defects

Film Imperfections

Lead Termination

45 Resistance (R) Change

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14 R Change

25 Open

31 R Change

25 R Change

25 R Change, Open

9 Open

Film Material Damage 9 R Change, Open

Moisture, Temp.

Voltage/Current, Temp. Voltage/Current, Temp. Moisture, Temp., Voltage/Current

Moisture, Temp., Contamination Temp., Voltage/ Current Temp., Voltage/ Current Shock, Vibration, Temp., Voltage/ Current Temp., Voltage/ Current


DESIGN: - TOPIC P3


Resistor (cont'd) Wirewound Wire Imperfection 32 Open Voltage/Current,

Temp. Wire Insulation Flaw 20 R Change, Short Voltage/Current,

Temp. Corrosion 31 R Change, Short Temp., Moisture Lead Defects 10 Open Shock, Vibration, Open

Voltage/Current Intrawinding 6 R Change, Short Temp., Voltage/ Insulation Breakdown Current

Capacitors Ceramic Dielectric Breakdown 49 Short Voltage, Temp.

Connection Failure Voltage, Temp.

Surface 18 Open Temp., Cycling Contamination 3 Capacitance Drift Temp., Voltage Low Insulation Resistance 29 Short Temp., Voltage

Plastic/Paper Connection Failure 46 Open Temp., Cycling Cracked Dielectric 11 Short Temp., Voltage Capacitance Change 42 Degraded Temp., Voltage

Tantalum Loss of Electrolyte 17 Capacitance Drift Temp., Voltage (Nonsolid) Leakage Current 46 Short Voltage, Temp.

Intermittent High 36 Open Temp., Cycling Impedance

Inductive Devices Transformer Wire Overstress 25 Open Voltage, Current

Faulty Leads 5 Open Vibration, Shock Corroded Windings 24 Short Moisture, Temp. Insulation Breakdown 25 Short Voltage, Moisture, Insulation Temp. Deterioration 20 Short Moisture, Temp.

RF Coil Wire Overstress 37 Open Voltage, Current Faulty Leads 16 Open Vibration, Shock Insulation Breakdown 14 Short Voltage, Moisture,

Failure Modes. Accelerating Factors

Plastic/Paper

Tantalum (Nonsolid)

Surface Contamination Low Insulation Resistance

Connection Failure Cracked Dielectric Capacitance Change

Loss of Electrolyte Leakage Current Intermittent High Impedance

Inductive Devices Transformer Wire Overstress

Faulty Leads Corroded Windings Insulation Breakdown Insulation Deterioration

32

20

31 10

25 5

24 25

Open

R Change, Short

R Change, Short Open

6 R Change, Short

49 Short

18 Open 3 Capacitance Drift

29 Short

46 Open 11 Short 42 Degraded

17 Capacitance Drift 46 Short 36 Open

Open Open Short Short

20 Short

Voltage/Current, Temp. Voltage/Current, Temp. Temp., Moisture Shock, Vibration, Voltage/Current Temp., Voltage/ Current

Voltage, Temp.

Temp., Cycling Temp., Voltage

Temp., Voltage

Temp., Cycling Temp., Voltage Temp., Voltage

Temp., Voltage Voltage, Temp. Temp., Cycling

Voltage, Current Vibration, Shock Moisture, Temp. Voltage, Moisture, Temp. Moisture, Temp.

RF Coil Wire Overstress Faulty Leads Insulation Breakdown

Insulation Deterioration

37 Open 16 Open 14 Short

32 Short

Voltage, Current Vibration, Shock Voltage, Moisture, Temp. Moisture, Temp.


DESIGN: - TOPIC P3

DESIGN: - TOPIC P3

Topic D10: Fiber Optic Design Criteria Fiber optics are relatively new when compared with most electronic devices. With the increased use of fiber optics comes the need to address fiber optic reliability so that preventive design measures can be instituted. This section will present specific failure modes/mechanisms and their causes and prevention to aid designers/planners in establishing a reliable system. Tables D10-1 thru D10-3

and'Fiber S& Cable6 T a b f e ^ figu reô f 80% confidence bound except connectors.

Table D10-1: Common Failure Mechanisms (Transmitters)

Open Circuit

Short or Open Circuit

Current (PIN) Dark

> Photo Diode (APD) Dark Current

of the an APD at1.3j im&


DESIGN: - TOPIC P3

Table D10-3: Common Failure Mechanisms (Fiber & Cable)

Mode Causes Prevention

Cable Open Stress corrosion or fatigue Residual or threshold tension less Circuit Fracture due to microcracks than 33% of the rated proof tested

tensile strength

Cable Intermittent Hydrogen migrates into the Design cables with materials that core of the fiber do not generate hydrogen

Cable Open Temperature cycling, Design a jacket that can prevent Circuit Breakage ultraviolet exposure, water & shrinking, cracking, swelling or

fluid immersion splitting

Cable Opaque Circuit Radiation Design to be nuclear radiation Inoperative hardened

Table D10-4: Fiber Optic Component Failure Rates

Component Type Failure Rate (10"6 Hrs.) MTBF (Hrs.)

Fiber 4.35 - 5.26 210.000

Cable 1.15-1.81 750.000

Splices .022 - .64 27.000.000

Connectors # of Matings MIL-T-29504 1000 MIL-C-28876 500 N/A MIL-C-38999 500

N/A

MIL-C-83522 500 MIL-C-83526 1000 FC-Style 1000

Light Emitting Diodes (LEDS) AIGaAs/GaAs .13 - .88 4,000,000 InGaAsP/lnP .78-1.92 850,000 AIGaAs/Si 2.08 - 8.33 320,000

Laser Diodes AIGaAs/GaAs 1.27-9.1 410,000 - 1.3jim wavelength .79-9.1 620,000 InGaAsP/lnP .13-2.4 3,700,000

Photodetectors APD .12-1.54 4,000,000 PIN .57 - 3.58 1,000,000


SedlioFi; fh

Contents

A1 Reliability and Maintainability Analyses 77 A2 Reliability Prediction Methods 80 A3 Maintainability Prediction Methods 81 A4 Testability Analysis Methods 84 A5 Reliability Analysis Checklist 85 A6 Use of Existing Reliability Data 86 A7 Maintainability/Testability Analysis Checklist. 87 A8 FMECA Analysis Checklist 88 A9 Redundancy Equations 89

A10 Parts Count Reliability Prediction 92 A11 Reliability Adjustment Factors 105 A12 SMT Assessment Model 108 A13 Fi nite Element Analysis 113 A14 Common Thermal Analysis Procedures 115 A15 Sneak Circuit Analysis 119 A16 Dormant Analysis 122 A17 Software Reliability Prediction and Growth.... 124


Rel iabi l i ty and ma in ta inab i l i t y analyses are a necessary part of most development programs. They provide a means of determining hoy* weK the cfes?gn is progressing t o w a r d s m e e t i n g the p r o g r a m s goafs and requsrerosn is . 'They also provide means of evaluating the impac t of important design dec i s i ons sucti as coo l i ng approaches, classes of pars quality being, used, f i nd s r o a s of feiiE tn terancf t . in order for the. governrnen? to receive She outputs of contractor performed analyses, appropr ia te contract rjelEversble data Items rnust be raqyirscl


MIL-STD-756 MIL-STD-1629

MI-HDBK-217 MIL-HDBK-472 RADC-TR-87-55 RADC-TR-77-287 RADC-TR-89-223 RADC-TR-89-276 RADC-TR-89-281 RADC-TR-90-109 RL-TR-91-29

RL-TR-91-87

RL-TR-91-155

RL-TR-92-197

"Reliability Modeling and Prediction" "Procedures for Performing a Failure Mode, Effects and Criticality Analysis" "Reliability Prediction of Electronic Equipment" "Maintainability Prediction" "Predictors of Organizational-Level Testability Analysis" "A Redundancy Notebook" "Sneak Circuit Analysis for the Common Man" "Dormant Missile Test Effectiveness" "Reliability Assessment Using Finite Element Techniques" "Integration of Sneak Analysis with Design"

"A Rome Laboratory Guide to Basic Training in TQM Analysis Techniques" " A Survey of Reliability, Maintainability, Supportability and Testability Software Tools" "Computer Aided Assessment of Reliability Using Finite Element Methods" "Reliability Assessment of Critical Electronic Components"


ANALYSIS - TOPIC A10

Topic A1: Reliability and Maintainability Analyses

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Table A1-2: Summary of Failure Effects Analysis Characteristics

Analysis Type & s \ y y Inductive X Deductive X Specialized Application X X

Time Dependency X

Advanced Math X Single Failures X X X X

Multiple Failures X External Influences X X X Any Design Stage X X X

Early Design Stage X X

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Logistics Application X X

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Topic M : Reliability Analysis Checklist Major Concerns Comments

Models Are all functional elements included in the reliability block diagrams/model?

Are all modes of operation considered in the math model?

Do the math model results show that the design achieves the reliability requirement?

Allocation Are system reliability requirements allocated (subdivided) to useful levels?

Does the allocation process consider complexity, design flexibility and safety margins?

Prediction Does the sum of the parts equal the value of the module or unit?

Are the environmental conditions and part quality representative of the requirements?

Are the circuit and part temperatures defined and do they represent the design?

Are equipment, assembly, subassembly and part reliability drivers identified?

System design drawings/diagrams must be reviewed to be sure that the reliability model/diagram agrees with the hardware. Duty cycles, alternate paths, degraded conditions and redundant units must be defined and modeled. Unit failure rates and redundancy equations are used from the detailed part predictions in the system math model.

Useful levels are defined as: equipment for subcontractors, assemblies for subcontractors, circuit boards for designers.

Conservative values are needed to prevent reallocation at every design change.

Many predictions conveniently neglect to include all the parts producing optimistic results (check for solder connections, connectors, circuit boards).

Optimistic quality levels and favorable environmental conditions are often assumed causing optimistic results.

Temperature is the biggest driver of part failure rates; low temperature assumptions will cause optimistic results.

Identification is needed so that corrective actions for reliability improvement can be considered.

Are part failure rates from acceptable sources (i.e., MIL-HDBK-217)?

Use of generic failure rates require submission of backup data to provide credence in the values.

Is the level of detail for the part failure rate models sufficient to reconstruct the result?

Are critical components such as VHSIC, Monolithic Microwave Integrated Circuits (MMIC), Application Specific Integrated Circuits (ASIC) or Hybrids highlighted?

Each component type should be sampled and failure rates completely reconstructed for accuracy.

Prediction methods for advanced parts should be carefully evaluated for impact on the module and system.



Topic A6: Use of Existing Reliability Data System development programs often make use of existing equipment (or assembly) designs, or designs adapted to a particular application. Sometimes, lack of detailed design information prevents direct prediction of the reliability of these Items making use of available field and/or test failure data the only practical way to estimate their reliability. If this situation exists, the following table summarizes the information that is desired.

Table A6-1: Use of Existing Reliability Data

Information Required Equipment Field Data

Equipment Test Data

Piece Part Data

Data collection time period X X X Number of operating hours per equipment X X Total number of part hours X Total number of observed maintenance actions

X

Number of "no defect found" maintenance actions

X

Number of induced maintenance actions X Number of "hard failure" maintenance actions

X

Number of observed failures X X Number of relevant failures X X Number of nonrelevant failures X X Failure definition X X Number of equipment or parts to which data pertains

X X X

Similarity of equipment of interest to equipment for which data is available

X X

Environmental stress associated with data X X X Type of testing X Field data source X



Topic A7: Maintainabiiity/Tesfability Analysis Checklist!

Major Concerns Comments

Are the maintainability/testability prediction techniques and data used clearly described? Is there a clear description of the maintenance concept and all ground rule assumptions?

Are worksheets provided which show how LRU repair times were arrived at?

Are step-by-step repair descriptions provided to back up repair time estimates?

Are fault isolation time estimates realistic?

Repair level, LRU/module definition, spares availability assumptions, test equipment availability assumptions, tools availability assumptions, personnel assumptions, environmental conditions.

The breakout of repair time should include: fault isolation, disassembly, interchange, reassembly and checkout.

Overestimating BIT/FIT capability is the primary cause of optimistic repair time estimates.

Are fault isolation ambiguity levels considered in the analysis?

Can repair times be reconstructed from the worksheets and is addition, subtraction, multiplication and division correct?

Are preventive maintenance tasks described?

Is all the equipment included in the prediction?

Has the best procedure been selected to provide estimates for the testability attributes?

Are the numerical values of the testability attributes within specified tolerances?

Does the test equipment, both hardware and software, meet all design requirements.

Are the simulation and emulation procedure to be used to simulate/emulate units of the system, for diagnostics development, reasonable and practical?

Checking is mundane but often results in errors and inconsistencies being found.

This includes frequency, maintenance time and detailed task description.

Because of the number of variables which effect testability and the number of different procedures available to effect analyses, there must be rationale and logic provided to explain why the particular approach was taken.

All test points should be accessible.



T @ p l e M : F I M E O A A n a l y s e s G f o e c k M

Major Concerns Comments

• Is a system definition/description provided compatible with the system specification?

• Are ground rules clearly stated?

• Are block diagrams provided showing functional dependencies at all equipment indenture levels?

• Does the failure effect analysis start at the lowest hardware level and systematically work to higher indenture levels?

• Are failure mode data sources fully described?

• Are detailed FMECA worksheets provided? Do the worksheets clearly track from lower to higher hardware levels? Do the worksheets clearly correspond to the block diagrams? Do the worksheets provide an adequate scope of analysis?

• These include approach, failure definition, acceptable degradation limits, level of analysis, clear description of failure causes, etc.

• This diagram should graphically show what items (parts, circuit cards, sub-systems, etc.) are required for the successful operation of the next higher assembly.

• The analysis should start at the lowest level specified in the SOW (e.g. part, circuit card, subsystem, etc.)

• Specifically identify data sources per MIL-HDBK-338, Para 7.3.2, include relevant data from similar systems.

• Worksheets should provide an item name indenture code, item function, list of item failure modes, effect on next higher assembly and system for each failure mode, and a cr'rticality ranking. In addition, worksheets should account for multiple failure indenture levels for Class I and Class II failures.

Are failure severity classes provided? Are specific failure definitions established?

Are results timely?

Are results clearly summarized and are clean comprehensive recommendations provided?

Are the results being submitted (shared) to enhance other program decisions?

Typical classes are: - Catastrophic (life/death) - Critical (mission loss) - Marginal (mission degradation) - Minor (maintenance/repair)

Analysis must be performed "during" the design phase not after the fact.

Actions for risk reduction of single point failures, critical items, areas needing BIT/FIT, etc.

BIT design, critical parts, reliability prediction, derating, fault tolerance.



Topic A9: Redundancy Equations Many military electronic systems readiness and availability requirements exceed the level of reliability to which a serial chain system can be practically designed. Use of high quality parts, a sound thermal design and extensive stress derating may not be enough. Fault tolerance, or the ability of a system design to tolerate a failure or degradation without system failure, is required. The most common form of fault tolerance is redundancy where additional, usually identical, units are added to a system in parallel with the other units. Because this situation is very common, the reliability equations for common redundancy situations are included below.

The following represents a sample list of specific redundancy relationships which define failure rate as a function of the specific type of redundancy employed. For a comprehensive treatment of redundancy concepts and the reliability improvements achievable through their applications see RADC-TR-77-287, "A Redundancy Notebook."



Table A9-1: Redundancy Equation Approximations Summary

Redundancy Equations With Repair Without Repair All units are active on-line with equal unit failure rates, (n-q) out of n required for success.

Equation 1

V q ) / n ! n! ( X ) o+1

(n-q-1)!(^

Equation 4

fyn-q)/n n 1

i-n-q

Two active on-line units with different failure and repair rates. One of two required for success.

Equation 2

^1/2 XaXB [(MA+WB)+(*A+?iB)]

Equation 5 _ Xa2XB+XAXB2

V 2 m X A 2 + X B 2 + X A X B

One standby off-line unit with n active on-line units required for success. Off-line spare assumed to have a failure rate of zero. On-line units have equal failure rates.

Equation 3

^n/n+1 = n[nU(1-P)p]x,

H+n(P+1)X,

Equation 6

^n/n+1 : NX

:P+1

Key: X x / y is the effective failure rate of the redundant configuration where x of y units are

required for success n = number of active on-line units, nl is n factorial (e.g., 51=5x4x3x2x1=120,

11=1,01=1) X = failure rate of an individual on-line unit (failures/hour) q = number of on-line active units which are allowed to fail without system failure ji = repair rate (jj.=1/Mct, where Met is the mean corrective maintenance time in

hours) P = probability switching mechanism will operate properly when needed (P=1 with

perfect switching) Notes: 1. Assumes all units are functional at the start 2. The approximations represent time to first failure 3. CAUTION: Redundancy equations for repairable systems should not be applied if

delayed maintenance is used.



Example 1: A system has five active units, each with a failure rate of 220 f/106 hours, and only three are required for successful operation. If one unit fails, it takes an average of three hours to repair it to an active state. What is the effective failure rate of this configuration?

Solution: Substituting the following values into Equation 1: -

n = 5

q = 2

\l = 1/3

\S'2)!S = H/5

(5 -2 -1)! (1/3) f/hour

X 3 / 5 = .00575 f/106 hours

Example 2: A ground radar system has a 2 level weather channel with a failure rate of 50 f/106 hours and a 6 level weather channel with a failure rate of 180 f/106

hours. Although the 6 level channel provides more comprehensive coverage, the operation of either channel will result in acceptable system operation. What is the effective failure rate of the two channels if one of two are required and the Wct is 1 hour?

Solution: Substituting the following values into Equation 2:

X A = 50 • 10"®

X B = 180 • 10"®

M-a = ^B = 1 /Mct = 1

X. (50 - 10"6)(180 -10"6) [ (1+1) + (50 • 10"b + 180 • 10"6)] „8

* /q = c c = 1.8 • 10 f/hour ^ (1)(1) + (1 + 1)(50 • 10'6 +180 • 1(T6)

Xy2 = .018 f/106 hours



Topic A10: Parts Count Reliability Prediction A standard technique for predicting reliability when detailed design data such as part stress levels is not yet available is the parts count reliability prediction technique. The technique has a "built-in" assumption of average stress levels which allows prediction in the conceptual stage or source selection stage by estimation of the part types and quantities. This section contains a summary of the MIL-HDBK-217F, Notice 1 technique for eleven of the most common operational environments:

G B Ground Benign

g f Ground Fixed

G m Ground Mobile

N S Naval Sheltered

N Y Naval Unsheltered

A I C Airborne Inhabited Cargo

A | F Airborne Inhabited Fighter

A U C Airborne Uninhabited Cargo

a U F Airborne Uninhabited Fighter

a r w Helicopter (Both Internal and External Equipment)

s F Space Flight

Assuming a series reliability model, the equipment failure rate can be expressed as:

n XEQUlP = 2 (Nj)(^gj)(^Qj)

i=1

where

%QUIP = = total equipment failure rate (failures/106 hrs)

xgi = generic failure rate for the ith generic part type (failures/106 hrs)

= quality factor for the ith generic part type N, = quantity of the ith generic part type n = number of different generic part types



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Microcircuit Quality Factors - tzq

Description

Class S Categories:

1. Procured in full accordance with MIL-M-38510, Class S requirements.

2. Procured in full accordance with MIL-l-38535 and Appendix B thereto (Class V).

3. Hybrids: (Procured to Class S requirements (Quality Level K) of MIL-H-38534.

.25

Class B Categories:

1. Procured in full accordance with MIL-M-38510, Class B requirements.

2. Procured in full accordance with MIL-l-38535, (Class Q).

3. Hybrids: Procured to Class B requirements (Quality Level H) of MIL-H-38534.

1.0

Class B-1 Category:

Fully compliant with all requirements of paragraph 1.2.1 of MIL-STD-883 and procured to a MIL drawing, DESC drawing or other government approved documentation. (Does not include hybrids). For hybrids use custom screening section on the following page.

2.0

Microcircuit Learning Factor -Years in Production, Y

<.1 2.0 .5 1.8

1.0 1.5 1.5 1.2

>2.0 1.0

n L = .01 exp(5.35 - .35Y)

Y = Years generic device type has been in production



Microclrcuit Quality Factors (cont'd): n Q Calculation for Custom Screening Programs

Group MIL-STD-883 Screen/Test (Note 3) Point Valuation

1*

TM 1010 (Temperature Cycle, Cond B Minimum) and TM 2001 (Constant Acceleration, Cond B Minimum) and TM 5004 (or 5008 for Hybrids) (Final Electricals @ Temp Extremes) and TM 1014 (Seal Test, Cond A, B, or C) and TM 2009 (External Visual)

50

2*

TM 1010 (Temperature Cycle, Cond B Minimum) or TM 2001 (Constant Acceleration, Cond B Minimum) TM 5004 (or 5008 for Hybrids) (Final Electricals @ Temp Extremes) and TM 1014 (Seal Test, Cond A, B, or C) and TM 2009 (External Visual)

37

3 Pre-Burn in Electricals TM 1015 (Burn-in B-Level/S-Level) and TM 5004 (or 5008 for Hybrids) (Post Burn-in Electricals @ Temp Extremes)

30 (B Level) 36 (S Level)

4*

5

6

T

8

9

10

11

TM 2020 Pind (Particle Impact Noise Detection)

TM 5004 (or 5008 for Hybrids) (Final Electricals @ Temperature Extremes)

TM 2010/17 (Internal Visual)

TM 1014 (Seal Test, Cond A, B, or C)

TM 2012 (Radiography)

TM 2009 (External Visual)

TM 5007/5013 (GaAs) (Wafer Acceptance)

TM 2023 (Non-Destructive Bond Pull)

11

11 (Note 1)

7

7 (Note 2)

7

7 (Note 2)

1

1 87

n Q = 2+ z P o i n t Valuations

*NOT APPROPRIATE FOR PLASTIC PARTS NOTES:

1. Point valuation only assigned if used independent of Groups 1, 2 or 3. 2. Point valuation only assigned if used independent of Groups 1 or 2. 3. Sequencing of tests within groups 1, 2 and 3 must be followed. 4. TM refers to the MIL-STD-883 Test Method. 5. Nonhermetic parts should be used only in controlled environments (i.e., G g and other

temperature/humidity controlled environments).

EXAMPLES: 87 1. Mfg. performs Group 1 test and Class B burn-in: % q - 2 + 50+30 - 3.1

87 2. Mfg. performs internal visual test, seal test and final electrical test: t t q - 2 + 7 + 7 + 1 1 - 5.5

Other Commercial or Unknown Screening Levels k q = 10


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Table A10-7: KQ Factor for Use with Inductive, Electromechanical and Miscellaneous Parts

Part Type Established Reliability MIL-SPEC Non-MIL

Inductive Devices .25 1.0 10

Rotating Devices N/A N/A N/A

Relays, Mechanical .60 3.0 9.0

Relays, Solid State and Time Delay (Hybrid & Solid State)

N/A 1.0 4

Switches, Toggle, Pushbutton, Sensitive

N/A 1.0 20

Switches, Rotary Wafer N/A 1.0 50

Switches, Thumbwheel N/A 1.0 10

Circuit Breakers, Thermal N/A 1.0 8.4

Connectors N/A 1.0 2.0

Interconnection Assemblies N/A 1.0 2.0

Connections N/A N/A N/A

Meters, Panel N/A 1.0 3.4

Quartz Crystals N/A 1.0 2.1

Lamps, Incandescent N/A N/A N/A

Electronic Filters N/A 1.0 2.9

Fuses N/A N/A N/A



i T o p l e M 1 s M ® M I t y Ad l |ys tm@irs f i F s e t t o r s

"What if" questions are often asked regarding reliability figures of merit. For a rapid translation, tables for different quality levels, various environments and temperatures are presented to make estimates of the effects of the various changes. The data base for these tables is a grouping of approximately 18000 parts from a number of equipment reliability predictions performed in-house on military contracts. The ratios were developed using this data base and MIL-HDBK-217F algorithms. The relative percentages of the part data base are shown as follows:

3% 2%

D Transistors

H Capacitors

H Resistors

I Integrated Circuits

B3 Inductors

S3 Diodes

EH Miscellaneous

Table A11-1: Part Quality Factors (Multiply MTBF by)

To Quality Class Space Full Military Rugged ized Commercial

Space From Full Military Quality Ruggedized Class Commercial

X 0.8 0.5 0.2 Space From Full Military Quality Ruggedized Class Commercial

1.3 X 0.6 0.2 Space

From Full Military Quality Ruggedized Class Commercial

2.1 1.6 X 0.4

Space From Full Military Quality Ruggedized Class Commercial 5.3 4.1 2.5 X

IC Semiconductor Passive Part

Class S Class B Class B-1 Class D IC Semiconductor Passive Part

JANTXV JANTX JAN NONMIL IC Semiconductor Passive Part ER(S) ER(R) ER(M) NONMIL

CAUTION: Do not apply to Mean-Time-Between-Critical-Failure (MTBCF).



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Topic A12: Surface Mount Technology (SMT) Assessment Model ;

The SMT Model was developed to assess the life integrity of leadless and leaded devices. It provides a relative measure of circuit card wearout due to thermal cycling fatigue failure of the "weakest link" SMT device. An analysis should be performed on all circuit board SMT components. The component with the largest failure rate value (weakest link) is assessed as the overall board failure rate due to SMT. The model assumes the board is completely renewed upon failure of the weakest link and the results do not consider solder or lead manufacturing defects. This model is based on the techniques developed in the Rome Laboratory technical report RL-TR-92-197, "Reliability Assessment of Critical Electronic Components."

X s m t = Average failure rate over the expected equipment life cycle due to surface mount device wearout. This failure rate contribution to the system is for the Surface Mount Device on each board exhibiting the highest absolute value of the strain range:

[ ( a s A T - a G C ( A T + T r i s e ) ) x 1 0 " 6 ]

1 ECF 1 s m t = ^

ECF = Effective cumulative number of failures over the Weibull characteristic life.

Table A12-1: Effective Cumulative Failures - ECF

L C ECF OSMT

0 - . 1 .13 .11-.20 .15 .21 - .30 .23 .31 - .40 .31 .41 - .50 .41 .51 - .60 .51 .61 - .70 .61 .71 - .80 .68 .81 - .90 .76

>.9 1.0

LC = Design life cycle of the equipment in which the circuit board is operating.



asMT = The Weibull characteristic life. asMT is a function of device and substrate material, the manufacturing methods, and the application environment used.

asMT =

where: CR

Nf

Nf

where:

n l CR

= Temperature cycling rate in cycles per calendar hour

= Average number of thermal cycles to failure

= a 5 ( i k | ( a s A T • a c c ( A T + T r , s e ) ) | x 1 0 ~ 6 ) "2 o 2 6 (WLC)

d = Distance from center of device to the furthest solder joint in mils (thousands of an inch)

h = Solder joint height in mils for leadless devices. Use h = 8 for all leaded configurations.

as = Circuit board substrate thermal coefficient of expansion (TCE)

A j = Use environment temperature difference

acc = Package material thermal coefficient of expansion (TCE)

T r i s e = Temperature rise due to power dissipation (Pd) Pd = 0JCP 9JC = Thermal resistance 7Watt

P = Watts

kic = Lead configuration factor

Table A12-2: CR - Cycling Rate Values

Equipment Type Number of Cycles/Hour

Consumer (television, radio, recorder) Computer Teleco mmunications Commerical Aircraft Industrial Military Ground Applications Military Aircraft

.0042

.17

.0042

.34

.021

.03

.12



Table A12-3: k^q - Lead Configuration Factor

Lead Configuration t c L c

Leadless 1 J or S Lead 150 Gull Wing 5,000

Table A12-4: execTCE Package Values

Substrate Material otcc Average Value

Plastic 7 Ceramic 6

Table A12-5: AT - Use Environment Temperature Difference

Environment AT

GB 7

GF 21

GM 26

A IC 31

Auc 57

A I F 31

AUF 57

ARW 31 NY 61 Ns 26



Table A12-6: ag - TCE Substrate Values

Substrate Material a S FR-4 Laminate 18 FR-4 Multilayer Board 20 FR-4 Multilayer Board w/Copper Clad Invar 11 Ceramic Multilayer Board 7 Copper Clad Invar 5 Copper Clad Molybdenum 5 Carbon-Fiber/Epoxy Composite 1 Kevlar Fiber 3 Quartz Fiber 1 Glass Fiber 5 Epoxy/Glass Laminate 15 Polimide/Glass Laminate 13 Polyimide/Kevlar Laminate 6 Polyimide/Quartz Laminate 8 Epoxy/Kevlar Laminate 7 Aluminum (Ceramic) 7 Epoxy Aramid Fiber 7 Polyimide Aramid Fiber 6 Epoxy-Quartz 9 Fiberglass Teflon Laminates 20 Porcelainized Copper Clad Invar 7 Fiberglass Ceramic Fiber 7

Example: A large plastic encapsulated leadless chip carrier is mounted on a epoxy-glass printed wiring assembly. The design considerations are: a square package is 1480 mils on a side, solder height is 5 mils, power dissipation is .5 watts, thermal resistance is 20°C/watt, the design life is 20 years and environment is militaiy ground application. The failure rate developed is the impact of SMT for a single circuit board and accounts for all SMT devices on this board. This failure rate is added to the sum of all of the component failure rates on the circuit board.

, ECF X S M T = ^SMT


- i Nf = 3.5 ( ^ | ^ | ( a S A T - a c c ( A T + TR|SE))|x10-6y2-26 (rrLC)

Ford: d = 1(1480) = 740 mils

For h: h = 5 mils

For as: as = 15 (Table A12-6

For AY: AJ = 21 (Table A12-5 - Gp)

For occ: «CC = 7 (Table A12-4

For TRISE: TRISE = 0JC P = 20(.5) = 10°C

For 7CLC: TCLC = 1 (Table A12-3 - Leadless

For CR: CR = .03 cycles/hour (Ts

"< - 3 . 5 ( ^ | (15(2 , ) .7 ( 2 , t ,0 ) ) | x ,0^ ) - 2 - 2 6 ( , )

- Ts'fcft ' "

= .41



Step 1

Step 2

Step 3

Step 4

FEM Results Displacement Due to Vibration Loads

'T Displacement Due to Thermal Loads

Interpretation of Local Displacements/Stresses

Vibration and Thermal Displacements Component Relative to Board

Life Analysis

Stress

N

Cycles to Failure

Probabilistic Reliability Analysis

Cycles to hanure Distribution

Time

Figure A13-1



Topic A14: Common Thermal Analysis Procedures The following graphs and associated examples provide a guide for performing basic integrated circuit junction temperature calculations for three of the most common types of cooling designs: impingement, cold wall, and flow through modules. This procedure is intended to provide the Reliability Engineer with a simple means of calculating approximate junction temperatures and for performing a quick check of more detailed thermal analysis calculations.

Card-Mounted, Flow-through Modules

Q Notes: 1. Module dissipation uniformly distributed and applied on both sides. 2. The part junction temperature is obtained as follows:

W A T B A + < 6 J C + e C B > Q P where

T j is the junction temperature t a is the cooling air inlet AT B A is the weighted average heat-exchanger-to-cooling-air inlet temperature difference (See Note 4) @jq is the junction-to-case thermal resistance in °C/W @CB ®s tiierma' resistance between the case and the heat exchanger in °C/W Qp is the part power dissipation in watts

3. All temperatures are in °C 4. Weighted average temperature difference is the value at a location two thirds of the distance from the inlet to

the outlet, as shown in sketch. Experience has shown that the temperature at this location approximates the average board temperature.

Figure A14-1: Estimated Temperature of Card-mounted Parts Using Forced-air-cooled Flow-through Modules



Card-Mountedp Air-Cooled Coidwails

T H E R M A L P L A N E T H I C K N E S S = 1.27 x 1 0 ~ 4 m (0 .005 in)

2 . 5 4 x 1 0 ~ 4 m ( 0 . 0 1 0 in) k 5 .08 x 1 0 ~ 4 m ( 0 . 0 2 0 in)

v 7 .62 x 1 0 " 4 m ( 0 . 0 3 0 in) 0.2 x 1 0 ~ 4 m ( 0 . 0 4 0 in) \ 1 2 . 7 x 1 0 " 4 m ( 0 . 0 5 0 in)

19 .04 x 1 0 ~ 4 m (0 .075 in) 2 5 . 4 x 1 0 " 4 m (0.1 in)

C O L D W A L L I N T E R F A C E

C O O L I N G A I R F L O W

> C O L D W A L L 4

C I R C U I T B O A R D

T w i

Notes: 1 . A T c e from curve is for L/W = 2; for other L/W ratios, multiply ATCE from curve by 0.5 L/W

2. The junction temperature is obtained as follows:

0.03 Qj T J = T A + M A + A T C E + Q T ( 0 . 0 7 6 1 / W + 0 . 2 5 ) + Qp ( 0 J C + 0 C B )

where T j is the junction temperature T^ is the air inlet temperature Q j is the total card power dissipation in watts Qp is the part power dissipation in watts m a is the airflow rate in Kg/Min ATce is the temperature difference between center of card and card edge W is the card width in meters 0JC is the junction-to-case thermal resistance in °C/W 6cB is the case-to-mounting surface thermal resistance in °C/W

3. All temperatures are in °C

4. The card edge to card guide interface thermal resistance is 0.0761 °C/W per meter of card width

5. The coldwall convective thermal resistance is 0.25°C/W

Figure A14-2: Estimated Temperature of Card-mounted Parts Using Forced-air Cooled Coldwalls



Air Impingement, Card-Mounted

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5 5 W / m 2 (0 .1 W / i n 2 ) 7.5 W / m 2 ( 0 . 0 5 W / i n 2 )

A I R V E L O C I T Y , m / s

Notes: 1. The part j unction temperature is obtained as follows:

TJ = T A + ATBA + (0JC + 0CB) Qp where

T j is the junction temperature T a is the local cooling air temperature A TBA IS the local card-to-air temperature difference 0JC is the junction-to-case thermal resistance in °C/W 8CB >s the case-to-mounting-surface thermal resistance in °C/W Qp is the part power dissipation in watts

2. All temperatures are in °C

3. Assumes all the heat is uniformly distributed over both sides of the board

4. Assumes no air temperature rise (add any rise in air temperature to the result)

Figure A14-3: Estimated Temperature of Card-mounted Parts Using Forced-air Impingement Cooling at Sea Level



Example 1: Card Mounted, Air Cooled Coldwalls Estimate the junction temperature of a 0.25-W microcircuit mounted at the center of a coldwall-cooled circuit board, 0.152 X 0.102 m, with a total power dissipation of 20 W. The part, which has a mounting base of 0.00635 X 0.00953 m, is attached to the board with a 7.6 X 10~5 m (3 mils) thick bonding compound whose thermal conductivity (k) is 0.25 W/m-°C. The forced airflow rate is 1.8 kg/min with an inlet temperature of 45°C. The board contains a 5.08 X 10"4 (0.020 inch) thick copper thermal plane. The 9 j c of the part is 50°C/W.

1. From Figure A14-2, ATQE = 57°C for L/W = 2

. x , , nM. 0.152 m . Actual L W - - 1 . 4 9 , so

Corrected ATQE « (0.5) (1.49) (57°C) - 42.5°C

7.6 X 10"5m _ 2. 0p r = ——— 5 = 5.03 C/W U D (0.25 W/m C) (0.00635m) (0.00953 m)

3. From Note 2 in Figure A14-2 0.03QT

T j = TA + m + ATCE + QT (0.0761 W + 0.25) + Qp (CUc + ©CB) m a

= 45+ — E 9 1 42 5 + 20 ^ + 0.25^ + 0.25 (50 + 5.03)

T j = 122°C

Example 2: Air Impingement, Card Mounted Cooling Estimate the junction temperature of a part dissipating 0.25 W and mounted on a circuit board cooled by impingement with ambient air at 40°C and a velocity of 15 m/s. The circuit board, whose dimensions are 0.102 X 0.152 m, has a total power dissipation of 20 W. The part, whose mounting base is 0.00635 X 0.00953 m, is attached to the board with a 7.61 X 10"5 m (3 mils) thick bonding compound whose thermal conductivity (k) is 0.25 W/m-°C. The junction-to-case thermal resistance (9JC) of the partis 50°C/W.

1. Compute the card heat flux density (see Note 3 in Figure A14-3):

2(0.102 m) (0.152 m)= 6 4 5 W / m 2

2. From Figure A14-3: ATBA = 17°C

0 A 7.61 X 10"5m _ Af 3. 0 Q R = 5— = 5.03 C/W (0.25W/m C) (0.00635 m) (0.00953 m)

4. From Note 1 in Figure A14-3 T j « TA + ATBA + (0JC + ®CB) Q p = 4 0 + 17+ (50 + 5.03) 0.25

T j = 71 °C



Topic A15: Sneak Circuit Analysis Electronics that operate within their specifications are still vulnerable to critical failures. Hidden within the complexity of electronic designs are conditions that slip past standard stress tests. These conditions are known as sneak circuits.

Definitions

Sneak Circuit : A condition which causes the occurrence of an unwanted function or inhibits a desired function even thougn all components function properly.

Sneak Paths: Unintended electrical paths within a circuit and its external interfaces.

Sneak Timing: Unexpected interruption or enabling of a signal due to switch circuit timing problems.

Sneak Indications: Undesired activation or de-activation of an indicator.

Sneak Labels: Incorrect or ambiguous labeling of a switch.

Sneak Clue: Design rule applied to a circuit pattern to identify design inconsistencies.

Cause of Sneaks

Complex designs with many interfaces Flaws unknowingly designed into equipment Switching and timing requirements Incomplete analyses and test

Why Do Sneak Analysis?

Method for detecting hidden failures Verification of interface switching and timing requirements Improves system/unit reliability

Where are Sneak Circuits?

Electrical power systems Switching circuits Distribution and control systems Software control functions Interface configurations



Table A15-1: Typical Clue Statements

Clue Sneak Impact

Fanout Exceeded Design Concern Unpredictable Outputs

Unterminated CMOS Input

Design Concern Device Damage

Large Time Constant Sneak Timing Unpredictable Switching Times

Uncommitted Open Collector Output

Design Concern False Unstable Logic

Performing Sneak Analysis Time to complete analysis: An average Sneak Circuit Analysis (SCA) is a lengthy process that requires several months to complete. Redrawing the electronics of a system into hundreds of topographical patterns and checking each one against a multitude of sneak clues is a time consuming task.

• Cost of analysis: SCA specialists will be required due to the need for proprietary sneak clues. Their cost of analysis is based on part count and design complexity. Outside specialists, not familiar with the design, will require extra time and money to complete a detailed analysis of the functions and operation of a design. This learning curve cost is in addition to the cost of analysis.

Avai labi l i ty of resul ts: A manual SCA requires preproduction level drawings to prevent late design changes from inserting new sneaks into the system after performing the analysis. Extra time must be available to review the results or taking the necessary corrective action will require hardware rework, recall, or redesign rather than drawing changes.


To perform a manual analysis, many independent contractors are available for contracts. If in-house work is contemplated, RADC-TR-89-223, "Sneak Circuit Analysis for the Common Man," is recommended as a guide. Automated tools are available including the Rome Laboratory prototype called SCAT (Sneak Circuit Analysis Tool). A new Rome Laboratory tool, Sneak Circuit Analysis Rome Laboratory Engineering Tool (SCARLET), is in development for future use.



Example: Subsystem Sneak Circuit Reverse Current Operation Figure A15-1a shows the original circuit which was designed to prevent routine opening of the cargo door unless the aircraft was on the ground with the gear down and locked. The secondary switch permits emergency operation of the door when the gear is not down. Figure A15-1b shows the network tree diagram which indicates the existence of a sneak path. If the emergency and normal door open switches are both closed, the gear will be inadvertently lowered. The solution to the problem is the addition of a diode to prevent reverse current flow as shown in Figure A15-1c.

(a) ORIGINAL CIRCUIT

-J CARGO DOOR L

GEAR X O DOWN \

CARGO DOOR

T I (b) NETWORK TREE

w-

(c) REVISED CIRCUIT

i CARGO DOOR

Figure A15-1: Sneak Circuit Example



Topic At6: -Dormant Analysis In the past, analysis techniques for determining reliability estimates for dormant or storage conditions relied on rules of thumb such as "the failure rate will be reduced by a ten to one factor" or "the failure rate expected is zero." A more realistic estimate, based on part count failure results, can be calculated by applying the conversion factors shown in Table A16-1. The factors convert active failure rates by part type to passive or dormant conditions for seven scenarios. For example, to convert the reliability of an active airborne receiver to a captive carry dormant condition, determine the number of components by type, then multiply each by the respective active failure rate obtained from handbook data, field data, or vendor estimates. The total active failure rate for each type is converted using the conversion factors of Table A16-1. The dormant estimate of reliability for the receiver is determined by summing the part results.

Example: Aircraft Receiver Airborne Active Failure Rate to Captive Carry Passive Failure Rate

Conversion Device Qty. X^ Xj Factor Xp

IC 25 0.06 1.50 .06 .090 Diode 50 0.001 0.05 .05 .003 Transistor 25 0.002 0.05 .06 .003 Resistor 100 0.002 0.20 .06 .012 Capacitor 100 0.008 0.80 .10 080 Switch 25 0.02 0.50 20 .100 Relay 10 0.40 4.00 .20 .800 Transformer 2 0.05 0.10 20 .020 Connector 3 1.00 3.00 .005 .015 PCB 1 0.70 0.70 .02 .014 TOTALS — — 10.9 — 1.137

Xa = Part (Active) Failure Rate (Failures per Million Hours) Xj = Total Part (Active) Failure Rate (Failures per Million Hours) Xp = Part (Passive) (Dormant) Failure Rate (Failures per Million Hours)

Mean-Time-Between-Failure (Active) = 92.000 hours

Mean-Time-Between-Failure (Passive) = 880.000 hours



Table A 1 6 - 1 : Dormant Conversion Factors (Multiply Active Failure Rate by)

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Topic A17: Software Reliability Prediction and Growth Software failures arise from a population of software faults. A software fault (often called a "bug") is a missing, extra, or defective code that has caused or can potentially cause a failure. Every time a fault is traversed during execution, a failure does not necessarily ensue; it depends on the machine state (values of intermediate variables). The failure rate of a piece of software is a function of the number and location of faults in the code, how fast the program is being executed, and the operational profile. While most repair activity is imperfect, the hoped-for and generally observed result is that the times between failures tend to grow longer and longer as the process of testing and fault correction goes on. A software reliability growth model mathematically summarizes a set of assumptions about the phenomenon of software failure. The model provides a general form for the failure rate as a function of time and contains parameters that are determined either by prediction or estimation.

The following software reliability prediction and growth models are extracted from Rome Laboratory Technical Report RL-TR-92-15, "Reliability Techniques For Combined Hardware and Software Systems." These models can be used to estimate the reliability of initially released software along with the reliability improvement which can be expected during debugging.

Initial Software Failure Rate n K WQ

Xo = - — ; — failures per CPU second

rj = host processor speed (instructions/sec) K = fault exposure ratio which is a function of program data dependency

and structure (default = 4.2 x 10"7) W 0 = estimate of the total number of faults in the initial program

(default = 6 faults/1000 lines of code) I = number of object instructions which is determined by number of

source lines of code times the expansion ratio

Programming Language Expansion Ratio Assembler 1 Macro Assembler 1.5

where

C COBOL FORTRAN JOVIAL Ada

2.5 3 3 3 4.5



Software Reliability Growth

X(t) = Xq e-IPfl

where A,(t) = software failure rate at time t (in CPU time) Xq = initial software failure rate

t = CPU execution time (seconds)

P = decrease in failure rate per failure occurrence

» -

B = fault reduction factor (default = .955) Wo = initial number of faults in the software program per 1,000

lines of code

Example 1: Estimate the initial software failure rate and the failure rate after 40,000 seconds of CPU execution time for a 20,000 line Ada program:

rj = 2 MIPS = 2,000,000 instructions/sec

K = 4.2 x 10"7

Wo = (6 faults/1000 lines of code) (20,000 lines of code) = 120 Faults

I = (20,000 source lines of code) (4.5) = 90,000 instructions

i _ (2,000,000 inst./sec) (4.2 x 10-7) (120 faults) ^ ~ 90,000 inst.

Ao = .00112 failures/CPU second

q d ô / Arr \ , .00112 failures/sec v

P = B Wo = («955) ( 120 faults }

p = 8.91 x 10"6 failures/sec

X (40,000) = .00112 ei ( 8 - 9 1 x 1 ° " 6 failures/sec) (40,000 sec)]

X (40,000) = .000784 failures/CPU second


Bec i fc i f i : T

Testing

Contents T1 ESS Process 129 T2 ESS Placement 130 T3 Typical ESS Profile 131 T4 RGT and RQT Application 133 T5 Reliability Demonstration Plan

Selection 134 T6 Maintainability Demonstration Plan

Selection 136 T7 Testability Demonstration Plan

Selection 137 T8 FRACAS (Failure Reporting and

Corrective Action System) 138 T9 Reliability Demonstration Test Plan

Checklist 140 T10 Reliability Test Procedure Checklist 144 T11 Maintainability Demonstration Plan

and Procedure Checklist 145 T12 R&M Test Participation Criteria 146 T13 R&M Demonstration Checklist 147 T14 Design of Experiments 148 T1 5 Accelerated Life Testing 153 T16 Time Stress Measurement 159


A well tailored reliability and maintainability program contains several; forms of testing. Depending on the program constraints, a program should be invoked to mature the "designed in reliability as well as to determine whether the contract quantitative reliability and maintainability requirements have been achieved prior to a commitment to production. All forms of testing (Environmental Stress Screening (ESS), Reliability Growth, Reliability Demonstration) must be tailored to fit specific program constraints. Test plans and procedures most be evaluated to ensure proper test implementation. Test participation depends on the program situation but test reports must be carefully evaluated by the government.


MIL-STD-471

MIL-STD-781

MIL-HDBK-781

DoD-HDBK-344

MIL-HDBK-189

RADC-TR-86-241

RADG-TR-89-160

RADC-TR-89-299

RADC-TR-90-269

RL-TR-91-300

"Maintainability Verification/Demonstration /Evaluation"

"Reliability Testing for Engineering Development, Qualification and Production"

"Reliability Test Methods, Plans, and Environments for Engineering Development, Qualification, and Production"

"Environmental Stress Screening of Electronic Equipment"

"Reliability Growth Management"

"Built-in-Test Verification Techniques"

"Environmental Extreme Recorder

"Reliability & Maintainability Operational Parameter Translation II

"Quantitative Reliability Growth Factors for ESS"

"Evaluation of Quantitative Environmental Stress Screening (ESS) Methods"


TESTING - TOPIC T10

Topic I I : ESS Process Environmental Stress Screening (ESS) has been the subject of many recent studies. Determination of the optimum screens for a particular product, built by a particular manufacturer, at a given time is an iterative process. Procedures for planning for and controlling the screening process are contained in DOD-HDBK-344 (USAF), "Environmental Stress Screening of Electronic Equipment." The process can be depicted as shown below:

Figure T1-1: ESS Process


TESTING - TOPIC T10

!@pb T2i isSS FSsesrn® ": Level of Assembly Advantages Disadvantages

Assembly • Cost per flaw precipitated is lowest (unpowered screens)

• Test detection efficiency is relatively low

• Small size permits batch screening

• Test equipment cost for powered screens is high

• Low thermal mass allows high rates of temperature change

• Temperature range greater than operating range allowable

Unit • Relatively easy to power and monitor performance during screen

• Thermal mass precludes high rates of change or requires costly facilities

• Higher test detection efficiency than assembly level

• Assembly interconnections (e.g., wiring backplane) are screened

• Cost per flaw significantly higher than assembly level

• Temperature range reduced from assembly level

System • All potential sources of flaws are screened

• Difficult and costly to test at temperature extremes

• Unit interoperability flaws detected

• High test detection efficiency

• Mass precludes use of effective vibration screens or makes use costly

• Cost per flaw is highest


TESTING - TOPIC T10

Topic T3: Typical ESS Profile

Screen Type, Parameter and Conditions

Assemblies (Printed Wiring Assemblies) (SRU)*

Equipment or Unit (LRU/LRM)*

Thermal Cycl ing Screen Temperature Range (Minimum) (See Note 1 )

From - 50°C to + 75°C From -40°C to +71 °C

Temperature Rate of Change (Minimum) (See Notes 1 & 2)

20°C/Minute 15°C/Minute

Temperature Dwell Duration (See Note 3)

Until Stabilization Until Stabilization

Temperature Cycles 20 to 40 12 to 20

Power On/Equipment Operating No (See Note 5)

Equipment Monitoring No (See Note 6)

Electrical Testing After Screen Yes (At Ambient Temperature)

Yes (At Ambient Temperature)

Random Vibrat ion (See Notes 7 and 8) Acceleration Level 6 Grms 6 G rms

Frequency Limits 20 - 2000 Hz 20 - 2000 Hz

Axes Stimulated Serially or Concurrently

3 3 (See Note 9)

Duration of Vibration (Minimum) • Axes stimulated serially • Axes stimulated concurrently

10 Minutes/Axis 10 Minutes

10 Minutes/Axis 10 Minutes

Power On/Off Off On (See Note 5)

Equipment Monitoring No Yes (See Note 6)

Piece Parts: Begin the manufacturing and repair process with 100 defects per million or less (See Note 10).

*SRU - Shop Replaceable Unit *LRM - Line Replaceable Module *LRU - Line Replaceable Unit


TESTING - TOPIC T10

Notes: 1. All temperature parameters pertain to agreed upon selected sample points inside the

unit being screened, not chamber air temperature.

2. Rapid transfers of the equipment between one chamber at maximum temperature and another chamber at minimum temperature are acceptable. SRU temperature rates of change may be reduced if equipment damage will occur at 2Q°C/minute.

3. The temperature has stabilized when the temperature of the part of the test item considered to have the longest thermal lag is changing no more than 2°C per hour.

4. A minimum of 5 thermal cycles must be completed after the random vibration screen. Random vibration frequently induces incipient failures.

5. Shall occur during the low to high temperature excursion of the chamber and during vibration. When operating, equipment shall be at maximum power loading. Power will be OFF on the high to low temperature excursion until stabilized at the low temperature. Power will be turned ON and OFF a minimum of three times at temperature extremes on each cycle.

6. Instantaneous go/no-go performance monitoring during the stress screen is essential to identify intermittent failures when power is on.

7. Specific level may be tailored to individual hardware specimen based on vibration response survey and operational requirements.

8. When random vibration is applied at the equipment level, random vibration is not required at the subassembly level. However, subassemblies purchased as spares are required to undergo the same random vibration required for the equipment level. An "LRU mock-up" or equivalent approach is acceptable.

9. One axis will be perpendicular to plane of the circuit board(s)/LRM(s).

10. The Air Force or its designated contractor may audit part defective rates at its discretion. The test procedure will include thermal cycling as outlined below. Sample sizes and test requirements are included in the "Stress Screening Military Handbook," DOD-HDBK-344.

Minimum Temperature Range From - 54°C to + 100°C Minimum Temperature Rate of Change The total transfer time from hot-to-cold or cold-

to-hot shall not exceed one minute. The working zone recovery time shall be five minutes maximum after introduction of the load from either extreme in accordance with MIL-STD-883D. Until Stabilization (See Note 3) 25 No Yes (At high and low temperatures)

Temperature Dwell Minimum Temperature Cycles Power On/Equipment Monitoring Electrical Testing After Screen


TESTING - TOPIC T10

Topic 14: 1GT and RQT Application The Reliability Qualification Test (RQT) is an "accounting task" used to measure the reSiabiSity of a fixed design configuration. St has the benefit of holding the contractor accountable some day down the road from his initial design process. As such, he is encouraged to seriously carry out the other design related reliability tasks. The Reliability Growth Test (RGT) is an "engineering task" designed to improve the design reliability. It recognizes that the drawing board design of a complex system cannot be perfect from a reliability point of view and allocates the necessary time to fine tune the design by finding problems and designing them out. Monitoring, tracking and assessing the resulting data gives insight into the efficiency of the process and provides non l iab i l i t y persons with a tool for evaluating the development's reliability status and for reallocating resources when necessary. The forms of testing serve very different purposes and complement each other in development of systems and equipments. An RGT is not a substitute for an RQT, or other reliability design tasks.

Table 14-1: RGT and RQT Applicability as a Function of System/Program Constraints

System/Program Parameter

Reliability Growth Test Apply Consider Don't Apply

Reliability Qualification Test

Apply Consider Don't Apply

Challenge to state-of-the-art Severe use environment One-of-a-kind system High quantities to be produced Benign use environment -Critical mission Design flexibility exists No design flexibility Time limitations Funding limitations Very high MTBF system

X X

X X X X

X

X

X

X X

X X X X


TESTING - TOPIC T10

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TESTING - TOPIC T10

T o p S e T i e M s m t a i r i s f e s S I i ^ m m S e l e c t i o n


TESTING - TOPIC T10

T © p f e r w t e f i t i i i t y P l m S © t e © t i © ^

Test Calendar Time Characteristic Required

Program Constraints Number of Equipments Available Test Facility

Limitations

Desired Confidence in Results

Fixed sample size type tests

Time required is proportional to

vary depending on

Provides for producer's risks of 10%. Provides

les will

(consumer and proportional to producer) (1 -consumer risk =confidence)

N o t e s :

1. Sample size dependent on total number of sample maintenance tasks selected as per i A. 10.4 of MIL-STD-471 A.

2. Demonstration facility must have capability for insertion of simulated faults.


TESTING - TOPIC T10

Topic T8; FRACAS (Failure Reporting and Correctiwe Action System) Early elimination of failure trends is a major contributor to reliability growth and attaining the needed operational reliability. To be effective, a closed loop coordinated process must be implemented by the system/equipment contractor. A description of the major events and the participant's actions is shown below.

Event Funct ions Act ions

Failure or Malfunction

Failure Report

Data Logged

Failure Review

Failure Analysis

Failure Correction

Post Data Review

Operators:

Maintenance:

Quality:

Maintenance:

Quality:

R&M:

R&M:

Design:

R&M:

Physics of Failure:

Quality:

Design:

Vendor:

Quality:

R&M:

Identify a problem, call for maintenance, annotate the incident

Corrects the problem, logs the failure.

Inspects the correction.

Generates the failure report with supporting data (time, place, equipment, item, etc.)

Insures completeness and assigns a travel tag for the failed item for audit control.

Log all the failure reports, validate the failures and forms, classify the failures (inherent, induced, false alarm).

Determine failure trends (i.e., several failures of the same or similar part).

Review operating procedures for error.

Decide which parts will be destructively analyzed.

Perform failure analysis to determine the cause of failure (i.e., part or external).

Inspect incoming test data for the part.

Redesign hardware, if necessary.

New part or new test procedure.

Evaluate incoming test procedures, inspect redesigned hardware.

Close the loop by collecting and evaluating post test data for reoccurrence of the failure.

Figure 18-1: Failure Reporting System Flow Diagram


TESTING - TOPIC T10

Table T8-1: FRACAS Evaluation Checklist

Topic Items to Be Addressed

General • Closed loop (i.e., reported, analyzed, corrected and verified)

• Responsibility assigned for each step

• Overall control by one group or function

• Audit trail capability

• Travel tags for all failed items

• Fast turn-around for analysis

Failure Report • Clear description of each event

• Surrounding conditions noted

• Operating time indicated

• Maintenance repair times calculated

• Built-in-test indications stated

Failure Analysis • Perform if three or more identical or similar parts fail

• Perform if unit reliability is less than half of predicted

• Results should indicate: overstress condition, manufacturing defect, adverse environmental condition, maintenance induced or wearout failure mode

Failure Data • Collated by week and month by unit

• Compared to allocated values

• Reliability growth tracked

• Problems indicated and tracked

• Correction data collected for verification


TESTING - TOPIC T10

Tmte TO; RelSatetiiSty mrnm^ma>m Test


Purpose and Scope • Statement of overall test objectives • General description of all tests to be performed

Reference Documents

• List all applicable reference documents

Test Facilities • Description of test item configuration • Sketches of system layout during testing • Serial numbers of units to be tested • General description of test facility • Test safety features • Identification of test location • General description of failure analysis facility • Security of test area • Security of test equipment and records • Test safety provisions

Test Requirements • Pre-reliability environmental stress screening (ESS) • Test length • Number of units to be tested • Number of allowable failures • Description of MIL-HDBK-781 test plan showing accept, reject

and continue test requirements • List of government furnished equipment • List and schedule of test reports to be issued

Test Schedule • Start date (approximate) • Finish date (approximate) • Test program review schedule • Number of test hours per day • Number of test days per week

Test Conditions • Description of thermal cycle • Description of thermal survey • Description of vibration survey • Description of unit under test mounting method • Description of test chamber capabilities • List of all limited life items and their expected life


TESTING - TOPIC T10


Test Conditions • Description of all preventive maintenance tasks and (cont 'd) their frequency

• Description of unit under test calibration requirements • Description of unit under test duty cycle • General description of unit under test operating modes and

exercising method Test Monitoring • Description of test software and software verification method

• List of all units under test functions to be monitored and monitoring method

• List of all test equipment parameters to be monitored and monitoring method

• Method and frequency of recording all monitored parameters Test Participation • Description of all contractor functions

• Description of all contractor responsibilities • Description of all government responsibilities • Description of test management structure

Failure Definitions The following types of failures should be defined as relevant in the test plan: • Design defects • Manufacturing defects • rnysicai or Tunctionai degradation oeiow specification limits

• Intermittent or transient failures • Failures of limited life parts which occur before the specified

life of the part • Failures which cannot be attributed to a specific cause • Failure of built-in-test (BIT)

The following types of failures should be defined as nonrelevant in the test plan: • Failures resulting from improper installation or handling • Failure of instrumentation or monitoring equipment which is

external to equipment under test • Failures resulting from overstress beyond specification limits

due to a test facility fault • Failures resulting from procedural error by technicians • Failures induced by repair actions • A secondary failure which is the direct result of a failure of

another part within the system.


TESTING - TOPIC T10

Topic items to Be Addressed

Test Ground Rules The following test ground rules should be stated in the test plan: • Transient Failures - Each transient or intermittent failure is to

be counted as relevant. If several intermittent or transient failures can be directly attributed to a single hardware or software malfunction which is corrected and verified during the test, then only a single failure will be counted as relevant.

• Classification of Failures - All failures occurring during reliability testing, after contractor failure analysis, shall be classified as either relevant or nonrelevant. Based on the failure analysis, the contractor shall justify the failure as relevant or nonrelevant to the satisfaction of the procuring activity.

• Pattern Failure - A pattern failure is defined as three or more relevant failures of the same part in identical or equivalent applications whose 95th percentile lower confidence limit failure rate exceeds that predicted.

• Malfunctions Observed During Test Set Up, Troubleshooting or Repair Verification - Malfunctions occurring during test set up, troubleshooting or repair verification tests shall not be considered as reliability test failures; however, such malfunctions shall be recorded and analyzed by the contractor to determine the cause of malfunctions and to identify possible design or part deficiencies.

• Test Time Accumulation - Only the time accumulated during the equipment power "on" portion of the test cycle shall be considered as test time, provided that all functions are operating as required. Operating time accumulated outside the operational cycles such as during tests performed to check out the setup or to verify repairs shall not be counted. Also, time accumulated during degraded modes of operation shall not be counted.

• Design Changes to the Equipment: - After test reject decision—With procuring activity

approval, the equipment may be redesigned and retested from time zero.

- Major design change prior to test reject—The contractor may stop the test for purposes of correcting a major problem. The test will restart from time zero after the design change has been made.

- Minor design change prior to test reject—With procuring activity approval, the test may be halted for the purpose of making a minor design change. Test time will resume from the point at which it was stopped and the design change shall have no effect on the classification of previous failures. Minor changes made as a result of other testing may be incorporated, with procuring activity approval, without declaring a failure of the equipment under test.


TESTING - TOPIC T10


Test Ground Rules • Failure Categorization - In order to clearly evaluate test (cont 'd) results and identify problem areas, failure causes will be

categorized as: (1) deficient system design, (2) deficient system quality control, and (3) deficient part design or quality.

Test Logs The following types of test logs should be described in the test plan:

• Equipment Data Sheets - used to record the exact values of all parameters measured during functional testing of the equipment.

• Test Log - a comprehensive narrative record of the required test events. All names and serial numbers of the equipments to be tested shall be listed before start of the test. An entry shall be made in the test log each time a check is made on the equipment under test, including data, time, elapsed time, and result (e.g., pass/malfunction indication/failure or etc.). An entry shall be made in the log whenever a check is made of the test facilities or equipments (such as accelerometers, thermocouples, input power, self-test, etc.). In the event of a failure or malfunction indication, all pertinent data, such as test conditions, facility conditions, test parameters and failure indicators, will be recorded. The actions taken to isolate and correct the failure shall also be recorded. Whenever engineering changes, or equipment changes are implemented, an entry shall be made in the log.

• Failure Summary Record - the failure summary record must chronologically list all failures that occur during the test. This record must contain all the information needed to reach an accept or reject decision for the test. Each failure must be described and all failure analysis data must be provided.

• Failure Report - for each failure that occurs, a failure report must be initiated. The report should contain the unit that failed, serial number, time, data, symptoms of failure and part or parts that failed .

*Most of these contents also apply to reliability growth testing.


TESTING - TOPIC T10

T@pSe TIO: IJMafslSIff T@st Pr@e@ciyr©


TESTING - TOPIC T10

Topic T11: Maintainability Demonstration Plan and Procedure Checklist

Topic Items to Be Addressed Purpose and Scope

Reference Documents

Test Facilities

Test Requirements

Test Schedule

Test Conditions

Test Monitoring

Test Participation

Test Ground Rules with Respect to

Testabi l i ty Demonstration

Statement of general test objectives General description of test to be performed

List of all applicable reference documents

Description of test item configuration Sketches of system layout during testing Serial numbers of units to be tested General description of site and test facility Description of all software and test equipment

Description of MIL-STD-471 test plan requirements Method of generating candidate fault list Method of selecting and injecting faults from candidate list List of government furnished equipment List and schedule of test reports to be issued Levels of maintenance to be demonstrated Spares and other support material requirements

Start and finish dates (approximate) Test program review schedule

Description of environmental conditions under which test will be performed Modes of equipment operation during testing

Method of monitoring and recording test results

Test team members and assignments Test decision making authority

Instrumentation failures Maintenance due to secondary failures Technical manual usage and adequacy Maintenance inspection, time limits and skill level

Repair levels for which requirements will be demonstrated Built-in-test requirements to be demonstrated External tester requirements to be demonstrated Evaluation method for making pass/fail decision Performance of FMEA prior to test start Method of selecting and simulating candidate faults Acceptable levels of ambiguity at each repair level


TESTING-TOPICT12

T o b S G T1i2s m l M m m m n M m M ^ Participation Criteria: Degree of Participation Depends On:

Availability of program resources to support on-site personnel

How important R&M are to program success

• Availability and capability of other government on-site personnel

Test Preliminaries All test plans and procedures must be approved

Agreements must be made among government personnel with respect to covering the test and incident reporting procedures

Units under test and test equipment including serial numbers should be documented

Working fire alarms, heat sensors and overvoltage alarms should be used

• Trial survey runs should be made per the approved test plan

Test Conduct Approved test plans and procedures must be available and strictly adhered to

Equipment must not be tampered with

Test logs must be accurately and comprehensively maintained

Appropriate government personnel must be kept informed

Only authorized personnel should be allowed in area (a list should be posted) Test logs, data sheets, and failure reports should be readily available for government review

Units under test should be sealed to prevent tampering or unauthorized repair

A schedule of inspections and visits should be maintained

No repairs or replacements should be made without a government witness

Government representatives must take part in failure review process

Failed items should have "travel tags" on them

• Technical orders should be used for repair if available


TESTING - TOPIC T10

Topic T13: Reliability and Maintainability Demonstration Reports-Checklist

• Identification and description of equipment/system tested

• Demonstration objectives and requirements Test Plans, Risks and Times Test Deviations and Risk Assessment

Data Analysis Techniques Statistical Equations

Test Results (Summarized)

Test Conditions Test Facilities

Accept/Reject Criteria

Reliability • Test Hours • Number of Failures/Incidents • Classification of Failures • Data Analysis Calculations • Application of Accept/Reject

Criteria • Failure Trends/Design and

Process Deficiencies • Status of Problem Corrections

Maintainability Maintenance Tasks Planned and Selected Task Selection Method

Personnel Qualifications Performing Tasks Documentation Used During Maintenance

Measured Repair Times

Data Analysis Calculations Application of Accept/Reject Cntena Discussion of Deficiencies identified

Testability • Summary data for each item involved in testability demonstration

including original plans, summanzed results and any corrective action taken.

• Recommended action to be taken to remedy testability deficiencies or improve the level of testability achievable through prime equipment engineering changes, ATE improvements and/or test program set improvements.

Data • Test Logs and Failure Reports • Failure Analysis Results


TESTING - TOPIC T10

Topic T14: Design of Experiments Design of Experiments is a very efficient, statistically based method of systematically studying the effects of experimental factors on response variables of interest. The efficiency is achieved through greatly reduced test time because the effects of vary-ing multiple input factors at once can be systematically studied. The technique can be applied to a wide variety of product design, process design, and test and evalua-tion situations. Many books have been written on various experimental design strategies which cannot possibly be addressed in these few pages. It is the intent of this section only to give the reader a brief introduction to Design of Experiments by providing a single numerical example of what is called a fractional factorial design. Some other competing design strategies, each with their own strengths or weak-nesses, include Full Factorial, Plackett-Burman, Box-Burman, and Taguchi.

Improved levels of reliability can be achieved through the use of Design of Experiments. Design of Experiments allows the experimenter to examine and quantify the main effects and interactions of factors acting on reliability. Once identi-fied, the main factors affecting reliability (some of which may be uncontrollable, such as weather) can be dealt with systematically and scientifically. Their adverse effects on the system design can be minimized, thereby meeting performance specifications while remaining insensitive to uncontrollable factors. The following example illustrates the general procedure and usefulness of Design of Experiments. The example is broken down into a series of steps which illustrate the general procedure of designing experiments.

Example: Fractional Factorial Design An integrated circuit manufacturer desired to maximize the bond strength of a die mounted on an insulated substrate since it was determined that bonding strength problems were resulting in many field failures. A designed experiment was con-ducted to maximize bonding strength.

Step 1 - Determine Factors: It isn't always obvious which factors are important. A good way to select factors is through organized "brainstorming". Ishikawa charts (see Introduction) are helpful in organizing cause and effect related data. For our example, a brainstorming session was conducted and four factors were identified as affecting bonding strength: (1) epoxy type, (2) substrate material, (3) bake time, and (4) substrate thickness.

Step 2 - Select Test Settings: Often, as with this example, high and low settings are selected. This is referred to as a two-level experiment. (Design of Experiments techniques are often used for more than two-level experiments.) The four factors and their associated high and low settings for the example are shown in Table T14-1. The selection of high and low settings is arbitrary (e.g. Au Eutectic could be"+" and Silver could be "-").


TESTING - TOPIC T10

Table T14-1: Factors and Settings

Factor Levels Low (-) High (#)

A. Epoxy Type Au Eutectic Silver B. Substrate Material Alumina Beryllium Oxide

C. Bake Time (at 90°C) 90 Min 120 Min D. Substrate Thickness .025 in .05 in

Step 3 - Set Up An Appropriate Design Matrix: For our example, to investigate all possible combinations of four factors at two levels (high and low) each would require 16 (i.e., 24) experimental runs. This type of experiment is referred to as a full factorial. The integrated circuit manufacturer decided to use a one half replicate fractional factorial with eight runs. This decision was made in order to conserve time and resources. The resulting design matrix is shown in Table T14-2. The Table T14-2 "+, -" matrix pattern is developed utilizing a commonly known Design of Experiments method called Yates algorithm. The test runs are randomized to minimize the possibility of outside effects contaminating the data. For example, if the tests were conducted over several days in a room where the temperature changed slightly, randomizing the various test trials would tend to minimize the effects of room temperature on the experimental results. The matrix is orthogonal which means that it has the correct balancing properties necessary for each factor's effect to be studied statistically independent from the rest. Procedures for setting up orthogonal matrices can be found in any of the references cited.

Step 4 - Run The Tests: The tests are run randomly at each setting shown in the rows of the array. The trial run order is determined by a random number table or any other type of random number generator. Resultant bonding strengths from testing are shown in Table T14-2 .

Table T14-2: Orthogonal Design Matrix With Test Results

Treatment Combination

Random Trial Run Order A

Factors B C D

Bonding Strength (psi) y

1 6 - _ - 73 2 5 + + 88 3 3 - + _ + 81 4 8 + + 77 5 4 + - + 83 6 2 + + 81 7 7 + + - 74 8 1 + + + + 90

Mean y = . 80.875


TESTING - TOPIC T10

Step 5 - Analyze The Results: This step involves performing statistical analysis to determine which factors and/or interactions have a significant effect on the response variable of interest. As was done in Table T14-3, interactions and aliasing (aliasing is defined as two or more effects that have the same numerical value) patterns must be identified. The impact on the response variable caused by "A or BCD" cannot be differentiated between factor A or the interaction of BCD. This is the penalty which is paid for not performing a full factorial experiment (i.e., checking every possible combination). The determination of aliasing patterns are unique to each experiment and are described in many Design of Experiments textbooks. The assumption is usually made that 3-way interactions such as BCD are negligible. An Analysis of Variance is then performed as shown in Table T14-4 to determine which factors have a significant effect on bonding strength. The steps involved in performing an Analysis of Variance for this example are:

5A. Calculate Sum of Squares: From Table T14-3 the Sum-of-Squares for a two level, single replicate experiment is computed for all factors and interactions as illustrated below for the A factor (Epoxy Type).

Sum of Sq. (Factor A) • # of treatment combinations ( A v g ( + ) . A v g W ) 2

Sum of Sq. (Factor A) = | (2.2S)2 = 10.125

5B. Calculate Error: The Sum of Squares for the error in this case is set equal to the sum of the Sum of Squares values for the three two-way interactions (i.e., AB or CD, AC or BD, BC or AD). This is known as pooling the error. This error is calculated as follows: Error = 1.125 + 1.125 + .125 = 2.375.

5C. Determine Degrees of Freedom. Degrees of Freedom is the number of levels of each factor minus one. Degrees of Freedom (df) is always 1 for factors and interactions for a two level experiment as shown in this simplified example. Degrees of Freedom for the error (dferr) in this case is equal to 3 since there are 3 interaction Degrees of Freedom, dtp denotes degrees of freedom for a factor.

5D. Calculate Mean Square. Mean Square equals the sum of squares divided by the associated degrees of freedom. Mean Square for a two level, single replicate experiment is always equal to the sum of squares for all factors. Mean Square for the error in this case is equal to the Sum of Squares error term divided by 3 (3 is the df of the error).

5E. Perform F Ratio Test for Signif icance. To determine the F ratio the mean square of the factor is divided by the mean square error (.792) from Table T14-4. F (a, dfp, d f e r r ) represents the critical value of the statistical F-distribution and is found in look-up tables in most any statistics book. Alpha (a) represents the level at which you are willing to risk in concluding that a significant effect is not present when in actuality it is. If the F ratio is greater than the looked up value of F (a, dfps dferr) then the factor


TESTING - TOPIC T10

does have a significant effect on the response variable. (F (.1,1,3) = 5.54 in this case).

As a word of caution the above formulations are not intended for use in a cookbook

Combination BCD ACD CD ABD BD AD ABC y 1 _ - + - + + - 73 2 + + + 88 3 + - + + 81 4 + + + 77 5 + _ _ + + 83 6 + + + 81 7 + + + - _ _ 74 8 + + + + + + + 90

Avg (+) 82 80.5 81.25 84 81.25 80.75 85.5 Avg (-) 79.75 81.25 80.5 77.75 80.5 81 76.25 A = Avg(+) -Ava (-) 2.25 -.75 .75 6.25 .75 -25 9.25

Values

Source Sum of

Squares Degrees of

Freedom Mean

Square F ratio* Signi f icant

Ef fec t

Epoxy Type (A) 10.125 10.125 12.789 Yes

Substrate Material (B) 1.125 1.125 1.421 No

Bake Time (C) 78.125 78.125 98.684 Yes

Substrate Thickness (D) 171.125 171.125 216.158 Yes

A x B or C x D 1.125 - - ~

A x C or B x D 1.125 - - -

B x Cor A x D 0.125

CD ABD BD AD ABC

Bonding Strength4

X

8

+ +

+ +

+

+

+

+

+

+

+

+

+ + +

+ + +

73 88 81 77 83 81 74 90

Avg (+) Avg(-) A = Avg(+) -Avg (-)

82 80.5 81.25 84 81.25 80.75 85.5 79.75 81.25 80.5 77.75 80.5 81 76.25

2.25 -.75 .75 6.25 .75 -25 9.25

The mean bonding strength calculated from this column is 80.875.

Table T14-4: Results of Analysis of Variance

Sum of Degrees of Mean Signi f icant Source Squares Freedom Square F ratio* Ef fec t

Epoxy Type (A) 10.125

Substrate Material (B) 1.125

Bake Time (C) 78.125

Substrate Thickness (D) 171.125

A x B or C x D

A x C or B x D

B x Cor A x D

Error

1.125

1.125

0.125

2.375

10.125 12.789

1.125 1.421

78.125 98.684

171.125 216.158

Yes

No

Yes

Yes

.792 'Example Calculation: F = Mean Square/Error = 10.1257.792 = 12.789


TESTING -T0P1CT14

Step 6 - Calculate Optimum Settings: From the Analysis of Variance, the factors A, C, and D were found to be significant at the 10% level. In order to maximize the response, i.e. bonding strength, we can determine optimum settings by inspecting the following prediction equation:

y = (mean bonding strength) + 2.25A + 6.25C + 9.25D

Since A, C, and D are the only significant terms they are then the only ones found in the prediction equation. Since A, C, and D all have positive coefficients they must be set at high to maximize bonding strength. Factor B, substrate material, which was found to be nonsignificant should be chosen based on its cost since it does not affect bonding strength. A cost analysis should always be accomplished to assure that all decisions resulting from designed experiments are cost-effective.

Step 7 - Do Confirmation Run Test: Since there may be important factors not considered or nonlinear effects, the optimum settings must be verified by test. If they check out, the job is done. If not, some new tests must be planned.

Design of Experiments References:

Barker, T. B., "Quality By Experimental Design," Marcel Dekker Inc., 1985.

Box, G.E.P., Hunter, W. G., and Hunter, J. S., "Statistics for Experiments," John Wiley & Sons, New York, 1978

Davies, O. L , "The Design and Analysis of Industrial Experiments," Hafner Publishing Co.

Hicks, C.R., "Fundamental Concepts in the Design of Experiments," Holt, Rinehart and Winston, Inc, New York, 1982

Schmidt, S. R. and Launsby, R. G., "Understanding Industrial Designed Experiments," Air Academy Press, Colorado Springs CO, 1989

Taguchi, G., "Introduction to Quality Engineering," American Supplier Institute, Inc, Dearborn Ml, 1986


TESTING - TOPIC T10

Topic T15: Accelerated Life Testing Accelerated life testing employs a variety of high stress test methods that shorten the life of a product or quicken the degradation of the product's performance. The goal of such testing is to efficiently obtain performance data that, when properly analyzed, yields reasonable estimates of the product's life or performance under normal conditions.

Why Use It?

Considerable savings of time and money

• Quantify the relationship between stress and performance

Identify design and manufacturing deficiencies

Why Not?

Difficulty in translating the stress data to normal use levels

High stress testing may damage systems

Precipitated failures may not represent use level failures

Test Methods Most accelerated test methods involving electronics are limited to temperature or voltage. However, other methods have included: acceleration, shock, humidity, fungus, corrosion, and vibration.

Graphical Analysis

The advantages are:

Requires no statistics

Easily translates the high stress data to normal levels

Very convincing and easy to interpret #

Provides visual estimates over any range of stress

Verifies stress/performance relations


TESTING - TOPIC T10

The disadvantages are:

Does not provide objectiveness

• Has statistical uncertainty

Relies on an assumed relationship which may not fit the data

Test Design All test conditions should be limited to three elevated stress levels (considering budget, schedule, and chamber capabilities) with the following conditions:

Test stress should exceed maximum operating limits

Test stress should not exceed maximum design limits

Stress levels only for normal use failure modes

Test Units The units shall be allocated to the particular stress levels so that most of the units are at the lower stress levels and fewer units at the higher. If 20 test units are available, a reasonable allocation would be 9 units at the lowest level and 7 and 4 at the higher levels. This allocation scheme is employed so that the majority of the test data is collected nearest to the operating levels of stress. Three units should be considered a minimum for the higher levels of stress; if fewer than 10 units are available for test, design for only two levels.

Data Analysis: Probability Plot The operational performance (time before failure in most cases) of nearly all electronic and electromechanical systems can be described by either the Lognormal or Weibull probability density functions (pdf). The pdf describes how the percentage of failures is distributed as a function of operating time. The probability plot of test data is generated as follows:

Rank the failure times from first to last for each level of test stress (nonfailed units close out the list).

For each failure time, rank i, calculate its plotting position as:

Where n is the total number of units on test at that level.

Plot P versus the failure time for each failure at each stress level on appropriately scaled graph paper (either Logarithmic or Weibull).


TESTING - TOPIC T10

Visually plot lines through each set (level of stress) of points. The lines should plot parallel, weighting the tendency of the set with the most data heaviest. If the lines do not plot reasonably parallel, investigate failure modes.

Data Analysis: Relationship Plot

The relationship plot is constructed on an axis that describes unit performance as a function of stress. Two of the most commonly assumed relations are the inverse Power and the Arrhenius Relationship. The relationship plot is done as follows:

On a scaled graph, plot the 50% points determined from the probability plot for each test stress.

Through these 50% points, plot a single line, projecting beyond the upper and lower points.

From this plot locate the intersection of the plotted line and the normal stress value. This point, read trom the time axis, represents the time at which 50% of the units will fail while operating under normal conditions.

Plot the time determined in step three on the probability plot. Draw a line through this point parallel to those previously drawn. This resulting line represents the distribution of failures as they occur at normal levels of stress.

Example: Probability and Relationship Plots Consider an electronic device life test that demonstrates an Arrhenius performance/stress relationship that fails lognormally at any given level of stress. Engineers wish to determine the unit s reliability (MTBF) at 90°C (maximum operating temperature). There are 20 units available for test.

After reviewing the design and considering the potential failure modes, the engineers concluded ihat the units could survive at temperatures in excess of 230°C without damage. The engineers did. however, estimate that non-regular failure modes will be precipitated above this temperature, therefore, 230°C was established as the maximum test level with 150°C and 180°C as interim stress levels. The test units were allocated to three test levels and run for 1000 hours. The resulting failure times are shown in Table T15-1.


TESTING - TOPIC T10

Table T15-1: Test Results

9 Units @ 150°C Time to Failure (Hrs.) Rank P

7 Units @ 180°C Time to Failure (Hrs.) Rank P

4 Units @ 230 C Time to Failure (Hrs.) Rank P

567 688 750 840 910 999

1 2 3 4 5 6 7 8 9

5.5 16.6 27.7 38.8 50.0 61.1

417 498 568 620 700 770 863

1 2 3 4 5 6 7

7.1 21.4 35.7 50.0 64.3 78.6 92.9

230 290 3t>0 410

1 2 3 4

12.5 37.5 62 5 87.5

* Unit still operating at 1000 hours

The probability and relationship plots are shown in Figures T15-1 & T15-2. From Figure T15-2 it is estimated that 50% of the units will fail by 3500 hours while operating at 90°C. Further, from Figure T15-1, it can be estimated that at 90°C, 10% of the units will fail by 2200 hours and 10% will remain (90% failed) at 5000 hours.

This type of testing is not limited to device or component levels of assembly. Circuit card and box level assemblies can be tested in a similar manner. Generally, for more complex test units, the probability plot will be developed on Weibull paper, while the relationship plot will likely require a trial and error development utilizing several inverse power plots to find an adequate fit.


TESTING - TOPIC T10

o l o o 1 o o 1 o LO 1 00 T— 1 Y-

^

(ainoH) eiuj i 6uiuuny

Figure T15-1: Lognormal Plot


TESTING - TOPIC T10

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Figure T15-2: Arrhenius Plot


TESTING-TOPICT16

Topic T16: Time Stress Measurement Environmental factors, such as temperature, humidity, vibration, shock, power quality, and corrosion impact the useful lifetime of electronic equipment. Knowing the environmental conditions under which the equipment is operated provides insight into equipment failure mechanisms. The capability to measure environmental parameters will help reduce and control the incidence of Retest OK (RTOK) and Cannot Duplicate (CND) maintenance events which account for 35% to 65% of the indicated faults in Air Force avionics systems. Many of these RTOK and CND events are environmentally related and a record of the environmental conditions at the time of occurrence should greatly aid in the resolution of these events.

Active Time Stress Measurement Devices (TSMD)

Module TSMD: The module developed by the Rome Laboratory is physically 6" x 4" x 1.25" and measures and records temperature, vibration, humidity, shock, corrosion and power transients. This module operates independently of the host equipment and records and stores data for later retrieval.

Micro TSMD: The micro version of the TSMD is a small hybrid circuit that is suitable for mounting on a circuit card in a Line Replaceable Unit (LRU). All the parameters measured by the module TSMD are recorded in the micro version.

Fault Logging TSMD: A new advanced device has been developed that is suitable for circuit board mounting and includes environmental parameters being measured prior to, during, and after a Built-in-Test (BIT) detected fault or event. The environment data will be used to correlate faults with environmental conditions such as temperature, vibration, shock, cooling air supply pressure, and power supply condition to better determine what impact environment has on system failure.

• Quick Reliabi l i ty Assessment Tool (QRAT): The objective of the effort is to build a stand-alone, compact, portable, easily attachable system for quick reaction measurement and recording of environmental stresses. The parameters it measures include voltage, temperature, vibration and shock. The system which includes a debrief laptop computer, an electronics module with internal sensors, a battery pack, remote sensors, various attachment plates, and will fit in a ruggedized suitcase. The electronics module is be 3" x 2" x 0.5" and contains the sensors, digital signal processor, and 512K bytes of EEPROM for storage of data. Three axis continuous vibration data will be recorded and stored in a power spectral density format. The user could choose to use either the sensors internal to the electronics module or the remote sensors. The debrief computer is used to tailor the electronics module to the specific needs of the user and to graphically display the collected data. Some potential uses for the collected data are: identification of environmental design envelopes, determination of loads and boundary


TESTING - TOPIC T10

conditions for input into simulation techniques, and characterization of failures in specific systems.

Passive Environmental Recorders

• High and Low Temperature Strip Recorders: Strip recorders offer a sequence of chemical mixtures deposited as small spots on a paper. Each spot changes color at a predetermined temperature showing that a given value has been exceeded.

• Temperature Markers: Markers are available to measure temperature extremes. The marking material either melts or changes color at predetermined temperatures.

• Humid i ty Str ip . Recorders: Using crystals that dissolve at different humidity levels, a strip recorder is available that indicates if a humidity level has been surpassed.

Shock Ind ica tors : Single value indicators that tell when an impact acceleration exceeds the set point along a single axis.

Application, Active Devices

Avionic Environmental Stress Recording

• Transportation Stress Recording

Flight Development Testing

Warranty Verification

• Aircraft: A-10, A-7, B-1, and EF-111

For More Information:

For more information on the active TSMD devices under development at Rome Laboratory, write:

Rome Laboratory/ERS Attn: TSMD 525 Brooks Rd. Griffiss AFB, NY 13441-4505


Appendix 1 Operational Parameter Translation


OPERATIONAL PARAMETER TRANSLATION

Because field operation introduces factors which are uncontrollable by contractors (e.g. maintenance policy), "contract" reliability is not the same as "operational" reliability. For that reason, it is often necessary to convert, or translate, from "contract" to "operational" terms and vice versa. This appendix is based on RADC-TR-89-299 (Vol I & II), "Reliability and Maintainability Operational Parameter Translation II" which developed models for the two most common environments, ground and airborne. The translation models are summarized in Table 1-1.

Definitions

Mean-Time-Between-Failure-Field (MTBFp) includes inherent maintenance events which are caused by design or manufacturing defects.

M T B F = Total Operating Hours or Flight Hours F " Inherent Maintenance Events

Mean-Time-Between-Maintenance-Field (MTBMp) consists of inherent, induced and no defect found maintenance actions.

MTBM - T o t a * Operating Hours or Flight Hours F ~ Total Maintenance Events

Mean-Time-Between Removals-Field (MTBRp) includes all removals of the equipment from the system.

MTBR - T o t a l Operating Hours or Flight Hours F ~ Total Equipment Removals

• Gp = is the predicted MTBF (i.e. MIL-HDBK-217).

• 0 D = is the demonstrated MTBF (i.e. MIL-HDBK-781). RF = is the equipment type or application constant. C = is the power on-off cycles per mission. D = is the mission duration.

Equipment Operating Hour to Flight Hour Conversion For Airborne Categories - MTBFp represents the Mean-Time-Between-Failure in Equipment Operating Hours. To obtain MTBFp in terms of flight hours (for both fighter and transport models), divide MTBFp by 1.2 for all categories except counter measures. Divide by .8 for counter measure equipment.

ROME LABORATORY RELIABILITY ENGINEER'S TOOLKIT A-3

OPERATIONAL PARAMETER TRANSLATION February 15,1993

Example Estimate the MTBM of a fighter radar given a mission length of 1.5 hours, two radar shutdowns per mission and a predicted radar MTBF of 420 hours. Using Model 1B in Table 1-1,

MTBFp = 8p-6 4 Rp ( § --57 = (420 hr . ) - " 1.7 ( ) " 5 7

MTBFp = 69 equipment operating hours between maintenance.

Since this is below the dependent variable lower bound of (.24)(420) = 101 hours, the estimated MTBMp is taken to be 101 equipment operating hours between maintenance. Since this equipment is often turned on for pre and post flight checkout, the number of flight hours between maintenance is somewhat less than the actual equipment operating hours. The number of flight hours between maintenance is approximately 101/1.2 = 84 hours.

A-4 ROME LABORATORY RELIABILITY ENGINEER'S TOOLKIT

OPERATIONAL PARAMETER TRANSLATION

Table 1-1: Reliability Translation Models

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Appendix 2 Example R&M Requirement Paragraphs


EXAMPLE R&M REQUIREMENT PARAGRAPHS

R J Reliability Requirements

Guidance: The use of the latest versions and notices of all military specifications, standards and handbooks should be specified. See Toolkit Section R, "Requirements" for task tailoring guidance. When specifying an MTBF, it should be the "upper test MTBF (G0)" as defined in MIL-STD-781. When specifying MTBCF, the maintenance concept needs to be clearly defined for purposes of calculating reliability of redundant configurations with periodic maintenance. If immediate maintenance will be performed upon failure of a redundant element then specifying the system MTTR is sufficient. If maintenance is deferred when a redundant element fails, then the length of this deferral period should be specified.

R.1.1 Mission Reliabil i ty: The (system name) shall achieve a mean-time-between-critical-failure (MTBCF) of hours under the worst case environmental conditions specified herein. MTBCF is defined as the total uptime divided by the number of critical failures that degrade full mission capability (FMC). FMC is that level of performance which allows the system to perform its primary mission without degradation below minimum levels stated herein. For purposes of analyzing redundant configurations, calculation of MTBCF shall reflect the expected field maintenance concept.

R.1.2 Basic Reliability: The (system name) shall achieve a series configuration mean-time-between-failure (MTBF) of hours under the worst case environmental conditions specified herein. The series configuration MTBF is defined as the total system uptime divided by the total number of part failures.

R.1.3 Reliability Configuration: The reliability requirements apply for the delivered configuration of the system. Should differences exist between this configuration and a potential production configuration, all analyses shall address the reliability effects of the differences.

Guidance: If equipment or system performance criteria are not stated elsewhere in the statement of work or specification, the following paragraph must be included.

R.1.4 Reliability Performance Criteria: The minimum performance criteria that shall be met for full mission capability of the (system name) system is defined as (specify full mission capability).

R.1.5 Reliability Design Requirements: Design criteria and guidelines shall be developed by the contractor for use by system designers as a means of achieving the required levels of reliability.

Guidance: For more critical applications, Level II or I, derating should be specified. See Topic D1 for derating level determination. Baseline thermal requirements such as ambient and extreme temperatures, pressure extremes, mission profile and



duration, temperature/pressure rates of change and maximum allowable temperature rise should be specified.

R.1.5.1 Thermal Management and Derating: Thermal management (design, analysis and verification) shall be performed by the contractor such that the reliability quantitative requirements are assured. RADC-TR-82-172, MRADC Thermal Guide for Reliability Engineers," shall be used as a guide. Derating criteria shall be established for each design such that all parts used in the system are derated to achieve reliability requirements. As a minimum, Level 3 of AFSC Pamphlet 800-27 "Part Derating Guidelines" shall be used for this design.

Guidance: If the system is for airborne use, MIL-STD-5400 must be referenced in place of MIL-E-4158 (ground equipment).

R.1.5.2 Parts Selection: All parts employed in the manufacture of the system shall be selected from the government generated and maintained Program Parts Selection List (PPSL), Electrical/Electronic Parts and the PPSL for Mechanical Parts. Parts not covered by the above referenced PPSLs shall be selected in accordance with MIL-E-4158 and MIL-STD-454 and require approval by the procuring activity.

a. M i c r o c l r c u i t s . Military standard microcircuits must be selected in accordance with Requirement 64 of MIL-STD-454. All non-JAN devices shall be tested in accordance with the Class B screening requirements of MIL-STD-883, Method 5004 and 5008, as applicable. All device types shall be tested to the quality conformance requirements of MIL-STD-883, Method 5005 and 5008 Class B.

b. Semiconductors. Military standard semiconductors must be selected in accordance with Requirement 30 of MIL-STD-454. All non-JANTX devices shall be screened in accordance with Table II of MIL-S-19500. All device types shall be tested to the Group A, Table III and Group B, Table IV quality conformance requirements of MIL-S-19500, as a minimum. The following device restrictions apply:

(1 ) Only solid glass metallurgical^ bonded axial lead diodes and rectifiers shall be used.

(2) TO-5 packages shall be limited to the solid metal header type. (3) All semiconductor device junctions must be protected and no organic

or desiccant materials shall be included in the package. (4) Devices using aluminum wire shall not use thermocompression wedge

bonding.

(5) Aluminum TO-3 packages shall not be used.

(6) Germanium devices shall not be used.



c. Electrostatic Sensitive Parts. Certain types of integrated circuits are susceptible to electrostatic discharge damage. Appropriate discharge procedures are necessary when handling, storing or testing these parts and design selections of desired devices should include a consideration of the effectiveness of the input or other protective elements included in the device design.

R.1.6 Reliability Test and Evaluation: The quantitative reliability levels required by paragraph (R.1) shall be verified by the following:

R.1.6.1 The final approved reliability analyses for the various configurations and worst case environments shall demonstrate compliance with the quantitative requirements cited in paragraph (R.1).

R.1.6.2 The contractor shall demonstrate that the reliability (mission and/or basic) requirements have been achieved by conducting a controlled reliability test in accordance with MIL-HDBK-781 Test Plan (specify MIL-HDBK-781 Test Plan). (See Topic T5 and Appendix 5 for Plan Selection). The lower test (MTBCF and/or MTBF) to be demonstrated shall be hours tested in a environment. Relevant failures are defined as any malfunction which causes loss or degradation below the performance level specified for the (equipment/system) and can be attributed to design defect, manufacturing defect, workmanship defect, adjustment, deterioration or unknown causes. Nonrelevant failures are failures caused by installation damage, external test equipment failures, mishandling, procedural errors, dependent failures and external prime power failures.

Guidance: A growth test may apply if the next phase is production. If one is required, it's appropriate to require a higher risk (e.g., 30 percent) demonstration test. See RADC-TR-84-20 "Reliability Growth Testing Effectiveness," Topic T4 and Appendix 6 for further guidance.

R.1.6.3 The contractor shall conduct a controlled fixed length dedicated reliability growth test of hours using MIL-HDBK-189 as a guide. The test shall be at the same environmental conditions as the RQT. Although there is no pass/fail criteria, the contractor shall track the reliability growth process to ensure improvement is taking place by effective implementation of corrective action.

Guidance: See Electronic Systems Center Report TR-85-148, "Derated Application of Parts for ESC Systems Development" (Attachment 2) for a recommended derating verification procedure.

R.1.6.4 The contractor shall verify the thermal and electrical stresses on percent (3 to 5 percent sample is typical) of the semiconductor and microcircuit parts by measurement while the equipment is operated at the worst case environment, duty cycle and load. The results of the measurements shall be compared to the derating requirements and the verification shall be considered successful if measured values are less than specified derated levels.



B^ impS® D ^ u l r a m a n E s to BSi© S M ^ ^ r S off

R„2 Reliability Program Tasks R.2.1 Reliability Program: The contractor shall conduct a reliability program in accordance with MIL-STD-785 including the following tasks as a minimum to assure reliability consistent with state-of-the-art.

R.2.2 Subcontractor Control: The contractor shall establish management procedures and design controls including allocation of requirements in accordance with Task 102 of MIL-STD-785 which will insure that products obtained from subcontractors will meet reliability requirements.

R.2.3 Reliability Design Reviews: The status of the reliability design shall be addressed at all internal and external design reviews. Task 103 of MIL-STD-785 shall be used as a guide.

R.2.4 Failure Reporting, Analysis and Corrective Action System (FRACAS): The contractor shall establish, conduct and document a closed loop failure reporting, analysis and corrective action system for all failures occurring during system debugging, checkout, engineering tests and contractor maintenance. Failure reports shall be retained by the contractor and failure summaries provided to the procuring activity thirty days after start of system engineering test and evaluation, and updated monthly thereafter. Failure reporting shall be to the piece part level.

R.2.5 Reliability Modeling: The contractor shall develop reliability models for all system configurations in accordance with Task 201 of MIL-STD-785 and Task 101 and 201 of MIL-STD-756. The specific mission parameters and operational constraints that must be considered are: (or reference applicable SOW and specification paragraphs).

R.2.6 Reliability Allocations: Reliability requirements shall be allocated to the LRU level in accordance with Task 202 of MIL-STD-785.

R.2.7 Reliability Prediction: The contractor shall perform reliability predictions in accordance with (Task 201 (basic reliability)) and/or (Task 202 (mission reliability)) of MIL-STD-756. The specific technique to be used shall be method 2005 parts stress analysis of MIL-STD-756. Electronic part failure rates shall be used from MIL-HDBK-217 and nonelectronic part failure rates from RADC-TR-85-194. All other sources of part failure rate data shall require review and approval of the procuring activity prior to use. A environmental factor, worst case operating conditions and duty cycles shall be used as a baseline for developing part failure rates. The results of the thermal analysis shall be included and shall provide the temperature basis for the predicted reliability. The part quality grade adjustment factor used shall be representative of the quality of the parts selected and applied for this system procurement.

R.2.8 Parts Program: The contractor shall establish and maintain a parts control program in accordance with Task 207 of MIL-STD-785 and Procedure 1 of MIL-STD-965. Requests for use of parts not on the government generated and



maintained PPSL shall be submitted in accordance with the CDRL. Amendments to the PPSL as a result of such requests, after procuring activity approval, shall be supplied to the contractor by the Program Contracting Officer not more often than once every 30 days.

Guidance:The level of detail of the FMECA must be specified (e.g., part, circuit card, etc.). The closer the program is to full scale engineering development, the greater the level of detail needed.

R.2.9 Failure Modes, Effects and Criticality Analysis (FMECA): The contractor shall perform a limited FMECA to the level to identify design weaknesses and deficiencies. Potential failure modes shall be identified and evaluated to determine their effects on mission success. Critical failures shall be investigated to determine possible design improvements and elimination means. MIL-STD-785, Task 204 shall be used as a guide.

Guidance: Reliability critical items should be required where it's anticipated that the design will make use of custom VLSI, hybrids, microwave hybrids and other high technology nonstandard devices. See Topic D5 for a critical item checklist.

R.2.10 Reliability Critical Items: Task number 208 of MIL-STD-785 applies. The contractor shall prepare a list of critical items and present this list at all formal reviews. Critical items shall include: items having limited operating life or shelf life, items difficult to procure or manufacture, items with unsatisfactory operating history, items of new technology with little reliability data, single source items, parts exceeding derating limits, and items causing single points of failure.

R.2.11 Effects of Storage, Handling, Transportation: The contractor shall analyze the effects of storage, handling and transportation on the system reliability.

R.2.12 Reliabil i ty Quali f ication Test: The contractor shall demonstrate compliance with the quantitative reliability requirements in accordance with MIL-STD-785 Task 302. Test plans and reports shall be developed and submitted.

R.2.13 Reliability Development/Growth Test: Test plans that show data tracking growth, testing methods and data collection procedures shall be developed and submitted for the Growth Test Program.

Guidance: When specifying ESS, the level (circuit card, module, assembly, etc.) at which the screening is to be performed must be specified. Different levels of screening should be performed at different hardware assembly levels. See R&M 2000 guidelines in Section T for recommended screening as a function of hardware assembly level.

R.2.14 Environmental Stress Screening: Task number 301 of MIL-STD-785 applies. A burn-in test of (specify the number of hours or temperature cycles) at temperature and vibration level extremes shall be performed at the

level. At least (hours/cycles) of failure free operation shall be experienced before termination of the burn-in test for each unit. DOD-HDBK-344, ESS of Electronic Equipment, shall be used as a guide.



EraropP® R s q p f e m ^ f e to Si® B y m m Specification ;

M.1 Maintainability Requirements M.1.1 Maintainability Quantitative Requirements: The (system name) shall be designed to achieve a mean-corrective-maintenance-time (MCT) of no greater than

minutes and a maximum-corrective maintenance-time (MMAXCT) of no greater than minutes (95th percentile) at the (specify organization, intermediate or depot level), when repaired by an Air Force maintenance technician of skill level or equivalent.

Guidance: Preventive maintenance requirements are considered an option to be implemented when items are used in the design that are subject to wearout, alignment, adjustment or have fault tolerance that must be renewed. If the option is exercised, then attach the paragraph below to M. 1.1.

M.1.2 Preventive maintenance shall not exceed minutes for eauh period and the period shall not be more frequent than every .

M.1.3 The mean time to restore system (MTTRS) following a system failure shall not be greater than . MTTRS includes all corrective maintenance time and logistics delay time.

M.1.4 The mean maintenance manhours (M-MMH) shall not be greater than hours per year. M-MMH is defined as follows: (operating hours per year) + (system MTBF) (system MTTR) (number of maintenance personnel required for corrective action).

Guidance Above definition of M-MMH assumes that a repair is made when each failure occurs. If a delayed maintenance concept is anticipated through the use of fault tolerance, then MTBCF should be used (instead of MTBF) in the above definition. If only a limited number of site visits are allowed, then this value should be used in the above definition in place of "operating hours per year + system MTBF/1

M.1.5 Maintainabil i ty Design: The system design shall provide modularity, accessibility, built-in-test (BIT) and other maintainability features to provide installation simplicity, ease of maintenance and the attainment of the maintainability requirements (both corrective and preventive). Line Replaceable Units (LRUs) such as printed circuit boards or assemblies shall be replaceable without cutting or unsoldering connections. All plug-in modules shall be mechanically keyed/coded to prevent insertion of a wrong module.



M.1.5.1 Testability: The system design shall be partitioned based upon the ability to isolate faults. Each item shall have sufficient test points for the measurement or stimulus of internal circuit nodes to achieve the capability of detecting 100 percent of all permanent failures using full resources. Automatic monitoring and diagnostic capabilities shall be provided to show the system status (operable, inoperable, degraded) and to detect 90 percent of all permanent failures. The false alarm rate due to self-test circuitry shall be less than 1 percent of the series failure rate. Self-test circuitry shall be designed to correctly isolate the fault to a group of four (4) LRUs, or less, 95 percent of the time.

M.1.6 Maintainability Test and Evaluation: Maintainability requirements for the (system name) shall be verified by the following:

M.1.6.1 Maintainability Analysis. The results of the final maintainability prediction shall be compared to the quantitative requirements and achievement determined if the predicted parameters are less than or equal to the required parameters.

M.1.6.2 Maintainability Demonstration. A maintainability demonstration shall be performed in accordance with Test Method (Test Method 9 is commonly specified, see Appendix 7 for further guidance) of MIL-STD-471. A minimum sample size of 50 tasks shall be demonstrated. The consumer's risk for the maintainability demonstration shall be equal to 10 percent. Fault detection and isolation requirements shall be demonstrated as part of the maintainability test.

M.1.6.3 Testability Demonstration. A testability demonstration shall be performed on the (system name) in accordance with Notice 2 of MIL-STD-471 A.



[^©mpE® B f l e ^ l n & k E I I ^ t o r fe® StstecmcTft o f W a r t

M.2 Maintainability Program Tasks M.2.1 Maintainability Program: The contractor shall conduct a maintainability program in accordance with MIL-STD-470 appropriately tailored for full scale development including the following tasks as a minimum to assure maintainability consistent with the requirements.

M.2.2 Testability Program: Testability characteristics and parameters are related to, and shall be treated as part of the maintainability program. The contractor shall conduct a testability program in accordance with MIL-STD-2165 appropriately tailored for FSD including the following tasks as a minimum to assure testability consistent with the requirements.

M.2.3 Maintainabil ity Design Review: The status of the maintainability/ testability design shall be addressed at all internal and external design reviews.

M.2.4 Subcontractor Control: The contractor shall specify maintainability requirements to all subcontractors to insure that (equipment/system name) requirements of this program are attained. Task 102 of MIL-STD-470 shall be used as a guide.

M.2.5 Maintainability/Testability Modeling: The contractor shall establish a maintainability model using MIL-STD-470, Task 201 which reflects the construction and configuration of the FSD design. Linkages with MIL-STD-2165, Task 201 to relate testability/diagnostic design characteristics to maintainability parameters shall be provided.

M.2.6 Maintainability Prediction: The contractor shall predict maintainability figures of merit using Procedure V of MIL-HDBK-472 (Notice 1) at the on equipment level. MIL-STD-470, Task 203 shall be used as a guide.

M.2.7 Maintainability/T estability Design Criteria: The contractor shall develop design criteria to be used in the design process to achieve the specified maintainability and testability requirements. In addition, a design analysis showing failure modes, failure rates, ease of access, modularity and the capability to achieve the fault detection/isolation requirement shall be provided. RADC-TR-74-308 "Maintainability Engineering Design Handbook," RADC-TR-82-189 "RADC Testability Notebook," Task 202 of MIL-STD-2165 and Task 206 of MIL-STD-470A shall be used as a guide.

Guidance: Maintainability demonstration reports are only necessary if a maintainability test is specified in the maintainability specification requirements.

M.2.8 Maintainability/Testability Demonstration: A test plan and test report shall be submitted by the contractor. Task 301 of MIL-STD-470 and Task 301 of MIL-STD-2165 shall be used as guides.


Appendix 3 R&M Software Tools


R&M SOFTWARE TOOLS

Several hundred R&M software tools exist throughout Government, industry and academia. Table 3-1 lists software tool types with associated supplier reference numbers. The numbered list of suppliers follows. The list includes addresses and telephone numbers confirmed to be accurate as of Aug 92. The Rome Laboratory doesn't in any way endorse or encourage use of any specific supplier's tools listed. Potential software tool users should thoroughly research any claims made by software suppliers and carefully study their own needs before obtaining any software. Further information on R&M software tools can be obtained in the reports referenced below. The reports contain data relative to software tool's hardware requirements, claimed capabilities, interface capabilities, demonstration package availability and price.

R&M Software Tool References RL-TR-91-87 "A Survey of Reliability, Maintainability, Suppoliability and

Testability Software Tools"

RMST 91 "R&M Software Tools," Reliability Analysis Center

Table 3-1: Software Tool Type/Supplier Reference Number Listing

Software Tool Type Supplier Reference Numbers

1. Reliability Prediction 1a. Component Prediction Tools (e.g. MIL-HDBK-

217, Bellcore, etc.) 1b. System Modeling (e.g. Markov, Monte Carlo,

Availability) 1c. Mechanical Component Data 2. Failure Mode and Effects Analysis (FMEA) 3. Fault Tree Analysis 4. Reliability Testing

(e.g. MIL-HDBK-781, ESS, etc.) 5. Reliability Management 6. Maintainability Prediction 7. Testability Analysis 8. Thermal Analysis 9. Finite Element Analysis 10. Statistical Analysis (e.g. Weibull) 11. Sneak Circuit Analysis 12. Design of Experiments 13. Logistics

1,5,9,10,15,16,17,19,20,21,27, 28,32,34, 36,38,39 1,5,6,17,19,20,22,32,33,35,36

15,27,31 1,5,19,20,21,27 I,5,14,16,17,18,21,22,32,33 13,16,18,25,32

32,35 5,10,17,19,21,27,32 2,3,4,5,19,21,23,24,30,32 26,32,38 8,26,32,37 II,12,16,25,29,40,41 32,35 25 1,5,17,20,21,38


R&M SOFTWARE TOOLS

R&M Software Tool Supplier Listing

1. Advanced Logistics Developments 11. PO Box 232 College Point NY 11356 (718)463-6939

2. ARINC Research Corp 12. 2551 Riva Road Annapolis MD 21401 (301)266-4650

3. Automated Technology Systems Corp 25 Davids Drive 13. Hauppauge NY 11788 (516)231-7777

4. CINA, Inc. PO Box 4872 14. Mountain View CA 94040 (415)940-1723

5. COSMIC 382 East Broad St 15. Athens GA 30602 (404)542-3265

6. Decision Systems Assoc 746 Crompton 16. Redwood City CA 94061 (415)369-0501

7. DETEX Systems, Inc. 1574 N. Batavia, Suite 4 17. Orange CA 92667 (714)637-9325

8. Engineering Mechanics Research Corp PO Box 696 Troy Ml 48099 (313)689-0077

9. Evaluation Associates Inc. GSB Building, 1 Belmont Ave Bala Cynwyd PA 19004 (215)667-3761

10. Evaluation Software 2310 Claassen Ranch Lane Paso Robles CA 93446 (805)239-4516

Fulton Findings 1251 W. Sepulveda Blvd #800 Torrance CA 90502 (310)548-6358

G.R. Technologies (Pister Grp) PO Box 38042 550 Eglinton Ave, West Toronto Ontario, M5N 3A8 (416)886-9470

H&H Servicco PO Box 9340 North St. Paul MN 55109 (612)777-0152

Idaho National Engineering Lab EG&G Idaho, Inc. Idaho Falls ID 83415 (208)526-9592

Innovative Software Designs, Inc. Two English Elm Court Baltimore MD 21228 (410)788-9000

Innovative Timely Solutions 6401 Lakerest Court Raleigh NC 27612 (919)846-7705

Item Software Ltd 3031 E. LaJolla St Anaheim CA 92806 (714)666-8000

18. JBF Associates 1000 Technology Park Ctr Knoxville TN 37932 (615)966-5232

19. JORI Corp 4619 Fontana St Orlando FL 32807 (407)658-8337

20. Logistic Engineering Assoc 2700 Navajo Rd, Suite A El Cajon CA 92020 (619)697-1238


R&M SOFTWARE TOOLS

21. Management Sciences Inc. 6022 Constitution Ave, N.E. Albuquerque NM87110 (505)255-8611

22. Energy Science & Technology Software Ctr PO Box 1020 Oak Ridge TN 37831 (615)576-2606

23. Naval Air Warefare Ctr/AD, ATE Software Center Code PD22 Lakehurst NJ 08733 (908)323-2414

24. NAVSEA Code 04 D52 Washington DC 20362 (703)602-2765

25. Nutek, Inc. 30400 Telegraph Rd, Suite #380 Birmingham Ml 48010 (313)642-4560

26. Pacific Numerix Corporation 1200 Prospect St, Suite 300 La Jolla CA 92037 (619)587-0500

27. Powertronic Systems, Inc. 13700 Chef Menteur Hwy New Orleans LA 70129 (504)254-0383

28. Prompt Software Co 393 Englert Court San Jose CA 95133 (408)258-8800

29. Pritsker Corporation 8910 Perdue Rd, Suite 500 Indianapolis IN 46286 (317)879-1011

30. RACAL-REDAC 1000 Wyckoff Ave Mahwah NJ 07430 (201)848-8000

31. Reliability Analysis Center (RAC) PO Box 4700, 201 Mill St Rome NY 13440 (315)337-0900

32. Rome Laboratory/ERS 525 Brooks Rd Griffiss AFB NY 13441-4505 (315)330-4205

33. SAIC 5150 El Camino Real, Suite C-31 Los Altos CA 94022 (415)960-5946

34. Sendrian Resources Corp (SRC) 42 San Lucas Ave Newbury Lake CA 91320 (805)499-7991

35. SoHaR Incorporated 8421 Wilshire Blvd, Suite 201 Beverly Hills CA 90211 (213)653-4717

36. Spentech Company 2627 Greyling Drive San Diego CA 92123 (619)268-3742

37. Swanson Analysis Systems Inc. Johnson Rd, PO Box 65 Houston PA 15342 (412)746-3304

38. Systems Effectiveness Assoc 20 Vernon Street Norwood MA 02062 (617)762-9252

39. T-Cubed Systems, Inc. 31220 La Baya Dr, Suite 110 West lake Village CA 91362 (818)991-0057

40. Team Graph Papers Box 25 Tamworth NH 03886 (603)323-8843

41. Teque, Inc. 11686 N. Daniels Dr. Germantown Wl 53022 (414)255-7210


Appendix 4 Example Design Guidelines


EXAMPLE DESIGN GUIDELINES

This Appendix contains an example set of design guidelines structured to include verification methods. These guidelines are an example only and don't apply to all situations.

a. Thermal Design

(1) Integrated Circuit Junction Temperatures

Design Guidelines: The design of the environmental cooling system (ECS) should be capable of maintaining an average integrated circuit junction temperature of 55°C or less under typical operating conditions. Under worst case steady state conditions, components should operate at least 50°C below their rated maximum junction temperature.

Analysis Recommendation: Thermal finite element analysis should be performed to project operating temperatures under specified environmental conditions. The analysis should consider ECS performance, environmental impacts, and system thermal design. Average junction temperatures should include all integrated circuits within the system. Average temperature rise should include all components on an individual module.

Test Recommendations: Thermally instrumented observations should be made of components under specified environmental conditions. Instrumentation can be by direct contact measurement or by infrared photography.

(2) Thermal Gradients

Design Guideline: The maximum allowable temperature rise from any junction to the nearest heat sink should be 25°C. The average temperature rise from integrated circuit junctions to the heat sink should be no greater than 15°C. To minimize gradients, more complex and power-intensive devices should be placed to minimize their operating temperature.

Analysis Recommendation: Automated design tools that perform component placement should be programmed to produce this result. A thermal finite element analysis should be used to evaluate the projected thermal gradient under the specified environmental conditions.

Test Recommendation: Thermally instrumented observation of components under specified environmental conditions. Instrumentation can be by direct contact measurement or by infrared photography.

(3) Thermal Expansion Characteristics

Design Guideline: Component and board materials should be selected with compatible thermal coefficients of expansion (TCE). Additionally, coldplate materials should be selected for TCE compatibility with the attached printed wiring board. TCE mismatch results in warpage of the laminated assembly, which can reduce module clearances and stress circuit board component leads and solder joints.

ROME LABORATORY RELIABILITY ENGINEERS TOOLKIT A-25


Analysis Recommendat ion: A finite element analysis should be performed to identify the stress patterns in the solder joints attaching the components to the board. I C E compatibility should be evaluated for the components, circuit board, and coldplate.

Test Recommendat ion: Environmental stress tests should be utilized in the development phase to verify the design analysis and environmental stress screening should be used in production to ensure consistency throughout the production cycle.

(4 ) Heat Transport Media

Design Guideline: The design should use a thermal conduction medium that is integral to the mechanical design of the board or module. Heat pipes, metal rails or internal planes are examples of thermally conductive media. The unit should meet temperature design requirements by cooling through the integral thermal conduction medium without depending on any other heat loss.

Analysis Recommendation: Thermal finite element analysis should be used to project heat flow under specified environmental conditions. Modules employing heat pipes for cooling should meet operating temperature requirements when the module heat sink is inclined at an angle of 90 degrees from the horizontal.

Test Recommendat ion: Thermally instrumented observation should be made of components under specified environmental conditions. Instrumentation can be by direct contact measurement or by infrared photography.

(.5) Component A t tachment

Des ign Gu ide l ine : Surface contact should be maximized between the component and the heat transport media. This can be achieved by direct pressure thermal compounds or solder. The technique used should be reversible for component removal during board repairs such that damage is not induced to nearby devices. If a thermal compound is used, it should not migrate or react with other components during testing or service use.

Analysis Recommendation: Specialized stress analyses should be performed to quantify thermal and mechanical stresses involved in removing the component from the board after production installation.

Test Recommenda t i on : Demonstration of repair techniques should be performed early in the development phase.

(6 ) Thermal Cycl ing

Des ign Gu ide l ine : The unit should be designed to dampen its thermal response to the thermal excursions required by the specification. This can be achieved by using a large thermal mass or by using the cooling medium to insulate the unit from its environment to the maximum extent possible.



Analysis Recommendation: Thermal finite element analysis to project heat flow and temperature excursions under specified environmental conditions.

Test Recommendation: Thermally instrumented observation of components under specified environmental excursions. Instrumentation can be by direct contact measurement or by infrared photography.

b. Testability Design (1) Bottom-up Fault Reporting

Design Guideline: Incorporate autonomous self-testing at the lowest levels that are technically feasible. Utilize positive indication to report chip, module and subsystem status. The design should not depend upon external stimuli to perform fault detection or isolation to a replaceable element.

Analysis Recommendation: As soon as automated testability analysis tools become available, they should be used for the applicable engineering design workstations.

Test Recommendation: Hardware demonstration should be conducted early in the development phase to verify simulation results through the insertion of faults using the currently available version of the operational program, firmware and microcode.

(2) Fault Logging

Design Guideline: Modules should contain a non-volatile fault log that can be accessed by a system maintenance controller or by test equipment. The use of the fault log will improve reliability by reducing depot "Cannot Duplicates." Failure of the fault log should not cause a critical system failure, but should be observable to the maintenance controller.

Analysis Recommendation: Compliance should be verified by inspection. Operation should be verified by simulation.

Test Recommendation: Not applicable.

(3) Start-up Bullt-ln-Test (BIT)

Design Guideline: The module should execute a BIT internal diagnostic routine immediately after power-up or receipt of an "Execute BIT" command. BIT should provide a complete functional test of the module to the maximum extent possible without transmitting any signals on external interface media. BIT should provide a complete functional test of the module and should include:

(1) Verification of internal data paths

(2) Verify station physical address



(3) Verify message identification process from system

(4) Verify proper functioning of all internal memory and other components

Any failure encountered during execution of BIT should be retried at lease once to confirm the response. Any confirmed failures should prevent the module from becoming enabled. A failed module should respond only to "RESET," "Execute BIT," and "Report Status" commands.

Analysis Recommendation: System design simulation tools should be used to verify operation of the BIT. These tools should include fault simulations as well as operational simulation.

Test Recommendation: Hardware demonstration should be conducted early in the development phase to verify simulation results through insertion of faults using currently available versions of the operational program, firmware and microcode.

(4) Background Diagnostics

Design Guideline: During normal operation, the module should continuously monitor itself through a background diagnostic test. The background diagnostic should provide coverage to the maximum extent possible without interfering with normal station operation. Failure of any test in the background diagnostic should cause the module to re-execute the failed test to screen out transient anomalous responses. If the failure is confirmed, the module should become immediately disabled.

Analysis Recommendation: System design simulation tools should be used to verify operation of the BIT. These tools should include fault simulations as well as operational simulation.

Test Recommendation: Hardware demonstration should be conducted early in the development phase to verify simulation results through insertion of faults using currently available versions of the operational program, firmware and microcode. Hardware demonstration may be performed by physically inserting faults in a module or by instrumenting a module to allow insert»on of faults through external methods.

c. Mechanical Packaging Design

(1) Mechanical Insertion/Extraction-Induced Stresses

Design Guideline: Each module should withstand, without damage or separation, a minimum force equal to at least 100 pounds on insertion and four ounces per contact on extraction. Additionally, the backplane for the assembly should withstand the same forces at all module positions applied repeatedly in any sequence with any combination of modules present or missing.

Analysis Recommendation: A mechanical loads analysis should be performed to verify compliance with the mechanical requirements.

A-28 ROME LABORATORY RELIABILITY ENGINEERS TOOLKIT


Test Recommendation: The total computed force should be applied to simulate module insertion and extraction. The force should be applied in 2 seconds and maintained for 15 seconds.

(2) Insertion/Extraction Durability

Design Guideline: Modules should be capable of withstanding 500 cycles of mating and unmating with no degradation of module performance. The module should also be capable of withstanding 500 cycles of lateral displacement to simulate the use of thermal clamping devices. The backplane of the module's host assembly should be capable of withstanding 500 of the same cycles on each of its module positions.


Test Recommendation: Each module/backplane position should be subjected to 500 cycles of insertion/extraction. The maximum specified insertion and extraction forces should be applied in 2 seconds and maintained for 15 seconds. Five hundred lateral displacement cycles should be applied to the module.

(3) Mechanical Vibration-Induced Stresses

Design Guideline: The larger components are more susceptible to mechanical stresses because they have a larger mass and because they are more constrained by the high number of pin-outs that act as attachment points. Module stiffness should be maximized to prevent board flexing resulting in stress fractures at the solder joints or component leadframe.

Analysis Recommendation: Mechanical finite element analysis should be performed to identify module characteristics throughout the specified vibrational environment.

Test Recommendation: Developmental units should be specially instrumented with accelerometers early in the development program. These units could use dummy masses attached using the intended production technique. Standard endurance and qualification tests should be performed in accordance with MIL-STD-810, "Environmental Test Methods and Engineering Guidelines."

(4) Module Torque Stresses

Design Guidelines: The module should be capable of withstanding a 6 inch-pound torque applied in 2 seconds and maintained for 15 seconds in both directions along the header in a direction perpendicular to the plane of the header without detrimental effect to the mechanical or electrical properties of the module.




Test Recommendation: The required torque should be applied in 2 seconds and maintained for 15 seconds. During the time the torque is applied, the module should be rigidly supported with a zone between the interface plane and 0.5 inch above the interface panel.

(5) Module Cantilever Load

Design Guideline: The module should be capable of withstanding a force of 2 pounds applied perpendicular to the header height along the center line midway between the two extractor holes.


Test Recommendation: The required force should be applied in two directions and should be applied in 2 to 10 seconds and maintained for 10 to 15 seconds without detrimental effect to the header structure.

(6) Module Retention

Design Guideline: Module retention techniques must be carefully designed to integrate the insertion mechanism, required connector insertion force, thermal contact area, and extraction mechanism. Conventional electronics have required the same considerations, but to a lesser degree because of their more conventional housings.

Analysis Recommendation: Specialized analyses should be used to quantify torque requirements and limitations of the wedge-clamping device, lever moments of insertion or extraction devices, tolerance buildups of the module slot and connector placement and mechanical deflections of the backplane.

Test Recommendations: Standard endurance and qualification tests in accordance with MIL-STD-810, "Environmental Test Methods and Engineering Guidelines."

(7) Connector Contact Integrity

Design Guideline: Each contact pin, as mounted in the connector, should withstand a minimum axial force of 20 ounces.


Test Recommendation: The required force should be applied in 2 seconds along the length of the contact in either direction and maintained for 15 seconds.



(8) Connector Float

Design Guideline: The connector-to-module Interface should be sufficiently flexible to compensate for specified misalignments or tolerance buildup between the module and the backplane connector shells.

Analysis Recommendation: Tolerance review should be performed early In design process.

Test Recommendation: Demonstration testing can be performed easily during the Initial mechanical design phase.

(9) Keying Pin Integrity

Design Guideline: When installed in the module, the keying pins should meet the following integrity requirements. Each keying pin should withstand a:

Torque of 20 inch-ounces

Pullout force of 9 pounds

Pushout force of 40 pounds

Cantilever load of 10 pounds


Test Recommendation: The required forces should be applied to the keying pin in 2 seconds and maintained for 15 seconds.

d. Power Supply Design

(1) Overcurrent Protection

Design Guideline: The power supply should supply 125 percent of its rated output for 2 ± 0.25 seconds, after which the power supply will shut down (shut down is defined as all outputs at less than 1 mv and 1 ma current, but all status and control lines still operating). Operation should not resume until the power supply is reset. In addition, the power supply outputs should be short circuit protected.

Analysis Recommendation: Compliance with the specified operation should be verified throughout the design process.

Test Recommendation: Specified operation of the protective device should be induced by application of the anomalous condition protected against. Correct operation of the protective device should be observed. Normal specified power supply operation should be verified after removal of the anomalous condition.



(2) Overvoltage Protection

Design Guidel ine: The output should be sensed for overvoltage. An overvoltage on the output should immediately shut down the power supply. Operation should not resume until the power supply is reset. The overvoltage limits should be compatible with device logic absolute maximum limits. The overvoltage protection and sense circuits should be constructed such that an overvoltage on a failed power supply will not cause any other paralleled power supply to also shut down.



(3) Abnormal Thermal Operation

Design Guideline: In the event of an above-normal internal temperature, the power supply should be capable of continued operation at a reduced power output. Thermal sense circuits should regulate the output to the extent necessary to keep semiconductor junctions at or below specified levels. The power supply should resume operation at rated output if internal temperatures return to normal.



(4) Thermal Shutdown

Design Guideline: When thermal limiting is no longer capable of maintaining internal temperature at an acceptable level, the power supply should automatically shut down. Operation should not resume until the power supply is reset. Temperature sense circuits should remain active during shut down.





(5) Power Supply Status Reporting

Design Guideline: There should be an interface on each power supply module that will allow data communication between the power supply and a CPU located on a separate module. Each power supply module will be addressed individually. The data and control lines should interface to the power supply module through the backplane connector. The following power supply parameters should be read by the CPU:

Overcurrent status

Overvoltage status

Thermal limiting mode status

Thermal shutdown status

Percentage of full output power available

The following commands should be issued by the CPU to the power supply module:

Reset

Percentage of full output power required


Test Recommendation: Specified operation of the protective device (i.e., monitoring mechanism and control) should be induced by application of the anomalous condition protected against. Correct operation of the protective device should be observed. Normal specified power supply operation should be verified after removal of the anomalous condition.

(6) Power Supply Input Protection

Design Guideline: The power supply should automatically shut down if the input voltage is not within the specified allowable range, and at any time when the control circuits in the power supply do not have adequate voltage to regulate the outputs. This should include the time during normal start-up when generators are not producing their normal output voltage.





(7) Backplane Conditions

Design Guideline: A sufficient number of connector pins should be paralleled so that no backplane connector pin carries more than 5 amps of current.



(8) M-of-N Power Supply Redundancy

Design Guideline: The quantity of power supplies for a system of functional elements should be determined to allow uninterrupted operation if one of the power supplies fails. When all power supplies are functional, they should share the system load equally by operating at reduced output. If the system power requirement is less than that available from one power supply, redundancy should not be used unless a critical function is involved.

Analysis Recommendation: Compliance should be verified by electrical loads analysis.


(9) Current Sharing

Design Guideline: The power supplies should be constructed so that units which have the same output voltage may operate in parallel. The design should be such that power supply failures will not cause degradation of parallel power supplies. Each power supply should provide its proportional share (±10%) of the total electric load required at the configured output voltage.

Analysis Recommendation: Compliance with the specified operation should be verified as a part of the design process.

Test Recommendation: A demonstration should be conducted under load to verify that the parallel power supplies power up and power down in unison. Failure and reset of one of the power supplies should be simulated or induced to demonstrate proper operation of the remaining units through the transition.

(10) Protective Device Operation

Design Guideline: During parallel operation, each power supply protective device should be capable of sensing and operating independently of the other power supplies. Master-slave type operation should not be permitted under any circumstances.

Analysis Recommendation: Compliance with the specified operation should be verified as a part of the design process.



Test Recommendation: A demonstration should be conducted under load to verify proper operation of each protective device during parallel operation.

e. Memory Fault Tolerance (1) Block Masking

Design Guideline: Known locations of defective memory should be mapped out of the memory directories. In this manner, permanently failed cells can be prevented from contributing to double error occurrences in combination with soft errors. At power-up or reinitialization, BIT should perform a memory test routine and leave a memory map of all good blocks. At the conclusion of the memory test routine, all words contained in the memory blocks marked good should have been initialized in an error free data pattern. Program loader software should make use of the good memory block map, the process memory mapping registers, and information stored in program file headers to load distributed operating systems and application programs into the remaining good areas of main memory. Repair or replacement of the module should not be required until the number of remaining good blocks of memory are insufficient to meet operational requirements.

Analysis Recommendation: An analysis should be performed to identify the optimum combination of component/bit mapping, hardware control and software control.


(2) Error Detection/Correction

Design Guideline: As a minimum, single error correct/double error detect code should be used in large bulk semiconductor memories. It should be considered in any application involving large amounts of semiconductor memory, but may impose unacceptable speed and complexity penalties in some applications (e.g., CPU).

Analysis Recommendation: A detailed timing analysis should be conducted to determine the impact of this technique on the specific application.

Test Recommendation: System bench testing should be used to insert faults and confirm expected system operation.


Appendix 5 Reliability Demonstration Testing


RELIABILITY DEMONSTRATION TESTING

1 . 0 Reliabil i ty Demonstrat ion Test ing: This appendix presents tables and examples which summarize the following:

MIL-HDBK-781 "Reliability Test Methods, Plans and Environments for Engineering Development, Qualification and Production"

Confidence Interval Calculations

Poisson's Exponential Binomial Limits

2 . 0 MIL-HDBK-781 Test Plans: Tables 5-1 and 5-2 summarize standard test plans as defined in MIL-HDBK-781. These plans assume an exponential failure distribution. For nonexponential situations the risks are different.

The fixed length test plans (Table 5-1) must be used when the exact length and cost of the test must be known beforehand and when it is necessary to demonstrate a specific MTBF to a predetermined confidence level by the test as well as reach an accept/reject decision.

The probability ratio sequential test (PRST) plans (Table 5-2) will accept material with a high MTBF or reject material with a very low MTBF more quickly than fixed length test plans having similar risks and discrimination ratios. However, different MTBF's may be demonstrated by different accept decision points for the same test plan and the total test time may vary significantly.

Additional guidance on test plan selection is provided in Section T, Topic T5.

2 . 1 Fixed Length Test Plan Example: If the design goal MTBF (Oq) for a system is specified as 750 hours and Test Plan XID is chosen, the following statements can be made:

a. There is a 20 percent probability of rejecting a system whose true MTBF is 750 hours (producers risk).

b. There is a 20 percent probability of accepting a system whose true MTBF is 500 hours (consumers risk).

c. The lower test MTBF (8|) is 500 hours (750/1.5).

d. The duration of the test is 10,750 hours (21.5 x 500).

e. The test will reject any system which experiences 18 or more failures.

f. The test will accept any system which experiences 17 or less failures.


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2 .2 PRST Test Plan Example: If the design goal MTBF (0O) for a system is specified as 750 hours and Test Plan SID is chosen, the following statements can be made:

a. There is a 20 percent probability of rejecting a system whose true MTBF is 750 hours (producers risk).

b. There is a 20 percent probability of accepting a system whose true MTBF is 500 hours (consumers risk).

, c. The lower test MTBF (0i) is 500 hours (750/1.5).

d. The minimum time to an accept decision is 2095 hours (4.19 x 500). e. The expected time to an accept decision is 5700 hours (11.4 x 500).

(Expected time to decision based on assumption of a true MTBF equal to 0o).

f. The maximum time to reach an accept decision is 10950 hours (21.9 x 500).

3 . 0 Confidence Level Calculat ion (Exponential Dis t r ibut ion) : There are two ways to end a reliability test, either on a specified number of failures occurring (failure truncated), or on a set period of time (time truncated). There are usually two types of confidence calculations of interest, either one sided (giving the confidence that an MTBF is above a certain value) or two sided (giving the confidence that an MTBF is between an upper and lower limit). Table 5-4 provides a simple means to estimate one or two sided confidence limits. Multiply the appropriate factor by the observed total life (T) to obtain the desired confidence interval.

Example 1 - Failure Truncated Test with Replacement: Twenty items are tested and replaced until 10 failures are observed. The tenth failure occurs at 80 hours. Determine the mean life of the items and the one-sided and two-sided 95% confidence intervals for the MTBF.

Solution: The mean life is (20 items) (80 hours/items) /10 failures = 160 hours. From Table 5-4, Note 2 applies, d = (2)(10) = 20. The following factors are obtained from the table:

95% two-sided lower factor = .0585 95% two-sided upper factor = .208 95% one-sided lower factor = .0635

Multipling these factors by 1600 total part hours (i.e., (20 items) (80 hours/item)) results in a 95% confidence that the MTBF is between 94 hours and 333 hours, or a 95% confidence that the MTBF is at least 102 hours.



Table 5-4: Factors for Calculation of Mean Life Confidence Intervals from Test Data

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Example 2 - Time Terminated Test without Replacement: Twenty items are placed on test for 100 hours with seven failures occuring at the 10, 16, 17, 25, 31, 46 and 65 hour points. Determine the one-sided lower 90% confidence

Solution: The total number of part hours accumulated is:

10 + 16 + 17 + 25 + 31 +46+ 65+ (13 non-failed items) (100 hours) = 1510 hrs.

The MTBF is 1510 hours/7 failures = 216 hrs.

From Table 5-4, Note 3 applies, d = 2(7+1) = 16.

The factor from the table is .0848 for the 90% one-sided lower limit. Therefore, we are 90% confident that the MTBF is greater than (.0848)(1510 hours) = 128 hours.

4 . 0 Poisson Distribution: The Poisson distribution is useful in calculating the probability that a certain number of failures will occur over a certain length of time for systems exhibiting exponential failure distributions (e.g., non-redundant electronic systems). The Poisson model can be stated as follows:

where P(r) = probability of exactly r failures occurring

X = the true failure rate per hour (i.e., the failure rate which would be exhibited over an infinite period)

t = the test time

r = the number of failure occurrences

e = 2.71828

! = factorial symbol (e.g., 4! = 4 x 3 x 2 x 1 = 24, 0! = 1,1! = 1 )

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ftz a


Appendix 6 Reliability Growth Testing


RELIABILITY GROWTH TESTING

1 .0 RGT Definition: MIL-STD-785 distinguishes reliability growth testing (RGT) from reliability qualification testing (RQT) as follows:

Reliability Growth Test (RGT): A series of tests conducted to disclose deficiencies and to verify that corrective actions will prevent recurrence in the operational inventory. (Also known as "TAAF" testing).

Reliability Qualification Test (RQT): A test conducted under specified conditions, by, or on behalf of, the government, using items representative of the approved production configuration, to determine compliance with specified reliability requirements as a basis for production approval. (Also known as a "Reliability Demonstration," or "Design Approval" test.)

2 . 0 RGT Application Effectiveness: An effective way to explain the concept of RGT is by addressing the most frequently asked questions relative to its use as summarized from "Reliability Growth Testing Effectiveness" (RADC-TR-84-20). For more information consult this reference and MIL-HDBK-189, "Reliability Growth Management."

Who pays for the RGT? Does the government end up paying more? The usual case is that the government pays for the RGT as an additional reliability program cost and in stretching out the schedule. The savings in support costs (recurring logistics costs) exceed the additional initial acquisition cost, resulting in a net savings in Life Cycle Cost (LCC). The amount of these savings is dependent on the quantity to be fielded, the maintenance concept, the sensitivity of LCC to reliability and the level of development required. It is the old "pay me now or pay me later situation" which in many cases makes a program manager's situation difficult because his or her performance is mainly based on the "now" performance of cost and schedule.

Does RGT allow contractors to "get away with" a sloppy initial design because they can fix it later at the government's expense? It has been shown that unforeseen problems account for 75% of the failures due to the complexity of today's equipment. Too low an initial reliability (resulting from an inadequate contractor design process) will necessitate an unrealistic growth rate in order to attain an acceptable level of reliability in the allocated amount of test time. The growth test should be considered as an organized search and correction system for reliability problems that allows problems to be fixed when it is least expensive. It is oriented towards the efficient determination of corrective action. Solutions are emphasized rather than excuses. It can give a nontechnical person an appreciation of reliability and a way to measure its status.

Should all development programs have some sort of growth program? The answer to this question is yes in that all programs should analyze and correct failures when they occur in prequalification testing. A distinction should be in the level of formality of the growth program. The less challenge there is to the state-of the-art, the less formal (or rigorous) a reliability growth program should be. An extreme example would be the case of procuring off-the-shelf equipment to be part of a military system. In this situation, which really isn't a development, design flexibility to correct reliability problems is mainly constrained to newly developed



interfaces between the "boxes" making up the system. A rigorous growth program would be inappropriate but a failure reporting and corrective action system (FRACAS) should still be implemented. The other extreme is a developmental program applying technology that challenges the state-of-the-art. In this situation a much greater amount of design flexibility to correct unforeseen problems exists. Because the technology is so new and challenging, it can be expected that a greater number of unforeseen problems will be surfaced by growth testing. All programs can benefit from testing to find reliability problems and correcting them prior to deployment, but the number of problems likely to be corrected and the cost effectiveness of fixing them is greater for designs which are more complex and challenging to the state-of-the-art.

How does the applicability of reliability growth testing vary with the following points of a development program?

(1) Complexity of equipment and challenge to state-of-the-art? The more complex or challenging the equipment design is, the more likely there will be unforeseen reliability problems which can be surfaced by a growth program. However, depending on the operational scenario, the number of equipments to be deployed and the maintenance concept, there may be a high LCC payoff in using a reliability growth program to fine tune a relatively simple design to maximize its reliability. This would apply in situations where the equipments have extremely high usage rates and LCC is highly sensitive to MTBF.

(2) Operational environment? All other factors being equal, the more severe the environment, the higher the payoff from growth testing. This is because severe environments are more likely to inflict unforeseen stress associated with reliability problems that need to be corrected.

(3) Quantity of equipment to be produced? The greater the quantities of equipment, the more impact on LCC by reliability improvement through a reliability growth effort.

What reliability growth model(s) should be used? The model to be used, as MIL-HDBK-189 says, is the simplest one that does the job. Certainly, the Duane is most common, probably with the AMSAA developed by Dr. Larry H. Crow of the Army Materiel Systems Analysis Activity second. They both have advantages; the Duane being simple with parameters having an easily recognizable physical interpretation, and the AMSAA having rigorous statistical procedures associated with it. MIL-HDBK-189 suggests the Duane for planning and the AMSAA for assessment and tracking. When an RQT is required, the RGT should be planned and tracked using the Duane model; otherwise, the AMSAA model is recommended for tracking because it allows for the calculation of confidence limits around the data.

Should there be an accept/reject criteria? The purpose of reliability growth testing is to uncover failures and take corrective actions to prevent their recurrence. Having an accept/reject criteria is a negative contractor incentive towards this purpose. Monitoring the contractor's progress and loosely defined



thresholds are needed but placing accept/reject criteria, or using a growth test as a demonstration, defeat the purpose of running them. A degree of progress monitoring is necessary even when the contractor knows that following the reliability growth test he will be held accountable by a final RQT. Tight thresholds make the test an RQT in disguise. Reliability growth can be incentivized but shouldn't be. To reward a contractor for meeting a certain threshold in a shorter time or by indicating "if the RGT results are good, the RQT will be waived," the contractor's incentive to "find and fix" is diminished. The growth test's primary purpose is to improve the design, not to evaluate the design.

What is the relationship between an RQT and RGT? The RQT is an "accounting task" used to measure the reliability of a fixed design configuration. It has the benefit of holding the contractor accountable some day down the road from his initial design process. As such, he is encouraged to seriously carry out the other design related reliability tasks. The RGT is an "engineering task" designed to improve the design reliability. It recognizes that the drawing board design of a complex system cannot be perfect from a reliability point of view and allocates the necessary time to fine tune the design by finding problems and designing them out. Monitoring, tracking and assessing the resulting data gives insight into the efficiency of the process and provides nonliabi l i ty persons with a tool for evaluating the development's reliability status and for reallocating resources when necessary. The forms of testing serve very different purposes and complement each other in development of systems and equipments. An RGT is not a substitute for an RQT or any other reliability design tasks.

How much validity/confidence should be placed on the numerical results of RGT? Associating a hard reliability estimate from a growth process, while mathematically practical, has the tone of an assessment process rather than an improvement process, especially if an RQT assessment will not follow the RGT. In an ideal situation, where contractors are not driven by profit motives, a reliability growth test could serve as an improvement and assessment vehicle. Since this is not the real world, the best that can be done if meaningful quantitative results are needed without an RQT, is to closely monitor the contractor RGT. Use of the AMSAA mode! provides the necessary statistical procedures for associating confidence levels with reliability results. In doing so, closer control over the operating conditions and failure determinations of the RGT must be exercised than if the test is for improvement purposes only. A better approach is to use a less closely controlled growth test as an improvement technique (or a structured extension of FRACAS, with greater emphasis on corrective action) to fine tune the design as insurance of an accept decision in an RQT. With this approach, monitoring an improvement trend is more appropriate than development of hard reliability estimates. Then use a closely controlled RQT to determine acceptance and predict operational results.

3.0 Duane Model: Because the Duane model is the one most commonly used, it will be further explained. The model assumes that the plot of MTBF versus time is a straight line when plotted on log-log paper. The main advantage of this model is that it is easy to use. The disadvantage of the model is it assumes that a fix is incorporated immediately after a failure occurs (before further test time is accumulated). Because fixes are not developed and implemented that easily in real



life, this is planning to<

is rarely tr tool. Below

the case. Despite this problem, it is still considered a useful wis a brief summary of the Duane model.

a. Growth Rate

b. Cumulative MTBF MTBFC = ™T«

c. Instantaneous MTBF

d. Test Time 1 T - [ ( M T B F i ) ( K ) (1-a) ] a

e. Preconditioning period at which system will realize an initial MTBF of MTBFC

where k = a constant which is a function of the initial MTBF a = the growth rate T = the test time

The instantaneous MTBF is the model's mathematical representation of the MTBF if all previous failure occurrences are corrected. Therefore, there is no need to selectively purge corrected failures from the data.

The scope of the up-front reliability program, severity of the use environment and system state-of-the-art can have a large effect on the initial MTBF and, therefore, the test time required. The aggressiveness of the test team and program office in ensuring that fixes are developed and implemented can have a substantial effect on the growth rate and, therefore, test time. Other important considerations for planning a growth test are provided in Table 6-1.

Table 6-1: RGT Planning Considerations

To account for down time, calendar time should be estimated to be roughly twice the number of test hours.

• A minimum test length of 5 times the predicted MTBF should always be used (if the Duane Model estimates less time). Literature commonly quotes typical test lengths of from 5 to 25 times the predicted MTBF

For large MTBF systems (e.g., greater than 1000 hours), the preconditioning period equation does not hold; 250 hours is commonly used.

• The upper limit on the growth rate is .6 (growth rates above .5 are rare).


Tpc = ! (MTBFPRED)


K2 =

4 .2

. . [ ^ o j f f i S S S i p

fter T hours of!

MTBF(t) = ^ j t t t

To fc of an

The

the to

ions

LABORATORY RELIABILITY ENGINEER'S TOOLKIT A-57


40 percent of the equipment Is new design; the remainder is comprised of mature, off-the-shelf items.

- The MIL-HDBK-217 MTBF prediction is 300 hours (A,p = 1/300).

• An RGT program is to be conducted during which 3000 hours will be accumulated on the equipment.

The operational cycle for the equipment is a ten-hour aircraft mission.

The test profile eliminates the period of operation in a relatively benign environment (e.g., the cruise portion of the mission) resulting in a test cycle of two hours.

The predicted number of failures in the equipment prior to testing is:

K-j = 30,000 x (0.4) x (1/300) = 40

The initial MTBF is:

The test acceleration factor is:

C 1 0 C Fa = y = 5

The rate of surfacing failures during the test is:

K2 = ( M f ^ ) x 5 = 0.0003846

The equipment MTBF after incorporation of corrective actions to eliminate those failures identified in the RGT program is:

MTBF(3000) = : - „ „ „ n O 0 / i e „ „ „ „ = 232hours (5 x 3J0 + 40 x 0.0003846 e 0 " 0 0 0 3 8 4 6 x 3 0 0 0 )

Hence, the predicted reliability growth is from an initial MTBF of 156 hours to an improved MTBF of 232 hours, approximately a 50 percent improvement.


Appendix 7 Maintainability/Testability

Demonstration Testing


MAINTAINABILITY/TESTABILITY DEMONSTRATION TESTING

Table 7-1: Summary

Maintainability Demonstration Test Plan

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Appendix 8 Reliability and Maintainability

Data Sources


RELIABILITY AND MAINTAINABILITY EDUCATION SOURCES

1 .0 Air Force Databases

Wright-Patterson AFB OH 45433-5001

DSN: 787-6021

Wright-Patterson AFB OH 45433-5001 (513) 257-5361 DSN: 787-5361

ROME LABORATORY RELIABILITY TOOLKIT A-67


;-data il and ships,



Naval Aviation Logistics Data Analysis System (NALDA): NALDA cont;

NAVAIR Air Station, Code 424 : River MD 20670

624-6621

326-4454

3-3 DC 20380-0001

(703) 696-1060 DSN: 226-1060

3 . 0

Troop Support Sample Data Collection (TSSDC): TSSDC is a sample

operating hours of

US-Army Aviation Troop v A M Q A T - I . M n r

4300 Goodfellow Blvd. St Louis MO 63120-1798 (314) 263-2734 DSN: 693-2734

Work Order Logistics File (WOLF): WOLF is a maintenance database

USAMC Materiel Readiness Support Activity AMXMD-RA

KY 40511-5101 (606) 293-4110 DSN: 745-4110



Reliabil i ty, Avai labi l i ty, Maintainabil i ty and Logist ics Data Base (RAM/LOG): RAM/LOG contains testing data on Aircraft.

US Army Aviation Troop Command 4300 Goodfellow Blvd St Louis MO 63120-1798 (314) 263-1791 DSN: 693-1791

USAMC Materiel Readiness Support Activity Deficiency Reporting System

This system tracks equipment and component deficiencies for all equipments.

Commander USAMC Materiel Readiness Support Activity ATTN: AMXMD-RS Lexington KY 40511-5101 (606) 293-3577 DSN: 745-3577

4 .0 Other Government Databases

Reliability Analysis Center (RAC): RAC is a Department of Defense Information Analysis Center sponsored by the Defense Technical Information Center, managed by the Rome Laboratory, and currently operated by IIT Research Institute (IITRI). RAC is chartered to collect, analyze and disseminate reliability information pertaining to electronic systems and parts used therein. The present scope includes integrated circuits, hybrids, discrete semiconductors, microwave devices, opto-electronics and nonelectronic parts employed in military, space and commercial applications.

Data is collected on a continuous basis from a broad range of sources, including testing laboratories, device and equipment manufacturers, government laboratories and equipment users (government and non-government). Automatic distribution lists, voluntary data submittals and field failure reporting systems supplement an intensive data solicitation program.

Reliability data and analysis documents covering most of the device types mentioned above are available from the RAC. Also, RAC provides reliability consulting, training, technical and bibliographic inquiry services.

For further technical assistance and information on available RAC Services, contact:

Reliability Analysis Center 201 Mill Street Rome NY 13440-6916 Technical Inquiries: (315) 337-9933 Non-technical Inquiries: (315) 337-0900 DSN: 587-4151



All Other Requests Should Be Directed To:

Rome Laboratory ERSS/Duane A. Gilmour GriffIss AFB NY 13441 -5700 Telephone: (315) 330-2660 DSN: 587-2660

Government Industry Data Exchange Program (GIDEP): The GIDEP program is a cooperative activity between government and industry participants for the purpose of compiling and exchanging technical data. It provides an on-line menu driven means of searching for desired information. Table 8-1 summarizes several separate GIDEP data banks which contain R&M related information.

Table 8-1: GIDEP Data Bank Summary

Data Bank Content

Engineer ing Test reports, nonstandard part justification data, failure analysis data, manufacturing processes data.

Reliability and Maintainability Failure mode and replacement rate data on parts, reports on theories, methods, techniques and procedures related to reliability and maintainability practices.

Failure Experience Failure information generated on significant problems on parts, processes, materials, etc. Includes ALERTS and failure analysis information.

GIDEP provides special services such as the ALERT system which notifies all participants of significant problem areas and the Urgent Data Request System which allows all participants queried for information to solve a specific problem. The current information found on-line is usually a brief summary of a report or collected data which provides a reference for further detailed information found on microfilm; however, GIDEP is working on a new system which will provide full text reports and ALERTS on-line.

GIDEP Operations Center Corona CA 91720-5000 (714) 273-4677 DSN: 933-4677




Appendix 9 Reliability and Maintainability

Education Sources



1 .0 R&M Education Sources

The following is a list of organizations that offer various types of R&M training (Academic Offerings, short courses, home study, etc.). This is in no way a complete listing of all the R&M education sources. For further information on the individual sources, call or write to the address provided.

DOD Programs

Air Force Institute of Technology/LS Wright-Patterson AFB OH 45433 DSN 785-6336 (513) 255-6336

Private Institution Academic Programs

University of Arizona Aerospace & Mechanical Eng Dept BIdg 16, Rm 200B Tucson AZ 85721 (602) 621-2495

New Jersey Institute of Technology Electrical Engineering Dept Newark NJ 07102 (201) 596-3511

Army Management Engineering College

AMXOM/QSAT Rock Island IL 61299-7040 DSN: 793-0503 (309) 782-0503

University of Maryland Center for Reliability Engineering Chemical & Nuclear Engineering College Park MD 20742

Individual courses on R&M subjects have been included in the curricula of many schools, including Pennsylvania State University, VPI, USC, Virginia Tech, SMU and Syracuse University.

Short Course/Home Study Programs

Reliability Analysis Center American Society for Quality Control 201 Mill Street 611 E. Wisconsin Avenue Rome NY 13440-6916 PO Box 3005 (315) 337-0900 Milwaukee Wl 53201 -3005

(800) 248-1946

Society of Automotive Engineers 400 Commonwealth Drive Warrendale PA 15096-0001 (412) 772-7148

The Continuing Engineering Education Center

George Washington University Washington DC 20052 (800) 424-9773



of Albany, Milwaukee

2.0

A-76 ROME LABORATORY RELIABILITY TOOLKIT


Appendix 10 R&M Specifications, Standards,

Handbooks and Rome Laboratory Technical Reports


R&M SPECIFICATIONS, STANDARDS, HANDBOOKS AND ROME LABORATORY TECHNICAL REPORTS



Table 10-1: Reliability Standards and Handbooks

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R&M SPECIFICATIONS, STANDARDS, HANDBOOKS AND ROME LABORATORY TECHNICAL REPORTS aa i i i i i :

Table 10-2:

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6 I

S S 5: S 3 2 3

I

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t i l l It %

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Table 10-3: Custodial Agencies for R&M Documents

I

!

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1

i

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Table 10-4: Other. R&M Related Standards, Specifications, Pamphlets and Regulations

Document Date Tit le

MIL-STD-454M Notice 3

MIL-STD-883D

MIL-STD-965A

MIL-STD-1309D

MIL-STD-1388/1A Notice 3

MIL-STD-1388/2B

MIL-STD-1547A

MIL-STD-1562W

MIL-BUL-103J

MIL-STD-2165

MIL-E-5400T

MIL-M-38510J

MIL-H-38534

MIL I 38535A

MIL-STD-1772B

MIL-S-19500H Supplement 1 Amendment 2

30 Oct 91 Standard General Requirements for Electronic

Equipment

16 Nov 91 Test Methods and Procedures for Microcircuits

13 Dec 85 Parts Control Program 12 Feb 92 Definition of Terms for Testing Measurement and

Diagnostics

28 Mar 91 Logistics Support Analysis

28 Mar 90 Logistics Support Analysis Record, DoD Requirements for a

1 Dec 87 Electronic Parts, Materials and Processes for Space and Launch Vehicles

25 Sep 91 List of Standard Microcircuits

31 Oct 91 List of Standardized Military Drawings (SMDs)

26 Jan 85 Testability Program for Electronic Systems and Equipment

14 May 90 Electronic Equipment. Aerospace. General

Specification for

1t> Nov 91 Microcircuits. General Specification for

22 Aug 90 Hybrid Microcircuits. General Specification for

29 Nov 91 Integrated Circuits (Microcircuits) Manufacturing, General Specification for

22 Aug 90 Hybrid Microcircuit. General Specification for

30 Apr 90 Semiconductor Devices. General Specification for 28 Sep 90 30 Jul 91



Documen t Date T i t l e

ESD-TR-85-148 Mar 85

RELI

MNTY

MIL-HDBK-978B

DoD Dir. 5000.1

MIL-STD-810E Notice 1

24 Apr 87

Dec 89

MIL-HDBK-H108 29 Apr 60

1 Sep 89

23 Feb 91

DoD Inst. 5000.2 23 Feb 91

9 Feb 90

Derating Application of Parts for ESD System Development

DoD Reliability Standardization Document Program Plan, Revision 4

DoD Maintainability Standardization Document Program Plan, Revision 3

Sampling Procedures and Tables for Life & Reliability Testing (Based on Exponential Distribution)

NASA Parts Application Handbook

Defense Acquisition

Defense Acquisition Management Policies and Procedures

Environmental Test Methods and Engineering Guidelines



Table 10-5: Rome Laboratory Reliability & Maintainability Technical Reports RL-TR AD No. T i t le

RL Apr

RL-TR-92-96 Apr 1992

RL-TR-91 -29 Mar 1991

RL-TR-91-39 Apr 1991

RL-TR-91-48

RL-TR-91-87 Apr 1991

RL-TR-91-121 Jul 1991

RL-TR-91-1 Ju

of an Mirror

RL-TR-91-155 Jul 1991

RL-TR-91-180 Aug'

RL Sei

ADA241476 Using

RL-TR-91-220 Sei

RL-TR-91-251 Oct 1991

RL-TR-91-300 Nc

RL-TR-91-305 Set

il Stress

(TQM), An Overview

RL-TR-91-353 De

RL-TR-91-402 Dec'

Mission/Mc Cycling i of Reliability



RADC-TR AD No. Ti t le RADOTR-9Q-31

RADC-TR-90-64

RADC-TR-90-72

RADC-TR-90-1 Vol. I Vol. II

RADC-TR-90-1

RADC-"

RADC-

RADC-

RADC-TR-89-160

RADC-1

RADC-" Vol. I Vol. II Vol. Ill

RADC-TR-89-223

RADC-TR-89-276

RAD C-TR-89-277

RADC-1

RADC-Vol. I Vol. II

RADC-"

ADA215737

ADB141961L

iluation

BIT-2



RADC-TR AD No. Title RADC-TR-88-13 ADB122629L VHSIC Impact on System Reliability

RADC-TR-88-69 Vol. I

Vol. II

RADC-TR-88-72

RADC-TR-88-97

ADA200204 R/M/T Design for Fault Tolerance, Program Manager's Guide

ADA215531 R/M/T Design for Fault Tolerance, Design Implementation Guide

ADA193759 Reliability Assessment of Surface Mount Technology

ADA200529 Reliability Prediction Models for Discrete Semiconductor Devices

RADC-TR-88-110

RADC-TR-88-118

RADC-TR-88-124

RADC-TR-88-124

RADC-TR-88-211

RADC-TR-88-304 Vol. I. Part A Vol. II. Part B

RADC-TM-87-11

RADC-TR-87-13

RADC-TR-87-55

ADA202704 Reliability/Maintainability/Testability Design for Dormancy

ADA201346 Operational and Logistics Impact on System Readiness

ADA201946 Impact of Fiber Optics on System Reliability/Maintainability

ADA201946 Impact of Fiber Optics on System Reliability/Maintainability

ADA206346 Testability/Diagnostics Encyclopedia Program (Part I)

ADB132720L Reliability Design Criteria for High Power Tubes ADB132721L Review of Tube and Tube Related Technology

ADA189472 Availability Equations For Redundant Systems, Both Single and Multiple Repair

ADB119216L Maintenance Concepts for VHSIC

ADA183142 Predictors of Organizational-Level Testability Attributes

RADC-TR-87-92 ADB117765L Large Scale Memory Error Detection and Correction

RADC-TR-87-177 ADA189488

RADC-TR-87- 225 ADA193788

Reliability Analyses of a Surface Mounted Package Using Finite Element Simulation

Improved Readiness Thru Environmental Stress Screening



RADC-TR AD No. Title RADC-TR-86-138

RADC-TR-86-148

RADC-TR-86-149


RADC-TR-86-241

RADC-TR-85-66

RADC-TR-85-91

RADC-TR-85-148

RADC-TR-85-150

RADC-TR-85-228 Vol. I

Vol. II

RAD C-TR-85-229

ADA174333

ADA176128

ADA176847

ADB110761 ADB111438L

ADA182335

ADA157242

ADA158843

ADB098377L

ADA162617

RADC Guide to tnvironmental Stress Screening

Reliability Growth Prediction

Environmental Stress Screening

Tools For Integrated Diagnostics

Built-in-Test Verification Techniques

Study and Investigation to Update the Nonelectronic Reliability Notebook

Impact of Nonoperating Periods on Equipment Reliability

Smart BIT

A Rationale and Approach for Defining and . Structuring Testability Requirements

RADC-TR-85-194 ADA163900 RADC Nonelectronic Reliability Notebook

ADA165231 Impact of Hardware/Software Faults on System Reliability - Study Results

ADA165232 Procedures for Use of Methodology

ADA164747 Reliability Prediction for Spacecraft

RADC-TR-85-268

RL-TR-84-20


RADC-TR-84-83

ADA167959

ADA141232

ADB087426 ADB087507L

Prediction and Analysis of Testability Attributes: Organizational Level Testability Prediction

Reliability Growth Testing tffectiveness

Reliability/Maintainability Operational Parameter Translation

ADai 45971 Ballpark Reliability Estimation Techniques

RADC-TR-84-100 ADB086478L Thermal Stress Analysis of Integrated Circuits Using Finite Element Methods

ROME LABORATORY RELIABILITY E N G I N E E R ' S TOOLKIT A - 9 1


RADC-TR RADC-

RADC-TR-84-182

RADC-TR-84-203

RADOTR-84-244

RADOL

RADOL

RADG-TR-83-2

RADOTR-83-4

RADC-TR-83-13


RADC-TR-83-36

RADC-TR-83-49

RADC-TR-83-72


RADC-1

RADC-TR-83-172

RADC-TR-83-180

VLSI

ADA154161

ADA153761

ADA127546

ADA13158

RADC-TR-83-257

A-92 LABORATORY RELIABILITY } TOOLKIT


RADC-TR RADC-" ADA141147 ard

RADC-TR-83-316 3/Softv

RADC-TR-82-172

RADC-TR-82-179

RADC-1

RADC--

RADC-" ual

ROME LABORATORY RELIABILITY; I TOOLKIT A-93

Appendix 11 Acronyms


ACRONYMS

ACRONYMS

BCWS Budget Cost of Work Scheduled

BEA Budget Estimate Agreement BES Budget Estimate

Submission BIMOS Bipolar/Metal Oxide

Semiconductor BIST Built-in Self Test BIT Built-in-Test BITE Built-in-Test Equipment BIU Bus Interface Unit BJT Bipolar Junction Transistor BLER Block Error Rate BPPBS Biennial Planning,

Programming, and Budgeting System

B/S or bps Bits Per Second C Centigrade C-ROM Control Read Only Memory C3 Command, Control and

Communications C3CM Command, Control,

Communications and Countermeasures

C3I Command, Control, Communications Intelligence

CA Contracting Activity CAD Computer Aided Design CADBIT Computer Aided Design for

Built-in Test CAE Computer Aided

Engineering CALS Computer Aided Acquisition

Logistics & Support CAM Content Addressable

Memory CAS Column Address Strobe CASS Computer Aided Schematic

System CAT Computer Aided Test CB Chip Boundary CCB Capacitive Coupled Bit CCB Configuration Control Board CO) Ceramic Chip Carrier CCD Charged Coupled Device CDF Cumulative Density

Function

CDIP Ceramic Dual In-Line Package

CDR Critical Design Review CDRL Contract Data

Requirements List CFAR Constant False Alarm Rate CFE Contractor Furnished

Equipment CFSR Contract Fund Status

Report CGA Configurable Gate Array CI Configuration Item CIM Computer Integrated

Manufacturing CINC Commander-in-Chief CISC Complex Instruction Set

Computer CIU Control Interface Unit CLCC Ceramic Leaded Chip

Carrier CLIN Contract Line Item Number CM Centimeter CM Configuration Manager or

Management CML Current Mode Logic cms Complementary Metal Oxide

Semiconductor cm Can Not Duplicate CNI Communications,

Navigation, and Identification

CO Contracting Officer CODEC Coder Decoder COMM Communications COMSEC Communications Security COPS Complex Operations Per

Second CPCI Computer Program

Configuration Item CPFF Cost-Plus-Fixed-Fee CP IF Cost-Pius-Incentive-Fee CPM Control Processor Module CPU Central Processing Unit CRC Cyclic Redundance Check CS Chip Select CSC Computer Software

Component


ACRONYMS

CSCI Computer Software Configuration Item

CSP . Common Signal Processor CSR Control Status Register CTE Coefficient of Thermal

Expansion CTR Current Transfer Ratio CV Capacitance-Voltage dB Decibel dc Direct Current D/A Digital-to-Analog DAB Defense Acquisition Board DC Duty Cycle DECTED Double Error Correcting,

Triple Error Detecting DED Double Error Detection DEM/VAL Demonstration and

Validation DESC Defense Electronics Supply

Center DID Data Item Description DIP Dual In-Line Package DISC Defense Industrial Supply

Center DLA Defense Logistics Agency D Level Depot Level DID Data Item Description DMR Defense Management

Review DOD Department of Defense DOS Disk Operating System DOX Design of Experiments DP Data Processor DPA Destructive Physical

Analysis DRAM Dynamic Random Access

Memory DRS Deficiency Reporting

System DSP Digital Signal Processing DT&E Development Test &

Evaluation DT1C Defense Technical

Information Center DUT Device Under Test DoD Department of Defense DoD ADL Department of Defense

Authorized Data List

eV Electron Volt Ea Activation Energy in

Electron Volts Eox Electronic Field Strength in

Oxide EAROM Electrically Alterable Read

Only Memory ECC Error Checking and

Correction ECCM Electronic Counter

Countermeasures ECL Emitter Coupled Logic ECM Electronic

Countermeasures ECP Engineering Change

Proposal ECU Environmental Control Unit EDA Electronic Design

Automation EDAC Error Detection and

Correction EDM Engineering Development

Model EEPROM Electrically Erasable

Programmable Read Only Memory

EGC Electronic Gate Count EGS Electronic Ground System EGSE Electronic Ground Support

Equipment EM Electromigration EMC Electromagnetic

Compatibility EMD Engineering and

Manufacturing Development EMI Electromagnetic Interface EMP Electronic Magnetic Pulse EO Electro-optical EOS Electrical Overstress EP Electrical Parameter EPROM Erasable Programmable

Read Only Memory ER Part Established Reliability Part ERC Electrical Rule Check ESC Electronic System Center ESD Electrostatic Discharge ESM Electronics Support

Measure


ACRONYMS

ACRONYMS

ACRONYMS

LSE Lead System Engineer LSI Large Scale Integration LSSD Level Sensitive Scan

Design LSTTL Low Power Schottky

Transistor Transistor Logic LUT Look Up Table mm Millimeter mA Milliampere ms Millisecond mW Milliwatt M Maintainability m Million Mb Megabit Met Mean Corrective

Maintenance Time Mil 1000th of an Inch M-MM Mean Maintenance

Manhours MAC Multiplier Accumulator Chip MAJCOM Major Command MAP Modular Avionics Package MBPS Million Bits Per Second WGCR Mission Critical Computer

Resources MCFOS Military Computer Family

Operating System MCOPS Million Complex Operations

Per Second MCTL Military Critical Technology

List MCU Microcontrol Unit MD Maintainability

Demonstration MDCS Maintenance Data

Collection System MDM Multiplexer/Demultiplexer MDR Microcircuit Device

Reliability MDT Mean Down Time MELF Metal Electrode Face MENS Mission Element Needs

- Statement MENS Mission Equipment Needs

Statement MFLOPS Million Floating Point

Operations Per Second MHz Megahertz

MIL-STD Military Standard MIMIC Microwave Millimeter Wave

Monolithic Integrated Circuit MIN Maintenance Interface

Network MIPS Million Instructions Per

Second MISD Multiple Instructions Single

Data MLB Multilayer Board MLIPS Million Logic

Inferences/Instructions Per Second

MMBF Mean Miles Between Failure MMD Mean Mission Duration MMH/FH Maintenance Manhours Per

Flight Hour MMH/PH Mean Manhours Per

Possessed Hour MMIC Monolithic Microwave

Integrated Circuit MMM Mass Memory Module MMPS Million Multiples Per Second MMR Multimode Radar MMS Mass Memory Superchip mm Millimeter Wave m Maintenance Node mm Maintenance Network Node MNS Mission Need Statement MOA Memorandum of Agreement MODEM Modulator Demodulator MOPS Million Operations Per

Second MOS Metal Oxide Semiconductor MOSFET Metal Oxide Semiconductor

Field Effect Transistor MP Maintenance Processor MPCAG Military Parts Control

Advisory Group MRAP Microcircuit Reliability

Assessment Program MSB Most Significant Bit MSI Medium Scale Integration MIBCF Mean Time Between Critical

Failures MTBD Mean Time Between

Demand MTBDE Mean Time Between

Downing Events


ACRONYMS

MTBF Mean Time Between Failure MTBFF Mean Time Between

Functional Failure MTBM-IND Mean Time Between

Maintenance-Induced (Type 2 Failure)

MTBM-INH Mean Time Between Maintenance-Inherent (Type 1 Failure)

MTBM-ND Mean Time Between Maintenance-No Defect (Type 6 failure)

MTBM-P Mean Time Between Maintenance-Preventive

MTBM-TOT Mean Time Between Maintenance-Total

MTBMA Mean Time Between Maintenance Actions

MTBR Mean Time Between Removals

MTBUMA Mean Time Between Unscheduled Maintenance Actions

MTE Multipurpose Test Equipment

MTE Minimal Test Equipment MTI Moving Target Indicator MITE Mean Time to Error MTTF Mean Time To Failure MUX Multiplexer MV Mega Volt (Million Volt) MWPS Million Words Per Second NDI Nondevelopmental Items NDT Nondestructive Testing NMOS N-Channel Metal Oxide

Semiconductor ns Nanosecond O-Level Organizational Level O&M Operation and Maintenance OMB Office of Management and

Budget OPR Office of Primary

Responsibility CnS Operations Per Second ORD Operational Requirements

Document OROM Optical Read Only Memory OSD Office of the Secretary of

Defense

OT&E Operational Test & Evaluation

OTS Off-The-Shelf P Power Poly Polycrystalline Silicon PtSi Platinum Silicide PAL Programmable Array Logic PAT Programmable Alarm

Thresholds PC Printed Circuit PCA Physical Configuration

Audit PCB Printed Circuit Board PCO Procuring Contracting

Officer PD Power Dissipation PDF Probability Density Function PDL Program Design Language PDR Preliminary Design Review PEM Program Element Monitor PGA Pin Grid Array PIN Positive Intrinsic Negative PLA Programmable Logic Array PLCC Plastic Leadless Chip

Carrier PLD Programmable Logic Device PM Program Manager PMD Program Management

Directive PMOS P-Channel Metal Oxide

Semiconductor PMP Program Management Plan PMP Parts, Materials and

Processes PMR Program Management

Review PMRT Program Management

Responsibility Transfer PPM Parts Per Million PPSL Preferred Parts Selection

List PO Program Office PROM Programmable Read Only

Memory PRR Production Readiness

Review PRST Probability Ratio Sequential

Test


ACRONYMS

ACRONYMS

ACRONYMS

WAM Window Addressable Memory

WBS Work Breakdown Structure WRSK War Readiness Spares Kit WSI Wafer-Scale Integration WSIC Wafer-Scale Integrated

Circuit X Reactance XCVR Transceiver Y Admittance Z Impedance ZIF Zero Insertion Force
