Routability-driven Floorplanning With Buffer

Planning

Chiu Wing Sham

Evangeline F. Y. YoungDepartment of Computer Science & Engineering

The Chinese University of Hong Kong

Overview of Presentation

IntroductionCongestion modelBuffer planningImplementationExperimental resultsConclusion

Major Role of Floorplanning

Minimization of chip areaMinimization of interconnect cost

WirelengthTiming delayRoutability

Our Contributions

Improve the routability of the layout byAccurate estimations of congestion at

different locations of the packingConsider the positions of the buffer

blocks

Buffer Planning

Buffer planning is important to circuit designThe number of buffer insertions is large and

the total size of buffer insertions is significantBuffers cannot be inserted on macro blocksWithout planning ahead, buffer locations

will be poorly chosen or timing closure cannot be achieved

Design Flow

Simulated Annealing

FloorplanEvaluation

Move a new packing

Estimation ofcongestion

Computationof area andwirelength

Estimation ofbuffer usage

and bufferresource

Netlist and module information of

a floorplan

A floorplan with optimized area and routability

Design Flow

Simulated Annealing

FloorplanEvaluation

Move a new packing

Estimation ofcongestion

Computationof area andwirelength

Estimation ofbuffer usage

and bufferresource

Netlist and module information of

a floorplan

A floorplan with optimized area and routability

Traditional Congestion Model

The number of feasible routes for wire kpassing through each grid

6

61 3

3 4

3 1

3

The routes for wire k

The probability that wire k passing through this grid, Prob(x,y,k)=4/6=0.67

Our Congestion Model

Variable interval buffer insertion constraint Adjacent buffers are inserted at distance x [low, up] from each other for some given low and up

Make use of the information of buffer insertions to estimate congestion by probabilistic analysis

Our Congestion Model

As the buffers can be inserted in multi-ways:

r_success(l) = (P0 + … + Pn)/n,

where n is the total number of possible ways for buffer insertions, P0 … Pn are the probabilities of successful buffer insertion for each possible way and r_success(l) is the probability of successful buffer insertion for route l.

Assume that up is 3 and low is 2

B B BB BB BB B

Assume that up is 3 and low is 2

Our Congestion Model

Example:

Buffer resources, b_prob(x,y)

S 0.21.00.8

0.50.5 0.00.0 T

0.50.21.0

0.5 0.0

r_success(l)

= (P0+P1+P2)/3

= 0.413

P0 = 1.0*1.0P0 = 1.0*1.0

P1 = 1.0*0.2

P0 = 1.0*1.0

P1 = 1.0*0.2

P2 = 0.2*0.2

route (l)B BB BB B

0.10 0.30 0.25

0.00 0.50 0.40

0.00 0.10 0.30

Buffer resources, b_prob(x,y)

0.00 0.00 0.00

0.00 0.00 0.00

0.00 0.00 0.00

The number of feasible routes pass through each grid for wire k

0.10 0.30 0.25

0.00 0.50 0.40

0.00 0.10 0.30

Assume that up is 3 and low is 2

B

B

B 0.10 0.30 0.25

0.00 0.50 0.40

0.00 0.10 0.30

Our Congestion Model

r_success(0)= 0.25

0.25 0.25 0.25

0.00 0.00 0.25

0.00 0.00 0.25

r_success(1)= 0.50

0.75 0.75 0.25

0.00 0.50 0.75

0.00 0.00 0.75

r_success(2)= 0.50

1.25 1.25 0.25

0.00 1.00 0.75

0.00 0.50 1.25

r_success(3)= 0.50

1.75 1.25 0.25

0.50 1.50 1.25

0.00 0.50 1.75

r_success(4)= 0.50

2.25 1.25 0.25

1.00 2.00 1.25

0.00 1.00 2.25

r_success(5)= 0.00

The probability that wire k passing through this grid, Prob(x,y,k)=2.00/2.25=0.89

Our Congestion Model

Congestion of the grid (x,y)

- Average number of wires passing through the grid (x,y), weight(x,y):

k wireall

kyxrobPyxweight ),,(),(

Estimation of the Congestion

Compute these Prob(x,y,k) for all co-ordinates x, y and wires k by dynamic programming

To compute Prob(x,y,k), we can make use of the Prob(x’,y’,k’)s where (x’,y’)s are closer to the source than (x,y) and the distance between (x’,y’) and (x,y) is within the bound [low, up]

Estimation of Buffer Resources

Buffer resources at grid (x,y):

)),(_

),(_,1min(),(_

yxweightb

yxspacebyxprobb

where b_space(x,y) is the maximum number of buffer insertions allowed at the grid (x, y) which is related to the amount of empty space in that grid and b_weight(x,y) is the estimated total number of buffer insertions required at the grid (x,y)

Buffer resources, b_prob(x,y)

S 0.21.00.8

0.50.5 0.00.0 T

0.50.21.0

0.5 0.0

Implementation of the Floorplanner

Assume variable interval buffer insertion constraint

Estimate the wirelength by MSTEstimate the amount of buffer resourcesEvaluate the congestion by probabilistic

analysisApply two phases simulated annealing

Two Phases Simulated Annealing

Phase 1Using simulated annealingUsing cost function including area and wirelength

only, C1

Phase 2

Using simulated annealing

Using cost function including area, wirelength and congestion estimation, C2

Max_weightWireAreaCost

WireAreaCost

Two Phases Simulated Annealing

Temperature adjustmentMaintain the acceptance rate during the

transitional stage by adjusting the temperatureSimulated annealing process can be performed

smoothly although the cost function is changed

Calculating the new temperature, new_T = (new_C/ old_C)*old_T

A Simple Global Router

The nets are decomposed into two-pin wiresA wire is routable if it can be routed from the

source to the sink in the shortest Manhattan distance without violating the buffer constraints and the congestion constraints

The nets will be routed one after anotherThe routes satisfying the buffer requirement

and with the smallest congestion will be chosen

Experimental Results

Machine used is Pentium IV 1.2GHz with 512 Mb memory

The data sets used are ami33, ami49 and playout

Upper bound and lower bound of the variable interval buffer insertion constraint are approximately equal to 2100m and 4200m for 0.18m technology

Experimental ResultsCompare our two phases routability-driven floorplanner with buffer planning (F1) v.s. the traditional floorplanner (F2):

ami33 ami49 playout

F1 F2 F1 F2 F1 F2

Area 1296.61 1293.44 39754.35 39454.41 992.54 990.59

Wirelength 20.59 20.64 379.80 399.75 296.56 306.76

Congestion 2.13 3.07 0.07 0.08 18.48 19.61

Blocked wires 9.63 14.80 10.00 12.13 115.88 163.87

Total wires 256.00 256.00 504.00 504.00 1946.00 1946.00

Runtime 678.45 127.71 789.46 151.56 3498.23 494.45

Experimental ResultsCompare our two phases routability-driven floorplanner with buffer planning v.s. the traditional floorplanner:

Comparison with original floorplanner

ami33 ami49 playout

Area 0.26 % 0.76 % 0.19 %

Wirelength -0.25 % -4.91 % -3.32 %

Congestion -30.53 % -12.50 % -5.76 %

Blocked wires -34.93 % -17.56 % -29.29 %

Runtime 5.3x 5.2x 7.1x

ConclusionA routability-driven floorplanner with buffer

planning is implementedThe result shows that the floorplan can be less

congested and more routable without increasing the area of the floorplan significantly

Runtime is affordable when using two phases simulated annealing