Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock

RTL Coding tips Lecture 7,8

What is RTL (register transfer level)?

Combining data flow and behavioral modeling

Each digital system has both combinational and sequential parts

Use data flow for combinational and behavioral for sequential

Hint: It is important to note that, while coding at RTL, the non blocking procedural assignment should be used only to model sequential logic and the blocking procedural assignment to model combinational logic

combinational

Register

RTL Coding Guideline: Avoid Combinational Feedback

If first cloud is an adder (add input and feedback but feedback is unknown), 2nd cloud is multiplier with integer 2 (it will multiply unknown output of 1st cloud with 2, so produces unknown output.)

5

x

x x

x

5

0

5

10

10

How to use a register

reg [7:0]acc;

always@(acc)

acc = acc +1;

Any such code does not make sense in design and simulation. The simulator will never come out of this block as the change in acc will bring it back into the procedural block. If logic demands any such functionality, a register should be used to break the combinational logic

How to use register

// Register with asynchronous active-low reset

always @ (posedge clk or negedge rst )

begin

if(!rst )

acc_reg <= 16’b0;

else

acc_reg <= 1+acc_reg;

end

reg

clk rst

1

acc_regIf either +ve edge of clk or –ve edge of reset occurs, the code from begin-to-end will execute

Register with Synchronous Reset

always @ (posedge clk )

begin

if(!rst )

acc_reg <= 16’b0;

else

acc_reg <= 1+acc_reg;

end

About Stimulus: Loading memory from a file

System tasks $readmemb and $readmemh are used to load data from a text file written in binary or hexadecimal, respectively, into specified memory.

The example here illustrates the use of these tasks. First memory needs to be defined as:

reg [7:0] mem[0:63];

The following statement loads data from memory.dat file into mem:

$readmemb (“memory.dat”, mem);

Macros

Like #define in C, Verilog provides ‘define to assign a constant value to a tag:

‘define DIFFERENCE 6’b011001

The tag can then be used instead of a constant in the code. This gives better readability to the code. The use of the ‘define tag is shown here:

if (ctrl == ‘DIFFERENCE)

Digital Signal Processing Design Example

y[n]= 0.5 y[n-1]+ x[n]

Example

y[n]= 0.5 y[n-1]+ x[n]

module iir(input signed [15:0] x,input clk, rst _n,output reg signed [31:0] y);

reg signed [31:0] y_reg;always @(*) \\ combinational logic block y = (y_reg>>>1) + x;always @(posedge clk or negedge rst n) \\ sequential logic blockbeginif (!rst_n) y_reg <= 0;else y_reg <= y;end endmodule

module stimulus_irr;reg [15:0] X;reg CLK, RST N;wire [31:0] Y;integer i;iir IRR0(X, CLK, RST_N, Y); \\ instantiation of the moduleinitialbeginCLK =0;#5 RST_N =0; \\ resetting register before first posedge clk#2 RST_N= 1;endinitialbeginX= 0;for(i =0; i<10; i =i+1) \\ generating input values every clk cycle#20 X =X + 1;$finish;end

always \\ clk generation

#10 CLK = ~CLK;

initial

$monitor($time, " X %d, sum %d, Y %d", X, IRR0.y, Y);

initial

begin

#60 $stop;

end

endmodule

Simulation waveform

Verilog Tasks

Verilog task can be used to code functionality that is repeated multiple times in a module. A task has input, output and inout and can have its local variables.

All the variables defined in the module are also accessible in the task.

The task must be defined in the same module using task and end task keywords.

To use a task in other modules, the task should be written in a separate file and the file then should be included using an ‘include directive in these modules.

A simple task example

module simple_task();

task convert;

input [7:0] temp_in;

output [7:0] temp_out;

begin

temp_out = (9/5) *( temp_in + 32) ;

end

endtask

endmodule

Global variables in task

module task_global(); reg [7:0] temp_out; reg [7:0] temp_in; task convert; begin temp_out = (9/5) *( temp_in + 32); end endtask endmodule

Calling a task

module task_calling (temp_a, temp_b, temp_c, temp_d); input [7:0] temp_a, temp_c; output [7:0] temp_b, temp_d; reg [7:0] temp_b, temp_d; `include "mytask.v“ always @ (temp_a) begin convert (temp_a, temp_b); end always @ (temp_c) begin convert (temp_c, temp_d); end endmodule

Using TASK within another module

module RCA( input [3:0] a, input [3:0] b, input c_in, output reg c_out, output reg [3:0] sum );

reg carry[4:0];

integer i;

task FA( input in1, input in2, input carry in, output reg out,output carry_out);

{carry_out, out} = in1 + in2 + carry_in;

endtask

always@*

begin

carry[0]= c_in;

for(i =0; i<4; i= i+1)

begin

FA(a[i], b[i], carry[i], sum[i], carry[i+1]);

end

C_out = carry[4];

end

endmodule

Verilog Functions

Verilog function is in many respects like task as it also implements code that can be called several times inside a module.

A function is defined in the module using function and endfunction keywords. The function can compute only one output.

To compute this output, the function must have at least one input.

The output must be assigned to an implicit variable bearing the name and range of the function. The range of the output is also specified with the function declaration.

Function Example

A simple function

module simple_function(); function myfunction; input a, b, c, d; Begin myfunction = ((a+b) + (c-d)); end endfunction endmodule

Calling function

module function_calling(a, b, c, d, e, f); input a, b, c, d, e ; output f; wire f; `include "myfunction.v“ assign f = (myfunction (a,b,c,d)) ? e :0; endmodule

How to use function

module MUX4to1( input [3:0] in, input [1:0] sel, output out);

wire out1, out2;

function MUX2to1;

input in1, in2;

input select;

assign MUX2to1 = select ? in2:in1;

endfunction

assign out1 = MUX2to1(in[0], in[1], sel[0]);

assign out2= MUX2to1(in[2], in[3], sel[0]);

assign out= MUX2to1(out1, out2, sel[1]);

endmodule

Stimulus

/* stimulus for testing the module MUX4to1 */

module testFunction;

reg [3:0] IN;

reg [1:0] SEL;

wire OUT;

MUX4to1 mux(IN, SEL, OUT);

initial

begin

IN =1; SEL =0;

#5 IN =7; SEL =0;

#5 IN= 2; SEL =1;

#5 IN= 4; SEL= 2;

#5 IN =8; SEL= 3;

end

initial

$monitor($time, " %b %b %b\n", IN, SEL, OUT);

endmodule