RUSSELL P. KRAFT, Ph.D.

Lecturer Electrical, Computer, and Systems Engineering Department

School of Engineering Rensselaer Polytechnic Institute

BORN: January 5, 1955 EDUCATION: 1983 Ph.D., E.E., Rensselaer Polytechnic Institute 1978 M.Eng., E.E., Rensselaer Polytechnic Institute 1976 B.S., E.E., Rensselaer Polytechnic Institute PROFESSIONAL EXPERIENCE: September 2011-present. Lecturer, ECSE, Rensselaer Polytechnic Institute, Troy, NY. Dr. Kraft is responsible for several courses in ECSE and Core Engineering. With many of the studio and lab courses, there is a continuous demand for updating equipment, software, procedures, objectives, and training of support. May 2009-present. EDA Support, ECSE, Rensselaer Polytechnic Institute, Troy, NY. Dr. Kraft has installed & maintained the EDA tools for the research and teaching activities, for both faculty and students. This includes major tools suits from Cadence, Synopsys, Mentor, Agilent, Ansys, Comsol, Sonnet, MATLAB, Xilinx, and Virtutech. Additionally, several (~30) IC fabrication kits are supported for IBM, MITLL, NCSU, TI, HRL, NGC, CMP-IMAG, Raytheon, and Austria Microsystems. Some kits include libraries of cores and proprietary layouts, so a rigorous security procedure must be followed to restrict access and enforce NDAs. Other duties include creating all research accounts and assisting with day-to-day operations, when required. September 1995-2011. Research Staff, ECSE, Rensselaer Polytechnic Institute, Troy, NY. Dr. Kraft has been involved in the VLSI design of a fast RISC processor from the layout, MCM packaging, simulation tools, and future directions with regard to the device technologies and available processes. The new thrust is in 3D integrated circuit design for increased speed. Adj. Assist. Prof., Electrical, Computer and Systems Engineering Dept. and Computer Science Dept., Rensselaer Polytechnic Institute, Troy, NY. Teaching and course development for senior level linear and discrete time system laboratory course; undergraduate level circuit, instrumentation, and logic design courses; senior level computer networking courses on Ethernet, TCP/IP, router programming, switches, LAN & WAN design, and ACLs. October 1986-September 1995. Senior Project Manager, Center for Manufacturing Productivity, Rensselaer Polytechnic Institute, Troy, NY. Dr. Kraft's responsibilities with the CMP include manufacturing research in the areas of robotics, machine vision and image processing for automated assembly, inspection, verification, and metrology. His previous research efforts in image processing include applications in robot safety, the acquisition and processing of ultrasonic images of composites, task-level robotic programming, automated sheet metal parts inspection and punch verification, vision guided real time control of multiprocessor manufacturing equipment, electronics manufacturing/automated PWB

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inspection using neural nets, and other inspection and metrology related investigations. As a project manager, he was responsible for writing research proposals and obtaining funding to support graduate and undergraduate students as well as additional funding for participating faculty consultants. Adj. Assist. Prof., Electrical, Computer and Systems Engineering Dept. and Mechanical Engineering Dept., Rensselaer Polytechnic Institute, Troy, NY. Teaching and course development for senior level linear and discrete time system courses; theoretical and laboratory applications; undergraduate level circuit, instrumentation, and logic design courses; graduate level introductory overview of manufacturing and computer integrated manufacturing systems. January 1983-October 1986. Senior Controls Engineer, R&D Division, Mechanical Technology Inc., Latham, NY. As a development engineer, his work included the design and testing of computer vision enhancement filtering, convolution, correlation, and transform routines, the design of necessary lighting and optics for the enhancement of desired part features. A second major effort was the development of an optimized control system for Stirling engines through simulation and experimentation. This computer based embedded control system monitored and controlled all the functions of the engine. The vision research was developed into two high precision dimensional gauging products by Dr. Kraft that were subsequently patented. This development work was carried out with a team of technicians and shared responsibility with mechanical engineers, reporting directly to the division managers. September 1981-December 1982. Instructor, Electrical, Computer and Systems Engineering Department, Rensselaer Polytechnic Institute, Troy, NY. Dr. Kraft taught electrical engineering courses in linear systems, communication systems and digital control theory applications. He also developed a library of EE graphics programs for computer-aided instruction and design of control systems, circuits and digital filters. PERTINENT PUBLICATIONS Dr. Kraft has published 70 conference articles and 27 journal articles. He has more that have been accepted or in review and 3 additional articles in preparation in the VLSI area. Journal Articles (In preparation) R.P. Kraft, S.A. Steidl, P.M. Campbell and J.F. McDonald, "A Fast 16 GHz Clock using a

VCO PLL for a Fast RISC Engine using GaAs/AlGaAs HBT Technology". (In review) V. Sankaran, B. Chartrand, D.L. Millard, M.J. Embrechts, and R.P. Kraft, "Printed Wiring

Board Inspection Using Neural Networks," European Journal of Mechanical Engineering. (In review)

J.-W. Kim, J.F. McDonald "A SiGe HBT BiCMOS Reconfigurable Analog RF Crossbar for Ultra Wide Band and Ultra Wide Tuning Range Applications," Submitted to IET.

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(In review) M. Chu, J.-R. Guo, K. Zhou, C. You, J.-W. Kim, J.-D. Diao, R.P. Kraft, and J.F. McDonald,

"High Speed Interleaved ADC and Polyphase Filtering System in SiGe HBT technology", Special Issue Proceedings on SiGe, Proc. of the IEEE.

31. Ryan Clarke, Mitchell R. LeRoy, Srikumar Raman, Tuhin Guha Neogi, Russell P. Kraft,

and John F. McDonald, “160 Gb/s Serializer using Clock Doublers in 90 nm SiGe Technology,” IEEE Journal of Solid-State Circuits, vol. 50, no. 2, pp. 380-390, 2015.

30. Ryan Clarke, Philip Jacob, Okan Erdogan, Paul Belemjian, Srikumar Raman, Mitchell R.

LeRoy, Tuhin Guha Neogi, Russell P. Kraft, Diana-Andra Borca-Tasiuc, and John F. McDonald, “Thermal Modeling of 3-D Stacked DRAM Over SiGe HBT BiCMOS CPU,” IEEE Open Access Journal, vol. 3, pp. 43-54, Feb. 20, 2015, doi: 10.1109/ACCESS.2015.2396474.

29. Xuelian Liu, Mitchell R. LeRoy, Ryan Clarke, Michael Chu, Hadrian O. Aquino, Srikumar

Raman, Aamir Zia, Russell P. Kraft, John F. McDonald, “Design of BiCMOS SRAMs for high-speed SiGe applications”, IET Circuits Devices Syst., 2014, vol. 8, iss. 6, pp. 487-498, Apr. 2014, doi: 10.1049/iet-cds.2013.0375

28. X. Liu, S. Raman, R. Clarke, M.R. LeRoy, O. Erdogan, M. Chu, A. Gutin, R.P. Kraft, and

J.F. McDonald, “Design of High Speed Register Files Using SiGe HBT BiCMOS Technology”, IEEE Transactions on Circuits & Systems – II: Express Briefs, vol. 61, no. 3, pp. 178-182, 2014.

27. A. Gutin, P. Jacob, M. Chu, P.M. Belemjian, M. LeRoy, R.P. Kraft, and J.F. McDonald,

“Carry Chains for Ultra High Speed SiGe HBT Adders”, IEEE Transactions on Circuits & Systems – I: Regular Papers, vol. 58, no. 9, pp. 2201-2210, 2011.

26. J.-W. Kim, M. Chu, P. Jacob, A. Zia, R.P. Kraft, and J.F. McDonald, “Reconfigurable 40

GHz BiCMOS uniform delay crossbar switch for broadband and wide tuning range narrowband applications”, IET Circuits Devices Syst., vol. 5, no. 3, pp. 159 – 169, 2011.

25. M. Chu, R.-J. Guo, K. Zhou, C. You, J.F. McDonald and R.P. Kraft, "A 40GS/s Time

Interleaved ADC using SiGe BiCMOS technology," IEEE Journal of Solid-State Circuits, vol. 45, no. 2, pp. 380-390, 2010.

24. A. Zia, P. Jacob, J.-W. Kim, M. Chu, R.P. Kraft and J.F. McDonald, "A 3-D Cache With

Ultra-Wide Data Bus for 3-D Processor-Memory Integration," IEEE Transactions on VLSI Systems, vol. 18, no. 6, pp. 967-977, June, 2010.

23. P. Jacob, A. Zia, O. Erdogan, P.M. Belemjian, J.-W. Kim, M. Chu, R.P. Kraft, J.F. McDonald, and K. Bernstein “Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks”, Proceedings of the IEEE, Sp. Issue on 3D Electronics, vol. 97, no. 1, pp. 109-122, January, 2009.

22. C. You, J.-R. Guo, R.P. Kraft, M. Chu, B. Goda and J.F. McDonald, “A 12-Gb/s DEMUX

Implemented with SiGe High-Speed FPGA Circuits”, IEEE Transactions on Very Large Scale Integrated Systems, vol. 15, no. 9, pp. 1051-1054, September, 2007.

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21. Y.U. Yim, P.F. Curran, M. Chu, J.F. Mcdonald, and R.P. Kraft, “52 Gb/s 16:1 transmitter

in 0.13 µm SiGe BiCMOS technology”, Circuits, Devices & Systems, IET, vol. 1, no. 6, pp. 427-432, December, 2007

20. J.-R. Guo, C. You, M. Chu, P.F. Curran, J. Diao, B. Goda, R.P. Kraft and J.F. McDonald,

“Silicon Germanium Programmable Circuit for Gigahertz Applications”, IET Circuits, Devices & Systems (formerly IEE), vol. 1, no. 1, pp. 27-33, February, 2007.

19. I. Fidan, E. Roush, S. Tumkor, and R.P. Kraft, "Internet-Based Electronics Manufacturing

Troubleshooting Tool for Surface Mount PCB Assembly," International Journal of Advanced Manufacturing Technology, vol. 2006, no. 27, pp. 561-567, 2006.

18. P. Jacob, 0. Erdogan, A. Zia, P.M. Belemjian, R.P. Kraft, and J.F. McDonald, "Predicting

the Performance of a 3D Processor-Memory Chip Stack", IEEE Design & Test of Computers, vol. 22, no. 6, pp. 540-547, November/December, 2005.

17. P.M. Belemjian, O. Erdogan, R.P. Kraft, and J.F. McDonald, "SiGe HBT Microprocessor

Core Test Vehicle", Proc. IEEE (Special Issue on SiGe Technology – Guest Editors: R. Singh, D. Harame, and B. Meyerson), vol. 93, no. 9, pp. 1669-1678, September, 2005.

16 C. You, J.-R. Guo, R.P. Kraft, M. Chu, P. Curran, K. Zhou, B. Goda and J.F. McDonald,

“A 5-10 GHz SiGe BiCMOS FPGA with New Configurable Logic Block”, J. of Microprocessors and Microsystems, Elsevier, vol. 29, no. 2/3, pp. 121-131, April/May, 2005.

15. K. Zhou, R.-J. Guo, C. You, J. Mayega, R.P. Kraft, T. Zhang, B.S. Goda, and J.F.

McDonald, "Multi-GHz SiGe BiCMOS FPGAs with New Architecture and Novel Power Management Techniques," World Scientific Journal of Circuits, Systems, and Computers, vol. 14, no. 2, pp. 179-193, April, 2005.

14 J.-R. Guo, C. You, K. Zhou, M. Chu, P.F. Curran, J. Diao, B. Goda, R.P. Kraft and J.F.

McDonald, “A 10GHz 4:1 MUX and 1:4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC”, Integration, the VLSI Journal, Elsevier, vol. 38, no. 3, pp. 525-540, January, 2005.

13. T.W. Krawczyk, P.F. Curran, M.W. Ernest, S.A. Steidl, S.R. Carlough, J.F. McDonald,

and R.P. Kraft, "A Transmitter Architecture for High Speed, Short-Haul Serial Communication," IEE Proceedings Circuits, Devices & Systems, vol. 151, no. 4, pp. 315-321, August, 2004.

12. D. Gupta, A.M. Kadin, R.J. Webber, I. Rochwarger, D. Bryce, W.J. Hollander, Y.U. Yim,

Channakeshav, R.P. Kraft, J.-W. Kim, and J.F. McDonald, “Integration of Cryocooled Superconducting Analog-to-Digital Converter and SiGe Output Amplifier”, IEEE Trans. Appl. Supercond, vol. 13, no. 2, pp. 477-484, June, 2003.

11. B.S. Goda, J.F. McDonald, S.R. Carlough, T.W. Krawczyk Jr., and R.P. Kraft, "SiGe HBT

BiCMOS FPGAs for fast reconfigurable computing," IEE Proc.-Comput. Digit. Tech., vol. 147, no. 3, pp. 189-194, May, 2000.

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10. S.R. Carlough, R.A. Philhower, C.A. Maier, S.A. Steidl, P.M. Campbell, A. Garg, K.-S.

Nah, M.W. Ernest, J.R. Loy, T.W. Krawczyk Jr., P.F. Curran, R.P. Kraft, H.J. Greub, and J.F. McDonald, "A 2GHz Clocked AlGaAs/GaAs HBT Byte-Slice Datapath Chip," IEEE Journal of Solid State Circuits, vol. 35, no. 6, pp. 885-894, June, 2000.

9. B.L. Halpern, P. Komarenko, P.D. Fuqua, J.F. McDonald, G.R. Yang, J. Fortin, B. Wang,

J. Diao, H.Q. Lu, M. Tomozowa, I. Matthew, R. Kraft, T.M. Lu, H. Bakhru, and A. Kumar, “Properties of Parylene-N Using Atomic Hydrogen Enhanced Jet Vapor Deposition,“ Journal on Dielectrics for ULSI Multilevel Interconnection, Institute for Microelectronics InterConnection (IMIC), vol. 1, no 1, pp. 29-42, Fall, 1999.

8. I, Fidan, R.P. Kraft, S.J. Derby, “Design and Implementation of A flexible Intelligent

Electronics Remanufacturing System,” 1999 ASME International Mechanical Engineering Congress and Exposition (IMECE'99) Symposium on Electronics Manufacturing, November 14-19 1999 Nashville, TN, USA, Electronics Manufacturing Issues, Edited by C. Sahay, B. Sammakia, I. Kao, and D. Baldwin, vol. 104, pp. 83-90, November, 1999. (ISBN: 0-7918-1653-2)

7. I. Fidan and R.P. Kraft, "Integrated User Interface Design for Electronics

Remanufacturing Systems", Proceedings of 24th IEEE/CPMT IEMT Symposium, October 18-19 1999, Austin, TX, pp. 54-63, October, 1999.

(ISSN: 1089-8190 ISBN: 0-7803-5503-2 IEEE Catalog Number: 99CH36330) 6. A. Garg, Y.L. Le Coz, H.J. Greub, R.B. Iverson, R.F. Philhower, P.M. Campbell, C.A.

Maier, S.A. Steidl, M.W. Ernest, R.P. Kraft, S.R Carlough, J.W. Perry, T.W. Krawczyk, and J.F. McDonald, “Accurate High-Speed Performance Prediction for Full Differential Current-Mode Logic: The Effect of Dielectric Anisotropy,” IEEE Transactions on CAD, vol. 18, no. 2, pp. 212-219, February, 1999.

5. I. Fidan, R.P. Kraft, L.E. Ruff, and S.J. Derby, "Designed Experiments to Investigate the

Solder Joint Quality Output of a Prototype Automated Surface Mount Replacement System", IEEE Transactions on CPMT - Part C: Manufacturing, vol. 21, no. 3, pp. 172-181, July, 1998.

4. V. Sankaran, A.R. Kalukin, and R.P. Kraft, "Improvements to X-Ray Laminography for

Automated Inspection of Solder Joints", IEEE Transactions on CPMT - Part C: Manufacturing, vol. 21, no. 2, pp. 148-154, April, 1998.

3. I. Fidan, R.P. Kraft, L.E. Ruff, and S.J. Derby, "Integration Steps of a Fully-Automated

Remanufacturing Cell System for Fine-Pitch Surface Mounted Devices", IEEE Transactions on CPMT - Part C: Manufacturing, vol. 21, no. 1, pp. 71-78, January, 1998.

2. P.M. Campbell, H.J. Greub, A. Garg, S.A. Steidl, S. Carlough, M. Ernest, R. Philhower,

C. Maier, R.P. Kraft, and J.F. McDonald, "A Very-Wide Bandwidth Digital VCO Using Quadrature Frequency Multiplication and Division Implemented in AlGaAs/GaAs HBTs", IEEE Transactions on VLSI Systems, Vol. 6, No. 1, pp. 52-55, March, 1998.

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1. D.K. Frederick, T. Sadeghi, and R.P. Kraft, "Computer-Aided Control System Analysis and Design Using Interactive Graphics", Computer-Aided Control Systems Engineering, pp. 265-275, (M. Jamshidi & C.J. Herget, Ed.), North-Holland, 1985.

Conference Papers 76. X Liu, A. Zia, M.R. LeRoy, S. Raman, R. Clark, R. Kraft and J.F. McDonald, “A three-

dimensional DRAM using floating body cell in FDSOI devices,” Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on Digital Object Identifier: 10.1109/DDECS.2012.6219044, pp. 159-162, 2012.

75. J.F. McDonald, O. Erdogan, P. Jacobs, P. Belemjian, A. Gutin, Zia, M. Chu, Jin Woo

Kim, R. Clarke, N. DeSimone, S. Liu and R.P. Kraft, “Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers,” IEEE International Conference on 3D System Integration, 2009. 3DIC 2009. Digital Object Identifier: 10.1109/3DIC.2009.5306570, pp. 1-7, 2009.

74. S Deng, Z.R. Huang, J.-R. Guo, J.F. McDonald and R.P. Kraft, “Numerical investigation

of a SiGe HBT electro-optic modulator,” IEEE/LEOS Winter Topicals Meeting Series, 2009, Digital Object Identifier: 10.1109/LEOSWT.2009.4771632, pp. 14-15, 2009.

73. J.F. McDonald, M. Chu, J.-W. Kim, P. Jacob, A. Zia, Ryan Clarke, S. Liu, and R.P. Kraft,

“Diamond Heat Spreader Layers for 3D Processor Computer Chip Stacks,” Proc. First IEEE Conference on 3D Integrated Circuits, San Francisco, Ca, September 24, 2009.

72. J.F. McDonald, R.P. Kraft, P. Belemjian, O. Erdogan, P. Jacobs, A. Zia, A Gutin, R.

Clarke, Y. Masachi, and T.-M. Lu, "Diamond Heat Spreader Thermal Analysis for 3D Memory over Processor Chop Stacks and Effect on TSV Reliability," Proc. 25th VLSI Multilevel Interconnection Conference (VMIC 2008), Freemont, CA, pp. 217-221, October 28-30, 2008.

71. J.F. McDonald, R.P. Kraft, J.-R. Guo, P. Belemjian, O. Erdogan, P. Jacob, A. Zia, Y.

Yim, M. Chu, J.-W. Kim, S. Deng, R. Huang, and J.-Q. Lu, "3D Wafer Bonding with a Silicon germanium HBT BiCMOS for Compact Fast Light Modulator for Photonic Interconnect," Proc. 25th VLSI Multilevel Interconnection Conference (VMIC 2008), Freemont, CA, pp. 355-361, October 28-30, 2008.

70. J.F. McDonald, A. Zia, P. Belemjian, O. Erdogan, P. Jacobs, A. Gutin, R. Clarke, and

R.P. Kraft, "Test Results for a Fabricated 3 Tier, 3D DFDSOI SRAM," Proc. 25th VLSI Multilevel Interconnection Conference (VMIC 2008), pp. 187-193, Freemont, CA, October 28-30, 2008.

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69. A. Zia, P. Jacob, R.P. Kraft and J.F. McDonald, "A 3-tier, 3-D FD-SOI SRAM macro," Proc. of the IEEE International Conference on IC Design & Technology (ICICDT 2008), Grenoble, France, pp. 277-280, May 2008.

68. J.F. McDonald, and R.P. Kraft, "Tomographic Approach to Precise Wafer Thinning for 3D

Chip-Stacking, Photonic Interconnection and Heat Removal Enhancement," MRS Advanced Metallization Series, Vol. XXIII, October 9-11, 2008, Edited by A.J. McKerrow, Yosi Shacham-Diamond, Shoso Shingubara, Yukihiro Shimogaki, Ch. 8, p. 53, April/May 2008.

67. P. Jacobs, A. Zia, O. Erdogan, P. Belemjian, P. Jin, J.-W. Kim, M. Chu, R. Kraft, and J.F.

McDonald, "Amdahl’s Figure of Merit, SiGe HBT BiCMOS, and 3D Chip Stacking," Proc. IEEE Int. Conf. on Computer Design (ICCD 07), Squaw Creek Resort, Squaw Valley, CA, pp. 202-207, November 9-12, 2007.

66. J.F. McDonald, R. Kraft, A. Zia, P. Jacob, P. Belemjian, O. Erdogan, and J.-Q. Lu,

"Precise Wafer Thinning using the Mathematics of the Radon Transform for 3D Chip-Stacking, Photonic Interconnections, and Heat Removal Enhancement," 24th International VLSI Multilevel Interconnection Conference (VMIC 2007), Freemont Marriott, Freemont, CA, pp. 261-266, September 24-27, 2007.

65. A. Zia, P. Jacob, J.F. McDonald, R.P. Kraft, P. Belemjian, O. Erdogan, and P. Jin, "A 3D

FDSOI 1-T DRAM with Floating Body Capacitance Suitable for Processor Integration,” 24th International VLSI Multilevel Interconnection Conference (VMIC 2007), Freemont Marriott, Freemont, CA, pp. 261-266, September 25-27, 2007.

64. J.F. McDonald, R.P. Kraft, J.-R. Guo, P. Belemjian, O. Erdogan, P. Jacobs, A. Zia, Y.

Yim, M. Chu, J.-W. Kim, J. Diao, and J.-Q. Lu, "A Slow Wave Photonic Crystal Enhancement of Drude-Effect Light Modulators for Intra-Chip Optical Interconnections using 3D Wafer Bonding Techniques”, Proceedings of the 23rd International VLSI Multilevel Interconnection Conference (VMIC 2006), Freemont Marriott, Freemont, CA, pp. 243-248, September 26-28, 2006.

63. J.F. McDonald, R.P. Kraft, P. Belemjian, O. Erdogan, P. Jacob, and A. Zia, “A 3D SOI

SRAM Suitable for Processor Integration”, Proceedings of the 23rd International VLSI Multilevel Interconnection Conference (VMIC 2006), Freemont Marriot, Freemont, CA, pp. 220-227, September 26-28, 2006.

62. P. Jacob, O. Erdogan, A. Zia, P.M. Belemjian, R.P. Kraft and J.F. McDonald, “Predicting

the performance of a 3D processor-memory chip stack,” Design & Test of Computers, IEEE vol. 22, no. 6, Digital Object Identifier: 10.1109/MDT.2005.151, pp. 540-547, November-December 2005.

61. J.F. McDonald, P. Jacob, A. Zia, P. Belemjian, O. Erdogan, R.P. Kraft, A.Y. Zheng, K.

Rose, R. Gutmann, and J.-Q. Lu, "Evaluation of 3D Processor Memory Chip-stacks," Proc. 22nd VLSI Multilevel Interconnection Conference (VMIC 2005), Freemont California, pp. 459-467, October 3-6, 2005.

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60. C. You, J.-R. Guo, M. Chu, K. Zhou, R.P. Kraft, B. Goda, and J.F. McDonald, "An 11 GHz FPGA with Test Applications", Proc. Field Prog. Logic Conference (FPL05), Tampere, Finland, Paper 3.A.2, pp. 101-105, August 24-26, 2005.

59. Y.U. Yim, J.F. McDonald, and R.P. Kraft, "A 12-23GHz Ultra Wide Tuning Range

Voltage-Controlled Ring Oscillator with Hybrid Control Schemes", Proc. of the International Symposium on VLSI, ISVLSI05, Tampa Florida, pp. 278-279, May 11-12, 2005.

58. J.-R. Guo, C. You, M. Chu, O. Erdogan, R.P. Kraft, J.F. McDonald, "A High -Speed

Reconfigurable Gate Array for Gigahertz Applications", Proc. of the International Symposium on VLSI, ISVLSI05, Tampa Florida, pp. 124-129, May 11-12, 2005.

57. J.F. McDonald, R.P, Kraft, P. Belemjian, O. Erdogan, J.-Q. Lu, A.Y. Zheng, K. Rose, and

R.J. Gutmann, "A Wafer Bonding Approach for 3D Processor Memory Chip-stacks," Proceedings of the 21st VLSI Multilevel Interconnection Conference (VMIC 2004), Waikoloa Beach, HI, pp. 225-230, September 30-October 2, 2004. (246-252)

56. J.-R. Guo, C. You, M. Chu, K. Zhou, J. Diao, B. Goda, R.P. Kraft, and J.F. McDonald, “A

High Performance Field Programmable Gate Array For Gigahertz Applications”, 2004 Military and Aerospace Programmable Logic Devices (MAPLD) International Conference, Washington, D.C., September 8-10, 2004.

55. I. Fidan, E.M. Roush, S. Tumkor, R.P. Kraft, "Intelligent Simulation Environment for

Electronics Remanufacturing Systems," 2004 IEEE International Electronics Manufacturing Technology Symposium, San Jose, CA, July 14-16, 2004.

54. J.-R. Guo, C. You, K. Zhou, M. Chu, J. Diao, A George, R.P. Kraft and J.F. McDonald,

“The 10GHz 4:1 MUX and 1:4 DEMUX implemented by the Gigahertz SiGe FPGA“, Proceedings of the 2004 Great Lakes VLSI Symposium, Washington, D.C., pp. 40-44, April 26-28, 2004.

53. J.-R. Guo, C. You, M. Chu, R.W. Heikaus, K. Zhou, O. Erdogan, J.D. Diao, B.S. Goda,

R.P. Kraft and J.F. McDonald "The Gigahertz FPGA: Design consideration and Applications", 12th ACM International Symposium on Field Programmable Gate Arrays, Monterey, CA, p. 248, February 22-24, 2004.

52. J.F. McDonald, R.P, Kraft, P. Belemjian, O. Erdogan, and J. Mayega, "Interconnection

Impact Study for a 3D Chip-stack Computer Core," 20th VLSI Multilevel Interconnection Conference (VMIC 2003), Marina del Rey, CA, pp. 247-254, September 23-25, 2003.

51. C. You, J.-R. Guo, R.P. Kraft, M. Chu, R. Heikaus, O. Erdogan, P. Curran, B. Goda, K.

Zhou and J.F. McDonald, “Gigahertz FPGA by SiGe BiCMOS Technology,” Proceeding of FPL 2003: 13th International Conference on Field Programmable Logic and Applications, Lisbon, Portugal, pp. 11-21, August 26-28, 2003.

50. J. Diao, J.-R. Guo, M. Chu, R.P. Kraft, and J.F. McDonald, 'Modeling of two coupled

transmission lines in even and odd mode'. Proc. VLSI Multilevel Interconnection Conference (VMIC 2003). Los Angeles, CA, 2003.

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49. M. Chu, R. Heikaus, K. Zhou, J.-R. Guo, C. You, J.F. McDonald, R.P. Kraft, “Ultra High

Speed Interleaved A/D Conversion Using an fT Doubler Core in SiGe HBT Technology,” Proceedings of the 2003 I.E.E.E. Instrumentation and Measurement Technology Conference, Vail, CO, pp. 839-844, May 20-22, 2003.

48. C. You, J.-R. Guo, R.P. Kraft, K. Zhou, M. Chu, and J.F. McDonald, "A 5-20 GHz, Low

Power FPGA Implemented by SiGe HBT BiCMOS Technology", Proceedings of the 2003 Great Lakes VLSI Symposium, Washington, DC, pp. 37-40, April 28-29, 2003.

47, J. Mayega, O. Erdogan, P.M. Belemjian, K. Zhou, J.F. McDonald, and R.P. Kraft, "3D

Direct Vertical Interconnect Microprocessor Test Vehicle", Proceedings of the 2003 Great Lakes VLSI Symposium, Washington, DC, pp. 141-146, April 28-29, 2003.

46. J.F. McDonald, R.P. Kraft, K. Zhou, J.-R. Guo, Y. Chao, R. Heikaus, M. Chu and B

Goda, “SiGe HBT BiCMOS Field Programmable Gate Arrays for Agile Mixed Signal Applications”, Proceedings of the 2003 Government Microelectronic Applications Conference (GOMAC 2003), Tampa, FL, pp. 560-563, March 31-April 3, 2003.

45. J.-R. Guo, C. You, K. Zhou, M. Chu, B.S. Goda, R.P. Kraft, J.F. McDonald, “A Scalable 2

V, 20 GHz FPGA using SiGe HBT BiCMOS Technology”, Eleventh International Symposium on Field Programmable Gate Arrays (ISFPGA), Monterey, CA, February 23-25, 2003.

44. J.-R. Guo, C. You, K. Zhou, M. Chu, B.S. Goda, R.P. Kraft, J.F. McDonald, “A Scalable

Low-Power, Low-Voltage 9GHz FPGA using SiGe HBT BiCMOS Technology”, International Solid State Circuits Conference (ISSCC) 2003, February 9-13, 2003.

43. K. Zhou, Channakeshav, M. Chu, J.-R. Guo, S.-C. Liu, R.P. Kraft, C. You and J.F.

McDonald, “Gigahertz SiGe BiCMOS FPGA’s with New Architectures and Novel Power Management Schemes,” Proceedings of the 2002 I.E.E,E. International Conference on Field-Programmable Technology (FPT2003), Hong Kong, pp. 182-189, December 16-18, 2002.

42. J.-Q. Lu, Y. Kwon, A. Jindal, K.-W. Lee, J. McMahon, G. Rajagopalan, A.Y. Zeng, R.P.

Kraft, B. Altemus, B. Xu, E. Eisenbraun, J. Castracane, J.F. McDonald, T.S. Cale, A. Kaloyeros, R.J. Gutmann, "Processing Technology for High Density Multifunctional Integration (HDMI) using Wafer Bonding and Monolithic Inter-Wafer Interconnection", (invited), 19th International VLSI Multilevel Interconnection Conference (VMIC 2002), pp. 445-454, Singapore, November 18-20, 2002.

41. J.-Q. Lu, K.W. Lee, Y. Kwon, G. Rajagopalan, J. McMahon, B. Altemus, M. Gupta, E.

Eisenbraun, B. Xu, A. Jindal, R.P. Kraft, J.F. McDonald, J. Castracane, T.S. Cale, A. Kaloyeros and R.J. Gutmann, “Processing of Inter-Wafer Vertical Interconnects in 3D ICs", Advanced Metallization Conference in 2002 (AMC 2002), San Diego, CA, October 1-3, 2002.

40. K. Zhou, Channakeshav, J.-R. Guo, C. You, J. Mayega, B.S. Goda, M. Chu, Y.U. Yim,

J.-W. Kim, P.F. Curran, R.P. Kraft, and J.F. McDonald, “Implementation of Gigahertz 1-

10

bit Full Adder on SiGe FPGA”, 2002 Military and Aerospace Programmable Logic Devices (MAPLD) International Conference, Laurel, Maryland, September 9-12, 2002.

39. K. Zhou, Channakeshav, J.-R. Guo, C. You, B.S. Goda, R.P. Kraft, and J.F. McDonald,

“Fast SiGe HBT BiCMOS FPGAs with new Architecture and Power Saving Techniques”, FPL 2002: 12th International Conference on Field Programmable Logic and Applications, La Grande Motte, France, pp. 59-69, September 2-4, 2002.

38. K. Zhou, Channakeshav, J.-R. Guo, C. You, R.P. Kraft, J. Mayega, P.F. Curran, and J.F.

McDonald, “Gigahertz FPGAs with new architectural ideas,” The 2002 45th Midwest Symposium on Circuits and Systems, MWSCAS-2002. vol. 3, Digital Object Identifier: 10.1109/MWSCAS.2002.1187015 , pp. III-235-III-238, 2002.

37. Channakeshav, K. Zhou, R. Kraft and J.F. McDonald, “Gigahertz FPGAs with new power saving techniques and decoding logic,” NASA/DoD Conference on Evolvable Hardware, 2002 Proceedings, Digital Object Identifier: 10.1109/EH.2002.1029866, pp. 60-62, 2002.

36. J.F. McDonald, R.P. Kraft, P. Belemjian, O. Erdogan, J. Mayega, R. Gutmann, T. Cale, K.W. Lee, and J.-Q. Lu “Design of a 3D SiGe HBT BiCMOS Computer”, 10th ICCD02 conference, June 5, 2002.

35. J.-Q. Lu, Y. Kwon, G. Rajagopalan, M. Gupta, J. McMahon, K.-W. Lee, R.P. Kraft, J.F.

McDonald, T.S. Cale, R.J. Gutmann, B. Xu, E. Eisenbraun, J. Castracane, and A. Kaloyeros, "A Wafer-Scale 3D IC Technology Platform using Dielectric Bonding Glues and Copper Damascene Patterned Inter-Wafer Interconnects", in Proceedings of 2002 IEEE International Interconnect Technology Conference (IITC), pp. 78-80, San Francisco Airport, June 3 - 5, 2002.

34. J.F. McDonald and R.P. Kraft, "A Theory for Modeling, Detection and Mitigation of SiGe

HBT Full Differential CML SEU Faults", 10th NASA Symposium on VLSI Design. 33. Y. Kwon, J.-Q. Lu, R.P. Kraft, J.F. McDonald, R.J. Gutmann and T.S. Cale, "Wafer

Bonding Using Dielectric Polymer Thin Film in 3D Integration", "Polymer Interfaces and Thin Films", Ed. C.W. Frank, Vol. 710 of Proceedings of MRS Fall Meeting, Boston, MA, November 26-30, 2001.

32. J.-Q. Lu, Y. Kwon, G. Rajagopalan, M. Gupta, D.-L. Bae, J. McMahon, C.K. Hong, R.P.

Kraft, O. Erdogan, P.M. Belemjian, J.F. McDonald, T.S. Cale, R.J. Gutmann, E. Eisenbraun, B. Xu, J. Castracane, and A. Kaloyeros, "Fabrication of Via-Chain Test Structures for 3D IC Technology Using Dielectric Glue Bonding on 200 mm Wafers," Advanced Metallization Conference in 2001 (AMC 2001), pp. 151-157, published by MRS 2002, Eds. A.J. McKerrow, Y. Shacham-Diamand, S. Zaima, and T. Ohba, Montreal, Canada, October 9-11, 2001.

31. J.-Q. Lu, R.P. Kraft, Y. Kwon, P. Belemjian, O. Erdogan, G. Rajagopalan, D.-L. Bae, C.K.

Hong, T.S. Cale, J.F. McDonald, and R.J. Gutmann "Design and Fabrication of Damascene Patterned Interconnections for “Face-to-Face” Wafer Bonded 3D-Stacked IC Test Structures," 18th International VLSI/ULSI Multilevel Interconnection Conference, Santa Clara Marriott, Santa Clara, CA, Sept. 24-28, 2001 (invited paper) in Proceedings

11

of 18th International VLSI Multilevel Interconnection Conference (VMIC 2001), pp. 442-450, T. Wade Ed., IMIC, 2001, Santa Clara, CA, September 24-28, 2001.

30. Y. Kwon, J.-Q. Lu, R.J. Gutmann, R.P. Kraft, J.F. McDonald, and T.S. Cale, "Wafer

Bonding Using low-k Dielectrics as Bonding Glues in Three-Dimensional Integration," Sixth International Symposium on Semiconductor Wafer Bonding: Science, Technology, and Applications, at 2001 Joint International Meeting: the 200th Meeting of The Electrochemical Society, Inc. and the 52nd Meeting of The International Society of Electrochemistry, San Francisco, CA, September 2-7, 2001.

29. B.S. Goda, R.P. Kraft, S.R. Carlough, T.W. Krawczyk Jr., and J.F. McDonald, “Gigahertz

Reconfigurable Computing using SiGe HBT BiCMOS FPGAs,” FPL 2001: 11th International Conference on Field Programmable Logic and Applications, Belfast, Northern Ireland, pp. 59-69, August 27-29, 2001.

28. J.-Q. Lü, Y. Kwon, R.P. Kraft, R.J. Gutmann, J.F. McDonald, and T.S. Cale, "Stacked

Chip-to-Chip Interconnections Using Wafer Bonding Technology with Dielectric Bonding Glues," in Proceedings of the 2001 IEEE International Interconnect Technology Conference (IITC), pp. 219-221, San Francisco Airport, CA, June 4 - 6, 2001.

27. J.-Q. Lu, Y. Kwon, R.P. Kraft, R.J. Gutmann, J.F. McDonald, and T.S. Cale, "200 mm

Wafer Bonding for 3-D Interconnects Using Low-k Dielectrics as Bonding Glue," Seventh International Conference on Dielectrics and Conductors for ULSI Multilevel Interconnection (DCMIC), paper no. 2E, pp. 59-66, Santa Clara, CA, March 5 - 7, 2001.

26. R.J. Gutmann, J.-Q. Lu, J.F. McDonald and R.P. Kraft, "IP Core-Based Design, High-

Speed Processor Design and Multiplexing LAN Architectures Enables by 3D Wafer Bonding Technologies," DesignCon 2001: Wireless and Optical Broadband Design Conference, paper # WB-13, Santa Clara Convention Center, Santa Clara, CA, January 30-31, 2001.

25. J.-Q. Lu, A. Kumar, Y. Kwon, E.T. Eisenbraun, R.P. Kraft, J.F. McDonald, R.J. Gutmann,

T.S. Cale, P. Belemjian, O. Erdogan, J. Castracane, A.E. Kaloyeros, "3-D Integration Using Novel Wafer Bonding Techniques," Advanced Materials Conference 2000, Santa Clara Marriott, Santa Clara CA, October 3, 2000.

24. I. Fidan and R.P. Kraft, "Inline Troubleshooting for the Electronics Manufacturing

Systems," 26th IEEE Electronics Manufacturing Technology/Packaging Convention 2000, IEMT/PackCon2000, Santa Clara Marriot, Santa Clara CA, October 3, 2000.

23. J.F. McDonald, R.P. Kraft, J.-Q. Lu, A. Kumar, T. Cale, T.-M. Lu, P. Belemjian, O.

Erdogan, Y. Kwon, A. Kaloyeros, and J. Castracane, "Face to Face Wafer Bonding for 3D Chip Stack Fabrication to Shorten Wire Lengths,'' 17th International VLSI Multilevel Interconnection Conference (VMIC 2000), Santa Clara Marriott, Santa Clara, CA, June 26-30, 2000.

22. J.F. McDonald, R. Kraft, and S. Nicholas, "Teaching Computer Hardware Design in the

Remote Distance 'Lab without Lights','' InterAmerican Conference on Engineering and

12

Technology Education, INTERTECH2000, University of Cincinnati, Cincinnati, OH, CD-ROM session 30, June 14-16, 2000.

21. W. Skinner, T. Tetrault, J. Hautala, J.F. McDonald, G.-R. Yang, J. Fortin, J. Diao, M.

Delarosa, C. Barnett, R. Kraft, C. You, T.-M. Lu, H. Bakhru, and A. Kumar, "Gas Cluster Ionized Beam Etching of Fluropolymers," Characterization of Atomic H Crosslinked Parylene-N using Jet Process Deposition,'' 2000 Dielectrics for ULSI Multilevel Interconnections Conference, DUMIC00, Santa Clara Marriott, Santa Clara, CA, February 27-28, 2000.

20. S. Steidl, S. Carlough, M. Ernest, A. Garg, R. Kraft, and J.F. McDonald, "A 16 GHz Fast

RISC Engine using GaAs/AlGaAs and SiGe HBT Technology", IEEE International Conference in Innovative Systems in Silicon, ISIS '97 Proceedings, pp. 72-81, October, 1997.

19. I. Fidan, R.P. Kraft, L.E. Ruff, and S.J. Derby, "Designed Experiments to Analyze the

Solder Joint Quality Output of a SMD Remanufacturing System," International Electronics Manufacturing Technology Symposium, IEEE/CPMT Proceedings 1996 IEMT Symposium, pp. 422-429, October, 1996.

18. A.R. Kalukin, V. Sankaran, B. Chartrand, D.L. Millard, R.P. Kraft, and M.J. Embrechts,

"An Improved Method for Inspection of Solder Joints Using X-Ray Laminography and X-Ray Microtomography," International Electronics Manufacturing Technology Symposium, IEEE/CPMT Proceedings 1996 IEMT Symposium, pp. 438-445, October, 1996.

17 V. Sankaran, B. Chartrand, D.L. Millard, M.J. Embrechts, and, R.P. Kraft, "Automated

Inspection of Solder Joints - A Neural Network Approach", International Electronics Manufacturing Technology Symposium, IEEE/CPMT Proceedings 1995 IEMT Symposium, pp. 232-237, October, 1995.

16. M.J. Embrechts, R.P. Kraft, V. Sankaran, and D.L. Millard, "IMAGINET: A Novel

Probabilistic Neural Network for Multiscale Image Classification", Intelligent Engineering Systems through Artificial Neural Networks, Vol. 6, (C.H. Dagli, M. Akay, C.L.P. Chen, B. Fernandez, and J. Gosh, Ed.), pp. 431-436, ASME Press, 1996.

15. V. Sankaran, M.J. Embrechts, L-E. Harsson, and R.P. Kraft, "Back-propagation

Applications in Electronics Manufacturing - Solder Joint Classification", World Congress on Neural Networks, WCNN'95 Proceedings Vol. 2, pp. II-642 - II-645, July, 1995.

14. V. Sankaran, M.J. Embrechts, L-E. Harsson, R.P. Kraft, and D.L. Millard "Applications of

Backpropagation in Printed Wiring Board Inspection", Intelligent Engineering Systems through Artificial Neural Networks, Vol. 5: Fuzzy Logic and Evolutionary Programming, (C.H. Dagli, M. Akay, C.L.P. Chen, B. Fernandez, and J. Gosh, Ed.), ANNIE '95 Proceedings, pp. 931-936, ASME Press, November, 1995.

13. M.J. Embrechts, L-E. Harsson, R.P. Kraft, D.L. Millard, and V. Sankaran, "Preprocessing

for the Inspection of Printed Wiring Boards with Neural Nets", Intelligent Engineering Systems through Artificial Neural Networks, Vol. 5: Fuzzy Logic and Evolutionary

13

Programming, (C.H. Dagli, M. Akay, C.L.P. Chen, B. Fernandez, and J. Gosh, Ed.), ANNIE '95 Proceedings, pp. 925-930, ASME Press, November, 1995.

12. M.J. Embrechts, R. Kraft, G. Kendall, D. Millard, and V. Sankaran, "Printed Circuit Board

Inspection with Neural Nets", Adaptive Computing in Engineering Design and Control - '94, Proceedings, pp. 185-190, September, 1994.

11. J. Korngold, R. Kraft, T. Luscher, M. Lee, and G. Shenoy, "Automated Feature and

Tolerance Modeling for In-Process Verification of 2D Punch Press Parts", ASME International Computers in Engineering Conference, CIE '93 Proceedings, pp. 1-11, August, 1993.

10. L.A. Gerhardt, R.P. Kraft, and D.R. Drechsler, "Automated Real-Time Inspection of

Automotive Locking Mechanisms using Computer Vision", IASTED International Conference Adaptive Control and Signal Processing, pp. 170-173, 1990.

9. P. Shah, R.P. Kraft, and S.J. Derby, "Development of Part Acquisition and Insertion

Routines Using the AIM Database", ASME International Computers in Engineering Conference and Exposition, CIE '90 Proceedings, Vol. 1, pp. 399-404, August, 1990.

8. L.A. Gerhardt, R.P. Kraft, P.D. Hill, and S. Neti, "Automated Inspection of Sandpaper

Products and Processes using Image Processing", SPIE Vol. 1197 Automated Inspection and High-Speed Vision Architectures III, pp. 191-201, 1989.

7. D.V. Shick, H.F. Tiersten, R.P. Kraft, J.F. McDonald, and P.K. Das, "Enhanced Trapped

Energy Mode Array Transducer Using Overtones", Acoustical Imaging, Vol. 12, pp. 351-360, 1982.

6. D.K. Frederick, T. Sadeghi, and R.P. Kraft, "Computer-Aided Control System Analysis

and Design Using Interactive Graphics", Control Systems Magazine, pp. 19-23, IEEE Control Society, December, 1982.

5. R.P. Kraft, J.F. McDonald, and J.F. Erkes, "Homomorphic Signal Dereverberation for a

Phased Array Imaging System", IEEE ICCASSP-82, Vol 1, pp. 121-124, December, 1982.

4. R.P. Kraft and J.F. McDonald, "Minimax Optimization of Two-Dimensional Cartesian and

Fresnel Lens Phased Arrays", Proceedings of SPIE's 25th International Symposium, New Methods for Optical, Quasi-Optical, Acoustic, and Electromagnetic Synthesis, Vol. 294, pp. 119-125, August, 1981.

3. P.K. Das, S. Talley, R. Kraft, H. Tiersten, and J.F. McDonald, "Ultrasonic Imaging Using

Trapped Energy Mode Fresnel Lens Transducers," Acoustical Imaging, Vol. 9, pp. 75-92, (Keith Y. Wang, Ed.), 1980.

2. R.P. Kraft, J.F. McDonald, and F. Ahlgren, "Minimax Optimization of Two-Dimensional

Focused Nonuniformly Spaced Arrays", ICASSP-79, pp. 286-289, April, 1979.

14

1. R. Kraft, A.A. Papadopoulos, J.F. McDonald, and H.A. Scarton, "Ultrasonic Phased Array Imaging for Non-Destructive Testing", Fluid Transients and Acoustics in the Power Industry, (Papadakis and Scarton, Ed.), pp. 351-358, ASME Press, 1978.

Technical Reports 11. R.J. Gutmann, et. al., “Task V.C.: 3D Chip Integration-Design, Fabrication, and Testing”,

Jan. 2001. 10. R.J. Gutmann, et. al., “3-D IC Integration by Wafer Bonding”, October 2000. 9. J.F. McDonald, et. al., “FRC-NY FRC 3D Chip Integration Project”, Progress Report,

Dec. 1999 8. J.F. McDonald, et. al., “MCM Packaging for F-RISC/G — Subnanosecond Fast RISC for

TeraOPS Parallel Processing Applications”, Technical Report, December 1997. 7. J.F. McDonald, et. al., “F-RISC/G and Beyond — Subnanosecond Fast RISC for

TeraOPS Parallel Processing Applications”, Semi-Annual Technical Report, April 1997 6. J.F. McDonald, et. al., “A 1.0 GOPS Fast Reduced Instruction Set Computer for Super

Workstation and TeraOPS Parallel Processor Applications”, (Final Contract Report), August 20, 1996.

5. R.P. Kraft, et. al., "Electronic Manufacturing Program Phase III Final Report", (Parts I, II,

& III), March 1996. 4. V. Sankaran, L.-E. Harsson, M.J. Embrechts, and R.P. Kraft, "Printed Wiring Board

Inspection Using Neural Networks", US Army FCIM Final Report, September 1995. 3. R.P. Kraft and J.F. McDonald, "Homomorphic Signal Dereverberation for a Phased Array

Imaging System", RPI Technical Report UI80-1, 1980. 2. R.P. Kraft and J.F. McDonald, "Grating Lobe Suppression in a Correlation Acquisition

Based Phased Array Imaging System", RPI Technical Report UI79-1, March 1979. 1. J.F. McDonald and R. Kraft, "Grating and Aperture Sidelobe Optimization of Phased

Arrays - Part II - Focused and Steered Uniformly Spaced Arrays", RPI Technical Report UI78-2, August 1978.

PATENTS 2. A.M. Offt, R.L. Jackson, R.P. Kraft, and J.F. Wagner, "Method and Apparatus for

Determining the Position of a Feature of an Object," U.S. Patent 4,744,664, May 1988.

15

1. L. Hoogenboom, R.L. Jackson, R.P. Kraft, and A.M. Offt, "Machine Vision Differential Measurement System," U.S. Patent 4,710,808, December 1987.

16

MASTERS & DOCTORAL STUDENTS I have advised or co-advised 8 masters theses (and several more unofficially):

Robert Kunz (ECSE) Prashant Shah (MEAE&M) Efstratios Varkaris (ECSE) Joseph Kenneally (MEA&EM) Mofeez Murtaza (ECSE) William Lois (ECSE) Alexey Gutin (ECSE) Chukwuemeka Igwilo (ECSE)

I have been on 4 doctoral committees: Vijay Sankaran (MEAE&M) Ismail Fidan (MEAE&M) Chao You (ECSE) Alexey Gutin (ECSE)

17

COURSES TAUGHT AT RENSSELAER YEAR FALL SPRING COURSE FORMAT # Sections Tot Enroll COURSE FORMAT # Sections Tot Enroll 15-16 MPS

ECSE4790 Lab 1 43 RTA

ECSE4760 Lab 1 0

LITEC ENGR2350

Studio 1 & Coord 64 LITEC ENGR2350

Studio 1 & Coord 0

14-15 MPS ECSE4790

Lab 1 42 RTA ECSE4760

Lab 1 12

LITEC ENGR2350

Studio 1 & Coord 65 LITEC ENGR2350

Studio 1 & Coord 69

ECSE Design ECSE4900

Indpndnt Prj Advisor

1

13-14 MPS ECSE4790

Lab 1 21 RTA ECSE4760

Lab 1 10

LITEC ENGR2350

Studio 1 & Coord 61 LITEC ENGR2350

Studio 1 & Coord 60

12-13 MPS ECSE4790

Lab 1 29 RTA ECSE4760

Lab 1 24

LITEC ENGR2350

Studio 1 & Coord 42 LITEC ENGR2350

Studio 1 & Coord 52

11-12 MPS ECSE4790

Lab 1 35 RTA ECSE4760

Lab 2 20

LITEC ENGR2350

Studio 1 & Coord 50 LITEC ENGR2350

Studio 1 & Coord 50

ECSE Design ECSE4900

Design Prj Advisor

8

10-11 MPS ECSE4790

Lab 1 35 RTA ECSE4760

Lab 2 17

LITEC ENGR2350

Studio 1 & Coord 64 LITEC ENGR2350

Studio 1 & Coord 64

09-10 MPS ECSE4790

Lab 1 28 RTA ECSE4760

Lab 2 26

LITEC ENGR2350

Studio 2 131 LITEC ENGR2350

Studio 1 & Coord 61

08-09 MPS

ECSE4790 Lab 1 17 RTA

ECSE4760 Lab 2 21

EI ENGR4300

Studio 2 (co-taught) 130 EI ENGR4300

Studio 3 (co-taught) 160

LITEC ENGR2350

Studio 1 LITEC ENGR2350

Studio 1 66

ECSE Designn Advisor

Design 5 ECSE Design Advisor

Design class 9

07-08 MPS ECSE4790

Lab 1 17 RTA ECSE4760

Lab 2 20

EI ENGR4300

Studio 2 135 EI ENGR4300

Studio 3 200

ECSE Design Advisor

Design class 4

Indep Study 3 06-07 MPS

ECSE4790 Lab 1 24 CAL

ECSE4760 Lab 2 45

EI ENGR4300

Studio 1 40 EI ENGR4300

Studio 1 40

ECSE Design Advisor

Design class 3

05-06 MPS ECSE4790

Lab 2 40 CAL ECSE4760

Lab 2 45

EC ECSE2010

Studio 1 40 EC ECSE2010

Studio 1 42

Indep Study 04-05 MPS

ECSE4790 Lab 2 40 CAL

ECSE4760 Lab 2 45

EC ECSE2010

Studio 1 42 EC ECSE2010

Studio 1 40

Indep Study 03-04 MPS Lab 2 40 CAL Lab 2 45

18

ECSE4790 ECSE4760 Indep Study 5 02-03 MPS

ECSE4790 Lab 2 40 CAL

ECSE4760 Lab 2 45

01-02 MPS

ECSE4790 Lab 2 40 CAL

ECSE4760 Lab 2 45

00-01 MPS ECSE4790

Lab 2 40 CAL ECSE4760

Lab 2 45

Comp Net I CSCI4967

Studio 2 (co-instr)

60 Comp Net II CSCI4963

Studio 2 36

99-00 COCO ECSE2610

Studio 3 115 CAL ECSE4760

Lab 2 30

Comp Net I CSCI4966

Studio 1 (co-instr)

25 Comp Net II CSCI4962

Studio 1 20

98-99 COCO ECSE2610

Studio 1 30 CAL ECSE4760

Lab 2 25

MSI MECL6800

Lect 1 15 E&I ENGR4220

Studio 1 30

IEE ENGR1310

Lab 8 (co-instr)

120

Sr Proj 2 97-98 MSI

MECL6800 Lect 1 + RSVP

(co-instr) 70 CAL

ECSE4760 Lab 1 14

E&I ENGR4220

Studio 1 30

IEE ENGR1310

Lab 8 (co-instr)

120

Sr Proj 3 MSI Indep Study

1

96-97 MSI MECL6800

Lect 1 (co-instr)

35 CAL ECSE4760

Lab 2 20

95-96 MSI MECL6800

Lect 1 + RSVP (co-instr)

160 CAL ECSE4760

Lab 3 25

Mast 1 Jr/Sr Proj 5 Jr/Sr Proj 5 94-95 MSI

MECL6800 Lect 1

(co-instr) 25 + 5 Indep

CAL ECSE4760

Lab 4 45

Mast 1 Indep Study ECSE6940

1

Jr/Sr Proj 3 93-94 MSI

MECL6800 Lect 1 +RSVP

(co-instr) 120 CAL

ECSE4760 Lab 4 50

Mast 1 Mast 1 Sr/Jr Proj 3 92-93 CAL

ECSE4760 Lab 4 60

Jr Proj 1 Sr Proj 1 91-92 CAL

ECSE4760 Lab 4 60

Mast 1 Mast 1 Sr Proj 4 Sr/Jr Proj 4 90-91 CAL

ECSE4760 Lab 4 45

Mast 1 Sr/Jr Proj 7 Sr Proj 5 89-90 DTS

ECSE4510 Lect 1

(co-instr) 90 CAL

ECSE4760 Lab 4 40

Mast 1 Mast 1 Sr/Jr Proj 12 Sr Proj 9 88-89 DTS

ECSE4510 Lect 1

(co-instr) 120 CAL

ECSE4760 Lab 5 45

Mast 1 Mast 1 Sr/Jr Proj 15 Sr/Jr Proj 20 87-88 DTS

ECSE4510 Lect 1

(co-instr) 130 CAL

ECSE4760 Lab 6 65

Mast 1 Sr/Jr Proj 11 Sr Proj 6 86-87 CAL

ECSE4760 Lab 6 70

Mast 1

19

As an Instructor ('79-'82): Linear Systems (self-paced) Communication Systems (self-paced) Computer Applications Lab 1 Masters Thesis Advisee Several Sr. Project Advisees REFERENCES Prof. John F. McDonald CII-6123, CIEEM 518-276-2765 Prof. Robert B. Kelley JEC-6048, ECSE 518-276-2653 Prof. Stephen J. Derby (ret.) JEC-5028, ME,AE&M 518-276-2991 Prof. Mark J. Embrechts CII-5217, DSES 518-276-4009 Prof. Henry Scarton JEC-4008, ME,AE&M 518-276-6728 Mr. Robert L. Jackson, Jr. Measurement Solutions International, Inc. P.O. Box 9028 Schenectady, NY 12309 518-346-7136 Dr. Jeffery A. Asher, PhD Vice President, Technical Operations Consumers Union 101 Truman Ave. Yonkers, NY 10703-1057 Jeff & Bob were supervisors at MTI Dr. Leo Hanifin Dean of the College of Engineering and Science University of Detroit Mercy 4001 W. McNichols Rd Detroit, MI 48221 313-993-1216 hanifinl@udmercy.edu COL Bryan Goda United States Military Academy West Point, New York 10996 845-938-5572 Bryan.Goda@usma.edu Prof. Warren DeVries Chair of Mechanical Engineering

Iowa State 515-294-5560 wdevries@iastate.edu Prof. Arthur Ruggles University of Tennessee, Knoxville (Oak Ridge National Labs, part time) 865-974-7563 aruggles@utk.edu Prof. David C. Whalley Dept. of Mfg. Eng. Loughborough University Loughborough Leicestershire LE11 3TU UK 44 (0) 1509 222930 D.C.Whalley@lboro.ac.uk Prof. Ahmed ElSawy Chair, Dept of M&TT College of Engineering Tennessee Tech University Box 5003; 920 N. Peachtree Ave. Cookevile, TN 38505-0001 931-372-3238 aelsawy@tntech.edu Profs. Whalley & ElSawy are familiar with/reviewed the intelligent elect. mfg. research Tom Kean, Ph.D. President, Algotronix, Ltd (www.algotronix.com) P.O. Box 23116 Edinburgh EH8 8JQ Scotland 44 (131) 556 9242 tom@algotronix.com Dr. Kean, formally of Xilinx, has formally reviewed the FPGA & SiGe logic research Prof. Donald W. Bouldin Prof. Electrical & Computer Eng. 420 Ferris Hall University of Tennessee, Knoxville TN 37996 865-974-5444 bouldin@utk.edu Prof. Bouldin is familiar with the SiGe logic & fast RISC processor research Prof. Robert Messler (ret.) Interm Assoc Dean for Academic & Student Affairs JEC-3014 Mat Sci & Eng 518-276-6620

20

Prof. Michael Wozny CII-7023, ECSE 518-276-2898

Former Undergraduate Students James Streitman (Rensselaer ’08) streij@rpi.edu

21

RELEVANT PAST PROJECTS (not including equipment grants from $20k to $250k) – a typical project was a 9 – 12 mo. effort, larger were multi-year

22. Focused Research Center Fast 3D Wafer Stacked ICs in SiGe 50% $500k Among several aspects of this large program, the project here was to develop a method of

designing and fabricating 3-D integrated circuits by bonding 2 or more wafers together and creating interconnections between pairs of wafers. The justification is that 3-D circuits will have shorted interconnect wires than 2-D circuits and subsequently be able to run faster. The test application designed for this project is a combination register file and adder circuit.

21. NSF Lab Without Lights 10% $80k To avail the latest cutting-edge digital hardware laboratory equipment to more students,

including those with physical handicaps, lab instruments were interfaced with a web server and code was written to allow a set of lab experiments to be completed anywhere in the world where a student has access to a web browser. Through the web browser and with software tools, students are able to control all functions on an oscilloscope, power supply, and prototyping board, including the interconnections on the programmable board and the configuration of FPGA chips.

20. DARPA F-RISC Project 40% $800k This very large multi-year program developed a small RISC processor operating in the

GHz range using GaAs HBT transistors and fast CML logic gates. Much of the early work was on characterizing the process and developing accurate models of the devices and circuits.

19. Electronics Manufacturing Program/Automated Rework Cell 10% $250k An automated robotic manufacturing rework cell was developed to replace defective

surface mount fine-pitched components on high-density PWBs. Through the use of a vision system and multiple specialized end-effectors, the system would remove a bad component, clean up excess solder on the pads, dispense solder paste, align and place a new component, and laser solder the leads.

18. Microtomography Inspection 20% $150k A study was made on the requirements of a tomographic system able to resolve features

on the order of a micron or better. Simulations and algorithms were developed to apply this work to the inspection of interconnections on integrated circuits as a tool to characterize new fabrication processes.

17 Neural Network vision inspection of PWBs (X-ray & Light images) 40% $200k Investigated the use of artificial neural networks in the inspection of solder joint on PWBs.

Using only images of good and bad joints to train the ANN, inspection accuracy approached that of human inspectors. Both visible light images and X-ray laminographic images were presented to the inspection system. Two-dimensional FFT and wavelet preprocessing of the data improved the accuracy, although initially it was desired to develop a system requiring no preprocessing

16. IRT X-ray Images of Solder Joints 20% $75k

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System controller and image acquisition software and hardware were developed to acquire images of solder joints on PWBs to inspect for voids and irregularities.

15. CNF Automated Lace Cutting System 30% $100k A multiprocessor real-time vision controlled hot air jet tracked a pattern stitched into a lace

material to cut along the edge accurately in 2-D on a moving web. The system used a true real-time operating system and networked dual processors with inputs from line scan cameras & a shaft encoder and outputs to dual x-y stages controlling the position of the cutters, the airflow, and the speed and acceleration of the web winding spool. The project developed all the line scan vision routines, motion control functions, and networking communication software for the dual processor vision guided cutting system.

14. McGard Automated Die Inspection System 25% $100k A system was designed, built, and delivered to inspect machined dies with a resolution of

.0001 in. and accuracy of .0005 in. using a high magnification lens on a video camera and an x-y stage. The system reads IGES data from a CAD system used to design the die and drives the x-y stage to appropriate positions enabling the vision system to view the desired features and compare the actual dimensions to the design values automatically.

13. DEC Dimensional Inspection of Sheet Metal Parts 15% $120k IGES Data from the CAD system used to design sheet metal parts was input into an object

oriented data base that extracted features from the graphic entities. These features (circular holes, slots, key holes, rectangular holes, tabs, etc.) are used as input to a vision-based inspection system to verify the parts from the punch press machine.

12. E-B Designs Automated Epoxy Dispensing 20% $80k Designed the illumination system and image processing function to detect the position and

orientation of the parts to be coated. Full translation (translation & rotation) of the data was required to map it into the reference frame of the motion controlled x-y table.

11. IBM Intelligent Sensor-based Robotic End Effector 30% $140k An extremely sophisticated end effector for handling wafers in a processing line was

developed. The end effector used a camera and a 4-LED structured light source to detect the position of the wafer so as to minimize the stresses on the wafer during transfers in and out of quartz glass boats, carrier cassettes, and domed wafer carriers. The intelligent sensing of the end effector, combined with a rigid/floating holding mechanism and a computer based controller/signal processor had the end effector actually directing the robot as to where to go to align the wafer with the destination and maintain zero stresses on the edges of the wafers from contact with the holders used for the processing steps.

10. Emhart Powers High Speed Glass Bottle Inspection 35% $130k Developed an electronic imaging based inspection system to detect flaws in glass bottles

such as cracks, chips, surface checks, and embedded bubbles. The detection had to occur at high speeds to allow on-line inspection at production rates up to 10 bottles/sec.

9. Simmonds Precision Aircraft Fuel Gauging System Development Project 30% $130k This phase I project investigated the use of several widely varying technologies to

determine the amount of fuel in an aircraft’s fuel tank under almost all possible

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circumstances the craft may experience. The most demanding conditions would be presented by a jet fighter undergoing evasive maneuvers that would cause the fuel to exist in some indeterminate state making gauging very difficult.

8. Automated Assembly Program Assembly Verification 20% $100k The AdeptVision II XGS system on the assembly workcell robot was used to verify the

correct assembly position of gear parts of a dial indicator gauge after robot placement using strategically positioned cameras. Robotic assembly system used 3 robots and conveyor systems coordinated by 2 PLCs with barcode reader inputs used to track subassemblies on the conveyors.

7. Pratt & Whitney GMAP Automated CMM Programming Project 25% $120k As part of a highly automated manufacturing system development, this project developed

the software to generate an inspection program for a CMM based on the dimensions and specifications of machined parts obtained from the CAD databases.

6. IBM/Navy CCAPS Electronic Manufacturing PWB Components Survey 30% $80k In a effort to track the current state of the art and future direction for the manufacturing of

electronic modules (PWBs), survey data was obtained from 50 contractors on the specific component technologies used and planned changes over the next 10 years. This data was collated and presented, keeping the identities of individual companies hidden, but showing trends of the entire industry combined.

5. Norton Coated Abrasives Inspection Project 25% $120k A vision system was developed using mathematical morphology transformations to

process images of the texture of coated abrasives (sand paper) to determine its coarseness and create a feedback control signal to adjust the manufacturing process to make corrections if the process was going out of specifications.

4. Robot Safety Automatic Multiple Sensing Project 10% $50k To improve the safety of robotic systems by limiting the exposure of operators or

bystanders to danger, a system was developed with multiple sensors such as for sound, vision, electromagnetic capacitance, ultrasound, etc. and used the sensing to determine if a human had entered the workspace and was in danger of being hit by the robot.

3. Anderson Instruments Intelligent Pressure Sensor Development Project 30% $90k An intelligent pressure sensor was developed to gauge the contents of food storage tanks.

A computer based sensing system was developed to compensate the measurement system’s analog circuits for changes in temperature, humidity, and barometric pressure and provide a calibration system for the tanks in order to improve the readout accuracy.

2. Automated Assembly Task Level Robotic Programming Project 50% $70k Robotic software was developed to permit high-level task oriented programming of a robot

arm. One specific example was a routine for the insertion of snap fasteners during an assembly operation that would automatically exchange end effectors if necessary, pick up a fastener from a feeder, locate the destination position using a vision camera attached to the robot, monitor the force while inserting the fastener, and automatically discard

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fasteners that went in too easily (undersized) or didn’t fit (oversized) and repeated with a new fastener after discarding the defective one.

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(Previously at MTI) 1. Coors EndSpector System 60% $400k This particular application included the inspection and dimensional gauging of beverage

can ends, a laser triangulation gauging system and a feature recognition system. These projects required the development of unique custom image processing routines, which utilized the functionality of the hardware-pipelined processor as fully as possible to minimize the computational time of the algorithms. In the can end inspection system, one of the measurements utilized a precision optical structured light and a highly magnified image to obtain a height dimension which could be resolved to 30 micro-inches with an overall accuracy of 100 micro-inches. This required several new filtering routines. First, the brushed metal surface of the part was very difficult to work with and created a large amount of image "noise" which had to be resolved to obtain the desired accuracies. After that, the precision optical light stripe had to be correlated with a previously measured optimized match pattern to accurately locate the position of the stripe in the image. Additionally, the illumination of the image presented problems that were caused by the high magnification and optimal histogram stretching to maximize the image contrast was performed using look-up tables on the frame grabber/image digitizing board. All image processing algorithms had to be modified to use the hardware pipelined array processing board designed for the six-board imaging system. Methods had to be devised to circumvent problems arising from the finite 16-bit image and word size of intermediate values and 8-bit word size of final results. Scaling in general always presents problems in algorithm implementation and improperly addressing the problem leads directly to success or failure of a given application. Certain types of filtering and correlation operations are impractical to perform in these theoretical forms because of speed, memory, accuracy and hardware cost contracts. However, slight modifications to the mathematical descriptions permit real implementations, which produce the desired results with nearly imperceptible degradation in performance.

In the feature recognition system, this technique was exploited fully to quickly locate

desired features in the image by pushing the cost- effective imaging hardware to its maximum extent. The results were very satisfactory and the algorithm could be easily adopted to recognize more features and discern between similar objects. As in every system, much of the design involved the proper lighting and optics to enhance and simplify the image processing. Various techniques were utilized in both the recognition system and the can end inspection/gauging system.